Digital-to-analog converter, manufacturing method and successive approximation analog-to-digital converter
By adopting a capacitive digital-analog converter (CDAC) with a three-dimensional layout in SAR ADC, the problems of large area occupied by CDAC and wiring signal interference in the prior art are solved, and more efficient area utilization and more accurate analog-to-digital conversion are achieved.
Patent Information
- Application Number
- CN202311686692.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-08
- Publication Date
- 2025-06-10
AI Technical Summary
The capacitive digital-to-analog converter (CDAC) in existing SAR ADCs has a large area, and the internally wired circuit signals have an impact on the operation of the capacitor, affecting the conversion accuracy.
Using a three-dimensional layout capacitive digital-analog converter (CDAC), by configuring a capacitance structure and control logic circuits between multiple metal layers, the total area of the CDAC is reduced, and the interference of circuit signals to the capacitor is reduced through the shielding layer.
It effectively reduces the total area of SAR ADC and reduces the impact of internal wiring on capacitor operation of CDAC, thereby improving conversion accuracy and overall performance.
Smart Images
Figure CN120128185A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a technology of a capacitive digital-to-analog converter, and particularly to a capacitive digital-to-analog converter with a three-dimensional layout, a manufacturing method thereof, and a successive approximation analog-to-digital converter. Background Art
[0002] In the current field of analog-to-digital converters (ADCs), successive approximation register (SAR) ADCs have become one of the most commonly used ADCs due to their high conversion accuracy.
[0003] However, in the layout adopted by current SAR ADCs, the capacitive digital-to-analog converter (CDAC) in the SAR ADC often requires a large area. This phenomenon not only increases the area of the SAR ADC, but also the circuit signals of the routing inside the CDAC will affect the operation of the capacitor. Therefore, how to improve the influence brought by the layout of the CDAC is one of the topics in this field. Summary of the Invention
[0004] The present disclosure provides a capacitive digital-to-analog converter (CDAC), including a capacitive structure and a control logic circuit. Two ends of the capacitive structure are respectively used to receive a positive reference voltage and a negative reference voltage. The control logic circuit is coupled to the capacitive structure and includes a plurality of switch groups, wherein each switch group includes a first switch circuit and a second switch circuit, and the first switch circuit and the second switch circuit each include a first end, a second end, and a control end. The first end of the first switch circuit receives the positive reference voltage via the first shielding layer of the CDAC, and the first end of the second switch circuit receives the negative reference voltage via the second shielding layer of the CDAC. The second end is used to be coupled to the capacitive structure. The control end is used to receive one of a plurality of conduction signals via the first metal layer of the CDAC. The capacitive structure is at least located in the second metal layer of the CDAC, and in the vertical direction, the first shielding layer and the second shielding layer are located above the first metal layer and below the second metal layer, wherein the vertical direction is perpendicular to the planar directions of the first metal layer, the second metal layer, the first shielding layer, and the second shielding layer.
[0005] The present disclosure provides a manufacturing method for manufacturing a CDAC. The manufacturing method includes: forming a control logic circuit including a plurality of switch groups; and forming a capacitor structure. The step of forming the control logic circuit including a plurality of switch groups includes: forming a plurality of first switch circuits, wherein a first end of each first switch circuit receives a positive reference voltage via a first shielding layer of the CDAC, and a control end of each first switch circuit receives one of a plurality of conduction signals via a first metal layer of the CDAC; and forming a plurality of second switch circuits, wherein a first end of each second switch circuit receives a negative reference voltage via a second shielding layer of the CDAC, and a control end of each second switch circuit receives another one of the plurality of conduction signals via the first metal layer. The capacitor structure is at least located in a second metal layer of the CDAC and is coupled to a plurality of second ends of the plurality of first switch circuits and the plurality of second switch circuits, wherein two ends of the capacitor structure are respectively used to receive the positive reference voltage and the negative reference voltage. In a vertical direction, the first shielding layer and the second shielding layer are located above the first metal layer and below the second metal layer, and the vertical direction is perpendicular to a planar direction of the first metal layer, the second metal layer, the first shielding layer, and the second shielding layer.
[0006] The present disclosure provides a successive approximation analog-to-digital converter (SAR ADC), including a CDAC, a comparator, and a logic decision circuit. The CDAC includes a capacitor structure and a control logic circuit coupled to each other, wherein two ends of the capacitor structure are respectively used to receive the positive reference voltage and the negative reference voltage to sample an input signal and generate a first signal and a second signal, and the control logic circuit is used to adjust the first signal and the second signal according to a plurality of conduction signals. The comparator is coupled to the CDAC to generate a decision signal according to the first signal and the second signal. The logic decision circuit is coupled to the CDAC and the comparator to generate a plurality of conduction signals and an output signal according to the decision signal. The logic control circuit receives the positive reference voltage and the negative reference voltage via a first shielding layer and a second shielding layer of the CDAC respectively, and receives the plurality of conduction signals via a first metal layer of the CDAC. The capacitor structure is at least located in a second metal layer of the CDAC. In a vertical direction, the first shielding layer and the second shielding layer are located above the first metal layer and below the second metal layer, wherein the vertical direction is perpendicular to a planar direction of the first metal layer, the second metal layer, the first shielding layer, and the second shielding layer.
[0007] Through the CDAC, its manufacturing method, and the SAR ADC of the present disclosure, the layout of the CDAC can be configured in a three-dimensional manner to reduce the total area of the CDAC and the SAR ADC, and reduce the influence of circuit signals of the wiring inside the CDAC on the operation of the capacitor structure, thereby improving the performance of the CDAC and the SAR ADC. Description of the Drawings
[0008] To make the above and other objects, features, and advantages of the present disclosure more apparent and understandable, the description of the accompanying drawings is as follows: Figure 1 It is a simplified functional block diagram of a SAR ADC illustrated according to some embodiments of the present disclosure; Figure 2A It is a top view schematic diagram of a CDAC illustrated according to some embodiments; Figure 2B It is a schematic diagram of a switch group illustrated according to some embodiments; Figure 3A It is a top view schematic diagram of a CDAC illustrated according to some embodiments of the present disclosure; Figure 3B It is a partial three-dimensional schematic diagram of a CDAC illustrated according to some embodiments of the present disclosure; and Figure 4 It is a flowchart of a manufacturing method of a CDAC illustrated according to some embodiments of the present disclosure. Detailed Embodiments
[0009] The embodiments of the present disclosure will be described below in conjunction with the relevant drawings. In the figures, the same reference numerals denote the same or similar components or method flows.
[0010] In the present disclosure, when a component is referred to as "linked", it may mean "electrically connected" or "optically connected", and when a component is referred to as "coupled", it may mean "electrically coupled" or "optically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation or interaction between two or more components. Unless otherwise specifically defined in the context, "a" and "the" can generally refer to a single or multiple. It will be further understood that the terms "comprising", "including", "having" and similar terms used herein specify the features, regions, integers, steps, operations, components and / or groups thereof described, but do not exclude one or more other features, regions, integers, steps, operations, components, components and / or groups thereof described or additional thereto.
[0011] Figure 1FIG. 0 is a simplified functional block diagram of a successive approximation analog-to-digital converter (SAR ADC) 100 illustrated according to some embodiments of the present disclosure. In some embodiments, the SAR ADC 100 includes a capacitive digital-to-analog converter (CADC) 110, a comparator 120, and a logic decision circuit 130. The CDAC 110 is coupled to the comparator 120 and the logic decision circuit 130 to receive an input signal DIN and sample the input signal DIN to generate a signal DAC+ and a signal DAC-. In addition, the CDAC 110 is further configured to receive enable signals EN1 to EN3 from the logic decision circuit 130 and adjust the output signals DAC+ and DAC- according to the enable signals EN1 to EN3.
[0012] The comparator 120 is coupled to the CDAC 110 and the logic decision circuit 130 to receive the signals DAC+ and DAC- from the CDAC 110, generate a decision signal COM according to the signals DAC+ and DAC-, and then transmit the decision signal COM to the logic decision circuit 130.
[0013] The logic decision circuit 130 is coupled to the CDAC 110 and the comparator 120 to receive the decision signal COM from the comparator 120, generate the enable signals EN1 to EN3 to the CDAC 110 according to the decision signal COM to control the conduction status of each switch in the CDAC 110, and generate an output signal DOUT according to the decision signal COM.
[0014] It should be noted that for the sake of brevity, other components and circuits in the SAR ADC 100 are omitted. The configuration of the SAR ADC 100 in the present disclosure is only an example and is not intended to limit the present disclosure. SAR ADCs with other configurations are all within the scope of the present disclosure.
[0015] For a detailed description of the internal structure of the CDAC 110, please further refer to Figures 2A - 2B and Figures 3A - 3B . Figure 2A FIG. 18 is a top view schematic diagram of a CDAC 200 illustrated according to some embodiments. In some embodiments, Figure 1 the CDAC 110 in Figure 2A can be implemented by the CDAC 200 in
[0016] In some embodiments, the CDAC 200 includes a capacitive structure 210 and a control logic circuit 220 that are coupled to each other. Both ends of the capacitive structure 210 receive a positive reference voltage Vrefp and a negative reference voltage Vrefn, respectively. The control logic circuit 220 includes switch groups 221-227, and each of the switch groups 221-227 includes three switch circuits. For example, the switch group 221 includes switch circuits 221_1, 221_2, and 221_3, the switch group 222 includes switch circuits 222_1, 222_2, and 222_3, the switch group 223 includes switch circuits 223_1, 223_2, and 223_3, and so on. The control logic circuit 220 is configured to receive enable signals EN1-EN3 and adjust the conduction states of the switch circuits 221_1-227_1, 221_2-227_2, and 221_3-227_3 (hereinafter simply referred to as "switch circuits 221_1-227_3") according to the enable signals EN1-EN3.
[0017] To illustrate the structure of the switch group in detail, please refer to Figure 2B . Figure 2B FIG. is a schematic diagram of the switch group 221 illustrated according to some embodiments. It should be noted that since the configurations and structures of the switch groups 222-227 are similar to that of the switch group 221, for the sake of brevity, the configuration and structure of the switch group 221 are described below with reference to Figure 2B to illustrate the configuration and structure of the switch group 221, and to illustrate the similarities and differences between the switch groups 222-227 and the switch group 221.
[0018] As Figure 2B shown, in some embodiments, each of the switch circuits 221_1-221_3 of the switch group 221 includes a first end, a second end, and a control end, wherein the first ends of the switch circuits 221_1-221_3 are coupled to the capacitive structure 210. In some embodiments, each of the switch circuits (hereinafter referred to as "switch circuits 222_1-227_3") of the switch groups 222-227 also includes a first end, a second end, and a control end. Similar to the first ends of the switch circuits 221_1-221_3, the first ends of the switch circuits 222_1-227_3 are also coupled to the capacitive structure 210. In some embodiments, two of the three switch circuits in each switch group may share an end point. For example, as Figure 2B shown, the switch circuits 221_2 and 221_3 in the switch group 221 share the second end.
[0019] In some embodiments, the second ends of the switching circuits 221_1 to 221_3 are respectively used to receive a positive reference voltage Vrefp, a common mode voltage VCM, and a negative reference voltage Vrefn. Similar to the second ends of the switching circuits 221_1 to 221_3, the second ends of the three switching circuits in each of the switch groups 222 to 227 are also respectively used to receive the positive reference voltage Vrefp, the common mode voltage VCM, and the negative reference voltage Vrefn.
[0020] In other words, for the switching circuits 221_1 to 227_3, the second ends of the switching circuits 221_1, 222_1,..., 227_1 with an index number of "1" receive the positive reference voltage Vrefp, the second ends of the switching circuits 221_2, 222_2,..., 227_2 with an index number of "2" receive the common mode voltage VCM, and the second ends of the switching circuits 221_3,..., 227_3 with an index number of "3" receive the negative reference voltage Vrefn. In some embodiments, the common mode voltage VCM, the positive reference voltage Vrefp, and the negative reference voltage Vrefn are different from each other.
[0021] In some embodiments, the control ends of the switching circuits 221_1 to 221_3 of the switch group 221 are used to receive a conduction signal EN3 to determine whether the switching circuits 221_1 to 221_3 are conducting or non-conducting. The control ends of the switching circuits of the switch groups 222 to 227 are used to receive the conduction signals EN1, EN2, or EN3, rather than all receiving the conduction signal EN3.
[0022] As Figure 2A shown, the control ends of the switching circuits of the switch group 221 are used to receive the conduction signal EN3, and the control ends of the switching circuits of the switch groups 223, 225, and 227 are also used to receive the conduction signal EN3. On the other hand, the control ends of the switching circuits of the switch group 224 are used to receive the conduction signal EN1, and the control ends of the switching circuits of the switch groups 222 and 226 are used to receive the conduction signal EN2.
[0023] In some embodiments, the conduction signals EN1 to EN3 are each a multi-bit (e.g., 3-bit) signal, where each bit is used to control the conduction status of each switching circuit in the switch group. For example, the first bit of the conduction signal EN3 can control the conduction status of the switching circuit 221_1, the second bit of the conduction signal EN3 can control the conduction status of the switching circuit 221_2, and the third bit of the conduction signal EN3 can control the conduction status of the switching circuit 221_3.
[0024] In addition, the switching circuits in the switching groups 221 to 227 that receive the same voltage (i.e., the positive reference voltage Vrefp, the common-mode voltage VCM, or the negative reference voltage Vrefn) and are controlled by the same conduction signal (i.e., the conduction signals EN1, EN2, or EN3) will conduct or turn off synchronously.
[0025] Specifically, the switching group 224 receives the conduction signal EN1, so one of the switching circuits 224_1 to 224_3 conducts, and the other two turn off. The switching groups 222 and 226 are controlled by the conduction signal EN2, so the switching circuits 222_1 and 226_1 that commonly receive the positive reference voltage Vrefp conduct or turn off synchronously, the switching circuits 222_2 and 226_2 that commonly receive the common-mode voltage VCM conduct or turn off synchronously, and the switching circuits 222_3 and 226_3 that commonly receive the negative reference voltage Vrefn conduct or turn off synchronously. The switching groups 221, 223, 225, and 227 are controlled by the conduction signal EN3, so the switching circuits 221_1, 223_1, 225_1, and 227_1 that commonly receive the positive reference voltage Vrefp conduct or turn off synchronously, the switching circuits 221_2, 223_2, 225_2, and 227_2 that commonly receive the common-mode voltage VCM conduct or turn off synchronously, and the switching circuits 221_3, 223_3, 225_3, and 227_3 that commonly receive the negative reference voltage Vrefn conduct or turn off synchronously.
[0026] As can be seen from the above, in some embodiments, the switching circuits in N of the switching groups 221 to 227 that receive the same voltage (i.e., the positive reference voltage Vrefp, the common-mode voltage VCM, or the negative reference voltage Vrefn) will conduct or turn off synchronously, the switching circuits in another 2N that receive the same voltage will conduct or turn off synchronously, and the switching circuits in yet another 4N that receive the same voltage will conduct or turn off synchronously, where N is a positive integer.
[0027] It should be noted that the number of switching groups and switching circuits in the present disclosure is only an example and is not intended to limit the present disclosure. Switching groups and switching circuits of other numbers are within the scope of the present disclosure. In some embodiments, each switching group includes only two switching circuits. In other embodiments, each switching group includes more than three switching circuits.
[0028] It should be noted that although Figure 2A (and as described below Figure 3A) The generation methods of the positive reference voltage Vrefp and the negative reference voltage Vrefn are illustrated as being generated from the power supply voltage VDD through multiple variable resistors R and operational amplifiers OP. However, the present disclosure is not limited thereto. The generation methods of the positive reference voltage Vrefp and the negative reference voltage Vrefn in the present disclosure are not limited to using electrical component voltage division or current flowing through a resistor, nor are they limited to using an operational amplifier. In addition, it should be noted that the positive reference voltage Vrefp and the negative reference voltage Vrefn are generated through different circuits. For example, the circuit for generating the positive reference voltage Vrefp and the circuit for generating the negative reference voltage Vrefn include different variable resistors and / or different operational amplifiers.
[0029] In Figure 2A 's embodiment, the capacitive structure 210, the wire connecting the capacitive structure 210 and the control logic circuit 220, and the wires for transmitting the conduction signals EN1 to EN3 are disposed in the same metal layer of the CDAC 200. Therefore, the total area of the CDAC 200 is at least equal to the sum of the areas of the capacitive structure 210, the wire connecting the capacitive structure 210 and the control logic circuit 220, and the wires for transmitting the conduction signals EN1 to EN3, and the circuit signals in the wires coupling the capacitive structure 210 and the control logic circuit 220 may also affect the operation of the capacitive structure 210. The following will describe in detail Figure 1 other implementation manners of the CDAC 110 in
[0030] Figure 3A is a top view schematic diagram of the CDAC 300 illustrated according to some embodiments of the present disclosure. In some embodiments, Figure 1 the CDAC 110 in Figure 3A can be implemented by the CDAC 300 in
[0031] Figure 3A The operation manner of the CDAC 300 in Figure 2A is similar to that of the CDAC 200 in Figure 2B , in other words, the configuration and operation manner of the switch group 321 are similar to those of the switch group 221 in
[0032] In Figure 3AIn the embodiment, in the Z direction, the capacitive structure 310 is disposed above the control logic circuit 320 and the wires for transmitting the conduction signals EN1 to EN3. Therefore, the capacitive structure 310 is drawn in dashed lines, where the Z direction is perpendicular to the multiple metal layers in the CDAC 300. Thus, the total area of the CDAC 300 is only at least equal to the area of the capacitive structure 310, so the total area of the CDAC 300 can be smaller than the total area of the CDAC 200.
[0033] The control logic circuit 320 receives the conduction signals EN1 to EN3 in a configuration similar to that of the control logic circuit 220 and controls the conduction states of the switching circuits 321_1 to 327_3. Different from the control logic circuit 220, the control logic circuit 320 is coupled to the capacitive structure 310 through a plurality of vias VIA_C instead of through wires, so the influence of circuit signals on the operation of the capacitive structure 310 can be reduced.
[0034] To clearly illustrate the structure of the CDAC 300, please further refer to Figure 3B , Figure 3B FIG. is a partial perspective view of the CDAC 300 illustrated according to some embodiments of the present disclosure. The connection manners of the switching circuits 321_1 to 327_3 are similar to each other. For example, the conduction signals EN1 to EN3 are all transmitted to the switching circuits 321_1 to 327_3 via the metal layer M3, the positive reference voltage Vrefp is all transmitted to the switching circuits 321_1 to 327_3 via the metal layer M4 of the CDAC 300, the negative reference voltage Vrefn is all transmitted to the switching circuits 321_1 to 327_3 via the metal layer M5 of the CDAC 300, and the common-mode voltage VCM is all transmitted to the switching circuits 321_1 to 327_3 via the metal layer M6 of the CDAC 300. Therefore, for the sake of brevity, Figure 3B the switching circuits 321_2 to 327_3 are omitted in
[0035] In some embodiments, the first end (e.g., source) of the switching circuit 321_1 passes through the metal layers M1 to M3 of the CDAC 300 via the vias VIA0 to VIA3 and is connected to the metal layer M4 to receive the positive reference voltage Vrefp via the metal layer M4; the second end (e.g., drain) of the switching circuit 321_1 is coupled to the capacitive structure 310 through the metal layers M1 to M5 via the via VIA_C; the control end (e.g., gate) of the switching circuit 321_1 is coupled to the metal layer M2 via another via VIA0, VIA1 and then coupled to the metal layer M3 via another via VIA2 to receive the conduction signal EN3.
[0036] In some embodiments, the capacitive structure 310 is located in the metal layer M7 of the CDAC 300. Further, in the Z direction, the metal layer M7 is located above the metal layers M4 - M6, and the metal layers M4 - M6 are located above the metal layers M1 - M3. In other words, the CDAC 300 can be implemented as a three-dimensional layout in which circuit structures (i.e., the capacitive structure and the control logic circuit 320) are arranged between different metal layers.
[0037] In some embodiments, the metal layers M4 - M6 are used as a shielding layer between the metal layers M3 and M7 to shield the capacitive structure 310 and the control logic circuit 320, so as to prevent the circuit signals in the control logic circuit 320 from interfering with the operation of the capacitive structure 310. It should be noted that although Figure 3B the positive reference voltage Vrefp, the negative reference voltage Vrepn, and the common-mode voltage VCM are respectively transmitted through the metal layers M4 - M6, the present disclosure is not limited thereto, and any two of the positive reference voltage Vrefp, the negative reference voltage Vrepn, and the common-mode voltage VCM can exchange the metal layers through which they are transmitted. For example, the positive reference voltage Vrefp can be transmitted through the metal layer M6 instead, and the common-mode voltage VCM can be transmitted through the metal layer M4 instead.
[0038] In some embodiments, the CDAC 300 includes more than three metal layers (e.g., the metal layers M4 - M6 and additional metal layers (not shown)) between the metal layers M3 and M7, and these metal layers are respectively coupled to the positive reference voltage Vrefp, the common-mode voltage VCM, or the negative reference voltage Vrefn to jointly serve as a shielding layer between the metal layers M3 and M7.
[0039] As Figure 3B shown, in some embodiments, the capacitive structure 310 can be located in both the metal layer M7 and the metal layer M8 of the CDAC 300, where the metal layer M8 is located above the metal layer M7 in the Z direction, and the metal layers M7 and M8 are connected through the via VIA7. In other words, the capacitive structure 310 can be disposed in multiple metal layers of the CDAC 300.
[0040] It should be noted that although Figure 3B the capacitive structure 310 in
[0041] It should be noted that although Figure 3BThe switch circuit 321_1 therein is illustrated as a Metal Oxide Semiconductor (MOS) transistor, and it can be an N-type transistor or a P-type transistor, but the present disclosure is not limited thereto. The switch circuits 221_1 to 227_3 and 321_1 to 327_3 in the present disclosure can be implemented by a switch, an inverter, a buffer, a latch, other similar circuits, or a combination thereof.
[0042] In addition, in some embodiments, the switch circuits 321_2 to 327_2 (i.e., the switch circuits with the index number "2") can be omitted, and the metal layer M6 (i.e., the metal layer receiving the common-mode voltage VCM) can be omitted.
[0043] Figure 4 FIG. 400 is a flowchart of a manufacturing method 400 of a CDAC illustrated according to some embodiments of the present disclosure. In some embodiments, the manufacturing method 400 includes steps S410, S420, S430, S440, and S450.
[0044] In step S410, a plurality of first switch circuits (e.g., switch circuits 321_1 to 327_1) are formed, wherein a first end (e.g., source) of each first switch circuit receives a positive reference voltage (e.g., positive reference voltage Vrefp) via a first shielding layer (e.g., metal layer M4) of the CDAC, and a control end (e.g., gate) of each first switch circuit receives a plurality of conduction signals (e.g., conduction signals EN1 to EN3) via a first metal layer (e.g., metal layer M3) of the CDAC.
[0045] In step S420, a plurality of second switch circuits (e.g., switch circuits 321_3 to 327_3) are formed, wherein a first end (e.g., source) of each second switch circuit is coupled to a negative reference voltage (e.g., negative reference voltage Vrefn) via a second shielding layer (e.g., metal layer M5) of the CDAC, and a control end (e.g., gate) of each second switch circuit receives a plurality of conduction signals via the first metal layer of the CDAC.
[0046] In step S430, a plurality of third switch circuits (e.g., switch circuits 321_2 to 327_2) are formed, wherein a first end (e.g., source) of each third switch circuit is coupled to a common-mode voltage (e.g., common-mode voltage VCM) via a third shielding layer (e.g., metal layer M6) of the CDAC, and a control end (e.g., gate) of each third switch circuit receives a plurality of conduction signals via the first metal layer of the CDAC, wherein the common-mode voltage, the positive reference voltage, and the negative reference voltage are different from each other.
[0047] In step S440, a signal receiving layer (e.g., metal layer M3) is formed to receive a plurality of conduction signals from an external circuit (e.g., logic decision circuit 130) and transfer the plurality of conduction signals to the first metal layer.
[0048] In step S450, a capacitor structure (e.g., capacitor structure 310) is formed, where the capacitor structure is at least located in the second metal layer (e.g., metal layer M7) of the CDAC and is coupled to the plurality of second terminals (e.g., drains) of the plurality of first switch circuits, the plurality of second switch circuits, and the plurality of third switch circuits.
[0049] In an embodiment of manufacturing method 400, in the vertical direction (e.g., direction Z), the second metal layer is above the first metal layer, the first shielding layer, the second shielding layer, the third shielding layer, and the signal receiving layer, the first shielding layer, the second shielding layer, and the third shielding layer are above the first metal layer and the signal receiving layer, the signal receiving layer is above the first metal layer, and the aforementioned vertical direction is perpendicular to the planar direction of the first metal layer, the second metal layer, the first shielding layer, the second shielding layer, the third shielding layer, and the signal receiving layer.
[0050] It should be noted that the number and sequence of steps in manufacturing method 400 of the present disclosure are only examples and are not used to limit the present disclosure. The number and sequence of other steps are all within the scope of the present disclosure. In some embodiments, step S430 may be omitted.
[0051] Through the SAR ADC, CDAC, and their manufacturing methods of the present disclosure, the CDAC in the SAR ADC can be configured in a three-dimensional layout. In addition to reducing the total area of the SAR ADC, it can also improve the influence of the wiring in the CDAC on the operation of the capacitor.
[0052] The above are only the preferred embodiments of the present disclosure. Without departing from the scope or spirit of the present disclosure, the structure of the present disclosure can be variously modified and equivalently changed. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the appended claims are covered by the present disclosure.
Symbol Description
[0053] 100: SAR ADC 110: CDAC 120: Comparator 130: Logic Decision Circuit 200: CDAC 210: Capacitor Structure 220: Control Logic Circuit 221~227: Switch Group 221_1~227_1: Switch Circuit 221_2 to 227_2: Switching circuit 221_3 to 227_3: Switching circuit 300: CDAC 310: Capacitor structure 320: Control logic circuit 321 to 327: Switch group 321_1 to 327_1: Switching circuit 321_2 to 327_2: Switching circuit 321_3 to 327_3: Switching circuit 400: Manufacturing method S410, S420, S430: Steps S440, S450: Steps DIN: Input signal DOUT: Output signal DAC+, DAC-: Signals COM: Decision signal EN1 to EN3: Conducting signals VDD: Power supply voltage VCM: Common mode voltage Vrefp: Positive reference voltage Vrefn: Negative reference voltage R: Variable resistor OP: Operational amplifier Z: Direction M1 to M8: Metal layers VIA0 to VIA3: Through-holes VIA7, VIA_C: Through-holes.
Claims
1. A capacitive digital-to-analog converter CDAC, characterized in that, it comprises: a capacitive structure, where both ends of the capacitive structure are respectively used to receive a positive reference voltage and a negative reference voltage; and a control logic circuit, coupled to the capacitive structure and comprising a plurality of switch groups, where each switch group comprises a first switch circuit and a second switch circuit, and the first switch circuit and the second switch circuit each comprise: a first end, where the first end of the first switch circuit receives the positive reference voltage via a first shielding layer of the CDAC, and the first end of the second switch circuit receives the negative reference voltage via a second shielding layer of the CDAC; a second end, used to be coupled to the capacitive structure; and a control end, used to receive one of a plurality of conduction signals via a first metal layer of the CDAC, where the capacitive structure is at least located in a second metal layer of the CDAC, and in a vertical direction, the first shielding layer and the second shielding layer are located above the first metal layer and below the second metal layer, where the vertical direction is perpendicular to the planar directions of the first metal layer, the second metal layer, the first shielding layer, and the second shielding layer.
2. The CDAC according to claim 1, characterized in that, each of the plurality of switch groups further comprises a third switch circuit, and the third switch circuit comprises: a first end, used to receive a common-mode voltage, where the common-mode voltage, the positive reference voltage, and the negative reference voltage are different from each other; a second end, used to be coupled to the capacitive structure; and a control end, used to receive another one of the plurality of conduction signals via the first metal layer.
3. The CDAC according to claim 2, characterized in that, it further comprises: a third shielding layer, coupled to the first end of the third switch circuit, used to receive the common-mode voltage and shield the capacitive structure and the control logic circuit, where in the vertical direction, the third shielding layer is located between the first metal layer and the second metal layer.
4. The CDAC according to claim 2, characterized in that, one of the first switch circuit, the second switch circuit, and the third switch circuit in each switch group conducts according to the plurality of conduction signals, and the other two of the first switch circuit, the second switch circuit, and the third switch circuit are turned off according to the plurality of conduction signals.
5. The CDAC according to claim 4, characterized in that, the N first switch circuits of N of the plurality of switch groups conduct or turn off synchronously, the N second switch circuits conduct or turn off synchronously, and the N third switch circuits conduct or turn off synchronously; the 2N first switch circuits of another 2N of the plurality of switch groups conduct or turn off synchronously, the 2N second switch circuits conduct or turn off synchronously, and the 2N third switch circuits conduct or turn off synchronously; and the 4N first switch circuits of yet another 4N of the plurality of switch groups conduct or turn off synchronously, the 4N second switch circuits conduct or turn off synchronously, and the 4N third switch circuits conduct or turn off synchronously, where N is a positive integer.
6. The CDAC according to claim 1, characterized in that, It further includes a first through hole extending along the vertical direction, wherein the second ends of the first switching circuit and the second switching circuit are coupled to the capacitive structure through the first through hole.
7. The CDAC according to claim 6, wherein, the capacitive structure is located in the second metal layer and a third metal layer of the CDAC. In the vertical direction, the third metal layer is above the second metal layer, and the second metal layer and the third metal layer are coupled to each other through a second through hole extending along the vertical direction.
8. The CDAC according to claim 1, wherein, it further includes a signal receiving layer and a third through hole. In the vertical direction, the signal receiving layer is above the first metal layer and is coupled to the first metal layer through the third through hole for receiving the plurality of conduction signals from an external circuit and transmitting the plurality of conduction signals to the first metal layer through the third through hole.
9. A manufacturing method for manufacturing a CDAC, wherein, the manufacturing method includes: forming a control logic circuit including a plurality of switch groups, including: forming a plurality of first switching circuits, wherein a first end of each first switching circuit receives a positive reference voltage via a first shielding layer of the CDAC, and a control end of each first switching circuit receives one of the plurality of conduction signals via a first metal layer of the CDAC; and forming a plurality of second switching circuits, wherein a first end of each second switching circuit receives a negative reference voltage via a second shielding layer of the CDAC, and a control end of each second switching circuit receives another one of the plurality of conduction signals via the first metal layer; and forming a capacitive structure, wherein the capacitive structure is at least located in a second metal layer of the CDAC and is coupled to second ends of the plurality of first switching circuits and the plurality of second switching circuits, and two ends of the capacitive structure are respectively used for receiving the positive reference voltage and the negative reference voltage, wherein in a vertical direction, the first shielding layer and the second shielding layer are above the first metal layer and below the second metal layer, and the vertical direction is perpendicular to the planar directions of the first metal layer, the second metal layer, the first shielding layer, and the second shielding layer.
10. A successive approximation analog-to-digital converter SAR ADC, wherein, it includes: a CDAC including a capacitive structure and a control logic circuit coupled to each other, wherein two ends of the capacitive structure are respectively used for receiving a positive reference voltage and a negative reference voltage to sample an input signal and generate a first signal and a second signal, and the control logic circuit is used for adjusting the first signal and the second signal according to a plurality of conduction signals; a comparator coupled to the CDAC for generating a decision signal according to the first signal and the second signal; and a logic decision circuit coupled to the CDAC and the comparator for generating the plurality of conduction signals and an output signal according to the decision signal. The logic control circuit receives the positive reference voltage and the negative reference voltage via a first shielding layer and a second shielding layer of the CDAC respectively, and receives the plurality of conduction signals via a first metal layer of the CDAC. The capacitive structure is at least located in a second metal layer of the CDAC, and in a vertical direction, the first shielding layer and the second shielding layer are located above the first metal layer and below the second metal layer, where the vertical direction is perpendicular to the planar directions of the first metal layer, the second metal layer, the first shielding layer, and the second shielding layer.