Receiver circuit and operating method thereof

Abstract

The invention relates to a receiver circuit. The receiver circuit includes: an input unit configured to receive a reception mode signal in a training mode and receive a normal signal in a normal mode; an enable control unit configured to determine whether to activate an enable signal according to a reception mode signal in a training mode; a first decision feedback equalizer configured to operate within an active period of the enable signal and to remove a first post component of the received normal signal by calibrating a current received value based on a previous received value of the received normal signal; and a second decision feedback equalizer configured to, when the enable signal is in an active state, remove the second to Nth post components of the reception normal signal by adjusting a driving capability of the input transistor to which the current reception value is applied according to a mode in which the reception normal signal is received.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0176342, filed on December 7, 2023, which is incorporated herein by reference in its entirety. Technical field

[0003] Various embodiments of the present disclosure generally relate to a semiconductor circuit, and more particularly, to a receiver circuit having an equalization function and an operation method thereof. Background art

[0004] An electronic device may include many electronic components, and in an electronic device, a computer system may include many semiconductor devices made of semiconductors. Among various semiconductor devices implemented using semiconductors, there are devices using a memory system as a storage medium. For example, a portable digital electronic device (such as a digital camera, a smart phone, and a tablet personal computer (PC)) may include a volatile memory device and a non - volatile memory device to store data. A volatile memory device is a memory device in which data stored is lost when power is cut off. Examples of volatile storage devices may include static random access memory (RAM) (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. A non - volatile memory device is a memory device that can retain data stored even when power is cut off. Examples of non - volatile memory devices may include read - only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase - change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory can be roughly classified into NOR flash memory and NAND flash memory.

[0005] Such memory devices can communicate with each other by transmitting and receiving clock signals and data. A memory device can transmit a signal having information corresponding to data through a signal bus such as a data bus. Each memory device may include a signal transmission circuit to transmit a signal through the signal bus. The signal transmission circuit can transmit a signal by transmitting an analog voltage via the signal bus. Generally, the signal transmission circuit can transmit an analog voltage corresponding to a high logic level and an analog voltage corresponding to a low logic level.

[0006] In a signal input and output (input / output) interface included in a memory device, data signals may be transmitted to a receiver through a channel. As the data rate increases, interference signals generated due to channel effects may increase, resulting in a degradation of signal quality. To improve the degraded signal integrity (SI) characteristics, an equalization function is used. As one of several equalizers providing the equalization function, a decision feedback equalizer (DFE) may improve SI characteristics by eliminating interference signals (i.e., post signals causing inter-symbol interference (ISI)).

[0007] In the equalization function of the DFE, a DFE using a direct feedback method may include a current adder DFE and a Gm control DFE. The current adder DFE may refer to a direct feedback DFE that performs an equalization function by directly calibrating a currently received signal using the value of a previously (subsequently) received signal. The Gm control DFE may refer to a direct feedback DFE that performs an equalization function by adjusting the driving ability of a transistor that inputs a currently received signal according to a pattern of the value of a previously received signal (i.e., by an indirect method). The current adder DFE consumes more current than the Gm control DFE, but may more effectively improve the SI characteristics of a received signal. Summary of the Invention

[0008] Various embodiments of the present disclosure are directed to providing a receiver circuit and an operating method thereof that confirm inter-symbol interference (ISI) occurring in a signal input through a training operation performed before normal operation after power-on, and adjust an equalization function applied in normal operation according to the confirmation result.

[0009] The technical problems to be solved by the present disclosure are not limited to the foregoing technical problems, and other unmentioned technical problems will be clearly understood by those skilled in the art from the following description.

[0010] Embodiments of the present disclosure include a receiver circuit, which may include: a first input unit configured to receive a first input pattern signal as a first received pattern signal according to a training reference level and receive a first input normal signal as a first received normal signal according to a normal reference level, wherein the first input pattern signal is applied through a first pad in a training mode and the first input normal signal is applied through the first pad in a normal mode after the training mode; a first enable control unit configured to determine whether to activate a first enable signal according to a confirmation result of a value of the first received pattern signal in the training mode; a first decision feedback equalizer configured to operate during an activation period of the first enable signal and remove a first post-cursor component of the first received normal signal by calibrating a current received value based on a first previously received value of the first received normal signal; and a second decision feedback equalizer configured to, when the first enable signal is in an activated state, remove second to Nth post-cursor components of the first received normal signal by adjusting a driving ability of a first input transistor to which the current received value is applied according to a pattern of second to Nth previously received values of the first received normal signal, where N is a natural number of 2 or greater.

[0011] Embodiments of the present disclosure include an operating method of a receiver circuit, which may include: a first receiving operation of receiving a first input pattern signal as a first received pattern signal according to a training reference level and receiving a first input normal signal as a first received normal signal according to a normal reference level, wherein the first input pattern signal is applied through a first pad in a training mode and the first input normal signal is applied through the first pad in a normal mode after the training mode; a first enable control operation of determining whether to activate a first enable signal according to a confirmation result of a value of the first received pattern signal; and when the first enable signal is in an activated state in the normal mode, removing a first post-cursor component of the first received normal signal by calibrating a current received value based on a first previously received value of the first received normal signal, and removing second to Nth post-cursor components of the first received normal signal by adjusting a driving ability of a first input transistor to which the current received value is applied according to a pattern of second to Nth previously received values of the first received normal signal, where N is a natural number of 2 or greater.

[0012] This technology can confirm inter-symbol interference (ISI) occurring in a signal input through a training operation performed before normal operation after power-on, and adjust an equalization function applied in normal operation according to the confirmation result.

[0013] That is, this technology can place at least two types of decision feedback equalizers (DFEs) in a receiver circuit, and then perform normal operation in a state of selecting and starting a DFE according to the degree of occurrence of ISI in an input signal confirmed through a training operation.

[0014] This enables minimizing the amount of current consumed by the receiver circuit during periods of normal operation in order to use the equalization function. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a diagram showing a receiver circuit according to an embodiment of the present disclosure.

[0016] Figure 2 is a diagram showing a first receiver operation unit among the components of the receiver circuit according to an embodiment of the present disclosure.

[0017] Figure 3 is a diagram showing Figure 2 a first enable control unit among the components of the first receiver operation unit shown in

[0018] Figure 4 is a diagram showing a second receiver operation unit among the components of the receiver circuit according to an embodiment of the present disclosure.

[0019] Figure 5 is a diagram showing Figure 2 a second enable control unit among the components of the second receiver operation unit shown in

[0020] Figure 6 is a diagram showing a first signal storage unit or a second signal storage unit among the components of the receiver circuit according to an embodiment of the present disclosure.

[0021] Figure 7 is a diagram showing a training operation performed by the receiver circuit according to an embodiment of the present disclosure

[0022] Figure 8 is a diagram showing another training operation performed by the receiver circuit according to an embodiment of the present disclosure

[0023] Figure 9 is a diagram showing the sequence of training operations performed by the receiver circuit according to an embodiment of the present disclosure.

[0024] Figure 10A and Figure 10B are circuit diagrams of a current adder DFE and a Gm control DFE applied to the receiver circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Various embodiments of the present disclosure will be described below with reference to the drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0026] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, features, etc.) included in "one embodiment", "example embodiment", "embodiment", "another embodiment", "some embodiments", "multiple embodiments", "other embodiments", "alternative embodiments", etc. are intended to mean that any such feature is included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0027] In the present disclosure, the terms "comprise", "comprises", "include" and "includes" are open-ended. As used in the appended claims, these terms specify the presence of the recited elements and do not preclude the presence or addition of one or more other elements. The terms in the claims do not preclude the device from including additional components (e.g., interface units, circuits, etc.).

[0028] In the present disclosure, various units, circuits, or other components may be described or claimed as "configured to" perform one or more tasks. In this context, "configured to" is used to denote structure by indicating that the block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, even when the specified block / unit / circuit / component is not currently operating (e.g., not turned on or not enabled), it can be said that the block / unit / circuit / component is configured to perform the task. A block / unit / circuit / component used in conjunction with "configured to" includes hardware, such as a circuit, a memory storing program instructions executable to implement the operation, etc. Additionally, "configured to" may include a general structure (e.g., a general circuit) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to be able to operate in a manner that can perform the recited task(s). "Configured to" may also include making a manufacturing process (e.g., a semiconductor manufacturing facility) suitable for manufacturing a device (e.g., an integrated circuit) that implements or performs one or more tasks.

[0029] As used in this disclosure, the terms "circuit" or "logic" refer to all of the following: (a) only hardware circuit implementations (e.g., only implementations in analog and / or digital circuits); and (b) combinations of circuits and software (and / or firmware), such as, for example (if applicable): (i) combinations of (one or more) processors or (ii) portions of (one or more) processors / software (including (one or more) digital signal processors), software, and (one or more) memories that work together to cause a device (e.g., a mobile phone or a server) to perform various functions; and (c) circuits that require software or firmware for operation even if the software or firmware is not physically present (e.g., (one or more) microprocessors or portions of (one or more) microprocessors). This definition of "circuit" or "logic" is applicable to all applications of the term in this application, including applications in any claims. As a further example, as used in this application, the terms "circuit" or "logic" also cover implementations that include only a processor (or processors) or a portion of a processor and its accompanying software and / or firmware. For example, the terms "circuit" or "logic" also cover, for example, an integrated circuit for a storage device if applicable to a particular claim element.

[0030] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns preceding the terms and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms "first" and "second" do not necessarily imply that the first value must be written before the second value. Further, although the terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. For example, a first circuit may be distinguished from a second circuit.

[0031] Further, the term "based on" is used to describe one or more factors that affect the determination result. This term does not exclude other factors that may affect the determination result. That is, the determination result may be based only on those factors or at least partially based on those factors. For example, the phrase "determine A based on B". Although in this case, B is a factor that affects the determination result of A, this phrase does not exclude that the determination result of A is also based on C. In other instances, A may be determined based only on B.

[0032] Herein, an item of data, data item, data entry, or entry of data may be a sequence of bits. For example, a data item may include the content of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a portion of a digital scanned image, a video signal or an audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to an embodiment, a data item may include discrete objects. According to another embodiment, a data item may include an information unit within a transmission data packet between two different components.

[0033] Figure 1 is a diagram showing an example of a receiver circuit according to an embodiment of the present disclosure.

[0034] Referring to Figure 1 , the receiver circuit 1 may include a first receiver operation unit 100 and a second receiver operation unit 200. The first receiver operation unit 100 may include a first decision feedback equalizer (DFE1) 103 (hereinafter referred to as the first equalizer) and a second decision feedback equalizer (DFE2) 104 (hereinafter referred to as the second equalizer). The second receiver operation unit 200 may include a third decision feedback equalizer (DFE3) 203 (hereinafter referred to as the third equalizer) and a fourth decision feedback equalizer (DFE4) 204 (hereinafter referred to as the fourth equalizer).

[0035] The first receiver operation unit 100 may receive, in a training mode, a first input pattern signal IN_PAT1_t0 applied through a first pad 106 as a first received pattern signal RV_PAT1_t0 according to a training reference level. Then, the first receiver operation unit 100 may determine whether to activate a first enable signal EN1 by confirming whether the value of the received first received pattern signal RV_PAT1_t0 has a predetermined pattern value.

[0036] The second receiver operation unit 200 may receive, in a training mode, a second input pattern signal IN_PAT2_t0 applied through a second pad 206 as a second received pattern signal RV_PAT2_t0 according to a training reference level. Then, the second receiver operation unit 200 may determine whether to activate a second enable signal EN2 by confirming whether the value of the received second received pattern signal RV_PAT2_t0 has a predetermined pattern value.

[0037] In this case, the training mode is an operation mode that can be entered and exited in response to a mode selection signal MD_SEL, and the first receiver operation unit 100 and the second receiver operation unit 200 may enter and exit the operation mode in parallel. That is, after entering the training mode, the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 may be respectively input to the first receiver operation unit 100 and the second receiver operation unit 200 in parallel. The operation of the first receiver operation unit 100 to determine whether to activate the first enable signal EN1 according to the value of the first received pattern signal RV_PAT1_t0 and the operation of the second receiver operation unit 200 to determine whether to activate the second enable signal EN2 according to the value of the second received pattern signal RV_PAT2_t0 may be executed in parallel.

[0038] However, the first receiver operation unit 100 and the second receiver operation unit 200 can operate independently. For example, after entering the training mode, when the first receiver operation unit 100 determines that the first enable signal EN1 is in the active state, the second receiver operation unit 200 can determine that the second enable signal EN2 is in the inactive state.

[0039] The first receiver operation unit 100 can receive, in the normal mode entered after exiting the training mode, a first input normal signal IN_NM1_t0 applied through the first pad 106 as a first received normal signal RV_NM1_t0 according to a normal reference level different from the training reference level. In this case, the first receiver operation unit 100 can enable at least one of the DFE1 103 and DFE2 104 included therein to improve the signal integrity (SI) characteristics of the first received normal signal RV_NM1_t0.

[0040] In particular, the first receiver operation unit 100 can select whether to enable the DFE1 103 according to the activation or deactivation of the first enable signal EN1 in the normal mode, and change the operation method of the DFE2 104 according to the activation or deactivation of the first enable signal EN1 in the normal mode.

[0041] For example, the first receiver operation unit 100 can, in response to the activation of the first enable signal EN1 in the training mode, enable the DFE1 103 in the normal mode, thereby removing the first postamble component of the first received normal signal RV_NM1_t0 based on the first previous (post) received value RV_NM1_t1 of the first received normal signal RV_NM1_t0. The first receiver operation unit 100 can also, in response to the activation of the first enable signal EN1 in the training mode, enable the DFE2 104 in the normal mode by a first operation method, thereby removing the second to Nth postamble components of the first received normal signal RV_NM1_t0 based on the second to Nth previous received values RV_NM1_t2:tN of the first received normal signal RV_NM1_t0. Here, N can be a natural number of 2 or greater.

[0042] Again, for example, the first receiver operation unit 100 can, in response to the deactivation of the first enable signal EN1 in the training mode, disable the DFE1 103 in the normal mode. The first receiver operation unit 100 can also, in response to the deactivation of the first enable signal EN1 in the training mode, enable the DFE2 104 in the normal mode by a second operation method, thereby removing the first to Nth postamble components of the first received normal signal RV_NM1_t0 based on the first to Nth previous received values RV_NM1_t1:tN of the first received normal signal RV_NM1_t0.

[0043] The second receiver operation unit 200 can receive, in a normal mode that it can enter after exiting the training mode, a second input normal signal IN_NM2_t0 applied through the second pad 206 as a second received normal signal RV_NM2_t0 according to a normal reference level different from the training reference level. In this case, the second receiver operation unit 200 can enable at least one of the DFE3 203 and the DFE4 204 included therein to improve the SI characteristics of the second received normal signal RV_NM2_t0.

[0044] In particular, the second receiver operation unit 200 can select whether to enable the DFE3 203 according to the activation or deactivation of the second enable signal EN2 in the normal mode, and change the operation method of the DFE4 204 according to the activation or deactivation of the second enable signal EN2 in the normal mode.

[0045] For example, the second receiver operation unit 200 can, in response to the activation of the second enable signal EN2 in the training mode, enable the DFE3 203 in the normal mode, so as to remove the first postamble component of the second received normal signal RV_NM2_t0 based on the first previously received value RV_NM1_t1 of the second received normal signal RV_NM2_t0. The second receiver operation unit 200 can also, in response to the activation of the second enable signal EN2 in the training mode, enable the DFE4 204 in the normal mode through a first operation method, so as to remove the second to Nth postamble components of the second received normal signal RV_NM2_t0 based on the second to Nth previously received values RV_NM1_t2:tN of the second received normal signal RV_NM2_t0.

[0046] Again, for example, the second receiver operation unit 200 can, in response to the deactivation of the second enable signal EN2 in the training mode, disable the DFE3 203 in the normal mode. The second receiver operation unit 200 can also, in response to the deactivation of the second enable signal EN2 in the training mode, enable the DFE4 204 in the normal mode through a second operation method, so as to remove the first to Nth postamble components of the second received normal signal RV_NM2_t0 based on the first to Nth previously received values RV_NM1_t1:tN of the second received normal signal RV_NM2_t0.

[0047] Each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 may include one main label component and N post-label components. In this case, the main label component may be the valid component of each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0, and may represent the target value of the signal actually applied through the pad. The post-label components may be the meaningless components of each of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0, and may be generated due to the inter-symbol interference (ISI) with the values of the signals RV_NM1_t1:tN and RV_NM2_t1:tN transmitted before receiving the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0.

[0048] Both the DFE1 103 included in the first receiver operation unit 100 and the DFE3 203 included in the second receiver operation unit 200 may be current adder DFE among the DFE using the direct feedback method. In this case, the current adder DFE may refer to a direct feedback DFE that performs an equalization function by directly calibrating the currently received signal using the value of the previously received signal. That is, when enabled in the normal mode, the DFE1 103 may perform an operation of removing the first post-label component of the first received normal signal RV_NM1_t0 based on the first previously received value RV_NM1_t1 of the first received normal signal RV_NM1_t0, and the DFE3 203 may perform an operation of removing the first post-label component of the second received normal signal RV_NM2_t0 based on the first previously received value RV_NM2_t1 of the second received normal signal RV_NM2_t0.

[0049] Both the DFE2 104 included in the first receiver operation unit 100 and the DFE4 204 included in the second receiver operation unit 200 may be Gm control DFE among the DFE using the direct feedback method. In this case, the Gm control DFE may refer to a direct feedback DFE that performs an equalization function by adjusting the driving ability of the transistor that inputs the currently received signal according to the pattern of the value of the previously received signal (i.e., by an indirect method).

[0050] That is to say, when using the first method in the normal mode, DFE2 104 can perform an operation of removing the second to Nth postamble components of the first received normal signal RV_NM1_t0 based on the second to Nth previous received values RV_NM1_t2:tN of the first received normal signal RV_NM1_t0, and DFE4 204 can perform an operation of removing the second to Nth postamble components of the second received normal signal RV_NM2_t0 based on the second to Nth previous received values RV_NM2_t2:tN of the second received normal signal RV_NM2_t0. When using the second method in the normal mode, DFE2 104 can perform an operation of removing the first to Nth postamble components of the first received normal signal RV_NM1_t0 based on the first to Nth previous received values RV_NM1_t1:tN of the first received normal signal RV_NM1_t0, and DFE4 204 can perform an operation of removing the first to Nth postamble components of the second received normal signal RV_NM2_t0 based on the first to Nth previous received values RV_NM2_t1:tN of the second received normal signal RV_NM2_t0.

[0051] With joint reference Figure 10A , the circuit configuration of the current adder DFE applied to each of DFE1 103 and DFE3 203 can be seen. In Figure 10A , IN_t0 and / IN_t0 can be one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 and their inverted signals respectively. In Figure 10A , IN_t1 and / IN_t1 can be the first previous received value RV_NM1_t1 or RV_NM2_t1 of one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 and their inverted received values respectively. In Figure 10A , ENABLE can be one of the first enable signal EN1 and the second enable signal EN2. As Figure 10A shown, it can be seen that the current adder DFE directly uses the values of the previously received signals to calibrate the currently received signals.

[0052] With joint reference Figure 10B , the circuit configuration of the Gm control DFE applied to each of DFE2 104 and DFE4 204 can be seen. In Figure 10B , IN_t0 and / IN_t0 can be one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 and their inverted signals respectively. In Figure 10BAmong them, IN_t1……IN_tN and / IN_t1…… / IN_tN can be the first to the Nth previous received values RV_NM1_t1:tN or RV_NM2_t1:tN of one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 respectively, and their inverted received values. In Figure 10B Among them, ENABLE can be one of the first enable signal EN1 and the second enable signal EN2. As Figure 10B shown, it can be seen that the Gm-controlled DFE performs the equalization function by adjusting the driving ability of the transistors that input the current received signal according to the pattern of the values of the previously received signals (i.e., by an indirect method).

[0053] In particular, in Figure 1 it can be seen that, according to one of the first enable signal EN1 and the second enable signal EN2, the first previously received value RV_NM1_t1 or RV_NM2_t1 of one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 is selectively used.

[0054] That is to say, in Figure 1 the first enable signal EN1 and the second enable signal EN2 are signals activated at a logic low level. When the first enable signal EN1 and the second enable signal EN2 are activated, it can be seen that the first previously received value RV_NM1_t1 or RV_NM2_t1 of one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 is not used for the equalization function. On the other hand, when the first enable signal EN1 and the second enable signal EN2 are deactivated, it can be seen that the first previously received value RV_NM1_t1 or RV_NM2_t1 of one of the first received normal signal RV_NM1_t0 and the second received normal signal RV_NM2_t0 is used for the equalization function.

[0055] Figure 2 is a diagram showing an example of the first receiver operation unit 100 among the components of the receiver circuit 1 according to an embodiment of the present disclosure. Referring to Figure 2 the above Figure 1 shown, the first receiver operation unit 100 may include a first input unit 101, a first enable control unit 102, DFE1 103, DFE2 104, and a first signal storage unit 105. The first receiver operation unit 100, the first input unit 101, the first enable control unit 102, DFE1 103, DFE2 104, and the first signal storage unit 105 include all the circuits, systems, software, firmware, and devices required for their respective operations and functions.

[0056] The first input unit 101 can receive, in a training mode, a first input pattern signal IN_PAT1_t0 applied through the first pad 106 as a first received pattern signal RV_PAT1_t0 according to a training reference level VRT.

[0057] The first input unit 101 can receive, in a normal mode entered after exiting the training mode, a first input normal signal IN_NM1_t0 applied through the first pad 106 as a first received normal signal RV_NM1_t0 according to a normal reference level VRN.

[0058] The first enable control unit 102 can determine whether to activate the first enable signal EN1 based on the result of confirming the value of the first received pattern signal RV_PAT1_t0 in the training mode.

[0059] More specifically, the first enable control unit 102 can activate the first enable signal EN1 in response to entering the training mode, and then, during the period of entering the training mode, deactivate the first enable signal EN1 in response to confirming that the value of the first received pattern signal RV_PAT1_t0 is a predetermined pattern value. In this way, the first enable signal EN1, which switches from the active state to the deactivated state during the period of entering the training mode, can continuously remain in the deactivated state until the first enable signal EN1 enters the training mode again and switches to the active state. That is to say, the first enable signal EN1, which switches from the active state to the deactivated state during the period of entering the training mode, can continuously remain in the deactivated state during the period of entering the normal mode after the training mode.

[0060] The first enable control unit 102 can activate the first enable signal EN1 in response to entering the training mode, and then, during the period of entering the training mode, continuously activate the first enable signal EN1 in response to confirming that the value of the first received pattern signal RV_PAT1_t0 is not a predetermined pattern value. That is to say, the first enable signal EN1, which continuously remains in the active state during the period of entering the training mode, can continuously remain in the active state even during the period of entering the normal mode after the training mode.

[0061] More specifically, the training mode can be divided into a first period and a second period.

[0062] In the first period of the training mode, the first input pattern signal IN_PAT1_t0 can be set to a first pattern and applied through the first pad 106.

[0063] In the second period of the training mode, which is entered after the first period of exiting the training mode, the first input pattern signal IN_PAT1_t0 can be set to a second pattern different from the first pattern and applied through the first pad 106.

[0064] In summary, the first input pattern signal IN_PAT1_t0 can be input in different pattern forms during the first time period and the second time period included in the training mode.

[0065] Therefore, during the first time period of the training mode, the first input unit 101 can receive the first input pattern signal IN_PAT1_t0 having the first pattern as the first received pattern signal RV_PAT1_t0 according to the first training reference level.

[0066] Therefore, during the second time period of the training mode, the first input unit 101 can receive the first input pattern signal IN_PAT1_t0 having the second pattern as the first received pattern signal RV_PAT1_t0 according to the second training reference level different from the first training reference level.

[0067] According to an embodiment, the first pattern of the first input pattern signal IN_PAT1_t0 may be a pattern including at least one "1" value between a plurality of "0" values. When the first pattern is set in this way, the first input unit 101 can set the first training reference level to a predetermined level higher than the normal reference level VRN. That is, during the first time period of the training mode, the first input unit 101 can determine the logic level of the first input pattern signal IN_PAT1_t0 through the first training reference level set to a predetermined level higher than the normal reference level VRN, and receive the first input pattern signal IN_PAT1_t0 as the first received pattern signal RV_PAT1_t0.

[0068] The second pattern of the first input pattern signal IN_PAT1_t0 may be a pattern including at least one "0" value between a plurality of "1" values. When the second pattern is set in this way, the first input unit 101 can set the second training reference level to a predetermined level lower than the normal reference level VRN. That is, during the second time period of the training mode, the first input unit 101 can determine the logic level of the first input pattern signal IN_PAT1_t0 through the second training reference level set to a predetermined level lower than the normal reference level VRN, and receive the first input pattern signal IN_PAT1_t0 as the first received pattern signal RV_PAT1_t0.

[0069] In summary, the training reference level VRT can be set to one of a level that is a predetermined level higher than the normal reference level VRN and a level that is a predetermined level lower than the normal reference level VRN according to the pattern of the first input pattern signal IN_PAT1_t0.

[0070] According to the operation of the first input unit 101 described above, the first enabling control unit 102 can activate the first enabling signal EN1 in response to the first time period of entering the training mode, and deactivate the first enabling signal EN1 when the first confirmation count reaches a predetermined count. The first confirmation count can be obtained by adding the count value of the number of "1" values included in the first reception mode signal RV_PAT1_t0 during the first time period of the training mode to the count value of the number of "0" values included in the first reception mode signal RV_PAT1_t0 during the second time period of the training mode. When the first confirmation count is different from the predetermined count, the first enabling control unit 102 can continuously activate the first enabling signal EN1.

[0071] DFE1 103 can operate during the activation period of the first enabling signal EN1, and remove the first postamble component of the first reception normal signal RV_NM1_t0 by directly calibrating the current reception value RV_NM1_t0 based on the first previous reception value RV_NM1_t1 of the first reception normal signal RV_NM1_t0. That is, the signal DFEOUT1 output from DFE1 103 can be added to the first reception normal signal RV_NM1_t0, so that the first postamble component of the first reception normal signal RV_NM1_t0 can be removed.

[0072] When the first enabling signal EN1 is in the active state, DFE2 104 can adjust the driving capabilities of the first input transistors 701 and 702 (see Figure 10B ) to which the current reception value RV_NM1_t0 is applied according to the pattern of the second to Nth previous reception values RV_NM1_t2:tN of the first reception normal signal RV_NM1_t0, so as to remove the second to Nth postamble components of the first reception normal signal RV_NM1_t0. That is, the signal DFEOUT2 output from DFE2 104 can be added to the first reception normal signal RV_NM1_t0, so that the second to Nth postamble components of the first reception normal signal RV_NM1_t0 can be removed.

[0073] When the first enabling signal EN1 is in the deactivated state, DFE2 104 can adjust the first input transistors 701 and 702 (see Figure 10B)'s driving ability to remove the first to Nth postamble components of the first received normal signal RV_NM1_t0. That is, the signal DFEOUT2 output from the DFE2 104 can be added to the first received normal signal RV_NM1_t0, so that the first to Nth postamble components of the first received normal signal RV_NM1_t0 can be removed.

[0074] According to the input order of the first received normal signal RV_NM1_t0, the first signal storage unit 105 can store up to N first received normal signals RV_NM1_t0. Therefore, the first signal storage unit 105 can store the first to Nth previously received values RV_NM1_t1:tN of the first received normal signal RV_NM1_t0. That is, when the DFE1 103 and the DFE2 104 perform the equalization function, the first to Nth previously received values RV_NM1_t1:tN stored in the first signal storage unit 105 can be used.

[0075] Figure 3 is a diagram showing Figure 2 the first enable control unit 102 among the components of the first receiver operation unit 100 shown in

[0076] Referring to Figure 3 , the above Figure 2 shown first enable control unit 102 may include a first AND gate AND1 to a fourth AND gate AND4 and a first counter 1021.

[0077] Specifically, the first AND gate AND1 included in the first enable control unit 102 can generate a first counting clock signal OPC1 in response to a mode selection signal MD_SEL and a first reception mode signal RV_PAT1_t0. That is, in the training mode where the mode selection signal MD_SEL is set to a logic high level, the first AND gate AND1 can output the first reception mode signal RV_PAT1_t0 as the first counting clock signal OPC1. In the normal mode where the mode selection signal MD_SEL is set to a logic low level, the first AND gate AND1 can block the input of the first reception mode signal RV_PAT1_t0.

[0078] The first counter 1021 included in the first enable control unit 102 can increment a first count value CNT1<1:0> in response to the first counting clock signal OPC1. For example, the first counter 1021 can increment the first count value CNT1<1:0> according to the number of times the first counting clock signal OPC1 transitions from a logic low level to a logic high level.

[0079] The first counter 1021 may initialize the first count value CNT1<1:0> in response to entering the training mode. That is, the first counter 1021 may initialize the first count value CNT1<1:0> in response to the mode selection signal MD_SEL transitioning from a logic low level to a logic high level. For example, the first count value CNT1<1:0> may be initialized to "00".

[0080] The second AND gate AND2, the third AND gate AND3, and the fourth AND gate AND4 included in the first enable control unit 102 may hold the first enable signal EN1 at a logic low level substantially in response to the fact that the first count value CNT1<1:0> is less than a predetermined value, and may allow the first enable signal EN1 to transition from a logic low level to a logic high level in response to the fact that the first count value CNT1<1:0> is the predetermined value. For example, as Figure 7 shown, the first enable signal EN1 may transition from a logic low level to a logic high level in response to the fact that the first count value CNT1<1:0> is "11".

[0081] Figure 4 is a diagram showing the second receiver operation unit 200 among the components of the receiver circuit 1 according to an embodiment of the present disclosure. Referring to Figure 4 , the above Figure 1 shown second receiver operation unit 200 may include a second input unit 201, a second enable control unit 202, DFE3 203, DFE4 204, and a second signal storage unit 205. The second receiver operation unit 200, the second input unit 201, the second enable control unit 202, DFE3 203, DFE4 204, and the second signal storage unit 205 include all circuits, systems, software, firmware, and devices required for their respective operations and functions.

[0082] The second input unit 201 may receive, in the training mode, the second input pattern signal IN_PAT2_t0 applied through the second pad 206 as the second received pattern signal RV_PAT2_t0 according to the training reference level VRT.

[0083] The second input unit 201 may receive, in the normal mode entered after exiting the training mode, the second input normal signal IN_NM2_t0 applied through the second pad 206 as the second received normal signal RV_NM2_t0 according to the normal reference level VRN.

[0084] The second enable control unit 202 may determine whether to activate the second enable signal EN2 based on the result of confirming the value of the second received pattern signal RV_PAT2_t0 in the training mode.

[0085] More specifically, the second enabling control unit 202 can activate the second enabling signal EN2 in response to entering the training mode, and then can deactivate the second enabling signal EN2 during the period of entering the training mode in response to confirming that the value of the second reception mode signal RV_PAT2_t0 is a predetermined mode value. In this way, the second enabling signal EN2 that switches from the activated state to the deactivated state during the period of entering the training mode can continuously maintain the deactivated state until the second enabling signal EN2 enters the training mode again and switches to the activated state. That is to say, the second enabling signal EN2 that switches from the activated state to the deactivated state during the period of entering the training mode can continuously maintain the deactivated state during the period of entering the normal mode after the training mode.

[0086] The second enabling control unit 202 can activate the second enabling signal EN2 in response to entering the training mode, and then can continuously activate the second enabling signal EN2 during the period of entering the training mode in response to confirming that the value of the second reception mode signal RV_PAT2_t0 is not a predetermined mode value. That is to say, the second enabling signal EN2 that continuously maintains the activated state during the period of entering the training mode can continuously maintain the activated state even during the period of entering the normal mode after the training mode.

[0087] More specifically, the training mode can be divided into a first period and a second period.

[0088] In the first period of the training mode, the second input mode signal IN_PAT2_t0 can be set to the first mode and applied through the second pad 206.

[0089] In the second period of the training mode that enters after exiting the first period of the training mode, the second input mode signal IN_PAT2_t0 can be set to a second mode different from the first mode and applied through the second pad 206.

[0090] In summary, the second input mode signal IN_PAT2_t0 can be input in different mode forms within the first period and the second period included in the training mode.

[0091] Therefore, in the first period of the training mode, the second input unit 201 can receive the second input mode signal IN_PAT2_t0 having the first mode as the second reception mode signal RV_PAT2_t0 according to the first training reference level.

[0092] Therefore, in the second period of the training mode, the second input unit 201 can receive the second input mode signal IN_PAT2_t0 having the second mode as the second reception mode signal RV_PAT2_t0 according to a second training reference level different from the first training reference level.

[0093] According to an embodiment, the first pattern of the second input pattern signal IN_PAT2_t0 may be a pattern including at least one "1" value between a plurality of "0" values. When the first pattern is set in this way, the second input unit 201 may set the first training reference level to a predetermined level higher than the normal reference level VRN. That is, in the first period of the training mode, the second input unit 201 may determine the logic level of the second input pattern signal IN_PAT2_t0 through the first training reference level set to be a predetermined level higher than the normal reference level VRN, and receive the second input pattern signal IN_PAT2_t0 as the second received pattern signal RV_PAT2_t0.

[0094] The second pattern of the second input pattern signal IN_PAT2_t0 may be a pattern including at least one "0" value between a plurality of "1" values. When the second pattern is set in this way, the second input unit 201 may set the first training reference level to a predetermined level lower than the normal reference level VRN. That is, in the second period of the training mode, the second input unit 201 may determine the logic level of the second input pattern signal IN_PAT2_t0 through the second training reference level set to be a predetermined level lower than the normal reference level VRN, and receive the second input pattern signal IN_PAT2_t0 as the second received pattern signal RV_PAT2_t0.

[0095] In summary, the training reference level VRT may be set to either a level that is a predetermined level higher than the normal reference level VRN or a level that is a predetermined level lower than the normal reference level VRN according to the pattern of the second input pattern signal IN_PAT2_t0.

[0096] According to the operation of the second input unit 201 described above, the second enable control unit 202 may activate the second enable signal EN2 in response to entering the first period of the training mode, and deactivate the second enable signal EN2 when the second confirmation count reaches a predetermined count. The second confirmation count may be obtained by adding the count value of the number of "1" values included in the second received pattern signal RV_PAT2_t0 in the first period of the training mode and the count value of the number of "0" values included in the second received pattern signal RV_PAT2_t0 in the second period of the training mode. When the second confirmation count is different from the predetermined count, the second enable control unit 202 may continuously activate the second enable signal EN2.

[0097] DFE3 203 can operate during the activation period of the second enable signal EN2, and remove the first postamble component of the second received normal signal RV_NM2_t0 by directly calibrating the current received value RV_NM2_t0 based on the first previous received value RV_NM2_t1 of the second received normal signal RV_NM2_t0. That is, the signal DFEOUT3 output from DFE3 203 can be added to the second received normal signal RV_NM2_t0, so that the first postamble component of the second received normal signal RV_NM2_t0 can be removed.

[0098] When the second enable signal EN2 is in the active state, DFE4 204 can adjust the driving capabilities of the second input transistors 701 and 702 (see Figure 10B ) to which the current received value RV_NM2_t0 is applied according to the pattern of the second to Nth previous received values RV_NM2_t2:tN of the second received normal signal RV_NM2_t0, to remove the second to Nth postamble components of the second received normal signal RV_NM2_t0. That is, the signal DFEOUT4 output from DFE4 204 can be added to the second received normal signal RV_NM2_t0, so that the second to Nth postamble components of the second received normal signal RV_NM2_t0 can be removed.

[0099] When the second enable signal EN2 is in the deactivated state, DFE4 204 can adjust the driving capabilities of the second input transistors 701 and 702 (see Figure 10B ) to which the current received value RV_NM2_t0 is applied according to the pattern of the first to Nth previous received values RV_NM2_t1:tN of the second received normal signal RV_NM2_t0, to remove the first to Nth postamble components of the second received normal signal RV_NM2_t0. That is, the signal DFEOUT4 output from DFE4 204 can be added to the second received normal signal RV_NM2_t0, so that the first to Nth postamble components of the second received normal signal RV_NM2_t0 can be removed.

[0100] According to the input order of the second received normal signal RV_NM2_t0, the second signal storage unit 205 can store at most N second received normal signals RV_NM2_t0. Therefore, the second signal storage unit 205 can store the first to Nth previous received values RV_NM2_t1:tN of the second received normal signal RV_NM2_t0. That is, when DFE3 203 and DFE4 204 perform the equalization function, the first to Nth previous received values RV_NM1_t1:tN stored in the second signal storage unit 205 can be used.

[0101] Figure 5is a diagram showing Figure 2 the second enable control unit 202 among the components of the second receiver operation unit 200 shown in

[0102] Referring to Figure 5 above, Figure 4 the second enable control unit 202 shown in

[0103] may include a fifth AND gate AND5 to an eighth AND gate AND8 and a second counter 2021.

[0104] Specifically, the fifth AND gate AND5 included in the second enable control unit 202 may generate a second count clock signal OPC2 in response to a mode selection signal MD_SEL and a second reception mode signal RV_PAT2_t0. That is, in the training mode where the mode selection signal MD_SEL is set to a logic high level, the fifth AND gate AND5 may output the second reception mode signal RV_PAT2_t0 as the second count clock signal OPC2. In the normal mode where the mode selection signal MD_SEL is set to a logic low level, the fifth AND gate AND5 may block the input of the second reception mode signal RV_PAT2_t0.

[0105] The second counter 2021 included in the second enable control unit 202 may increment a second count value CNT2<1:0> in response to the second count clock signal OPC2. For example, the second counter 2021 may increment the second count value CNT2<1:0> according to the number of times the second count clock signal OPC2 changes from a logic low level to a logic high level.

[0106] The second counter 2021 may initialize the second count value CNT2<1:0> in response to entering the training mode. That is, the second counter 2021 may initialize the second count value CNT2<1:0> in response to the mode selection signal MD_SEL changing from a logic low level to a logic high level. For example, the second count value CNT2<1:0> may be initialized to "00". Figure 7

[0107] The sixth AND gate AND6, seventh AND gate AND7, and eighth AND gate AND8 included in the second enable control unit 202 may keep the second enable signal EN2 substantially at a logic low level in response to the fact that the second count value CNT2<1:0> is less than a predetermined value, and may allow the second enable signal EN2 to change from a logic low level to a logic high level in response to the fact that the second count value CNT2<1:0> is the predetermined value. For example, as shown, the second enable signal EN2 may change from a logic low level to a logic high level in response to the fact that the second count value CNT2<1:0> is "11".Figure 6 It is a diagram showing the first signal storage unit 105 or the second signal storage unit 205 among the components of the receiver circuit 1 according to an embodiment of the present disclosure.

[0108] Referring to Figure 6 above, Figure 2 the first signal storage unit 105 shown above or Figure 4 the second signal storage unit 205 shown above may include first to Nth signal storage latches LF1 to LFN.

[0109] The current received signal IN_t0 input to the first signal storage unit 105 or the second signal storage unit 205 may be stored in the first signal storage latch LF1 among the N signal storage latches LF1 to LFN. In this way, when the current received signal IN_t0 is input to the first signal storage latch LF1, the signal stored in the first signal storage latch LF1 may be sent to the second signal storage latch LF2 as the first previously received signal IN_t1 and may be stored. Similarly, when the first previously received signal IN_t1 is input to the second signal storage latch LF2, the signal stored in the second signal storage latch LF2 may be sent to the third signal storage latch LF3 as the second previously received signal IN_t2 and may be stored. In this way, a maximum of N received signals IN_t0:tN-1 may be stored in each of the N signal storage latches LF1 to LFN.

[0110] The current received signal IN_t0 may be the first received normal signal RV_NM1_t0 or the second received normal signal RV_NM2_t0. The first to Nth previously received signals IN_t1:tN may be the first to Nth previously received signals RV_NM1_t1:tN or RV_NM2_t1:tN of each of the first received normal signal RV_NM1_t0 or the second received normal signal RV_NM2_t0.

[0111] Figure 7 It is a diagram showing a training operation performed by the receiver circuit 1 according to an embodiment of the present disclosure

[0112] Referring to Figure 7 at time point S1, the mode selection signal MD_SEL may transition from a logic low level to a logic high level and may enter the training mode.

[0113] When entering the training mode at time point S1, the first count value CNT1<0:1> and the second count value CNT2<0:1> are both initialized, and thus, the first enable signal EN1 and the second enable signal EN2 are both activated to a logic low level. In this way, in response to the fact that the first enable signal EN1 and the second enable signal EN2 are both activated to a logic low level at time point S1, the DFE1 103 included in the first receiver operation unit 100 and the DFE3 203 included in the second receiver operation unit 200 can both be set to the enabled state.

[0114] Time points S1 to S3 can be the first period of the training mode.

[0115] During the first period of the training mode, each of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can be set to the first mode (when the first mode is a mode having at least one "1" value among a plurality of "0" values) and applied.

[0116] The logic level of each of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can be determined by a first training reference level VRT<1> that is a predetermined level VIHL higher than the normal reference level VRN. Then, it can be determined whether to increment the value of the first count value CNT1<0:1> or the second count value CNT2<0:1> based on whether the determined logic level has the first mode, that is, based on whether both the first received mode signal RV_PAT1_t0 and the second received mode signal RV_PAT2_t0 have the first mode.

[0117] In the drawings, during the first period of the training mode, both the first received mode signal RV_PAT1_t0 and the second received mode signal RV_PAT2_t0 are received in the first mode. Therefore, both the first count value CNT1<0:1> and the second count value CNT2<0:1> can be incremented from "00" to "01".

[0118] At time point S3, the first period of the training mode can end and, at the same time, the second period can be entered. Therefore, the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can change from the first mode to the second mode, and thus the first count value CNT1<0:1> and the second count value CNT2<0:1> can be incremented from "01" to "10" respectively.

[0119] In this way, the time point S3 at which the first period of the training mode ends and the second period starts simultaneously can be a preset time point. For example, a predetermined time after the time point S1 or a time point at which a switching repetition of a predetermined system clock (not shown) occurs can be set as the time point S3. Therefore, the operation in which the first count value CNT1<0:1> and the second count value CNT2<0:1> are respectively incremented from "01" to "10" due to the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 changing from the first mode to the second mode at the time point S3 can be an operation that has been reflected in the designs of the first receiver operation unit 100 and the second receiver operation unit 200.

[0120] The time period from the time point S3 to the time point S4 can be the second period of the training mode.

[0121] During the second period of the training mode, each of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can be set to the second mode (when the second mode is a mode having at least one "0" value among a plurality of "1" values) and applied.

[0122] The logic level of each of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can be determined by a second training reference level VRT<2> that is lower than a normal reference level VRN by a predetermined level VIHL. Then, it can be determined whether to increment the values of the first count value CNT1<0:1> and the second count value CNT2<0:1> according to whether the determined logic level has the second mode, that is, according to whether both the first reception mode signal RV_PAT1_t0 and the second reception mode signal RV_PAT2_t0 have the second mode.

[0123] In the drawings, during the second period of the training mode, both the first reception mode signal RV_PAT1_t0 and the second reception mode signal RV_PAT2_t0 are received in the second mode. Therefore, both the first count value CNT1<0:1> and the second count value CNT2<0:1> can be incremented from "10" to "11".

[0124] In this way, when the second period of the training mode ends at the time point S4, both the first count value CNT1<0:1> and the second count value CNT2<0:1> can be the predetermined value "11". Therefore, at the time point S4, both the first enable signal EN1 and the second enable signal EN2 can change from the logic low level in the active state to the logic high level in the deactivated state.

[0125] That is to say, in response to the fact that the first enable signal EN1 and the second enable signal EN2 are both deactivated to the logic high level at the time point S4, the DFE1 103 included in the first receiver operation unit 100 and the DFE3 203 included in the second receiver operation unit 200 can both be set to the disabled state.

[0126] Different from the accompanying drawings, in another embodiment, when in the first period of the training mode, the first reception mode signal RV_PAT1_t0 is received in the first mode and the second reception mode signal RV_PAT2_t0 is not received in the first mode, the first count value CNT1<0:1> can count up from "00" to "01", while the second count value CNT2<0:1> can basically remain "00". In this case, although both the first count value CNT1<0:1> and the second count value CNT2<0:1> count up at the time points S3 and S4, only the first count value CNT1<0:1> can be "11", while the second count value CNT2<0:1> can be "10". Therefore, the first enable signal EN1 can change from the logic low level in the active state to the logic high level in the deactivated state, while the second enable signal EN2 can basically remain the logic low level in the active state. That is to say, at the time point when the second period of the training mode ends, the DFE1 103 included in the first receiver operation unit 100 can be set to the disabled state, while the DFE3 203 included in the second receiver operation unit 200 can basically remain in the enabled state.

[0127] Figure 8 It is a diagram showing another example of the training operation performed by the receiver circuit 1 according to an embodiment of the present disclosure.

[0128] Refer to Figure 8 , at the time point S5, the mode selection signal MD_SEL can change from the logic low level to the logic high level and can enter the training mode.

[0129] When entering the training mode at the time point S5, the first count value CNT1<0:1> and the second count value CNT2<0:1> are both initialized, and thus, the first enable signal EN1 and the second enable signal EN2 are both activated to the logic low level. In this way, in response to the fact that the first enable signal EN1 and the second enable signal EN2 are both activated to the logic low level at the time point S5, the DFE1 103 included in the first receiver operation unit 100 and the DFE3 203 included in the second receiver operation unit 200 can both be set to the enabled state.

[0130] The time points S5 to S7 can be the first period of the training mode.

[0131] During the first period of the training mode, each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be set to a first mode (when the first mode is a mode having at least one "1" value among a plurality of "0" values) and applied.

[0132] The logic level of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be determined by a first training reference level VRT<1> that is a predetermined level VIHL higher than the normal reference level VRN. Then, it can be determined whether to increment the value of the first count value CNT1<0:1> or the second count value CNT2<0:1> according to whether the determined logic level has the first mode, that is, according to whether both the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 have the first mode.

[0133] In the drawings, during the first period of the training mode, both the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 are received in the first mode. Therefore, both the first count value CNT1<0:1> and the second count value CNT2<0:1> are incremented from "00" to "01".

[0134] At time point S7, the first period of the training mode can end and simultaneously the second period can be entered. Therefore, the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can change from the first mode to the second mode, and thus the first count value CNT1<0:1> and the second count value CNT2<0:1> can be incremented from "01" to "10" respectively.

[0135] In this way, the time point S7 at which the first period of the training mode ends and simultaneously the second period is entered can be a preset time point. For example, a predetermined time after time point S5 or a time point at which a switching of a predetermined system clock (not shown) repeats can be set as time point S7. Therefore, the operation of incrementing the first count value CNT1<0:1> and the second count value CNT2<0:1> from "01" to "10" respectively due to the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 changing from the first mode to the second mode at time point S7 may be an operation that has been reflected in the design of the first receiver operation unit 100 and the second receiver operation unit 200.

[0136] The time points from S7 to S8 can be the second period of the training mode.

[0137] During the second period of the training mode, each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be set to the second mode (when the second mode is a mode having at least one "0" value among a plurality of "1" values) and applied.

[0138] The logic level of each of the first input pattern signal IN_PAT1_t0 and the second input pattern signal IN_PAT2_t0 can be determined by a second training reference level VRT<2> that is lower than the normal reference level VRN by a predetermined level VIHL. Then, it can be determined whether to increment the values of the first count value CNT1<0:1> and the second count value CNT2<0:1> based on whether the determined logic level has the second mode, that is, based on whether both the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 have the second mode.

[0139] In the drawing, during the second period of the training mode, none of the first received pattern signal RV_PAT1_t0 and the second received pattern signal RV_PAT2_t0 are input in the second mode (not received). Therefore, neither the first count value CNT1<0:1> nor the second count value CNT2<0:1> can be incremented from "10" (not counting), and they basically remain "10".

[0140] In this way, when the second period of the training mode ends at time point S8, both the first count value CNT1<0:1> and the second count value CNT2<0:1> can be "10", which is different from the predetermined value. Therefore, at time point S8, both the first enable signal EN1 and the second enable signal EN2 can basically remain in the active state of logic low level.

[0141] That is, in response to the fact that both the first enable signal EN1 and the second enable signal EN2 are continuously activated to logic low level at time point S8, both the DFE1 103 included in the first receiver operation unit 100 and the DFE3 203 included in the second receiver operation unit 200 can be continuously set to the enabled state.

[0142] Unlike the drawings, in another embodiment, when in the second period of the training mode, the first received mode signal RV_PAT1_t0 is received in the second mode and the second received mode signal RV_PAT2_t0 is not received in the second mode, the first count value CNT1<0:1> can count up from "10" to "11", while the second count value CNT2<0:1> can remain substantially at "10". Accordingly, the first enable signal EN1 can transition from the logic low level of the active state to the logic high level of the deactivated state, while the second enable signal EN2 can remain substantially at the logic low level of the active state. That is, at the time point when the second period of the training mode ends, the DFE1 103 included in the first receiver operation unit 100 can be set to the disabled state, while the DFE3 203 included in the second receiver operation unit 200 can remain substantially in the enabled state.

[0143] Figure 9 is a diagram showing the order of training operations performed by the receiver circuit 1 according to an embodiment of the present disclosure.

[0144] Referring Figure 9 , when entering the training mode, the DFE1 103 and DFE2 104 included in the first receiver operation unit 100 and the DFE3 203 and DFE4 204 included in the second receiver operation unit 200 can all be set to the enabled state (K10).

[0145] Subsequently, the training reference level VRT can be set to a first training reference level VRT<1> that is a predetermined level VIHL higher than the normal reference level VRN (K20).

[0146] After K20, the first period of the training mode can be entered, and the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can be input (K30). Each of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can have a first mode, which can be a mode having at least one "1" value among a plurality of "0" values.

[0147] After K30, the first training reference level VRT<1> can be compared with the potential levels of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 (K40). Further, the logic levels of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can be determined. In addition, the first received mode signal RV_PAT1_t0 and the second received mode signal RV_PAT2_t0 can be generated according to the logic levels corresponding to the determination results (K40).

[0148] It is possible to confirm whether the first received mode signal RV_PAT1_t0 and the second received mode signal RV_PAT2_t0 generated in K40 each have the first mode (K50). In this case, since the first mode is a mode having at least one "1" value among a plurality of "0" values, it is possible to confirm whether the logic levels of the first received mode signal RN_PAT1_t0 and the second received mode signal RN_PAT2_t0 each switch between logic lows to logic highs in K50.

[0149] In K50, when the first received mode signal RN_PAT1_t0 or the second received mode signal RN_PAT2_t0 does not switch differently from the first mode (No in K50), it is possible to enable the DFE1 103 or the DFE3 203 (K60) set to the enabled state in K10.

[0150] When the first received mode signal RN_PAT1_t0 or the second received mode signal RN_PAT2_t0 in K50 switches according to the first mode (Yes in K50), the training reference level VRT can be set to a second training reference level VRT<2> lower than the normal reference level VRN by a predetermined level VIHL (K70).

[0151] After K70, it is possible to enter the first period of the training mode and input the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 (K80). Each of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 can have a second mode, which can be a mode having at least one "0" value among a plurality of "1" values.

[0152] After K80, it is possible to compare the second training reference level VRT<2> with the potential levels of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0 (K90). Further, it is possible to determine the logic levels of the first input mode signal IN_PAT1_t0 and the second input mode signal IN_PAT2_t0. Further, it is possible to generate the first received mode signal RV_PAT1_t0 and the second received mode signal RV_PAT2_t0 according to the logic levels corresponding to the determination results (K90).

[0153] It is possible to confirm whether the first received mode signal RV_PAT1_t0 and the second received mode signal RV_PAT2_t0 generated in K90 each have a second mode (K100). In this case, since the second mode is a mode having at least one "0" value among multiple "1" values, it is possible to confirm in K100 whether the logic levels of the first received mode signal RN_PAT1_t0 and the second received mode signal RN_PAT2_t0 each switch between logic highs to logic lows.

[0154] In K100, when the first received mode signal RN_PAT1_t0 or the second received mode signal RN_PAT2_t0 does not switch differently from the second mode (No in K100), the DFE1 103 or DFE3 203 set to the enabled state in K10 can be enabled (K110).

[0155] When the first received mode signal RN_PAT1_t0 or the second received mode signal RN_PAT2_t0 in K100 switches according to the second mode (Yes in K100), the DFE1 103 or DFE3 203 set to the enabled state in K10 can be disabled (K120).

[0156] According to an embodiment, in the above K50, the first received mode signal RN_PAT1_t0 may not switch differently from the first mode, while the second received mode signal RN_PAT2_t0 may switch according to the first mode. In this case, the DFE1 103 can be continuously maintained in the enabled state through K60, and operations corresponding to K70, K80, K90, K100, K110, and K120 can be performed only for the second received mode signal RN_PAT2_t0.

[0157] According to an embodiment, in the above K100, the second received mode signal RN_PAT2_t0 may not switch differently from the second mode, while the first received mode signal RN_PAT1_t0 may switch according to the second mode. In this case, the DFE3 203 can be continuously maintained in the enabled state through K110, while the DFE1 103 can be disabled through K120.

[0158] The above embodiments of the present disclosure are not limited by the above embodiments and the drawings, and it is obvious to those skilled in the art to which the present invention pertains that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention.

[0159] For example, the positions and types of the logic gates and transistors shown in the above embodiments should be implemented differently according to the polarities of the input signals. In addition, the embodiments can be combined to form additional embodiments.

Claims

1. A receiver circuit comprising: a first input unit receiving a first input mode signal as a first reception mode signal according to a training reference level, and receiving a first input normal signal as a first reception normal signal according to a normal reference level, wherein the first input mode signal is applied through a first pad in a training mode, and the first input normal signal is applied through the first pad in a normal mode after the training mode; a first enabling control unit, which determines whether to activate a first enabling signal according to a confirmation result of a value of the first receiving mode signal in the training mode; a first decision feedback equalizer that operates during an activation period of the first enable signal and removes a first post-signal component of the first reception normal signal by calibrating a current reception value based on a first previous reception value of the first reception normal signal; and A second decision feedback equalizer, when the first enable signal is in an activated state, removes the second to Nth postscript components of the first received normal signal by adjusting the driving capability of the first input transistor to which the current received value is applied according to a pattern of the second to Nth previous received values ​​of the first received normal signal, where N is a natural number of 2 or greater.

2. The receiver circuit according to claim 1, wherein: When the first enable signal is in a deactivated state, the second decision feedback equalizer removes the first to Nth post-signal components of the first received normal signal by adjusting the driving capability of the first input transistor to which the current received value is applied according to a pattern of the first to Nth previous received values ​​of the first received normal signal.

3. The receiver circuit according to claim 2, wherein: The first enable control unit activates the first enable signal in response to entering the training mode, and deactivates the first enable signal in response to confirming that a value of the first reception mode signal is a predetermined mode value during a period of entering the training mode.

4. The receiver circuit of claim 2, further comprising: a second input unit, receiving a second input mode signal as a second reception mode signal according to the training reference level, and receiving a second input normal signal as a second reception normal signal according to the normal reference level, wherein the second input mode signal is applied through a second pad in the training mode, and the second input normal signal is applied through the second pad in the normal mode; a second enabling control unit, determining whether to activate a second enabling signal according to a confirmation result of a value of the second receiving mode signal in the training mode; a third decision feedback equalizer that operates during an activation period of the second enable signal and removes a first post-signal component of the second reception normal signal by calibrating a current reception value based on a first previous reception value of the second reception normal signal; and A fourth decision feedback equalizer, when the second enable signal is in an activated state, removes the second to Nth post-signal components of the second received normal signal by adjusting the driving capability of the second input transistor to which the current received value is applied according to a pattern of the second to Nth previous received values ​​of the second received normal signal.

5. The receiver circuit of claim 4, wherein: When the second enable signal is in a deactivated state, the fourth decision feedback equalizer removes the first to Nth post-signal components of the second received normal signal by adjusting the driving capability of the second input transistor to which the current received value is applied according to a pattern of the first to Nth previous received values ​​of the second received normal signal.

6. The receiver circuit of claim 5, wherein: The second enable control unit activates the second enable signal in response to entering the training mode, and deactivates the second enable signal in response to confirming that a value of the second reception mode signal is a predetermined mode value during a period of entering the training mode.

7. The receiver circuit according to claim 5, wherein: The first input mode signal and the second input mode signal are set to a first mode and applied in parallel through the first pad and the second pad in a first period of the training mode, and are set to a second mode different from the first mode and applied in parallel through the first pad and the second pad in a subsequent second period of the training mode, In a first period of the training mode, the first input unit and the second input unit receive the first input mode signal and the second input mode signal as the first receiving mode signal and the second receiving mode signal according to a first training reference level, respectively; and In a second period of the training mode, the first input unit and the second input unit receive the first input mode signal and the second input mode signal, respectively, as the first reception mode signal and the second reception mode signal according to a second training reference level different from the first training reference level.

8. The receiver circuit of claim 7, wherein: The first pattern includes at least one "1" value between a plurality of "0" values, The second mode includes at least one "0" value between a plurality of "1" values, The first training reference level has a level higher than the normal reference level by a predetermined level, and The second training reference level has a level lower than the normal reference level by the predetermined level.

9. The receiver circuit of claim 8, wherein: The first enable control unit activates the first enable signal in response to entering the training mode, and deactivates the first enable signal when the first confirmation number is a predetermined number, and The first confirmation number is obtained by adding a count value of the number of “1” values ​​included in the first reception pattern signal in a first period of the training pattern and a count value of the number of “0” values ​​included in the first reception pattern signal in a second period of the training pattern.

10. The receiver circuit of claim 9, wherein: The second enable control unit activates the second enable signal in response to entering the training mode, and deactivates the second enable signal when the second confirmation number is a predetermined number, and The second confirmation number is obtained by adding a count value of the number of “1” values ​​included in the second reception pattern signal in the first period of the training pattern and a count value of the number of “0” values ​​included in the second reception pattern signal in the second period of the training pattern.

11. A method of operating a receiver circuit, comprising: a first receiving operation, receiving a first input mode signal as a first receiving mode signal according to a training reference level, and receiving a first input normal signal as a first receiving normal signal according to a normal reference level, wherein the first input mode signal is applied through a first pad in a training mode, and the first input normal signal is applied through the first pad in a normal mode after the training mode; a first enable control operation, determining whether to activate a first enable signal according to a result of confirming the value of the first receiving mode signal; and When the first enable signal is in an activated state in the normal mode, a first post-signal component of the first reception normal signal is removed by calibrating a current reception value based on a first previous reception value of the first reception normal signal, and second to Nth post-signal components of the first reception normal signal are removed by adjusting a driving capability of a first input transistor to which the current reception value is applied according to a pattern of second to Nth previous reception values, where N is a natural number of 2 or greater.

12. The operating method according to claim 11, further comprising: When the first enable signal is in a deactivated state in the normal mode, the first to Nth postscript components of the first received normal signal are removed by adjusting the driving capability of the first input transistor to which the current received value is applied according to a pattern of the first to Nth previous received values ​​of the first received normal signal.

13. The operating method according to claim 12, wherein the first enabling control operation comprises: activating the first enable signal in response to entering the training mode, deactivating the first enable signal in response to confirming that the value of the first receive mode signal is a predetermined mode value during a period of entering the training mode; as well as The activation state of the first enable signal is maintained in response to confirming that the value of the first reception mode signal is not the predetermined mode value during the period of entering the training mode.

14. The operating method according to claim 12, further comprising: a second receiving operation, receiving a second input mode signal as a second receiving mode signal according to the training reference level, and receiving a second input normal signal as a second receiving normal signal according to the normal reference level, wherein the second input mode signal is applied through a second pad in the training mode, and the second input normal signal is applied through the second pad in the normal mode; a second enable control operation, determining whether to activate a second enable signal according to a result of confirming the value of the second receiving mode signal; and When the second enable signal is in an activated state in the normal mode, a first post-signal component of the second reception normal signal is removed by calibrating a current reception value based on a first previous reception value of the second reception normal signal, and second to Nth post-signal components of the second reception normal signal are removed by adjusting a driving capability of a second input transistor to which the current reception value is applied according to a pattern of second to Nth previous reception values.

15. The operating method according to claim 14, further comprising: When the second enable signal is in a deactivated state in the normal mode, the first to Nth postscript components of the second received normal signal are removed by adjusting the driving capability of the second input transistor to which the current received value is applied according to a pattern of the first to Nth previous received values ​​of the second received normal signal.

16. The operating method according to claim 15, wherein: The second enabling control operation includes: activating the second enable signal in response to entering the training mode, deactivating the second enable signal in response to confirming that the value of the second reception mode signal is the predetermined mode value during a period of entering the training mode; and The activated state of the second enable signal is maintained in response to confirming that the value of the second reception mode signal is not the predetermined mode value during the period of entering the training mode.

17. The operating method according to claim 15, wherein: The first input mode signal and the second input mode signal are set to a first mode and applied in parallel through the first pad and the second pad in a first period of the training mode, and are set to a second mode different from the first mode and applied in parallel through the first pad and the second pad in a subsequent second period of the training mode, The first receiving operation: receiving the first input mode signal as the first receiving mode signal according to the first training reference level during a first period of the training mode, and receiving the first input mode signal as the first reception mode signal according to a second training reference level different from the first training reference level during a second period of the training mode, The second receiving operation includes: receiving the second input mode signal as the second receiving mode signal according to the first training reference level during a first period of the training mode, and In a second period of the training mode, the second input mode signal is received as the second receiving mode signal according to the second training reference level.

18. The operating method according to claim 17, wherein: The first pattern includes at least one "1" value between a plurality of "0" values, The second mode includes at least one "0" value between a plurality of "1" values, The first training reference level has a level higher than the normal reference level by a predetermined level, and The second training reference level has a level lower than the normal reference level by the predetermined level.

19. The operating method according to claim 18, wherein the first enabling control operation comprises: activating the first enable signal in response to entering the training mode; a first counting operation of counting the number of "1" values ​​included in the first reception mode signal in a first period of the training mode; a second counting operation of counting the number of “0” values ​​included in the first reception mode signal in a second period of the training mode; When a first confirmed number obtained by adding the values ​​counted in the first counting operation and the second counting operation is a predetermined number, deactivating the first enable signal; as well as When the first confirmed number is different from the predetermined number, the activation state of the first enable signal is maintained.

20. The operating method according to claim 19, wherein the second enabling control operation comprises: activating the second enable signal in response to entering the training mode, a third counting operation of counting the number of "1" values ​​included in the second reception mode signal in the first period of the training mode; a fourth counting operation of counting the number of “0” values ​​included in the second reception mode signal in the second period of the training mode; When a second confirmed number obtained by adding the values ​​counted in the third counting operation and the fourth counting operation is a predetermined number, deactivating the second enable signal; as well as When the second confirmed number is different from the predetermined number, the activation state of the second enable signal is maintained.

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