Circuit board and method of manufacturing circuit board

Abstract

The invention provides a circuit board and a method of manufacturing the same. The circuit board includes: an insulating layer having a first surface and a second surface opposite to each other; and a first connection pad having a first portion embedded in the insulating layer and at least partially exposed from the first surface of the insulating layer and a second portion closer to the second surface than the first portion. A first width of the first portion in a direction parallel to the first surface is different from a second width of the second portion in the direction parallel to the first surface.

Description

Technical Field

[0001] The present disclosure relates to a circuit board and a method of manufacturing a circuit board. Background Art

[0002] In a semiconductor package manufacturing process using a lead frame, a chip attachment process (mounting a semiconductor chip on the lead frame) is followed by a wire bonding process that electrically connects the semiconductor chip and the lead frame with a metal wire. The wire bonding process is performed by, for example, a process of using ultrasonic waves to cause a local fusion phenomenon to bond the metal lead to the metal pad of the semiconductor chip.

[0003] With the development of the electronics industry and the acceleration of miniaturization and high performance of electronic devices, the size of semiconductor packages also tends to become smaller. In response to the miniaturization of package products, the size of bonding pads on a printed circuit board (PCB) for wire bonding is also decreasing. On the other hand, in order to reduce the bonding defect rate during the wire bonding process, it is necessary to increase the width of the bonding pads when manufacturing a printed circuit board (PCB). Summary of the Invention

[0004] The present disclosure aims to provide a circuit board and a method of manufacturing a circuit board, the circuit board realizing bonding pads with a fine pitch pattern (for mounting wire bonding chips) and ensuring the width of the bonding pads on which wire bonding is performed.

[0005] The object of the present disclosure is not limited to the above object, but can be extended in various ways within the scope of the concept and field of the present disclosure.

[0006] An embodiment of the present disclosure provides a circuit board, including: an insulating layer having a first surface and a second surface opposite to each other; and a first connection pad having a first portion and a second portion, the first portion being embedded in the insulating layer and at least partially exposed from the first surface of the insulating layer, the second portion being closer to the second surface than the first portion. The first width of the first portion in a direction parallel to the first surface is different from the second width of the second portion in the direction parallel to the first surface.

[0007] The first width may be greater than the second width.

[0008] The first portion and the second portion are formed in a stepped structure.

[0009] The circuit board may further include: a protective layer provided on the first surface of the insulating layer and having an opening to expose the first connection pad.

[0010] The circuit board may further include: a first circuit wiring embedded in the insulating layer and covered by the protective layer. The thickness of the first circuit wiring in a direction perpendicular to the first surface may be greater than the thickness of the first portion of the first connection pad in the direction perpendicular to the first surface.

[0011] The circuit board may further include: a conductive layer disposed on the first connection pad.

[0012] The conductive layer may be disposed on an exposed portion of the first connection pad.

[0013] The conductive layer may protrude from the first surface of the insulating layer.

[0014] The width of the conductive layer in a direction parallel to the first surface may be greater than the second width of the second portion of the first connection pad.

[0015] The width of the conductive layer in a direction parallel to the first surface may be greater than or equal to the first width of the first portion of the first connection pad.

[0016] The conductive layer may include a gold (Au) plating layer.

[0017] The first connection pad may include copper (Cu).

[0018] The first connection pad may be a bonding finger disposed in a bonding finger region.

[0019] The circuit board may further include: a second connection pad disposed on the second surface of the insulating layer.

[0020] The insulating layer may include a plurality of insulating layers, and the circuit board may further include a plurality of circuit layers disposed in and / or on the plurality of insulating layers.

[0021] Another embodiment of the present disclosure provides a method for manufacturing a circuit board, including: forming a first portion of a first connection pad on a seed layer, the first connection pad including a first metal; forming a second portion of the first connection pad on the first portion by patterning a plating resist covering the first portion and plating with the first metal, the second portion having a different width from the first portion; and forming an insulating layer to cover the first portion and the second portion.

[0022] The first width of the first portion in a direction parallel to an interface between the first portion and the second portion may be formed to be greater than the second width of the second portion in the direction parallel to the interface between the first portion and the second portion.

[0023] The method may further include: removing the seed layer to expose at least a portion of the first portion from the insulating layer.

[0024] The method may further include: forming a conductive layer on the first portion exposed from the insulating layer.

[0025] The method may further include: forming a protective layer on the insulating layer, the protective layer having an opening to expose the conductive layer.

[0026] According to an embodiment, a circuit board can implement bonding pads for mounting wire-bonded chips in a fine pitch pattern while ensuring a wide width of the bonding pads connected to bonding wires. By ensuring the width of the bonding pads, bonding pad omission defects can be improved during packaging. In addition, the width of the pads embedded in the insulating layer is designed to be relatively narrow to increase the design freedom and correspond to bonding fingers with a fine pitch caused by the reduction in package size.

[0027] According to an embodiment of a method for manufacturing a circuit board, by manufacturing the circuit board using an embedded trace substrate (ETS) method, it is possible to ensure the width of the connection surface of the bonding wires while maintaining the bonding pads in a fine pitch pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A cross-sectional view of a circuit board according to an embodiment is shown.

[0029] Figures 2 to 15 Shown is for manufacturing Figure 1 A process cross-sectional view of a method for manufacturing the shown circuit board is shown. DETAILED DESCRIPTION

[0030] In the following detailed description, only certain embodiments of the present disclosure are shown and described by way of illustration. The drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, like reference numerals denote like elements. In the drawings, some of the components are exaggerated, omitted, or shown briefly, and the dimensions of each component do not reflect the actual size.

[0031] The drawings are provided merely to allow for an easy understanding of the embodiments disclosed in this specification and should not be construed as limiting the spirit disclosed in this specification, and it should be understood that the present disclosure includes all variations, equivalents, and alternatives without departing from the scope and spirit of the present disclosure.

[0032] Terms including ordinal numbers such as "first", "second", etc. will only be used to describe various components and should not be construed as limiting these components. These terms are only used to distinguish one component from another.

[0033] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements. The terms “on” or “above” mean located on or below the target portion and do not necessarily mean located on the upper side of the target portion based on the direction of gravity.

[0034] It should be understood that the terms “comprises,” “comprising,” “has,” or “constitutes” indicate the presence of the features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof. Unless explicitly described to the contrary, the terms “comprises,” “comprising,” “has,” or “constitutes” will be understood to imply the inclusion of the stated elements without excluding any other elements.

[0035] The phrase “in a plan view” or “on a plane” means observing the target portion from above, and the phrase “in a cross-sectional view” or “on a cross-section” means observing the cross-section formed by vertically cutting the target portion from the side.

[0036] Throughout the specification, when a component is described as being “connected” to another component, the component can be “directly connected” to the other component, can be “connected” to the other component through a third component, or can be physically and / or electrically connected to the other component, and the component and the other component can be integrated while being represented by different names according to their positions or functions.

[0037] Figure 1 A cross-sectional view of a circuit board according to an embodiment is shown.

[0038] Referring to Figure 1 , the circuit board 100 may include an insulating layer 110 and a first connection pad 121 and a first circuit wiring 122 embedded in the insulating layer 110. The insulating layer 110, the first connection pad 121, and the first circuit wiring 122 may constitute an embedded pattern substrate. The circuit board 100 is a printed circuit board (PCB) and can be used for semiconductor packages.

[0039] The insulating layer 110 may have a first surface 110a and a second surface 110b opposite to each other and may include a resin insulating layer. The insulating layer 110 can use a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin prepared by impregnating a reinforcing material such as glass fiber or inorganic filler in a thermosetting resin or a thermoplastic resin. For example, the insulating layer 110 may include a prepreg, or the insulating layer 110 may include a thermosetting resin and / or a photocurable resin, and is not limited thereto.

[0040] The first connection pad 121 may be embedded in the insulating layer 110, and the upper and lower portions of the first connection pad 121 have different widths. The first connection pad 121 embedded in the insulating layer 110 may include a first portion 121a and a second portion 121b. The first portion 121a is disposed close to the first surface 110a of the insulating layer 110, and the second portion 121b is disposed closer to the second surface 110b of the insulating layer 110 than the first portion 121a. At least a part of the first portion 121a may be exposed from the first surface 110a of the insulating layer 110.

[0041] A first width W1 of the first portion 121a in a direction parallel to the first surface 110a of the insulating layer 110 may be greater than a second width W2 of the second portion 121b in a direction parallel to the first surface 110a of the insulating layer 110. In other words, the first width W1 of the first portion 121a in a direction parallel to the interface between the first portion 121a and the second portion 121b may be greater than the second width W2 of the second portion 121b in a direction parallel to the interface between the first portion 121a and the second portion 121b. The first width W1 of the first portion 121a exposed from the insulating layer 110 may be greater than the second width W2 of the second portion 121b. In this case, the first portion 121a and the second portion 121b of the first connection pad 121 may be formed in a stepped structure. Therefore, the first connection pad 121 embedded in the insulating layer 110 may implement a bonding pad with a fine pitch, and a wide surface area of the bonding pad on which wire bonding is performed may be ensured, thereby reducing bonding errors (defects).

[0042] The first conductive layer 141 may be stacked on the first connection pad 121. The first conductive layer 141 may be disposed on the first portion 121a of the first connection pad 121 exposed from the insulating layer 110. The exposed first portion 121a of the first connection pad 121 and the first surface 110a of the insulating layer 110 may be formed in the same plane. For example, the upper surface of the exposed first portion 121a of the first connection pad 121 and the first surface 110a of the insulating layer 110 may be at the same height, or the exposed first portion 121a of the first connection pad 121 may be formed to be slightly recessed in the first surface 110a of the insulating layer 110. The first conductive layer 141 stacked on the first connection pad 121 may at least partially protrude from the first surface 110a of the insulating layer 110.

[0043] The first connection pad 121 and the first circuit wiring 122 may include a copper (Cu) layer. The first conductive layer 141 may include a nickel (Ni) plating layer and a gold (Au) plating layer. The first conductive layer 141 may be formed by plating a nickel plating layer on the first connection pad 121 and plating a gold plating layer on the nickel plating layer.

[0044] In this embodiment, the first conductive layer 141 may be formed by an electroplating method. That is, the nickel plating layer and the gold plating layer may be formed by applying an electric current to the first connection pad 121 including copper to form a nickel metal film and a gold metal film. For another example, the first conductive layer 141 may be formed by an electroless plating method.

[0045] In a cross-section in the thickness direction of the circuit board 100, the width of the first conductive layer 141 may be greater than or equal to the width of the first connection pad 121. At a portion where the first conductive layer 141 is in contact with the first connection pad 121, the width of the first conductive layer 141 may be greater than or equal to the width of the first connection pad 121.

[0046] The first connection pad 121 may be a bonding finger provided in the bonding finger region, and a plurality of first connection pads 121 may constitute a plurality of bonding fingers. That is, the first connection pad 121 may be constructed with a bonding finger for a wire bonding pad, and when wire-bonded to a semiconductor chip lead, the wire may be bonded to the bonding finger.

[0047] The first protective layer 131 may be provided on the first surface 110a of the insulating layer 110. The first protective layer 131 may be open to expose the first connection pad 121. The first protective layer 131 may be stacked with the first circuit wiring 122 provided in the insulating layer 110 and may cover the first circuit wiring 122. The first protective layer 131 may be formed using a solder resist layer.

[0048] The thickness of the first circuit wiring 122 in a direction perpendicular to the first surface 110a of the insulating layer 110 may be greater than the thickness of the first portion 121a of the first connection pad 121 in a direction perpendicular to the first surface 110a of the insulating layer 110. The total thickness of the first connection pad 121 including the first portion 121a and the second portion 121b may be equal to the thickness of the first circuit wiring 122.

[0049] The second connection pad 125 and the second circuit wiring 126 may be further formed on the second surface 110b of the insulating layer 110. The second connection pad 125 and the second circuit wiring 126 may protrude from the second surface 110b of the insulating layer 110 and may be connected to the first circuit wiring 122 through a via 123. The second protective layer 135 may be formed around the second connection pad 125 on the second surface 110b of the insulating layer 110. The second protective layer 135 may be stacked with the second circuit wiring 126 and may cover the second circuit wiring 126, and may be formed using a solder resist layer.

[0050] The second connection pad 125 and the second circuit wiring 126 may include a copper (Cu) layer, and the second conductive layer 145 may be formed on the second connection pad 125. The second conductive layer 145 may include a nickel (Ni) plating layer and a gold (Au) plating layer. The nickel plating layer may be formed on the second connection pad 125, and the gold plating layer may be formed on the nickel plating layer.

[0051] Figure 1 The illustrated circuit board 100 shows a structure having connection pads 121 and 125 on respective surfaces of the insulating layer 110. Optionally, according to some aspects of the present disclosure, the second connection pad 125 provided on the second surface 110b of the insulating layer 110 may be omitted. The insulating layer 110 may include a plurality of insulating layers, and the plurality of insulating layers may each include a plurality of circuit layers. Accordingly, the circuit layers may be respectively formed on at least three insulating layers, and vias may extend in the thickness direction of the insulating layer to connect the circuit layers.

[0052] Figures 2 to 15 Illustrated is a process cross-sectional view of a method for manufacturing Figure 1 the illustrated circuit board. Reference will now be made to Figures 2 to 15 as well as Figure 1 to describe a method for manufacturing a circuit board.

[0053] Referring to Figures 2 to 5 , a first seed layer 71 is formed on at least one surface of a carrier substrate 60, and later, according to a circuit formation process, a first portion 121a of the first connection pad 121 is formed on the first seed layer 71. The carrier substrate 60 may represent a substrate in which a copper foil layer 62 is stacked on respective sides of an insulating substrate 61, and the first seed layer 71 may be separated from the copper foil layer 62 (see Figure 2 ). The first resist pattern 83 may be formed by exposing and developing a resist on the carrier substrate 60. The first resist pattern 83 may be formed by removing only a portion that will form the first portion 121a of the first connection pad 121. The first portion 121a of the first connection pad 121 may be formed by plating a conductive metal on a portion of the first seed layer 71 exposed through the openings of the patterned first resist pattern 83 (see Figure 4 ). When forming the first portion 121a of the first connection pad 121, the first resist pattern 83 is removed (see Figure 5 ).

[0054] Any material used as a conductive metal for a circuit in the field of circuit boards may be used for the first seed layer 71, and copper (Cu) is typically used. The first portion 121a of the first connection pad 121 may be connected to the first seed layer 71 on the carrier substrate 60 and may include the same type of metal as the first seed layer 71. For example, the first seed layer 71 and the first portion 121a of the first connection pad 121 may include copper (Cu).

[0055] This embodiment shows the following: A first portion 121a of the first connection pad 121 is formed on both surfaces of the carrier substrate 60, and according to some aspects of the present disclosure, the first portion 121a of the first connection pad 121 may also be formed only on one surface of the carrier substrate 60.

[0056] Referring to Figure 6 and Figure 7 , a second resist pattern 85 may be formed on the carrier substrate 60 on which the first portion 121a of the first connection pad 121 is formed. The second resist pattern 85 may be formed by exposing and developing the resist formed on the carrier substrate 60. The second resist pattern 85 may be formed by removing only the portion where the second portion 121b of the first connection pad 121 will be formed. The second portion 121b of the first connection pad 121 may be formed by plating a conductive metal on the first portion 121a of the first connection pad 121 exposed through the opening of the patterned second resist pattern 85 (see Figure 6 ). The second resist pattern 85 may also open in the portion of the first seed layer 71 where the first portion 121a of the first connection pad 121 is not formed. A conductive metal may be plated on the first seed layer 71, and the first circuit wiring 122 may be formed on this portion. After forming the first circuit wiring 122 and the second portion 121b of the first connection pad 121, the second resist pattern 85 is removed (see Figure 7 ).

[0057] Referring to Figure 8 , the insulating layer 110A is stacked to embed the first connection pad 121 therein, and a second seed layer 73 is formed on the insulating layer 110A. The second seed layer 73 may be provided to form the second connection pad 125 and the second circuit wiring 126. Any type of conductive metal may be used without limitation, and copper (Cu) is generally used.

[0058] The insulating layer 110A may include a resin insulating layer. The insulating layer 110A may use a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin prepared by impregnating a reinforcing material such as glass fiber or inorganic filler in a thermosetting resin or a thermoplastic resin. For example, the insulating layer 110A may include a prepreg, or may include a thermosetting resin and / or a photocurable resin, and the insulating layer 110A is not limited thereto.

[0059] Referring to Figures 9 to 12, formed according to a circuit formation process, a wiring pattern layer 125A for forming a second connection pad 125 and a second circuit wiring 126 can be formed on an insulating layer 110 (corresponding to the above 110A). The wiring pattern layer 125A can include the same type of material as the first circuit wiring 122 and the first connection pad 121. In this case, in order to form a via 123 for connecting the first circuit wiring 122 and the wiring pattern layer 125A, the insulating layer 110 can be partially etched to expose a part of the first circuit wiring 122 (see Figure 9 ). A patterned third resist pattern 87 can be formed on the second seed layer 73 (see Figure 10 ). The part of the third resist pattern 87 on which the wiring pattern layer 125A will be formed can be removed, and the second seed layer 73 can be exposed. A plating process can be performed on the exposed parts of the second seed layer 73 and the first circuit wiring 122 to form the wiring pattern layer 125A (see Figure 11 ). After forming the wiring pattern layer 125A, the third resist pattern 87 can be removed, and the embedded pattern substrate can be completed on the corresponding side of the carrier substrate 60 (see Figure 12 ).

[0060] According to the illustrated embodiment, each embedded pattern substrate is shown to include an insulating layer 110 and the first circuit wiring 122 and the second circuit wiring 126 as two metal layers, and is not limited thereto. It can include a larger number of stacked insulating layers and stacked wiring pattern layers, which fall within the scope of the present disclosure.

[0061] Referring to Figure 13 , an embedded pattern substrate is provided by separating the first seed layer 71 from the carrier substrate 60. A pair of embedded pattern substrates can be obtained by separating the first seed layer 71 formed on the corresponding surface of the carrier substrate 60 from the copper foil layer 62, and separate processes can be applied to the pair of embedded pattern substrates respectively.

[0062] Referring to Figure 14 , for Figure 13The embedded pattern substrate obtained therein is subjected to soft etching to remove a part of the second seed layer 73 and the first seed layer 71. When a part of the second seed layer 73 and the first seed layer 71 are removed, a first connection pad 121 and a first circuit wiring 122 are formed which are embedded in the insulating layer 110 and exposed toward the first surface 110a. The wiring pattern layers 125A provided on the second surface 110b of the insulating layer 110 are separated from each other to form second connection pads 125 and second circuit wirings 126. By removing the first seed layer 71, a part of a first portion 121a of the first connection pad 121 can be exposed from the insulating layer 110. In the process for removing the first seed layer 71, the surfaces of the first connection pad 121 and the first circuit wiring 122 exposed from the insulating layer 110 can be partially etched, for example, can be recessed in the surface of the insulating layer 110.

[0063] Referring to Figure 15 , on Figure 14 the corresponding surfaces of the embedded pattern substrate obtained therein, a first protective layer 131 and a second protective layer 135 are formed to cover the insulating layer 110 and the circuit wirings 122 and 126. The first protective layer 131 and the second protective layer 135 can include solder resist layers. The first protective layer 131 can be patterned such that the first connection pad 121 can be exposed from the first surface 110a of the insulating layer 110. The second protective layer 135 can be open in the second surface 110b of the insulating layer 110 on which the second connection pads 125 are provided to cover the second circuit wirings 126 and expose the second connection pads 125.

[0064] Referring to Figure 1 , a first conductive layer 141 and a second conductive layer 145 can be formed on the first connection pad 121 and the second connection pad 125 exposed by the protective layers 131 and 135 on the embedded pattern substrate obtained through Figure 15 therein. The first conductive layer 141 and the second conductive layer 145 can be formed by an electroplating method. A nickel plating layer and a gold plating layer can be formed by applying current to the first connection pad 121 and the second connection pad 125 including copper to form a nickel metal film and a gold metal film. Optionally, the first conductive layer 141 and the second conductive layer 145 can be formed by an electroless plating method.

[0065] Although the present invention has been described in connection with what are presently considered to be practical examples, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A circuit board, comprising: an insulating layer having a first surface and a second surface opposite to each other; as well as a first connection pad having a first portion and a second portion, the first portion being embedded in the insulating layer and at least partially exposed from the first surface of the insulating layer, the second portion being closer to the second surface than the first portion, A first width of the first portion in a direction parallel to the first surface is different from a second width of the second portion in the direction parallel to the first surface.

2. The circuit board according to claim 1, wherein: The first width is greater than the second width.

3. The circuit board according to claim 1, wherein: The first portion and the second portion are formed into a stepped structure.

4. The circuit board according to claim 1, further comprising: A protection layer is disposed on the first surface of the insulating layer and has an opening to expose the first connection pad.

5. The circuit board according to claim 4, further comprising: a first circuit wiring, embedded in the insulating layer and covered by the protective layer, The thickness of the first circuit wiring in a direction perpendicular to the first surface is greater than the thickness of the first portion of the first connecting pad in the direction perpendicular to the first surface.

6. The circuit board according to claim 1, further comprising: The conductive layer is disposed on the first connecting pad.

7. The circuit board according to claim 6, wherein: The conductive layer is disposed on the exposed portion of the first connection pad.

8. The circuit board according to claim 6, wherein: The conductive layer protrudes from the first surface of the insulating layer.

9. The circuit board according to claim 6, wherein: A width of the conductive layer in the direction parallel to the first surface is greater than the second width of the second portion of the first connection pad.

10. The circuit board according to claim 6, wherein: A width of the conductive layer in the direction parallel to the first surface is greater than or equal to the first width of the first portion of the first connecting pad.

11. The circuit board according to claim 6, wherein: The conductive layer includes a gold plated layer.

12. The circuit board according to claim 1, wherein: The first connection pad comprises copper.

13. The circuit board according to claim 1, wherein: The first connection pad is a bonding finger disposed in a bonding finger region.

14. The circuit board according to claim 1, further comprising: A second connecting pad is disposed on the second surface of the insulating layer.

15. The circuit board according to claim 1, wherein: The insulating layer includes a plurality of insulating layers, and The circuit board further includes a plurality of circuit layers disposed in and / or on the plurality of insulating layers.

16. A method for manufacturing a circuit board, comprising: forming a first portion of a first connection pad on the seed layer, the first connection pad comprising a first metal; forming a second portion of the first connection pad on the first portion by patterning a plating resist covering the first portion and plating with the first metal, the second portion having a different width from the first portion; as well as An insulating layer is formed to cover the first portion and the second portion.

17. The method according to claim 16, wherein: A first width of the first portion in a direction parallel to an interface between the first portion and the second portion is formed to be greater than a second width of the second portion in the direction parallel to the interface between the first portion and the second portion.

18. The method according to claim 16, further comprising: The seed layer is removed to expose at least a portion of the first portion from the insulating layer.

19. The method according to claim 18, further comprising: A conductive layer is formed on the first portion exposed from the insulating layer.

20. The method according to claim 19, further comprising: A protection layer is formed on the insulating layer, the protection layer having an opening to expose the conductive layer.

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