Memory element with improved p-n junction

Abstract

The present disclosure provides a memory element having an improved P-N junction. The memory device includes: a semiconductor substrate having a first surface and defining an active region below the first surface; a gate structure adjacent to the active region and recessed from the first surface to the semiconductor substrate; a doped member extending into the semiconductor substrate and surrounded by the active region; a conductive layer including a first portion extending from the first surface into the semiconductor substrate, and a second portion disposed over the doped member and coupled to the first portion; a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active region of the semiconductor substrate; a first contact disposed over the conductive layer and surrounded by a first dielectric layer; and a conductive pillar disposed over the first contact.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. patent application No. 18 / 531,966 (i.e., the priority date is "December 7, 2023"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a memory element and a manufacturing method thereof, and more particularly, to a memory element having an insulating layer and a conductive layer corresponding to the insulating layer to form a channel PN junction and a manufacturing method thereof. Background Art

[0004] Dynamic random access memory (DRAM) is a semiconductor configuration used to store bits of data in individual capacitors within an integrated circuit (IC). DRAM is typically formed as a trench capacitor DRAM cell. Advanced methods of fabricating buried gate electrodes involve constructing the gate electrode and word line of a transistor in a trench in the active area (AA) that includes a shallow trench isolation (STI) structure.

[0005] Over the past few decades, as semiconductor manufacturing technology has continued to improve, the size of electronic components has also shrunk accordingly. As the size of the PN junction is reduced to a few nanometers in length, undesired conduction within the PN junction may significantly reduce the performance of DRAM. Therefore, it is necessary to avoid PN junction leakage current. Summary of the invention

[0006] One aspect of the present disclosure provides a memory element. The memory element includes: a semiconductor substrate having a first surface and an active region defined below the first surface; a gate structure adjacent to the active region and recessed from the first surface into the semiconductor substrate; a doped component extending into the semiconductor substrate and surrounded by the active region; a conductive layer including a first portion extending from the first surface into the semiconductor substrate and a second portion disposed on the doped component and coupled to the first portion; a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped component and the active region of the semiconductor substrate; a first contact disposed on the conductive layer and surrounded by a first dielectric layer; and a conductive pillar disposed on the first contact and between the first contact and a capacitor, wherein the first portion of the conductive layer is disposed between the gate structure and the doped component.

[0007] Another aspect of the present disclosure provides a memory element. The memory element includes: a semiconductor substrate defining a first active region and a second active region; a gate structure adjacent to the first active region and the second active region and recessed from a first surface of the semiconductor substrate into the semiconductor substrate; a doping member extending into the semiconductor substrate and surrounded by the first active region; a conductive layer including a first portion extending from the first surface of the semiconductor substrate into the semiconductor substrate and a second portion disposed on the doping member and coupled to the first portion; a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doping member and the first active region of the semiconductor substrate, and a second insulating layer disposed on the gate structure, wherein the first insulating layer and the second insulating layer are separated from each other; a first contact and a second contact disposed on the conductive layer and surrounded by a first dielectric layer; and a first conductive pillar and a second conductive pillar disposed on the first dielectric layer, wherein the first portion of the conductive layer is disposed between the gate structure and the doping member.

[0008] Another aspect of the present disclosure provides a method for manufacturing a memory element. The manufacturing method includes the following steps: providing a semiconductor substrate defining an active region, wherein the semiconductor substrate includes a gate structure adjacent to the active region and an isolation structure surrounding the active region and the gate structure; forming a groove extending into the semiconductor substrate and located within the active region; and forming an insulating layer conforming to the groove. The manufacturing method further includes: removing a portion of the insulating layer to expose a first side of the groove, wherein the first side of the groove is adjacent to the gate structure; forming a first portion of a conductive layer on the first side of the groove; forming a doping member within the groove and on the insulating layer and the first portion of the conductive layer; forming a second portion of the conductive layer on the doping member and coupled to the first portion of the conductive layer; forming a first contact on the second portion of the conductive layer; performing an etching process to form a conductive pillar on the first contact and form a contact pad on the conductive pillar; and forming a second contact on the contact pad and forming a capacitor on the second contact.

[0009] In summary, since the insulating layer disposed between the doping member and the active region of the semiconductor substrate is coupled to the conductive layer adjacent to the gate structure and disposed on the above-mentioned doping member, leakage current from the P-N junction can be avoided. Therefore, the overall performance of the memory element and the process for manufacturing the memory element are improved.

[0010] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that a better understanding of the detailed description of the present disclosure below can be obtained. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The disclosure of the present application can be more fully understood when considering the accompanying drawings in conjunction with the embodiments and the claims. It should be noted that, in accordance with the standard industry practice, the features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features can be increased or decreased arbitrarily.

[0012] Figure 1 is a cross-sectional view illustrating a memory element according to some embodiments of the present disclosure.

[0013] Figure 2 is a cross-sectional view illustrating a memory element according to other embodiments of the present disclosure.

[0014] Figure 3 is a flowchart illustrating a method of manufacturing a memory element according to some embodiments of the present disclosure.

[0015] Figures 4 to 23 is a cross-sectional view illustrating an intermediate stage in the formation of a memory element according to some embodiments of the present disclosure.

[0016] Fig.24 and Fig.25 is a flowchart illustrating a method of manufacturing a memory element according to some embodiments of the present disclosure.

[0017] DESCRIPTION OF REFERENCE NUMERALS:

[0018] 100: First memory element

[0019] 101: Semiconductor substrate

[0020] 101a: First surface

[0021] 101b: Second surface

[0022] 101c: First groove

[0023] 102: Isolation structure

[0024] 103: Gate structure

[0025] 103a: Gate oxide

[0026] 103b: Gate electrode

[0027] 104: Active region

[0028] 104a: First active region

[0029] 104b: Second groove

[0030] 104c: First side

[0031] 104d: Second side

[0032] 104e: Implantation region

[0033] 104m: Second active region

[0034] 105: Doping member

[0035] 105a: Top surface

[0036] 105b: Doping material

[0037] 106: Insulating layer

[0038] 106a: First insulating layer

[0039] 106b: Second insulating layer

[0040] 106c: Top surface

[0041] 106x: Portion

[0042] 108: First conductive layer

[0043] 111: Conductive layer

[0044] 111a: First portion

[0045] 111b: Second portion

[0046] 113: First conductive material

[0047] 115: Second conductive material

[0048] 116’: Initial conductive pillar

[0049] 116a: Conductive pillar

[0050] 116b: Conductive pillar

[0051] 120: Second conductive layer

[0052] 121a: Contact

[0053] 121b: Contact

[0054] 121m: Contact

[0055] 122: First dielectric layer

[0056] 122’: Second dielectric layer

[0057] 123: Capacitor

[0058] 124: Third dielectric layer

[0059] 124a: Sub-layer

[0060] 124b: Sub-layer

[0061] 124c: Sub-layer

[0062] 125: Contact pad

[0063] 127: Bit line

[0064] 141: Patterned mask

[0065] 142: Opening

[0066] 200: Second memory element

[0067] CP: Contact pad

[0068] D1: Depth

[0069] D2: Depth

[0070] L1: Length

[0071] L2: Length

[0072] S300: Method

[0073] S301: Step

[0074] S302: Step

[0075] S303: Step

[0076] S304: Step

[0077] S305: Step

[0078] S306: Step

[0079] S307: Step

[0080] S308: Step

[0081] S400: Method

[0082] S401: Step

[0083] S402: Step

[0084] S403: Step

[0085] S404: Step

[0086] S405: Step

[0087] S406: Step

[0088] S407: Step

[0089] S408: Step

[0090] S409: Step

[0091] S410: Step

[0092] T1: Thickness

[0093] T2: Thickness

[0094] T3: Thickness

[0095] σ: Angle Detailed implementation manners

[0096] The present disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. The following specific examples of components and configurations simplify the present disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature above or on top of a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact.

[0097] In addition, the present disclosure may reuse element symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations discussed.

[0098] Furthermore, for ease of description, spatially relative terms may be used herein, such as "below", "beneath", "lower", "above", "upper", or similar terms, to describe the relative relationship between one component or feature shown in the drawings and another. Except for the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the element during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0099] Figure 1 is a cross-sectional view illustrating a first memory element 100 of some embodiments of the present disclosure. In some embodiments, the first memory element 100 includes a plurality of unit cells.

[0100] In some embodiments, the first memory element 100 includes a semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 includes a semiconductor material, e.g., silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrate 101 includes a bulk semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 includes lightly doped single-crystalline silicon. In some embodiments, the semiconductor substrate 101 is a p-type substrate.

[0101] In some embodiments, the semiconductor substrate 101 includes a first surface 101a and a second surface 101b opposite to the first surface 101a. In some embodiments, the first surface 101a is the front side of the semiconductor substrate 101, where electronic components or parts are subsequently formed thereon and electrically connected to an external circuit. In some embodiments, the second surface 101b is the back side of the semiconductor substrate 101, where no electronic components or parts are present.

[0102] In some embodiments, the semiconductor substrate 101 includes a plurality of active regions 104 separated from each other. Each active region 104 is a doped region in the semiconductor substrate 101. In some embodiments, each active region 104 extends horizontally above or below the first surface 101a of the semiconductor substrate 101. In some embodiments, each active region 104 includes the same type of dopant. In some embodiments, each active region 104 includes a dopant type different from the dopant type included in other active regions 104. In some embodiments, each active region 104 has the same conductivity type. In some embodiments, the active region 104 includes an N-type dopant.

[0103] In some embodiments, the semiconductor substrate 101 includes a first groove 101c extending into the semiconductor substrate 101. In some embodiments, the first groove 101c extends from the first surface 101a towards the second surface 101b of the semiconductor substrate 101. In some embodiments, the first groove 101c is disposed between a plurality of active regions 104, e.g., between the first active region 104a and the second active region 104m. In some embodiments, the first groove 101c gradually narrows from the first surface 101a towards the second surface 101b of the semiconductor substrate 101. In some embodiments, the depth of the first groove 101c is substantially greater than the depth of each active region 104.

[0104] In some embodiments, the first memory element 100 includes a gate structure 103 disposed within the first groove 101c. In some embodiments, the gate structure 103 is disposed between a plurality of active regions 104, such as between the first active region 104a and the second active region 104m.

[0105] In some embodiments, the gate structure 103 includes a gate oxide 103a disposed within the first groove 101c and a gate electrode 103b surrounded by the gate oxide 103a. In some embodiments, the gate oxide 103a is configured to conform to the first groove 101c and is located within the first groove 101c. In some embodiments, the gate oxide 103a is disposed along the entire sidewall of the first groove 101c. In some embodiments, the gate electrode 103b conforms to the gate oxide 103a. In some embodiments, the gate oxide 103a includes silicon oxide or a similar material. In some embodiments, the gate electrode 103b includes a conductive material, such as tungsten (W).

[0106] In some embodiments, the first memory element 100 further includes an isolation structure 102 adjacent to the gate structure 103. In some embodiments, the isolation structure 102 extends into the semiconductor substrate 101 from the first surface 101a towards the second surface 101b. In some embodiments, the isolation structure 102 is a shallow trench isolation (STI). In some embodiments, the isolation structure 102 defines the boundary of the active region 104. In some embodiments, the semiconductor substrate 101 is defined with active regions 104 and includes the isolation structure 102 surrounding the active regions 104 and the gate structure 103. In some embodiments, the isolation structure 102 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or a combination thereof. In some embodiments, the depth of the isolation structure 102 is substantially greater than the depth of the gate structure 103.

[0107] In some embodiments, the semiconductor substrate 101 includes a second groove 104b extending into the semiconductor substrate 101. In some embodiments, the second groove 104b is adjacent to the gate structure 103. In some embodiments, the second groove 104b extends from the first surface 101a toward the second surface 101b of the semiconductor substrate 101. In some embodiments, the second groove 104b gradually narrows from the first surface 101a toward the second surface 101b of the semiconductor substrate 101. In some embodiments, the second groove 104b is disposed within one of the active regions 104, such as within the first active region 104a. In some embodiments, the second groove 104b is disposed between the gate structure 103 and the isolation structure 102. In some embodiments, the depth of the second groove 104b is substantially equal to or less than the depth of the first groove 101c. In some embodiments, the depth of the second groove 104b is less than the depth of the first groove 101c. In some embodiments, the second groove 104b has a first side 104c adjacent to the gate structure 103 and a second side 104d opposite to the first side 104c.

[0108] In some embodiments, the first memory element 100 includes a first insulating layer 106a disposed within the second groove 104b. In some embodiments, the first side 104c of the second groove 104b is exposed through the first insulating layer 106a. In some embodiments, the first insulating layer 106a conforms to the second side 104d of the second groove 104b. In some embodiments, the first insulating layer 106a is disposed within the first active region 104a and surrounded by the first active region 104a. In some embodiments, the first insulating layer 106a is disposed within the first active region 104a and on top of the isolation structure 102 adjacent to the second groove 104b. In some embodiments, the first insulating layer 106a includes an oxide. In some embodiments, the first insulating layer 106a includes silicon oxide or a similar material.

[0109] In some embodiments, the first memory element 100 includes a doped member 105 extending into the semiconductor substrate 101 and surrounded by the first active region 104a. In some embodiments, the doped member 105 is disposed within the second groove 104b. In some embodiments, the doped member 105 is disposed on top of the first insulating layer 106a. In some embodiments, the first insulating layer 106a is disposed beneath the doped member 105 and surrounded by the first active region 104a. In some embodiments, the doped member 105 is disposed between the isolation structure 102 and the gate structure 103.

[0110] In some embodiments, the doping member 105 includes polysilicon. In some embodiments, the doping member 105 includes the same type of dopant as that contained in the active region 104. In some embodiments, the doping member 105 includes an N-type dopant.

[0111] In some embodiments, the first memory element 100 includes a conductive layer 111. In some embodiments, the conductive layer 111 is disposed over the first active region 104a. In some embodiments, the conductive layer 111 covers the first active region 104a. In some embodiments, the conductive layer 111 is disposed between the gate structure 103 and the isolation structure 102. In some embodiments, the conductive layer 111 is disposed over the doping member 105. In some embodiments, the doping member 105 is surrounded by the first insulating layer 106a and the conductive layer 111. In some embodiments, the conductive layer 111 includes a conductive material, such as a metal or an alloy. In some embodiments, the conductive layer 111 includes cobalt.

[0112] In some embodiments, the conductive layer 111 includes a first portion 111a extending from the first surface 101a into the first active region 104a of the semiconductor substrate 101, and a second portion 111b disposed over the doping member 105 and coupled to the first portion 111a. The first portion 111a is coupled to the second portion 111b and extends from the second portion 111b. In some embodiments, the first portion 111a of the conductive layer 111 is substantially orthogonal to the second portion 111b of the conductive layer 111.

[0113] In some embodiments, the first portion 111a and the second portion 111b are integral. In some embodiments, the first portion 111a and the second portion 111b are formed simultaneously or separately. In some embodiments, the formation of the first portion 111a is performed before the formation of the second portion 111b. The conductive materials in the first portion 111a and the second portion 111b may be the same or different.

[0114] In some embodiments, the first portion 111a of the conductive layer 111 is disposed between the gate structure 103 and the doping member 105. In some embodiments, the first portion 111a of the conductive layer 111 is disposed between the first active region 104a and the doping member 105. In some embodiments, the first portion 111a of the conductive layer 111 extends from the first surface 101a into the first active region 104a of the semiconductor substrate 101. In some embodiments, the first portion 111a of the conductive layer 111 is disposed within the first active region 104a. In some embodiments, the first portion 111a of the conductive layer 111 is disposed within the second groove 104b. In some embodiments, the first portion 111a of the conductive layer 111 contacts the doping member 105.

[0115] In some embodiments, the first portion 111a of the conductive layer 111 is disposed adjacent to the first insulating layer 106a. In some embodiments, the first portion 111a of the conductive layer 111 is coupled to the first insulating layer 106a. In some embodiments, the first portion 111a of the conductive layer 111 is disposed on the first side 104c of the second groove 104b. In some embodiments, the first portion 111a of the conductive layer 111 contacts the first insulating layer 106a and the first active region 104a. When a current (not shown) flows through the first memory element 100, the current may flow in the direction indicated by arrow A. In some embodiments, the current may flow from the second active region 104m to the first active region 104a along the gate structure 103. Since the first insulating layer 106a is disposed within the first active region 104a and blocks the current, the current flows to the first portion 111a of the conductive layer 111 and flows through the first portion 111a of the conductive layer 111 to the second portion 111b of the conductive layer 111. In addition, since the first insulating layer 106a is configured to limit the P-N junction area within the first active region 104a, the current must pass through the conductive layer 111, thereby avoiding P-N junction leakage current. The overall performance of the first memory element 100 is thus improved.

[0116] In some embodiments, in order to avoid junction leakage current, the length L1 of the first portion 111a of the conductive layer 111 is substantially equal to or less than the length L2 of the first insulating layer 106a. In some embodiments, the length L1 is less than the length L2. In some embodiments, the length L2 is greater than twice the length L1. In some embodiments, the length L2 is 2 to 30 times the length L1.

[0117] In some embodiments, the second portion 111b of the conductive layer 111 covers the doping member 105. In some embodiments, the second portion 111b of the conductive layer 111 contacts the doping member 105. In some embodiments, the second portion 111b is disposed over the first insulating layer 106a and the first active region 104a. In some embodiments, the second portion 111b of the conductive layer 111 is disposed over the first portion 111a of the conductive layer 111. In some embodiments, the second portion 111b of the conductive layer 111 contacts the first insulating layer 106a. In some embodiments, the doping member 105 is disposed between the first insulating layer 106a and the second portion 111b of the conductive layer 111.

[0118] In some embodiments, the first memory element 100 includes a second insulating layer 106b disposed over the gate structure 103. In some embodiments, the first insulating layer 106a and the second insulating layer 106b are separated from each other. In some embodiments, the second insulating layer 106b is disposed over the gate structure 103, the second active region 104m, and the isolation structure 102 adjacent to the second active region 104m. In some embodiments, the second insulating layer 106b contacts the gate structure 103. In some embodiments, the second insulating layer 106b includes an oxide. In some embodiments, the second insulating layer 106b includes silicon oxide or a similar material. In some embodiments, the first insulating layer 106a and the second insulating layer 106b include the same material. In some embodiments, the thickness T1 of the first insulating layer 106a is less than or equal to the thickness T2 of the second insulating layer 106b. In some embodiments, the first insulating layer 106a and the second insulating layer 106b are formed simultaneously or separately.

[0119] In some embodiments, a first portion 111a of the conductive layer 111 is disposed between the first insulating layer 106a and the second insulating layer 106b and is coupled to the first insulating layer 106a and the second insulating layer 106b. In some embodiments, a second portion 111b of the conductive layer 111 is disposed between the first insulating layer 106a and the second insulating layer 106b. In some embodiments, a top surface of the second portion 111b of the conductive layer 111 is substantially coplanar with a top surface 106c of the second insulating layer 106b. In some embodiments, a top surface 105a of the doping member 105 is substantially coplanar with the top surface 106c of the second insulating layer 106b. In some embodiments, the top surface 106c of the second insulating layer 106b is substantially lower than the second portion 111b of the conductive layer 111.

[0120] Figure 2 is a cross-sectional view illustrating a second memory element 200 of other embodiments of the present disclosure. In some embodiments, Figure 2 the second memory element 200 shown is similar to Figure 1The first memory element 100 shown, in addition, the second memory element 200 further includes a contact 121a disposed on the conductive layer 111, a conductive pillar 116a disposed on the contact 121a, and a capacitor 123 electrically connected to the conductive layer 111 via the contact 121a and the conductive pillar 116a. In some embodiments, a contact pad 125 is disposed on the conductive pillar 116a, and a contact 121b is disposed on the contact pad 125, such that the conductive pillar 116a, the contact pad 125, and the contact 121b are disposed between the contact 121a and the capacitor 123. In some embodiments, the capacitor 123 is electrically connected to a first active region 104a in the semiconductor substrate 101 through the contacts 121a, 121b, the conductive pillar 116a, the contact pad 125, and the conductive layer 111. In some embodiments, the capacitor 123 is disposed on the contacts 121a, 121b, the conductive pillar 116a, and the contact pad 125. In some embodiments, the conductive pillar 116a is disposed on the contact 121a and between the contact 121a and the contact pad 125. In some embodiments, the second memory element 200 is a DRAM.

[0121] In some embodiments, the second memory element 200 further includes a contact 121m disposed on the second active region 104m, a conductive pillar 116b disposed on the contact 121m, and a bit line 127 electrically connected to the second active region 104m in the semiconductor substrate 101 via the contact 121m and the conductive pillar 116b. In some embodiments, the contact 121m penetrates the second insulating layer 106b. In some embodiments, the contact 121m is surrounded by the second insulating layer 106b and electrically connected to the second active region 104m. In some embodiments, the bit line 127 is disposed adjacent to the contact pad 125. In some embodiments, the conductive pillar 116b is disposed on the contact 121m and between the contact 121m and the bit line 127.

[0122] In some embodiments, contacts 121a, 121b, 121m comprise a conductive material such as polysilicon, tungsten (W), copper (Cu), or a similar material. In some embodiments, capacitors 123, contact pads 125, and bit lines 127 comprise a conductive material such as polysilicon, tungsten (W), copper (Cu), or a similar material. In some embodiments, conductive pillars 116a, 116b comprise a conductive material such as polysilicon, tungsten (W), copper (Cu), or a similar material. Contacts 121a, 121b, 121m, capacitors 123, contact pads 125, conductive pillars 116a, 116b, and bit lines 127 comprise the same material or different materials. In some embodiments, contact pads 125, bit lines 127, and conductive pillars 116a, 116b are made of different conductive materials respectively. In some embodiments, the resistivity of the conductive material used to form contact pads 125 and bit lines 127 is less than the resistivity of the conductive material used to form conductive pillars 116a, 116b, and the conductive material used to form conductive pillars 116a, 116b has an etching selectivity relative to the conductive material sufficient to form contact pads 125 and bit lines 127. In some embodiments, each of conductive pillars 116a, 116b is a single-layer structure. In some embodiments, each of conductive pillars 116a, 116b is a multi-layer structure comprising the same or different conductive materials. In some embodiments, the thickness of each of conductive pillars 116a, 116b is greater than the thickness of contact pads 125.

[0123] In some embodiments, the second memory element 200 further comprises a first dielectric layer 122 surrounding contacts 121a, 121m and covering the conductive layer 111, the first insulating layer 106a, the second insulating layer 106b, the doping member 105, the active region 104, and the gate structure 103. In some embodiments, contacts 121a, 121m penetrate the first dielectric layer 122. In some embodiments, the first dielectric layer 122 comprises silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and / or other suitable dielectric materials.

[0124] In some embodiments, the second memory element 200 comprises a second dielectric layer 122' located above the first dielectric layer 122 and surrounding the conductive pillars 116a, 116b. In some embodiments, the conductive pillars 116a, 116b penetrate the second dielectric layer 122'. In some embodiments, the second dielectric layer 122' comprises silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and / or other suitable dielectric materials.

[0125] In some embodiments, the second memory element 200 includes a third dielectric layer 124 located above the second dielectric layer 122' and surrounding the capacitor 123. In some embodiments, the third dielectric layer 124 includes a plurality of sub-layers 124a, 124b, and 124c. In some embodiments, the sub-layer 124a is disposed above the second dielectric layer 122', and the contact pad 125 is surrounded by the sub-layer 124a. In some embodiments, the sub-layer 124b is disposed above the sub-layer 124a, and the contact 121b is surrounded by the sub-layer 124b. In some embodiments, the sub-layer 124c is disposed above the sub-layer 124b, and the capacitor 123 is surrounded by the sub-layer 124c. In some embodiments, the bit line 127 is surrounded by the third dielectric layer 124. In some embodiments, the bit line 127 is surrounded by the sub-layer 124a.

[0126] In some embodiments, a plurality of capacitors 123 are disposed within the third dielectric layer 124. In some embodiments, these capacitors 123 are electrically connected to corresponding active regions 104 in the semiconductor substrate 101 through a plurality of contact pads 125, a plurality of conductive pillars 116a, and a plurality of contacts 121a, 121b. In some embodiments, the capacitor 123 is disposed within the third dielectric layer 124. In some embodiments, the third dielectric layer 124 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and / or other suitable dielectric materials. The first dielectric layer 122, the second dielectric layer 122', and the third dielectric layer 124 include the same material or different materials. In some embodiments, the second dielectric layer 122' and the third dielectric layer 124 are interlayer dielectric layers (ILD).

[0127] Figure 3 is a flowchart illustrating a method S300 for fabricating the first memory element 100 or the second memory element 200 according to some embodiments of the present disclosure, Figures 4 to 23 is a cross-sectional view illustrating an intermediate stage in the formation process of the first memory element 100 or the second memory element 200 according to some embodiments of the present disclosure.

[0128] shown in Figures 4 to 23 The stage of is also schematically shown in Figure 3 the flowchart of. In the following discussion, the stage shown in Figures 4 to 23 is discussed with reference to Figure 3 the process steps shown. The method S300 includes a plurality of operations, and the description and illustration should not be construed as limiting the order of these operations. The method S300 includes a plurality of steps (S301, S302, S303, S304, S305, S306, S307, and S308).

[0129] See Figure 4, according to Figure 3 In step S301 of Figure 3 , a semiconductor substrate 101 is provided. The semiconductor substrate 101 is defined with a first active region 104a, and includes a gate structure 103 adjacent to the first active region 104a, and an isolation structure 102 surrounding the first active region 104a and the gate structure 103. In some embodiments, the gate structure 103 is disposed adjacent to the first active region 104a and extends from the first surface 101a towards the second surface 101b of the semiconductor substrate 101. In some embodiments, the isolation structure 102 extends from the first surface 101a towards the second surface 101b of the semiconductor substrate 101. In some embodiments, the gate structure 103 is disposed between the first active region 104a and the second active region 104m. In some embodiments, the first active region 104a includes an N-type dopant. In some embodiments, the semiconductor substrate 101 is a p-type substrate.

[0130] Refer to Figures 5 to 7 , according to Figure 3 In step S302 of Figure 3 , a second groove 104b extending into the semiconductor substrate 101 and located within the first active region 104a is formed. In some embodiments, refer to Figure 5 , a patterned mask 141 is disposed on the first surface 101a of the semiconductor substrate 101. In some embodiments, the patterned mask 141 includes an opening 142 disposed above the first active region 104a. The opening 142 exposes the first active region 104a adjacent to the gate structure 103. The patterned mask 141 is formed by the following steps, including (1) conformally coating a photosensitive material on the first surface 101 of the semiconductor substrate 101, (2) exposing a portion of the photosensitive material to radiation (not shown), (3) performing a post-exposure baking process, and (4) developing the photosensitive material to form the opening 142 to expose the first active region 104a adjacent to the gate structure 103.

[0131] Refer to Figure 6, a second groove 104b extending into the semiconductor substrate 101 is formed. In some embodiments, the second groove 104b extends within the first active region 104a. In some embodiments, the formation of the second groove 104b includes removing some portions of the semiconductor substrate 101. In some embodiments, the second groove 104b extends from the first surface 101a towards the second surface 101b of the semiconductor substrate 101. In some embodiments, the depth D1 of the second groove 104b is less than the depth D2 of the gate structure 103. In some embodiments, the second groove 104b has a first side 104c adjacent to the gate structure 103 and a second side 104d opposite to the first side 104c and adjacent to the isolation structure 102. In some embodiments, the second groove 104b is formed by etching or any other suitable process. In some embodiments, the second groove 104b is formed by dry etching. Refer to Figure 7 , in some embodiments, the patterned mask 141 is removed after the formation of the second groove 104b.

[0132] Refer to Figure 8 , according to Figure 3 In step S303 of, an implantation region 104e of the first active region 104a is formed on the first side 104c of the second groove 104b. In some embodiments, the implantation region 104e is formed by implanting implantants in the second groove 104b and towards the gate structure 103. In some embodiments, the implantation region 104e is formed by implanting implantants into the first active region 104a at an angle σ. In some embodiments, the angle σ with respect to the first surface 101a of the semiconductor substrate 101 is between 7 degrees and 30 degrees. In some embodiments, the implantation region 104e is formed by nitrogen ion implantation. In some embodiments, step S303 is omitted.

[0133] Refer to Fig. 9 , according to Figure 3 In step S304 of, an insulating layer 106 conforming to the second groove 104b is formed. In some embodiments, the insulating layer 106 is formed over the isolation structure 102, the second groove 104b, the gate structure 103, and the second active region 104m. In some embodiments, the insulating layer 106 is formed over the first surface 101a of the semiconductor substrate 101. In some embodiments, the insulating layer 106 is formed by deposition, oxidation, spin coating process, or any other suitable process. In some embodiments, the insulating layer 106 is formed by chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, or any other suitable process. In some embodiments, the insulating layer 106 includes an oxide, such as silicon oxide.

[0134] In some embodiments, the insulating layer 106 is not easily formed on the first side 104c of the second groove 104b. In some embodiments, the insulating layer 106 is not easily formed on the implantation region 104e. In some embodiments, the thickness T3 of the portion 106x of the insulating layer 106 above the implantation region 104e is less than the thickness T1 of the first insulating layer 106a of the insulating layer 106 above the second side 104d of the second groove 104b.

[0135] See Fig.10 , according to Figure 3 Step S305 of, remove the portion 106x of the insulating layer 106 to expose the first side 104c of the second groove 104b, wherein the first side 104c of the second groove 104b is adjacent to the gate structure 103. In some embodiments, the portion 106x of the insulating layer 106 is disposed above the implantation region 104e. In some embodiments, the portion 106x of the insulating layer 106 is removed by etching or any other suitable process. In some embodiments, the portion 106x of the insulating layer 106 is washed away by a dilute hydrofluoric acid solution (DHF). In some embodiments, the implant of the implantation region 104e is removed after the first side 104c of the second groove 104b is exposed.

[0136] In some embodiments, after removing the portion 106x of the insulating layer 106, the insulating layer 106 is separated into a first segment 106a disposed in the second groove 104b and a second segment 106b disposed above the gate structure 103. In some embodiments, after removing the portion 106x of the insulating layer 106, the thickness T1 of the first segment 106a of the insulating layer 106 is less than the thickness T2 of the second segment 106b of the insulating layer 106. The first segment 106a of the insulating layer 106 forms the first insulating layer 106a, and the second segment 106b of the insulating layer 106 forms the second insulating layer 106b.

[0137] See Figures 11 to 13 , according to Figure 3 In step S306 of, form a first portion 111a of the conductive layer 111 on the first side 104c of the second groove 104b. In some embodiments, see Fig.11 , a first conductive material 113 is disposed on the first side 104c of the second groove 104b, the first insulating layer 106a, and the second insulating layer 106b. In some embodiments, the first conductive material 113 conforms to the first side 104c of the second groove 104b. In some embodiments, the first conductive material 113 includes the first portion 111a of the conductive layer 111. In some embodiments, the first conductive material 113 is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or any other suitable process. In some embodiments, the first conductive material 113 includes cobalt.

[0138] In some embodiments, referring to Fig.12 , the first portion 111a of the conductive layer 111 is annealed. In some embodiments, the first conductive material 113 is annealed. In some embodiments, the first portion 111a of the conductive layer 111 is annealed at a temperature between 650 °C and 800 °C.

[0139] In some embodiments, referring to Fig.13 , the first conductive material 113 disposed on the first insulating layer 106a and the second insulating layer 106b is removed, and the first portion 111a of the conductive layer 111 is formed above the first side 104c of the second groove 104b. In some embodiments, the formation of the first portion 111a of the conductive layer 111 is performed after forming the insulating layer 106 and removing a portion 106x of the insulating layer 106.

[0140] In some embodiments, the first conductive material 113 disposed on the first insulating layer 106a and the second insulating layer 106b is removed by etching or any other suitable process. In some embodiments, the first conductive material 113 disposed on the first insulating layer 106a and the second insulating layer 106b is washed off with a dilute hydrofluoric acid solution (DHF). In some embodiments, the length L1 of the first portion 111a of the conductive layer 111 is substantially equal to or less than the length L2 of the first insulating layer 106a. In some embodiments, the length L1 is less than the length L2.

[0141] Referring to Fig.14 and Fig.15 , according to Figure 3 step S307 in Fig.14 , a doping member 105 is formed within the second groove 104b and above the insulating layer 106 and the first portion 111a of the conductive layer 111. In some embodiments, referring to

[0142] In some embodiments, referring to Fig.15, after forming the doped material 105b, a planarization process is performed, and a doped component 105 is formed within the second groove 104b. In some embodiments, the planarization process includes a grinding process, a chemical mechanical polishing (CMP) process, an etching process, another suitable process, or a combination thereof. In some embodiments, the top surface 105a of the doped component 105 is substantially coplanar with the top surface 106c of the second insulating layer 106b.

[0143] See Figures 16 to 18 , according to Figure 3 in step S308, a second portion 111b of the conductive layer 111 is formed over the doped component 105, wherein the second portion 111b of the conductive layer 111 is coupled to the first portion 111a of the conductive layer 111.

[0144] In some embodiments, see Fig.16 , a second conductive material 115 is disposed over the doped component 105, the first insulating layer 106a, and the second insulating layer 106b. In some embodiments, the second conductive material 115 is coupled to the first portion 111a of the conductive layer 111. In some embodiments, the second conductive material 115 includes the second portion 111b of the conductive layer 111 disposed over the doped component 105. In some embodiments, the second conductive material 115 is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or any other suitable process. In some embodiments, the second conductive material 115 includes cobalt.

[0145] In some embodiments, see Fig.17 , the second portion 111b of the conductive layer 111 is annealed. In some embodiments, the second conductive material 115 is annealed. In some embodiments, the second portion 111b of the conductive layer 111 is annealed at a temperature between 650 °C and 800 °C. In some embodiments, the second conductive material 115 reacts with the doped component 105. In some embodiments, the second conductive material 115 includes CoSiO 2 .

[0146] In some embodiments, see Fig.18, the second conductive material 115 disposed on the second insulating layer 106b and the isolation structure 102 is removed, and a second portion 111b of the conductive layer 111 is formed on the doping member 105 and coupled to the first portion 111a of the conductive layer 111. In some embodiments, after the formation of the first portion 111a of the conductive layer 111 and the formation of the doping member 105, the formation of the second portion 111b of the conductive layer 111 is performed. In some embodiments, the top surface of the second portion 111b of the conductive layer 111 is substantially coplanar with the top surface 106c of the second insulating layer 106b. In some embodiments, the first memory element 100 is formed.

[0147] In some embodiments, the second conductive material 115 disposed on the second insulating layer 106b and the isolation structure 102 is removed by etching or any other suitable process. In some embodiments, the second conductive material 115 disposed on the second insulating layer 106b and the isolation structure 102 is washed away by a dilute hydrofluoric acid solution (DHF).

[0148] In some embodiments, referring to Fig.19 , method S300 further includes forming a first dielectric layer 122 over the conductive layer 111, the first insulating layer 106a, and the second insulating layer 106b. In some embodiments, the first dielectric layer 122 is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or another suitable process. After the formation of the first dielectric layer 122, contacts 121a, 121m are formed within the first dielectric layer 122, and a planarization process may be selectively performed. Contact 121a is coupled to the second portion 111b of the conductive layer 111 and is surrounded by the first dielectric layer 122. Contact 121m is coupled to the second active region 104m and is surrounded by the first dielectric layer 122 and the second insulating layer 106b. In some embodiments, the planarization process includes a grinding process, a chemical mechanical polishing (CMP) process, an etching process, another suitable process, or a combination thereof. In some embodiments, contacts 121a, 121m include a conductive material.

[0149] Referring to Figure 20 to Figure 22 , in some embodiments, method S300 further includes forming a second dielectric layer 122' over the first dielectric layer 122. In some embodiments, after the formation of the second dielectric layer 122', contact pads 125 and conductive pillars 116a, 116b are formed within the second dielectric layer 122'.

[0150] In some embodiments, referring to Fig. 20, the first conductive layer 108 and the second conductive layer 120 are formed integrally on the current structure. In other words, the contacts 121a, 121m, and the first dielectric layer 122 may be covered by the first conductive layer 108 and the second conductive layer 120. The second conductive layer 120 is stacked on the first conductive layer 108. The first conductive layer 108 is composed of multiple layers including the same or different conductive materials. In some embodiments, the thickness of the first conductive layer 108 is greater than the thickness of the second conductive layer 120. Additionally, in some embodiments, the resistivity of the conductive material used to form the second conductive layer 120 is less than the resistivity of the conductive material used to form the first conductive layer 108, and the conductive material used to form the first conductive layer 108 has an etching selectivity relative to the conductive material sufficient to form the second conductive layer 120. The method of forming each of the conductive layers 108, 120 may include a deposition process (e.g., PVD process), an electroplating process, or a combination thereof.

[0151] In some embodiments, referring to Fig.21 , the first conductive layer 108 and the second conductive layer 120 are patterned to form the initial conductive pillars 116' and the contact pads CP. During such patterning, some portions of the first conductive layer 108 and some portions of the second conductive layer 120 are removed, and some portions of the first dielectric layer 122 can be exposed. The sidewalls of the formed initial conductive pillars 116' may be substantially coplanar with the sidewalls of the formed contact pads CP. In other words, the footprint area of each initial conductive pillar 116' may be substantially the same as the footprint area of the contact pad CP it covers. In some embodiments, the method of forming the initial conductive pillars 116' and the contact pads CP may include a lithography process and an anisotropic etching process (e.g., a dry etching process).

[0152] In some embodiments, referring to Fig. 22, the initial conductive pillar 116' is laterally recessed to form conductive pillars 116a, 116b, and at the same time, contact pads 125 and bit lines 127 are formed after etching the contact pads CP. In some embodiments, the method for laterally recessing the initial conductive pillar 116' includes an isotropic etching process (e.g., a wet etching process). In those embodiments where the conductive material used to form the contact pads 125 and bit lines 127 has an etching selectivity relative to the conductive material sufficient to form the conductive pillars 116a, 116b, damage to the contact pads CP during such an isotropic etching process can be avoided (or they can only be slightly consumed). In this way, the formed conductive pillars 116a, 116b can be laterally recessed relative to the contact pads 125 and bit lines 127. After the isotropic etching process, the conductive pillar 116a and the contact pad 125, and the conductive pillar 116b and the bit line 127 respectively form a T-shaped stacked structure on the contacts 121a, 121m. In some embodiments, the dielectric layer 122' is formed to cover and surround these T-shaped stacked structures. In some embodiments, the method for forming the dielectric layer 122' includes a deposition process (e.g., a CVD process), and may further include a planarization process to remove the excess material on the contact pads 125 and bit lines 127.

[0153] In some embodiments, referring to Fig.23, Method S300 further includes forming a third dielectric layer 124 over the second dielectric layer 122'. In some embodiments, some portions of the second dielectric layer 122' are removed, so that the contact pads 125, bit lines 127, and other portions of the second dielectric layer 122' are exposed. In some embodiments, a plurality of sub-layers 124a, 124b, 124c of the third dielectric layer 124 are formed over the second dielectric layer 122'. In some embodiments, the material of the third dielectric layer 124 is different from that of the second dielectric layer 122', such that the etching selectivity of the third dielectric layer 124 with respect to the second dielectric layer 122' is higher during subsequent processes. In some embodiments, the third dielectric layer 124 is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or another suitable process. After forming the third dielectric layer 124, the contact pads 125 and bit lines 127 are surrounded by the third dielectric layer 124. In some embodiments, contacts 121b and capacitors 123 are formed within the third dielectric layer 124 and over the contact pads 125. In some embodiments, a planarization process can be selectively performed. In some embodiments, the planarization process includes a grinding process, a chemical mechanical polishing (CMP) process, an etching process, another suitable process, or a combination thereof. In some embodiments, the capacitors 123 are coupled to the contacts 121a, 121b, conductive pillars 116a, and contact pads 125. In some embodiments, the bit lines 127 are coupled to the contacts 121m and conductive pillars 116b. In some embodiments, the contacts 121m, capacitors 123, contact pads 125, bit lines 127, conductive pillars 116a, and conductive pillars 116b include a conductive material.

[0154] Fig.24 , Fig.25 is a flowchart illustrating a method 400 for fabricating a first memory element 100 or a second memory element 200 according to some embodiments of the present disclosure.

[0155] Method S400 includes a plurality of operations, and the description and illustration should not be construed as limiting the order of these operations. Method S400 includes a plurality of steps (S401, S402, S403, S404, S405, S406, S407, S408, S409, and S410).

[0156] In some embodiments, according to Fig.24 step S401 therein, a semiconductor substrate is provided. In some embodiments, the semiconductor substrate is defined with an active region, and includes a gate structure adjacent to the active region, and an isolation structure surrounding the active region and the gate structure. In some embodiments, according to Fig.24 step S402 therein, a groove extending into the semiconductor substrate and located within the active region is formed. In some embodiments, according to Fig.24In step S403, an insulating layer conforming to the groove is formed.

[0157] In some embodiments, according to Fig.24 step S404 in, a portion of the insulating layer is removed to expose a first side of the groove, wherein the first side of the groove is adjacent to the gate structure. In some embodiments, according to Figure 4 step S405, a first portion of the conductive layer is formed on the first side of the groove. In some embodiments, according to Fig.24 step S406 in, a doped member is formed within the groove and on top of the insulating layer and the first portion of the conductive layer. In some embodiments, according to Fig.24 step S407 in, a second portion of the conductive layer is formed on top of the doped member and coupled to the first portion of the conductive layer.

[0158] In some embodiments, according to Fig.24 step S408 in, a first contact is formed on top of the second portion of the conductive layer. In some embodiments, according to Fig.25 step S409 in, an etching process is performed to form a conductive pillar on top of the first contact and a contact pad on top of the conductive pillar. In some embodiments, the etching process includes a first etching process and a second etching process. In some embodiments, the first etching process is anisotropic etching and the second etching process is isotropic etching.

[0159] In some embodiments, according to Fig.25 step S410 in, a second contact is formed on top of the contact pad and a capacitor is formed on top of the second contact.

[0160] In one aspect of the present disclosure, a memory element is provided. The memory element includes: a semiconductor substrate having a first surface and defining an active region below the first surface; a gate structure adjacent to the active region and recessed from the first surface into the semiconductor substrate; a doped member extending into the semiconductor substrate and surrounded by the active region; a conductive layer including a first portion extending from the first surface into the semiconductor substrate and a second portion disposed on top of the doped member and coupled to the first portion; a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active region of the semiconductor substrate; a first contact disposed on top of the conductive layer and surrounded by a first dielectric layer; and a conductive pillar disposed on top of the first contact and between the first contact and a capacitor, wherein the first portion of the conductive layer is disposed between the gate structure and the doped member.

[0161] In some embodiments, the first portion of the conductive layer is disposed between the gate structure and the doping member. In some embodiments, the gate structure includes a gate electrode and a gate oxide surrounding the gate electrode. In some embodiments, the doping member is disposed between the first insulating layer and the second portion of the conductive layer. In some embodiments, the doping member is surrounded by the first insulating layer and the conductive layer. In some embodiments, the first portion of the conductive layer contacts the doping member.

[0162] In some embodiments, the conductive layer is disposed over the active region. In some embodiments, the first portion of the conductive layer is coupled to the first insulating layer. In some embodiments, the first portion of the conductive layer is substantially orthogonal to the second portion of the conductive layer. In some embodiments, the first contact is disposed between the conductive pillar and the conductive layer. In some embodiments, the conductive pillar is a single-layer structure or a multi-layer structure. In some embodiments, the memory element further includes: a contact pad disposed over the conductive pillar.

[0163] In some embodiments, the contact pad and the conductive pillar are made of different conductive materials. In some embodiments, the resistivity of the contact pad is less than the resistivity of the conductive pillar. In some embodiments, the memory element further includes: a second contact disposed over the contact pad and between the capacitor and the contact pad. In some embodiments, the capacitor is electrically connected to the active region through the second contact, the contact pad, the conductive pillar, the first contact, and the conductive layer.

[0164] In another aspect of the present disclosure, a memory element is provided. The memory element includes: a semiconductor substrate defining a first active region and a second active region; a gate structure adjacent to the first active region and the second active region and recessed from a first surface of the semiconductor substrate into the semiconductor substrate; a doping member extending into the semiconductor substrate and surrounded by the first active region; a conductive layer including a first portion extending from the first surface of the semiconductor substrate into the semiconductor substrate, and a second portion disposed over the doping member and coupled to the first portion; a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doping member and the first active region of the semiconductor substrate, and a second insulating layer disposed over the gate structure, wherein the first insulating layer and the second insulating layer are separated from each other; a first contact and a second contact disposed over the conductive layer and surrounded by a first dielectric layer; and a first conductive pillar and a second conductive pillar disposed over the first dielectric layer, wherein the first portion of the conductive layer is disposed between the gate structure and the doping member.

[0165] In some embodiments, the gate structure includes a gate electrode and a gate oxide surrounding the gate electrode. In some embodiments, the doping member is disposed between the first insulating layer and the second portion of the conductive layer. In some embodiments, the doping member is surrounded by the conductive layer and the first insulating layer.

[0166] In some embodiments, the first portion of the conductive layer contacts the doping member. In some embodiments, the conductive layer is disposed over the first active region and the second active region. In some embodiments, the first portion of the conductive layer is coupled to the first insulating layer. In some embodiments, the first contact is disposed between the first conductive pillar and the conductive layer, and the second contact is disposed between the second conductive pillar and the second insulating layer.

[0167] In some embodiments, each of the first conductive pillar and the second conductive pillar forms a single-layer structure or a multi-layer structure. In some embodiments, the memory element further includes a contact pad disposed over the first conductive pillar. In some embodiments, the memory element further includes a bit line disposed over the second conductive pillar. In some embodiments, the contact pad, the bit line, the first conductive pillar, and the second conductive pillar are made of different conductive materials. In some embodiments, the resistivity of the contact pad and the bit line is less than the resistivity of the first conductive pillar and the second conductive pillar. In some embodiments, the memory further includes a third contact disposed over the contact pad and between the capacitor and the contact pad. In some embodiments, the capacitor is electrically connected to the first active region through the third contact, the contact pad, the first conductive pillar, the first contact, and the conductive layer.

[0168] In another aspect of the present disclosure, a method of manufacturing a memory element is provided. The manufacturing method includes the following steps: providing a semiconductor substrate defining an active region, wherein the semiconductor substrate includes a gate structure adjacent to the active region and an isolation structure surrounding the active region and the gate structure; forming a groove extending into the semiconductor substrate and located within the active region; and forming an insulating layer conforming to the groove. The manufacturing method further includes: removing a portion of the insulating layer to expose a first side of the groove, wherein the first side of the groove is adjacent to the gate structure; forming a first portion of a conductive layer on the first side of the groove; forming a doping member within the groove and over the insulating layer and the first portion of the conductive layer; forming a second portion of the conductive layer over the doping member and coupled to the first portion of the conductive layer; forming a first contact over the second portion of the conductive layer; performing an etching process to form a conductive pillar over the first contact and form a contact pad over the conductive pillar; and forming a second contact over the contact pad and forming a capacitor over the second contact.

[0169] In some embodiments, the etching process includes a first etching process and a second etching process. In some embodiments, the first etching process is an anisotropic etching, and the second etching process is an isotropic etching.

[0170] In some embodiments, the contact pad and the conductive pillar are made of different materials. In some embodiments, the resistivity of the contact pad is less than the resistivity of the conductive pillar.

[0171] In summary, since the insulating layer is configured to limit the P-N junction area within the active region, current must flow through the conductive layer coupled to the insulating layer, thereby avoiding P-N junction leakage current. Accordingly, the overall performance of the memory element and the process of manufacturing the memory element are improved.

[0172] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0173] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform the same function or achieve substantially the same result as the corresponding embodiments described herein can be used in accordance with the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A memory element, comprising: A semiconductor substrate having a first surface and an active region defined below the first surface; a gate structure adjacent to the active region and recessed from the first surface into the semiconductor substrate; a doped component extending into the semiconductor substrate and surrounded by the active region; a conductive layer comprising a first portion extending from the first surface into the semiconductor substrate, and a second portion disposed on the doped component and coupled to the first portion; a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped component and the active region of the semiconductor substrate; a first contact disposed on the conductive layer and surrounded by a first dielectric layer; and a first conductive column disposed on the first contact and between the first contact and a capacitor, The first portion of the conductive layer is disposed between the gate structure and the doped component. 2 . The memory device as claimed in claim 1 , wherein the gate structure comprises a gate electrode and a gate oxide surrounding the gate electrode. 3 . The memory device as claimed in claim 1 , wherein the doped component is disposed between the first insulating layer and the second portion of the conductive layer. 4 . The memory device as claimed in claim 1 , wherein the doped component is surrounded by the first insulating layer and the conductive layer. The memory device of claim 1 , wherein the first portion of the conductive layer contacts the doped component. The memory device as claimed in claim 1 , wherein the conductive layer is disposed on the active region.

7. The memory device of claim 1, wherein the first portion of the conductive layer is coupled to the first insulating layer. 8 . The memory device of claim 1 , wherein the first portion of the conductive layer is substantially orthogonal to the second portion of the conductive layer. 9 . The memory device as claimed in claim 1 , wherein the first contact is disposed between the first conductive pillar and the conductive layer. 10 . The memory device as claimed in claim 1 , wherein the first conductive pillar is a single-layer structure or a multi-layer structure.

11. The memory element of claim 1 , further comprising: A contact pad is disposed on the first conductive column. 12 . The memory device as claimed in claim 11 , wherein the contact pad and the first conductive pillar are made of different conductive materials. 13 . The memory element as claimed in claim 12 , wherein a resistivity of the contact pad is smaller than a resistivity of the first conductive pillar.

14. The memory element of claim 11, further comprising: A second contact is disposed on the contact pad and between the capacitor and the contact pad. 15 . The memory device as claimed in claim 14 , wherein the capacitor is electrically connected to the active region through the second contact, the contact pad, the first conductive pillar, the first contact and the conductive layer.

16. A memory element comprising: A semiconductor substrate, defining a first active region and a second active region; a gate structure adjacent to the first active region and the second active region and recessed from a first surface of the semiconductor substrate into the semiconductor substrate; a doped component extending into the semiconductor substrate and surrounded by the first active region; a conductive layer comprising a first portion extending from the first surface of the semiconductor substrate into the semiconductor substrate, and a second portion disposed on the doped component and coupled to the first portion; a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped component and the first active region of the semiconductor substrate, and a second insulating layer disposed on the gate structure, wherein the first insulating layer and the second insulating layer are separated from each other; a first contact and a second contact disposed on the conductive layer and surrounded by a first dielectric layer; and A first conductive column and a second conductive column are disposed on the first dielectric layer. The first portion of the conductive layer is disposed between the gate structure and the doped component. 17 . The memory device of claim 16 , wherein the gate structure comprises a gate electrode and a gate oxide surrounding the gate electrode.

18. The memory device of claim 16, wherein the doped component is disposed between the first insulating layer and the second portion of the conductive layer.

19. The memory device as claimed in claim 16, wherein the doped component is surrounded by the first insulating layer and the conductive layer.

20. The memory device of claim 16, wherein the first portion of the conductive layer contacts the doped component.

Images