Semiconductor element

Abstract

The invention provides a semiconductor element. The semiconductor element comprises a substrate; the first word line dielectric layer is located in the substrate and comprises a U-shaped profile; a first bottom conductive layer on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer; a first top conductive layer on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer; a first capping layer passing through the first top conductive layer and extending to the first bottom conductive layer; and a plurality of first spacers on the first top conductive layer and laterally surrounding the first capping layer. The first word line dielectric layer, the first bottom conductive layer, the first top conductive layer, and the first capping layer together form a first word line structure.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 2024103435545, filed on March 25, 2024, with the invention title of "Semiconductor Element and Its Manufacturing Method". Application No. 2024103435545 claims the priority and benefits of U.S. Provisional Application No. 18 / 531,977, filed on December 7, 2023, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element and a method of manufacturing the same. In particular, it relates to a semiconductor element having bottom and top conductive layers. Background Art

[0003] Semiconductor elements have been used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor elements has been continuously miniaturized to meet the growing demand for computing power. However, various problems occur during the miniaturization process, and such problems are continuously increasing. Therefore, there are still challenges in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is provided only for background information and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure, does not form the prior art of the present disclosure, and any description of the above "prior art" should not be taken as any part of this case. Summary of the Invention

[0005] One aspect of the present disclosure provides a semiconductor element, comprising: a substrate; and a first word line structure, comprising: a first word line dielectric layer located in the substrate and having a U-shaped cross-sectional profile, a first bottom conductive layer located on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer, a first top conductive layer located on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer, and a first capping layer. The first capping layer includes a bottom portion passing through the first top conductive layer and extending to the first bottom conductive layer, and a top portion located on the bottom portion and laterally surrounded by the first word line dielectric layer.

[0006] Another aspect of the present disclosure provides a semiconductor device, comprising: a substrate; a first word line dielectric layer located in the substrate and including a U-shaped cross-sectional profile; a first bottom conductive layer located on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer; a first top conductive layer located on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer; a first capping layer passing through the first top conductive layer and extending to the first bottom conductive layer; and a plurality of first spacers located on the first top conductive layer and laterally surrounding the first capping layer. The first word line dielectric layer, the first bottom conductive layer, the first top conductive layer, and the first capping layer together constitute a first word line structure.

[0007] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate and forming a first trench in the substrate, and conformally forming a first dielectric material layer in the first trench; forming a first bottom conductive layer on the first dielectric material layer and within the first trench, and forming a first top conductive layer on the first bottom conductive layer and within the first trench; conformally forming a spacer material layer on the first top conductive layer and the first dielectric material layer; performing a punch-through process to transform the spacer material layer into a plurality of first spacers attached to the first dielectric material layer, thereby forming a first inner trench that separates the first spacers and partially exposes the first top conductive layer; deepening the first inner trench to form a first extended inner trench that passes through the first top conductive layer and extends to the first bottom conductive layer; removing the first spacers and forming a capping material layer to completely fill the first trench; and performing a planarization process to transform the first dielectric material layer into a first word line dielectric layer and the capping material layer into a first capping layer. The first word line dielectric layer, the first bottom conductive layer, the first top conductive layer, and the first capping layer together constitute a first word line structure.

[0008] Due to the design of the semiconductor device of the present disclosure, problems such as line-end swing can be alleviated by replacing a part of the first top conductive layer with the bottom portion of the first capping layer. Additionally, the first bottom conductive layer and the first top conductive layer composed of materials with different work functions can be utilized to minimize gate-induced drain leakage.

[0009] The technical features and advantages of the present disclosure have been outlined above quite extensively, enabling a better understanding of the following detailed description of the present disclosure. Other technical features and advantages that form the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily utilized as a basis for modifying or designing other structures or processes to achieve the same objectives as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure can be obtained by reference to the detailed description and the claims when considered in conjunction with the drawings, in which like reference symbols represent like elements throughout the drawings, and:

[0011] Figure 1 A method for fabricating a semiconductor device is shown in the form of a flowchart according to an embodiment of the present disclosure.

[0012] Figures 2 to 16 Cross-sectional schematic views showing the process of fabricating a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 17 Cross-sectional schematic views showing a semiconductor device according to another embodiment of the present disclosure.

[0014] Figure 18 and Figure 19 Cross-sectional schematic views showing a partial process of fabricating a semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 20 Cross-sectional schematic views showing a semiconductor device according to another embodiment of the present disclosure.

[0016] Wherein, the reference numerals are explained as follows:

[0017] 1A: Semiconductor device

[0018] 1B: Semiconductor device

[0019] 1C: Semiconductor device

[0020] 1D: Semiconductor device

[0021] 10: Method

[0022] 101: Substrate

[0023] 103: Isolation layer

[0024] 105: Impurity region

[0025] 105-1: Source region

[0026] 105 - 3: Drain region

[0027] 107: Bottom dielectric layer

[0028] 200: First character line structure

[0029] 200 - BS: Bottom surface

[0030] 201: First character line dielectric layer

[0031] 201TS: Top surface

[0032] 203: First bottom conductive layer

[0033] 203TS: Top surface

[0034] 205: First top conductive layer

[0035] 205TS: Top surface

[0036] 207: First covering layer

[0037] 207TS: Top surface

[0038] 207 - 1: Bottom part

[0039] 207 - 3: Top part

[0040] 300: Second character line structure

[0041] 300 - BS: Bottom surface

[0042] 301: Second character line dielectric layer

[0043] 303: Second bottom conductive layer

[0044] 303TS: Top surface

[0045] 305: Second top conductive layer

[0046] 305TS: Top surface

[0047] 307: Second covering layer

[0048] 307 - 1: Bottom part

[0049] 307 - 3: Top part

[0050] 411: First bottom barrier layer

[0051] 411TS: Top surface

[0052] 413: First intermediate barrier layer

[0053] 421: Second bottom barrier layer

[0054] 421TS: Top surface

[0055] 423: Second intermediate barrier layer

[0056] 431: First thickening layer

[0057] 431TS: Top surface

[0058] 441: Second thickening layer

[0059] 511: First spacer

[0060] 511TS: Top surface

[0061] 521: Second spacer

[0062] 531: First inner groove

[0063] 533: First extended inner groove

[0064] 541: Second inner groove

[0065] 543: Second extended inner groove

[0066] 711: First dielectric material

[0067] 711TS: Top surface

[0068] 713: First insulating material

[0069] 721: First barrier material

[0070] 723: Second barrier material

[0071] 731: First conductive material

[0072] 733: Second conductive material

[0073] 741: Spacer material

[0074] 751: Covering material

[0075] 811: First mask layer

[0076] AA: Active area

[0077] S11: Step

[0078] S13: Step

[0079] S15: Step

[0080] S17: Step

[0081] S19: Step

[0082] TR1: Groove

[0083] TR2: Groove

[0084] W1: Width

[0085] W2: Width

[0086] W3: Width

[0087] W4: Width

[0088] Z: Direction Detailed Implementation Manner

[0089] The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present disclosure. The following describes examples of specific elements and their arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and should not limit the scope of the embodiments of the present disclosure. For example, when it is mentioned in the description that the first component is formed "on" or "above" the second component, it may include embodiments where the first component is in direct contact with the second component, and may also include embodiments where there are other components formed between the two without direct contact. Additionally, the present disclosure may repeat reference signs and / or markings in different embodiments. These repetitions are for the purpose of simplification and clarity, and are not used to define the relationship between the different embodiments and / or structures being discussed.

[0090] Furthermore, spatial-related terms are used herein, such as: "below", "beneath", "lower", "above", "higher", and their like, to facilitate the description of the relationship between one element or component shown in the drawings and another element or component. These spatial relationship terms are used to cover different orientations of the elements during use or operation outside the orientation depicted in the drawings. The element may be turned to a different orientation (rotated 90 degrees or other orientations), and the spatial-related adjectives used therein can be interpreted in the same way accordingly.

[0091] It should be understood that when an element or layer is referred to as "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer, or there may be intermediate elements or layers.

[0092] It should be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of the present disclosure, the first element, the first component, or the first part discussed below may be referred to as the second element, the second component, or the second part.

[0093] Unless otherwise indicated by the context, when this document refers to orientations, layouts, positions, shapes, dimensions, quantities, or other measures using terms such as "same", "equal", "planar", or "coplanar", it does not necessarily mean exactly the same orientation, layout, position, shape, dimension, quantity, or other measure, but is intended to cover orientations, layouts, positions, shapes, dimensions, quantities, or other measures that are nearly the same within an acceptable range of variation, such as those resulting from manufacturing processes. The term "substantially" may be used in this document to reflect this meaning. For example, an item described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable range of variation, such as those resulting from manufacturing processes.

[0094] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0095] It should be noted that in the description of the present disclosure, "above" or "up" corresponds to the arrow direction of the Z direction, and "below" or "down" corresponds to the opposite arrow direction of the Z direction.

[0096] Figure 1 A method 10 for preparing a semiconductor element 1A is shown in the form of a flowchart according to an embodiment of the present disclosure. Figures 2 to 16 A cross-sectional schematic diagram showing the process of preparing a semiconductor element 1A is shown according to an embodiment of the present disclosure.

[0097] Refer to Figures 1 to 3 , in step S11, a substrate 101 may be provided, an isolation layer 103 may be formed in the substrate 101 to define an active region AA, a plurality of first trenches TR1 may be formed in the active region AA, and a plurality of second trenches TR2 may be formed in the isolation layer 103.

[0098] Refer to Figure 2 , the substrate 101 may include a bulk semiconductor substrate. The bulk semiconductor substrate may include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors; or combinations thereof.

[0099] Refer to Figure 2, an isolation layer 103 can be formed in the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A lithography process and subsequent etching processes, such as anisotropic dry etching processes, can be performed to form trenches that penetrate the pad oxide layer, the pad nitride layer, and extend into the substrate 101. An insulating material can be deposited into the trenches and a planarization process, such as chemical mechanical polishing, can be subsequently performed until the top surface of the substrate 101 is exposed to remove excess fill material, providing a substantially planar surface for subsequent processing steps and simultaneously forming the isolation layer 103. The insulating material can be, for example, silicon oxide or other applicable insulating materials. In some embodiments, the isolation layer 103 can define an active region AA in the substrate 101.

[0100] Referring to Figure 2 , an impurity region 105 can be formed in the active region AA. In some embodiments, a p-type dopant or an n-type dopant can be used to form the impurity region 105 through an implantation process. The term "p-type dopant" refers to an impurity that creates valence electron defects when added to an intrinsic semiconductor material. In a silicon-containing semiconductor material, examples of p-type dopants include, but are not limited to, boron, aluminum, gallium, or indium. The term "n-type dopant" refers to an impurity that contributes free electrons to the intrinsic semiconductor material when added to the intrinsic semiconductor material. In a silicon-containing material, examples of n-type dopants include, but are not limited to, antimony, arsenic, or phosphorus.

[0101] Referring to Figure 2 , a bottom dielectric layer 107 can be formed on the substrate 101 to completely cover the impurity region 105 and the isolation layer 103. In some embodiments, the bottom dielectric layer 107 can include a material that has an etching selectivity with respect to the substrate 101 and the isolation layer 103. In some embodiments, the bottom dielectric layer 107 can include, for example, silicon nitride, boron nitride, boron silicon nitride, boron phosphorus nitride, silicon carbon boron nitride, or a combination of the foregoing. In some embodiments, the bottom dielectric layer 107 can include, for example, silicon nitride. In some embodiments, the fabrication technique of the bottom dielectric layer 107 can include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes.

[0102] Referring to Figure 2, a first mask layer 811 can be formed on the bottom dielectric layer 107. In some embodiments, the first mask layer 811 can be a photoresist layer and can include patterns of a plurality of first trenches TR1 and a plurality of second trenches TR2.

[0103] Referring to Figure 3 , the first mask layer 811 can be used as a mask to perform a trench etching process to remove portions of the bottom dielectric layer 107, the isolation layer 103, and the substrate 101, and at the same time form the first trenches TR1 in the substrate and the second trenches TR2 in the isolation layer 103. In some embodiments, the first trenches TR1 can be shallower than the second trenches TR2.

[0104] After forming the trenches TR1, TR2, the first mask layer 811 can be removed. The impurity region 105 can be divided into a source region 105-1 and two drain regions 105-3. The drain regions 105-3 can be formed between the isolation layer 103 and the first trenches TR1. The source region 105-1 can be formed between the first trenches TR1. In a cross-sectional perspective view, the bottom dielectric layer 107 can be divided into a plurality of segments.

[0105] Referring to Figure 1 and Figures 4 to 10 , in step S13, a layer of first dielectric material 711 can be conformally formed in the first trenches TR1 and the second trenches TR2, a plurality of first bottom conductive layers 203 and a plurality of second bottom conductive layers 303 can be formed on the layer of first dielectric material 711, and a plurality of first top conductive layers 205 and a plurality of second top conductive layers 305 can be formed on the first bottom conductive layers 203 and the second bottom conductive layers 303.

[0106] Referring to Figure 4 , the layer of first dielectric material 711 can be conformally formed on the bottom dielectric layer 107 and in the first trenches TR1 and the second trenches TR2. The layer of first dielectric material 711 can have a U-shaped cross-sectional profile within the trenches TR1, TR2. That is, the layer of first dielectric material 711 can be conformally formed along the surfaces of the trenches TR1, TR2. In some embodiments, the thickness of the layer of first dielectric material 711 can be in the range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0107] In some embodiments, the fabrication technique of the first dielectric material layer 711 may include a deposition process such as chemical vapor deposition or atomic layer deposition. In some embodiments, after depositing a liner polysilicon layer (not shown for clarity), the first dielectric material layer 711 may be formed by radical oxidation of the liner polysilicon layer. In some embodiments, after forming a liner silicon nitride layer (not shown for clarity), the first dielectric material layer 711 may be formed by radical oxidation of the liner silicon nitride layer. In some embodiments, the first dielectric material 711 may include a material having etch selectivity to the bottom dielectric layer 107 and the substrate 101. In some embodiments, the first dielectric material 711 may include a high-k dielectric material, an oxide (e.g., silicon oxide), a nitride, a oxynitride, or a combination of the foregoing.

[0108] In some embodiments, the high-k dielectric material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination of the foregoing. In some embodiments, the high-k dielectric material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination of the foregoing.

[0109] Referring to Figure 5 , a layer of first barrier material 721 may be conformally formed on the first dielectric material layer 711. In some embodiments, the first barrier material 721 may be, for example, titanium nitride, titanium, or a combination of the foregoing. In some embodiments, the first barrier material layer 721 may be, for example, titanium nitride. In some embodiments, the fabrication technique of the first barrier material layer 721 may include, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other applicable deposition processes.

[0110] Referring to Figure 5, a first conductive material 731 can be formed on the first barrier material 721 layer and completely fill the trenches TR1 and TR2. In some embodiments, the first conductive material 731 can be, for example, tungsten, cobalt, zirconium, tantalum, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), transition metal aluminides, titanium nitride, or a combination of the foregoing. In some embodiments, the first conductive material 731 can be, for example, tungsten or titanium nitride. In some embodiments, the fabrication technique for the first conductive material 731 layer can include, for example, physical vapor deposition, sputtering, electroplating, electroless plating, chemical vapor deposition, or other applicable deposition processes. In some embodiments, the first barrier material 721 layer can be optional. That is, the first conductive material 731 layer can be formed on the first dielectric material 711 layer and completely fill the trenches TR1 and TR2.

[0111] Referring to Figure 6 , a etch-back process can be performed to remove a portion of the first barrier material 721 and the first conductive material 731. After the etch-back process, the remaining first barrier material 721 is transformed into a plurality of first bottom barrier layers 411 and a plurality of second bottom barrier layers 421. The first bottom barrier layers 411 can be formed on the first dielectric material 711 layer and within the first trenches TR1. The second bottom barrier layers 421 can be formed on the first dielectric material 711 layer and within the second trenches TR2.

[0112] The remaining first conductive material 731 is transformed into a plurality of first bottom conductive layers 203 and a plurality of second bottom conductive layers 303. The first bottom conductive layers 203 can be formed on the first bottom barrier layers 411 and within the first trenches TR1. The second bottom conductive layers 303 can be formed on the second bottom barrier layers 421 and within the second trenches TR2.

[0113] For the sake of brevity, clarity, and convenience of description, only one layer of the first bottom barrier layer 411, one layer of the second bottom barrier layer 421, one layer of the first bottom conductive layer 203, and one layer of the second bottom conductive layer 303 are described.

[0114] Referring to Figure 6 , in some embodiments, the top surface 203TS of the first bottom conductive layer 203, the top surface 303TS of the second bottom conductive layer 303, the top surface 411TS of the first bottom barrier layer 411, and the top surface 421TS of the second bottom barrier layer 421 can be substantially coplanar. In some embodiments, the top surface 203TS of the first bottom conductive layer 203, the top surface 303TS of the second bottom conductive layer 303, the top surface 411TS of the first bottom barrier layer 411, and the top surface 421TS of the second bottom barrier layer 421 can be at different vertical levels (not shown).

[0115] In some embodiments, the thickness of the first dielectric material layer 711 attached to the bottom dielectric layer 107 may be reduced due to consumption during the etch-back and / or post-etch cleaning process. Accordingly, those portions of the first dielectric material layer 711 are ultimately thinner than other portions of the first dielectric material layer 711.

[0116] Referring to Figure 7 , a second barrier material layer 723 may be formed on the top surface 711TS of the first dielectric material layer 711 and within the trenches TR1, TR2. The second barrier material layer 723 formed within the first trench TR1 may be referred to as the first intermediate barrier layer 413 and may be formed on the first bottom conductive layers 203. The second barrier material layer 723 formed within the second trench TR2 may be referred to as the second intermediate barrier layer 423 and may be formed on the second bottom conductive layers 303. For simplicity, clarity, and convenience of description, only one first intermediate barrier layer 413 and one second intermediate barrier layer 423 are described.

[0117] In some embodiments, the first intermediate barrier layer 413 may also cover the first bottom barrier layer 411. The second intermediate barrier layer 423 may also cover the second bottom barrier layer 421. That is, in a cross-sectional perspective view, the first bottom conductive layer 203 may be surrounded by the first bottom barrier layer 411 and the first intermediate barrier layer 413. In a cross-sectional perspective view, the second bottom conductive layer 303 may be surrounded by the second bottom barrier layer 421 and the second intermediate barrier layer 423.

[0118] In some embodiments, the second barrier material 723 (i.e., the first intermediate barrier layer 413 and the second intermediate barrier layer 423) may be, for example, titanium nitride, titanium, or a combination of the foregoing. In some embodiments, the second barrier material 723 may be, for example, titanium nitride. In some embodiments, the second barrier material 723 may be the same material as the first bottom barrier layer 411. In some embodiments, the fabrication technique for the second barrier material layer 723 may include, for example, radio-frequency physical vapor deposition, or other applicable deposition processes. In some embodiments, the second barrier material layer 723 may be optional. That is, subsequent layers may be formed directly on the first bottom conductive layer 203 or the second bottom conductive layer 303.

[0119] Referring to Figure 8, a layer of first insulating material 713 can be conformally formed on the layer of first dielectric material 711, bottom dielectric layer 107, the layer of second barrier material 723, the first intermediate barrier layers 413, and the second intermediate barrier layers 423. In some embodiments, due to being conformal with the layer of first dielectric material 711, first intermediate barrier layers 413, and second intermediate barrier layers 423, the layer of first insulating material 713 formed within trenches TR1, TR2 may exhibit a U-shaped cross-sectional profile. In some embodiments, the first insulating material 713 can be, for example, a material having an etch selectivity with respect to the bottom dielectric layer 107. In some embodiments, the first dielectric material 711 and the first insulating material 713 can include the same material. In some embodiments, the first insulating material 713 can be, for example, silicon oxide. In some embodiments, the fabrication technique for the layer of first insulating material 713 can include, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. In some embodiments, the layer of first insulating material 713 can be optional. That is, subsequent layers can be directly formed on the first bottom conductive layer 203 or the second bottom conductive layer 303.

[0120] Referring to Figure 9 , a layer of second conductive material 733 can be formed on the layer of first insulating material 713 and completely fill trenches TR1, TR2. In some embodiments, the second conductive material 733 can be, for example, polysilicon, polycrystalline germanium, polysilicon germanium, doped polysilicon, doped polycrystalline germanium, doped polysilicon germanium, or a combination of the foregoing. In some embodiments, the layer of second conductive material 733 can be doped with a p-type dopant or an n-type dopant. In some embodiments, the fabrication technique for the layer of second conductive material 733 can include, for example, chemical vapor deposition, or other applicable deposition processes. In some embodiments, doping can be achieved through an implantation process after the deposition process. In some embodiments, doping can be performed by incorporating dopants during the deposition process.

[0121] Referring to Figure 10 , a back-etching process can then be performed to remove a portion of the second conductive material 733 to form a plurality of first top conductive layers 205 and a plurality of second top conductive layers 305. For the sake of brevity, clarity, and convenience of description, only one layer of first top conductive layer 205 and one layer of second top conductive layer 305 are described.

[0122] The first top conductive layer 205 can be formed on the layer of first insulating material 713 and within the first trench TR1.

[0123] The second top conductive layer 305 may be formed on the first insulating material 713 of the layer and within the second trench TR2. In some embodiments, the top surface 205TS of the first top conductive layer 205 and the top surface 305TS of the second top conductive layer 305 may be substantially coplanar.

[0124] Referring Figure 1 , Figure 11 and Figure 12 , in step S15, a plurality of first spacers 511 may be formed on the first top conductive layers 205, thereby forming a plurality of first inner trenches 531, and a plurality of second spacers 521 may be formed on the second top conductive layers 305, thereby forming a plurality of second inner trenches 541.

[0125] Referring Figure 11 , a layer of spacer material 741 may be conformally formed on the first insulating material 713 of the layer, the first top conductive layers 205, and the second top conductive layers 305. The trenches TR1, TR2 are not completely filled with the layer of spacer material 741. In some embodiments, the spacer material 741 may include a material having an etching selectivity with respect to the first top conductive layer 205 and the second top conductive layer 305. In some embodiments, the spacer material 741 may include a material having an etching selectivity with respect to the first top conductive layer 205, the first insulating material 713, and / or the first dielectric material 711. In some embodiments, the spacer material 741 may include, for example, silicon nitride. In some embodiments, the fabrication technique of the layer of spacer material 741 may include, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes.

[0126] Referring Figure 12 , a punch-through process may be performed to remove a portion of the spacer material 741. In some embodiments, the punch-through process may be an anisotropic etching process, such as an anisotropic dry etching process. After the punch-through process, the remaining spacer material 741 in the first trench TR1 may be referred to as a plurality of first spacers 511. A first inner trench 531 may be formed between adjacent pairs of the first spacers 511. The top surface 205TS of the first top conductive layer 205 may be partially exposed through the first inner trench 531. The remaining spacer material 741 in the second trench TR2 may be referred to as a plurality of second spacers 521. A second inner trench 541 may be formed between adjacent pairs of the second spacers 521. The top surface 305TS of the second top conductive layer 305 may be partially exposed through the second inner trench 541.

[0127] Referring Figure 1 and Figure 13, in step S17, the first inner grooves 531 and the second inner grooves 541 can be deepened to form a plurality of first extended inner grooves 533 and a plurality of second extended inner grooves 543, which partially expose the first bottom conductive layer 203 and the second bottom conductive layer 303.

[0128] Referring to Figure 13 , the deepening of the first inner grooves 531 and the second inner grooves 541 can be achieved by an anisotropic etching process using the first spacers 511 and the second spacers 521 as masks. For example, an anisotropic dry etching process can facilitate such deepening. In some embodiments, the anisotropic etching process can be a multi-stage etching process, where different stages use different etching chemicals to selectively remove the target layer.

[0129] For the sake of brevity, clarity, and convenience of description, only one layer of the first extended inner grooves 533 and one layer of the second extended inner grooves 543 are described.

[0130] Referring to Figure 13 , the first inner groove 531 is deepened to form a first extended inner groove 533, which passes through the first top conductive layer 205, the layer of the first insulating material 713, the first intermediate barrier layer 413, and extends downward to the first bottom conductive layer 203. Similarly, the second extended inner groove 543 cuts through the second top conductive layer 305, the layer of the first insulating material 713, the second intermediate barrier layer 423, and reaches the second bottom conductive layer 303. Accordingly, both the first top conductive layer 205 and the first intermediate barrier layer 413 are divided into two segments by the first extended inner groove 533. Similarly, the second top conductive layer 305 and the second intermediate barrier layer 423 are each divided into two segments by the second extended inner groove 543. The layer of the first insulating material 713 is segmented by the first extended inner groove 533 and the second extended inner groove 543, while the first bottom conductive layer 203 and the second bottom conductive layer 303 are partially exposed through the first extended inner groove 533 and the second extended inner groove 543.

[0131] Referring to Figure 1 and Figures 14 to 16 , in step S19, the first trenches TR1 and the second trenches TR2 can be completely filled to form a plurality of first cover layers 207 and a plurality of second cover layers 307.

[0132] Referring to Figure 14 , the first spacers 511 and the second spacers 521 can be selectively removed. After removing the first spacers 511 and the second spacers 521, when observed in cross-section, both the first extended inner groove 533 and the second extended inner groove 543 can present a T-shaped space. Specifically, the higher portion of the first extended inner groove 533 or the second extended inner groove 543 is wider than its respective lower portion.

[0133] Referring to Figure 15 , a covering material 751 can be formed to completely fill the first extended inner groove 533 and the second extended inner groove 543, thereby also filling the grooves TR1 and TR2. In some embodiments, the covering material 751 can be, for example, a material having an etching selectivity with respect to the first insulating material 713 and the first dielectric material 711. In some embodiments, the covering material 751 can be, for example, silicon nitride, boron nitride, borosilicon nitride, boron phosphide nitride, silicon carbon boron nitride, or a combination of the foregoing. In some embodiments, the covering material 751 can be, for example, silicon nitride. In some embodiments, the fabrication technique for the layer of covering material 751 can include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes.

[0134] Referring to Figure 16 , a planarization process such as chemical mechanical polishing can be performed until the isolation layer 103 (or the substrate 101) is exposed to remove the excess material and provide a substantially flat surface for subsequent processing steps. After the planarization process, the first dielectric material 711 remaining in the first groove TR1 can be referred to as the first word line dielectric layer 201. The first dielectric material 711 remaining in the second groove TR2 can be referred to as the second word line dielectric layer 301. The first insulating material 713 remaining in the first groove TR1 can be referred to as the first thickening layer 431. The first insulating material 713 remaining in the second groove TR2 can be referred to as the second thickening layer 441. The covering material 751 remaining in the first groove TR1 can be referred to as the first covering layer 207. The covering material 751 remaining in the second groove TR2 can be referred to as the second covering layer 307.

[0135] The first word line dielectric layer 201, the first bottom conductive layer 203, the first top conductive layer 205, and the first covering layer 207 together constitute the first word line structure 200. The second word line dielectric layer 301, the second bottom conductive layer 303, the second top conductive layer 305, and the second covering layer 307 together constitute the second word line structure 300. In some embodiments, the bottom surface 200-BS of the first word line structure 200 can be shallower than the bottom surface 300-BS of the second word line structure 300.

[0136] Referring to Figure 16, the first cover layer 207 may have a T-shaped cross-sectional profile that is conformal to the profile of the first extended inner trench 533. The first cover layer 207 may include a bottom portion 207-1 and a top portion 207-3. The bottom portion 207-1 may penetrate the first top conductive layer 205 and the first intermediate barrier layer 413 and extend downward to the first bottom conductive layer 203. The top portion 207-3 located above the bottom portion 207-1 may be supported on the bottom portion 207-1 and the first top conductive layer 205 and may be laterally surrounded by the first thickening layer 431. In some embodiments, the width W1 of the top portion 207-3 may be greater than the width W2 of the bottom portion 207-1. Similarly, the second cover layer 307 may have a similar structure, having a bottom portion 307-1 and a top portion 307-3 similar to those of the first cover layer 207, and further details of these components will not be repeated here for the sake of brevity. In some embodiments, the width ratio of the width W1 of the top portion 207-3 to the width W2 of the bottom portion 207-1 may be between about 4.0 and about 1.5.

[0137] In some embodiments, the first bottom conductive layer 203 and the first top conductive layer 205 may include materials having different work functions, thereby effectively reducing gate-induced drain leakage in the first word line structure 200. In addition, replacing a part of the first top conductive layer 205 with the bottom portion 207-1 of the first cover layer 207 may help alleviate problems such as line-end swing. Furthermore, combining the first thickening layer 431 may enhance the insulating ability of the first word line dielectric layer 201 by increasing its thickness. This is particularly advantageous because the first word line dielectric layer 201 may be prone to being consumed during processes such as back etching or cleaning, which may in turn lead to gate-induced drain leakage.

[0138] Figure 17 A cross-sectional schematic view of a semiconductor element 1B is shown according to another embodiment of the present disclosure.

[0139] Referring to Figure 17 , the semiconductor element 1B may have a structure similar to Figure 16 as shown. Figure 17 Those elements that are the same or similar in Figure 16 have been denoted by the same reference numerals, and repeated descriptions have been omitted.

[0140] For the semiconductor element 1B, a planarization process as shown in Figure 16 may be performed until the bottom dielectric layer 107 is exposed, such that the bottom dielectric layer 107 may be completely or only partially removed. Thus, the first word line dielectric layer 201 (or the second word line dielectric layer 301) may be laterally surrounded by the bottom dielectric layer 107. As in Figure 16Compared with that shown, the top portion 207-3 (or the top portion 307-3) can be thicker along the direction Z. The bottom dielectric layer 107 can serve as a buffer layer, a protective layer, or an etch stop layer for subsequent processes.

[0141] Figure 18 and Figure 19 A cross-sectional schematic diagram showing a part of the process for fabricating a semiconductor device 1C according to another embodiment of the present disclosure.

[0142] Referring to Figure 18 ,an intermediate semiconductor device can be fabricated through steps similar to those Figure 13 shown. A covering material layer 751 can be formed to fill the first trench TR1 and the second trench TR2 through steps similar to those Figure 15 shown, and its description will not be repeated here. It should be noted that the first spacers 511 and the second spacers 521 are not removed before depositing the covering material 751.

[0143] Referring to Figure 19 ,a planarization process can be performed as Figure 16 shown, and its description will not be repeated here. In the semiconductor device 1C, the first covering layer 207 can have a linear cross-sectional profile. The higher part of the first covering layer 207 can be laterally surrounded by the first spacers 511. In some embodiments, the top surface 511TS of the first spacers 511, the top surface 207TS of the first covering layer 207, the top surface 431TS of the first thickening layer 431, and the top surface 201TS of the first word line dielectric layer 201 can be substantially coplanar. Similarly, the second covering layer 307 can have a structure similar to that of the first covering layer 207, and for the sake of brevity, further details will not be repeated here. In some embodiments, the width ratio of the width W3 of the first covering layer 207 to the width W4 of the first bottom conductive layer 203 can be between about 0.20 and about 0.80.

[0144] Figure 20 A cross-sectional schematic diagram showing a semiconductor device 1D according to another embodiment of the present disclosure.

[0145] Referring to Figure 20 ,the semiconductor device 1D can have a structure similar to that Figure 19 shown. Figure 20 Elements that are the same or similar in Figure 19 have been denoted by the same reference numerals, and the repeated description has been omitted.

[0146] For the semiconductor device 1D, a process can be performed as Figure 16The planarization process shown until the bottom dielectric layer 107 is exposed, such that the bottom dielectric layer 107 can be completely or only partially removed. Thus, the first word line dielectric layer 201 (or the second word line dielectric layer 301) can be laterally surrounded by the bottom dielectric layer 107. As compared with Figure 19 that shown, the first capping layer 207 (or the second capping layer 307) can be thicker along the Z direction. The bottom dielectric layer 107 can serve as a buffer layer, a protective layer, or an etch stop layer for subsequent processes.

[0147] One aspect of the present disclosure provides a semiconductor device, comprising: a substrate; and a first word line structure, comprising: a first word line dielectric layer located in the substrate and comprising a U-shaped cross-sectional profile, a first bottom conductive layer located on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer, a first top conductive layer located on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer, and a first capping layer. The first capping layer comprises a bottom portion passing through the first top conductive layer and extending to the first bottom conductive layer, and a top portion located on the bottom portion and laterally surrounded by the first word line dielectric layer.

[0148] Another aspect of the present disclosure provides a semiconductor device, comprising: a substrate; a first word line dielectric layer located in the substrate and comprising a U-shaped cross-sectional profile; a first bottom conductive layer located on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer; a first top conductive layer located on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer; a first capping layer passing through the first top conductive layer and extending to the first bottom conductive layer; and a plurality of first spacers located on the first top conductive layer and laterally surrounding the first capping layer. The first word line dielectric layer, the first bottom conductive layer, the first top conductive layer, and the first capping layer together form a first word line structure.

[0149] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, which includes: providing a substrate and forming a first trench in the substrate, and conformally forming a first dielectric material layer in the first trench; forming a first bottom conductive layer on the first dielectric material layer and in the first trench, and forming a first top conductive layer on the first bottom conductive layer and in the first trench; conformally forming a spacer material layer on the first top conductive layer and the first dielectric material layer; performing a punch-through process to transform the spacer material layer into a plurality of first spacers attached to the first dielectric material layer, thereby forming a first inner trench that separates the first spacers and partially exposes the first top conductive layer; deepening the first inner trench to form a first extended inner trench that penetrates the first top conductive layer and extends to the first bottom conductive layer; removing the first spacers and forming a covering material layer to completely fill the first trench; and performing a planarization process to transform the first dielectric material layer into a first word-line dielectric layer and transform the covering material layer into a first covering layer. The first word-line dielectric layer, the first bottom conductive layer, the first top conductive layer, and the first covering layer together constitute a first word-line structure.

[0150] Due to the design of the semiconductor device of the present disclosure, problems such as line-end swing can be alleviated by replacing a part of the first top conductive layer 205 with the bottom part 207-1 of the first covering layer 207. Additionally, the first bottom conductive layer 203 and the first top conductive layer 205 composed of materials with different work functions can be utilized to minimize gate-induced drain leakage current. Furthermore, the integration of the first thickening layer 431 can enhance the insulation ability of the first word-line dielectric layer 201 by increasing its thickness. This enhancement is particularly advantageous because the first word-line dielectric layer 201 may be easily depleted during processes such as back-etching or cleaning, which in turn exacerbates the gate-induced drain leakage current.

[0151] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations of the foregoing.

[0152] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor element, comprising: a substrate; A first word line dielectric layer disposed in the substrate and comprising a U-shaped cross-sectional profile; a first bottom conductive layer located on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer; a first top conductive layer on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer; a first covering layer passing through the first top conductive layer and extending to the first bottom conductive layer; as well as a plurality of first spacers located on the first top conductive layer and laterally surrounding the first cover layer, The first word line dielectric layer, the first bottom conductive layer, the first top conductive layer, and the first covering layer together form a first word line structure. 2 . The semiconductor device as claimed in claim 1 , wherein a top surface of the first capping layer, a top surface of the first word line dielectric layer, and top surfaces of the plurality of first spacers are substantially coplanar. 3 . The semiconductor device of claim 1 , wherein a width ratio of a width of the first capping layer to a width of the first bottom conductive layer is between about 0.20 and about 0.

80. 4 . The semiconductor device as claimed in claim 2 , further comprising a first bottom barrier layer located between the first bottom conductive layer and the first word line dielectric layer. 5 . The semiconductor device as claimed in claim 2 , further comprising a first intermediate barrier layer located between the first bottom conductive layer and the first top conductive layer, wherein the first capping layer penetrates the first intermediate barrier layer.

6. The semiconductor device as described in claim 2 comprises a first thickening layer, which is located between the first top conductive layer and the first bottom conductive layer, between the first top conductive layer and the first word line dielectric layer, and between the first word line dielectric layer and the plurality of first spacers, wherein the first covering layer penetrates the first thickening layer. 7 . The semiconductor device as claimed in claim 2 , further comprising a source region and a drain region located in the substrate, wherein the first word line structure is located between the source region and the drain region. 8 . The semiconductor device as claimed in claim 2 , further comprising an isolation layer disposed in the substrate to define an active region, wherein the first word line structure is disposed in the active region. 9 . The semiconductor device as claimed in claim 8 , further comprising a second word line structure located in the isolation layer. 10 . The semiconductor device as claimed in claim 9 , wherein a bottom surface of the first word line structure is narrower than a bottom surface of the second word line structure.

11. The semiconductor device of claim 3, wherein the first bottom conductive layer comprises tungsten, cobalt, zirconium, tantalum, aluminum, ruthenium, copper, metal carbide, transition metal aluminide, or a combination thereof. 12 . The semiconductor device of claim 3 , wherein the first top conductive layer comprises polysilicon, polygermanium, polysilicon germanium, doped polysilicon, doped polygermanium, doped polysilicon germanium, or a combination thereof.

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