An IGBT chip structure and manufacturing method

Abstract

The present invention discloses an IGBT chip structure and a manufacturing method, belonging to the technical field of semiconductor devices. It includes a chip body, a diamond layer, and a collector metal layer. A porous two-dimensional network with dense middle and sparse periphery is etched on the diamond layer. Metal aluminum is arranged in the through holes of the porous two-dimensional network, and the metal aluminum is connected with the chip body and the collector metal layer to form a conduction path. By adding a diamond layer with a porous two-dimensional network between the chip body and the collector metal layer, the present invention enhances the heat dissipation capacity of the chip by utilizing the high thermal conductivity characteristic of diamond. At the same time, the metal aluminum in the pores of the porous two-dimensional network is used to achieve ohmic contact between the back metal and the chip body, meeting the electrical connection requirements of the IGBT chip application working conditions. In addition, through the processes of diamond deposition, etching, modification, etc. added in the manufacturing method and the cooperation with the chip back process, the efficient preparation of the IGBT chip structure is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to an IGBT chip structure and a manufacturing method thereof. Background Art

[0002] Most of the existing chip heat dissipation methods are external heat dissipation structures, and the common heat dissipation modes include natural heat dissipation, forced heat dissipation, liquid heat dissipation, refrigeration heat dissipation, diversion heat dissipation, heat pipe heat dissipation, etc. However, with the increase in the total power density of IGBT applications and the reduction of the physical size of the chip, the conventional method of installing a radiator is difficult to meet the current heat dissipation requirements of electronic chips, and the radiator structure is extremely large and not conducive to the high integration of the chip.

[0003] To solve the above problems, the present invention provides an IGBT chip structure and a manufacturing method thereof to solve the problem of low heat dissipation efficiency of the chip structure in the prior art. Summary of the Invention

[0004] The present invention provides an IGBT chip structure and a manufacturing method thereof. By adding a diamond layer with a porous two-dimensional network between the chip body and the collector metal layer, the high thermal conductivity of the diamond layer can be used to improve the heat dissipation ability, and at the same time, the honeycomb structure with dense middle and sparse periphery can be used to match the chip heat generation area to achieve uniform temperature of the IGBT chip.

[0005] To achieve the above object, the technical solution adopted by the present invention is:

[0006] The present invention discloses an IGBT chip structure, including a chip body, a diamond layer disposed on the back surface of the chip body, and a collector metal layer disposed on the back surface of the diamond layer. A porous two-dimensional network with dense middle and sparse periphery is etched on the diamond layer, and the porous two-dimensional network is filled with aluminum metal. The chip body and the collector metal layer are both connected to the aluminum metal to form a conduction path.

[0007] Preferably, the diamond layer is a boron-doped diamond film.

[0008] Preferably, the thickness of the diamond layer is 1 um to 2 um.

[0009] Preferably, the chip body includes a drift layer and a collector layer sequentially disposed from the front surface to the back surface. An emitter metal region, a gate region, an N-type emitter region, and a P-type base region are disposed on the front surface of the drift layer. The diamond layer is located between the collector layer and the collector metal layer.

[0010] Preferably, the drift layer is a phosphorus-doped silicon substrate layer, and the collector layer is a boron-doped silicon substrate layer.

[0011] Preferably, the collector metal layer includes an aluminum layer, a titanium layer, a nickel-vanadium alloy layer, and a silver layer connected in sequence from the front side to the back side, and the aluminum layer is connected to the diamond layer.

[0012] A manufacturing method of an IGBT chip structure is also disclosed, which is used to prepare the above IGBT chip structure and includes the following steps:

[0013] Deposit a diamond layer on the back surface of the chip body;

[0014] Etch a porous two-dimensional network with dense middle and sparse periphery on the diamond layer, and fill metallic aluminum in the through holes of the porous two-dimensional network;

[0015] Deposit a collector metal layer on the back surface of the etched diamond layer.

[0016] Preferably, before depositing the diamond layer, implant boron ions on the back surface of the chip body and perform laser annealing to form a collector layer, prepare a suspension with diamond micropowder and absolute ethanol, ultrasonically grind the surface of the collector layer with the suspension, and then ultrasonically clean with distilled water and absolute ethanol.

[0017] Preferably, before etching the surface of the diamond layer, clean the surface of the diamond layer using a wet chemical cleaning process; then deposit a film on the surface of the cleaned diamond layer using DC pulsed magnetron sputtering to form a mask structure; coat the surface of the mask structure with a positive photoresist, expose it to ultraviolet light, and then develop it in a developer; use nitric acid and phosphoric acid as corrosive acid solutions to remove the mask structure of the part where the positive photoresist is not attached, so that the mask structure is patterned, so as to etch the diamond layer to form a porous two-dimensional network subsequently.

[0018] Preferably, before depositing the collector metal layer, modify the surface of the diamond layer: first clean the surface of the chip body using a wet chemical cleaning process; deposit a tungsten coating on the surface of the diamond layer using magnetron sputtering.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention adds a diamond layer with high thermal conductivity between the back surface of the chip body and the collector metal layer to form a "silicon-diamond-metal" structure. The diamond layer has a porous two-dimensional network. The high thermal conductivity characteristic of diamond can enhance the heat dissipation capacity of the chip. At the same time, the conductive characteristic of metallic aluminum in the porous two-dimensional network provides a current path for the IGBT chip to realize the normal operation of the chip, solves the problem of uneven heat distribution with high temperature in the middle and low temperature around due to poor heat dissipation performance during the operation of the IGBT chip, and reduces the device performance difference and the risk of reliability failure caused by uneven heat.

[0021] Compared with the prior art, other technical solutions of the present invention also have the following beneficial effects:

[0022] The manufacturing method of the IGBT chip structure of the present invention is adapted to the current IGBT chip process flow, with simple process and high feasibility, and is suitable for popularization. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a schematic structural diagram of an IGBT chip structure in an embodiment of the present invention;

[0025] Figure 2 It is a schematic structural diagram of another IGBT chip structure in an embodiment of the present invention;

[0026] Figure 3 It is a schematic structural diagram of the connection of the collector layer, diamond layer, and collector metal layer in an embodiment of the present invention;

[0027] Figure 4 It is a schematic structural diagram of a porous two-dimensional network on the diamond layer in an embodiment of the present invention;

[0028] Figure 5 It is a flowchart of the manufacturing method of the IGBT chip structure in an embodiment of the present invention.

[0029] Description of the reference numerals: 1. Gate region; 2. Emitter metal region; 3. N-type emitter region; 4. P-type base region; 5. Drift layer; 6. Collector layer; 7. Diamond layer; 8. Collector metal layer; 9. Porous two-dimensional network; 10. Aluminum layer; 11. Titanium layer; 12. Nickel-vanadium alloy layer; 13. Silver layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0031] The present invention provides an IGBT chip structure and a manufacturing method thereof, aiming to improve the heat dissipation efficiency of the chip. By adding a diamond layer with a porous two-dimensional network between the chip body and the collector metal layer, the high thermal conductivity of the diamond layer can be used to improve the heat dissipation capacity. At the same time, the honeycomb structure with dense middle and sparse periphery can match the heat generation area of the chip to achieve uniform temperature of the IGBT chip.

[0032] In order to make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Embodiment 1

[0034] As Figures 1 to 5 shown, this embodiment provides an IGBT chip structure, including a chip body, a diamond layer 7 provided on the back surface of the chip body, and a collector metal layer 8 provided on the back surface of the diamond layer 7. A porous two-dimensional network 9 with dense middle and sparse periphery is etched on the diamond layer 7. The porous two-dimensional network 9 is a grid-like structure formed by arranging a plurality of through holes. Metal aluminum is provided in each through hole of the porous two-dimensional network 9. Both the chip body and the collector metal layer 8 are connected to the metal aluminum to form a conduction path. The dense middle and sparse periphery mainly rely on the aperture of a single through hole in the porous two-dimensional network 9. For example, the aperture of the through holes in the middle region is small, so it is dense, forming a dense middle region, while the aperture of the through holes in the peripheral region surrounding the middle region is large, so it is sparse, forming a sparse peripheral region. The dense middle region needs to correspond and match the high-heat region in the middle of the chip body, that is, the dense middle region needs to cover the high-heat region in the middle. The sparse peripheral region needs to correspond and match the low-heat regions around the chip body, and the sparse peripheral region needs to cover the low-heat regions around. Specifically, the aperture sizes of the through holes in the dense middle region and the sparse peripheral region need to be set according to the heat generation amount of the chip body.

[0035] By depositing a conductive and highly thermally conductive diamond layer 7 structure on the back of the chip body and etching to form a porous two-dimensional network 9 that is dense in the middle and sparse around, the high thermal conductivity of diamond is used to enhance heat dissipation, and the honeycomb structure design is used to increase the heat dissipation capacity in the middle to achieve uniform temperature of the IGBT chip. Aluminum metal is filled in the pores and combined with the chip body and the collector metal layer 8 to form a conduction path, realizing ohmic contact between the collector metal layer 8 and the chip body, meeting the electrical connection requirements of the IGBT chip application conditions. The high thermal conductivity of diamond can enhance the heat dissipation capacity of the chip, solve the problem of non-uniform heat distribution in the IGBT chip during operation, where the middle has concentrated heat and high temperature while the surrounding has low temperature, and reduce the device performance difference and the risk of reliability failure caused by uneven heat. The application scope of this IGBT chip structure includes: trench IGBT (Insulated Gate Bipolar Transistor), planar gate IGBT, MOSFET (Metal Oxide Semiconductor Field Effect Transistor), diode, thyristor and other silicon-based devices.

[0036] In one embodiment, the diamond layer 7 is a boron-doped diamond film. After diamond is doped with boron, the diamond layer 7 itself also has conductivity, thereby increasing the conduction path range between the chip body and the collector metal layer 8, which is indirectly beneficial for heat dissipation.

[0037] In one embodiment, the thickness of the diamond layer 7 is 1 um to 2 um.

[0038] In one embodiment, the chip body includes a drift layer 5 and a collector layer 6 arranged in sequence from the front to the back. The front of the drift layer 5 is provided with a gate region 1, an emitter metal region 2, an N-type emitter region 3, and a P-type base region 4. The diamond layer 7 is located between the collector layer 6 and the collector metal layer 8.

[0039] In one embodiment, the drift layer 5 is a phosphorus-doped silicon substrate layer, and the collector layer 6 is a boron-doped silicon substrate layer.

[0040] In one embodiment, the collector metal layer 8 includes an aluminum layer 10, a titanium layer 11, a nickel-vanadium alloy layer 12, and a silver layer 13 connected in sequence from the front to the back, wherein the aluminum layer 10 is connected to the diamond layer 7.

[0041] In one embodiment, the cross-sectional shape of a single through-hole in the porous two-dimensional network 9 is a regular hexagon, making the porous two-dimensional network arranged in a honeycomb pattern. Of course, the cross-sectional shape of a single through-hole in the porous two-dimensional network 9 can also be circular, rectangular or other shapes, which will not be elaborated here.

[0042] Example 2

[0043] As Figures 1 to 5 shown, this embodiment provides a method for fabricating an IGBT chip structure for producing the IGBT chip structure in Embodiment 1, including the following steps:

[0044] Deposit a diamond layer 7 on the back of the chip body;

[0045] Etch a porous two-dimensional network 9 with dense middle and sparse periphery on the diamond layer 7, and fill metal aluminum in the through holes of the porous two-dimensional network 9;

[0046] Deposit a collector metal layer 8 on the back of the etched diamond layer 7.

[0047] In one embodiment, before depositing the diamond layer 7, boron ions are implanted into the back of the chip body and laser annealed to form a collector layer 6. A suspension is prepared by mixing diamond micropowder and absolute ethanol, and the surface of the collector layer 6 is ultrasonically polished using the suspension, and then ultrasonically cleaned using distilled water and absolute ethanol.

[0048] In one embodiment, when depositing the diamond layer 7 on the back of the collector layer 6: First, deposit 1um - 2um of boron-doped diamond material on the collector layer 6, and then pattern the diamond thin film by dry etching to form a diamond layer 7 with a porous two-dimensional network 9 to provide a current conduction path. Then, deposit a collector metal layer 8 on the back of the diamond layer 7 to realize the electrode preparation of the chip.

[0049] In one embodiment, before etching the surface of the diamond layer 7, clean the surface of the diamond layer 7 using a wet chemical cleaning process; then coat the surface of the cleaned diamond layer 7 with a film by DC pulsed magnetron sputtering to form a mask structure; coat the surface of the mask structure with a positive photoresist, expose it to ultraviolet light, and then develop it in a developer; use nitric acid and phosphoric acid as corrosive acid solutions to remove the mask structure of the part where the positive photoresist is not attached, so that the mask structure is patterned, in order to etch the diamond layer 7 to form a porous two-dimensional network 9 subsequently.

[0050] In one embodiment, before depositing the collector metal layer 8, modify the surface of the diamond layer 7: First, clean the surface of the chip body using a wet chemical cleaning process to make the surface of the chip body free of organic contamination and particle attachment; deposit a tungsten coating on the surface of the diamond layer 7 by magnetron sputtering to inhibit the hydrolysis phenomenon at the bonding interface between the diamond layer 7 and the aluminum layer 10, and realize the surface modification of the diamond layer structure.

[0051] In one embodiment, it includes:

[0052] 1. Back process

[0053] ① Wafer thinning: After the front - side process of the chip body is completed, a protective film is pasted on the front side of the chip body, and the back side is thinned to a specified thickness.

[0054] ② Collector implantation: Boron ions are implanted on the back side, followed by laser annealing to form a doped - boron collector metal layer 8.

[0055] 2. Depositing a diamond layer

[0056] ① Pretreatment: A suspension is prepared by mixing about 1um diamond micropowder with absolute ethanol, and the surface of the collector layer 6 is ultrasonically polished using the suspension. Then, it is ultrasonically cleaned with distilled water and absolute ethanol for at least 10 min. The pretreatment is to increase the nucleation density of the diamond layer 7 on the collector layer 6 and at the same time enhance the adhesion strength between the diamond layer 7 and the collector layer 6.

[0057] ② Depositing a diamond layer: Using microwave plasma chemical vapor deposition (MPCVD), a 1 - 2um boron - doped diamond thin film (diamond layer 7) is prepared. The high thermal conductivity of diamond is used to enhance the heat dissipation of the chip, and the low resistivity (10 -3 Ω.cm) formed by the boron - doped diamond layer 7 is used to reduce the application loss of the chip. Process parameters: The reaction gas is a mixed gas of hydrogen (H2) - methane (CH4) - diborane (B2H6). CH4 and B2H6 are used as carbon sources and boron sources, and hydrogen is introduced into the reactor through the methane - diborane organic mixed liquid. The gas flow rate is 400 sccm for hydrogen, 24 sccm for methane, and 60 sccm for diborane. The deposition temperature is 900℃, the pressure is 18 kPa, and the time is 10 h.

[0058] 3. Etching the diamond layer

[0059] ① Cleaning: Use the standard wet chemical cleaning (RCA) process to clean the wafer surface, so that the surface of the diamond layer 7 has no organic contamination and no particle attachment, avoiding affecting the etching quality of the diamond layer 7 structure due to poor mask adhesion.

[0060] ② Aluminum - plating mask: Coating is carried out by DC pulsed magnetron sputtering. Aluminum metal is sputtered onto the surface of the diamond layer 7 in a high - purity argon environment to form a mask structure with a thickness of 150 - 200 nm, so that the diamond layer structure below the aluminum layer is not etched. Process parameters: The sputtering voltage is - 250V, the target current is 25A, and the pulse duty cycle is 50%. The vacuum pressure is 0.5×10 -3 Pa, and the temperature is 150℃.

[0061] ③ Exposure / development: A positive photoresist (positive resist) is coated on the surface of the aluminum thin film, exposed using ultraviolet light with a wavelength of 405 nm, and then developed in a developer. Deionized water is used to rinse and remove the developer.

[0062] ④Mask patterning: A wet etching process is used, with nitric acid and phosphoric acid as the corrosive acid solutions to remove the aluminum layer where the photoresist is not attached, thus patterning the aluminum layer for subsequent etching of the diamond layer to form a conductive porous two-dimensional network 9. Process parameters: The volume ratio of the wet etching solution is phosphoric acid (H3PO4): nitric acid (HNO3): acetic acid (CH3COOH): deionized water = 50:3:10:9, the temperature is 60 °C, and the time is 5 min.

[0063] ⑤Etching: Inductively coupled plasma (ICP) etching is used to etch the diamond layer 7. According to the chip heat dissipation requirements, a diamond layer 7 structure with a porous two-dimensional network 9 is designed to enhance the chip's heat dissipation capacity. The porous two-dimensional network 9 is filled with aluminum metal material to form an ohmic contact between the silicon wafer and the back metal. Process parameters: The gas atmosphere is 7 sccm of oxygen and 8 sccm of argon, the gas pressure is 0.3 Pa, the etching power is 600 W, the bias voltage is -160 V, and the etching time is 5 min to 10 min.

[0064] 4. Diamond surface modification

[0065] ①Cleaning: The standard wet chemical cleaning (RCA) process is used to clean the surface of the chip body, making the chip surface free of organic contamination and particle attachment, and avoiding affecting the bonding strength between the diamond and the back metal due to contamination.

[0066] ②Depositing a tungsten metal coating: Magnetron sputtering is used to deposit a tungsten (W) coating of about 50 nm on the diamond surface to inhibit the hydrolysis phenomenon at the diamond / aluminum bonding interface, achieve surface modification of the diamond structure, and increase the interfacial bonding strength between the diamond layer and the back metal aluminum. Process parameters: The current of the magnetron sputtering process is 0.9 A, and the voltage is 600 V. The gas atmosphere is a constant argon environment, the vacuum pressure < 8×10 -3 Pa, the temperature is 300 °C, and the time is 200 min.

[0067] 5. Back metal deposition

[0068] ①Aluminum metal deposition: Magnetron sputtering is used to deposit about 100 nm of Al metal to form a diamond / Al interface and a Si / Al interface with high bonding strength and good ohmic contact, reducing the working loss of the chip. Process parameters: The gas atmosphere is a constant Ar gas environment, the gas flow rate is 100 sccm. The magnetron sputtering power is 6000 W, and the time is 10 s.

[0069] ②Titanium-nickel-silver metal deposition: Magnetron sputtering is used to deposit a titanium metal layer with a thickness of about 100 nm, a nickel vanadium alloy layer with a thickness of 400 nm, and a nickel vanadium alloy layer with a thickness of 800 nm in sequence. The titanium layer 11 serves as a diffusion barrier layer, the nickel vanadium alloy layer 12 is a solderable layer, and the silver layer 13 is a protective layer to prevent the oxidation of the nickel vanadium alloy layer 12.

[0070] In one embodiment, a scheme for bonding the diamond layer 7 with the collector layer 6 is realized: In addition to depositing the diamond layer by the microwave plasma chemical vapor deposition method described in the text, the hot filament chemical vapor deposition method, the DC plasma chemical vapor deposition method, etc. can also be used.

[0071] In one embodiment, boron-doped diamond reactants are deposited: In addition to the hydrogen-methane (CH4)-diborane (B2H6) mixed gas described in the text, trimethylboron (B(CH3)3) and trimethyl borate (B(OCH3)3) can also be used as boron sources, and acetone (CH3COCH3) can be used as a carbon source to prepare a boron-doped diamond structure. The resistivity of the boron-doped diamond depends on the carbon-boron ratio of the mixed gas, that is, the gas flow ratio of the carbon source and the boron source.

[0072] In one embodiment, a diamond surface modification scheme: To enhance the bonding strength of the diamond-aluminum interface, in addition to the chemical method of sputtering a tungsten coating on the diamond surface described in the text, a titanium, titanium carbide, tungsten carbide, silicon, or silicon carbide coating can also be added to the diamond surface for treatment; or a method of forming Al(Si) and Al(Ti) alloys by doping silicon, titanium, etc. in the sputtered aluminum metal can be used.

[0073] The manufacturing method of the IGBT chip structure proposed in this embodiment does not conflict with the front process flow of current chip production. The key point of this embodiment is the cooperation between the diamond deposition, etching, modification, etc. processes added in the process and the back process of the chip to realize the preparation of the "silicon-diamond-metal" three-layer heat dissipation structure (collector layer 6, diamond layer 7, and collector metal layer 8).

[0074] It should be noted that for those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention, and any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. An IGBT chip structure, characterized in that, It includes a chip body, a diamond layer disposed on the back surface of the chip body, and a collector metal layer disposed on the back surface of the diamond layer. A porous two-dimensional network that is dense in the middle and sparse around is etched on the diamond layer. Metal aluminum is filled in the porous two-dimensional network. Both the chip body and the collector metal layer are connected to the metal aluminum to form a conduction path. The cross-sectional shape of a single through-hole in the porous two-dimensional network is a regular hexagon, making the porous two-dimensional network arranged in a honeycomb shape. The denseness in the middle and sparseness around are achieved by the aperture size of a single through-hole in the porous two-dimensional network.

2. The IGBT chip structure according to claim 1, wherein The diamond layer is a boron-doped diamond film.

3. The IGBT chip structure according to claim 2, characterized in that, The thickness of the diamond layer is 1 um to 2 um.

4. The IGBT chip structure according to any one of claims 1-3, characterized in that, The chip body includes a drift layer and a collector layer sequentially arranged from the front surface to the back surface. An emitter metal region, a gate region, an N-type emitter region, and a P-type base region are provided on the front surface of the drift layer. The diamond layer is located between the collector layer and the collector metal layer.

5. The IGBT chip structure according to claim 4, wherein, The drift layer is a phosphorus-doped silicon substrate layer, and the collector layer is a boron-doped silicon substrate layer.

6. The IGBT chip structure according to any one of claims 1-3, characterized in that, The collector metal layer includes an aluminum layer, a titanium layer, a nickel-vanadium alloy layer, and a silver layer sequentially connected from the front surface to the back surface. The aluminum layer is connected to the diamond layer.

7. A manufacturing method of an IGBT chip structure, characterized in that, A method for preparing the IGBT chip structure according to any one of claims 1 to 6 includes the following steps: Depositing a diamond layer on the back surface of the chip body; Etching a porous two-dimensional network that is dense in the middle and sparse around on the diamond layer, and filling metal aluminum in the through-holes of the porous two-dimensional network; Depositing a collector metal layer on the back surface of the etched diamond layer.

8. The manufacturing method of the IGBT chip structure according to claim 7, characterized in that, Before depositing the diamond layer, boron ions are implanted into the back surface of the chip body and laser annealed to form a collector layer. A suspension is prepared by mixing diamond micropowder and absolute ethanol, and the surface of the collector layer is ultrasonically polished using the suspension, and then ultrasonically cleaned using distilled water and absolute ethanol.

9. The manufacturing method of the IGBT chip structure according to claim 7, characterized in that, Before etching the surface of the diamond layer, the surface of the diamond layer is cleaned using a wet chemical cleaning process; then a mask structure is formed by coating a film on the surface of the cleaned diamond layer using DC pulsed magnetron sputtering. Coating a positive photoresist on the surface of the mask structure, exposing it to ultraviolet light, and then developing it in a developer; Using nitric acid and phosphoric acid as corrosive acid solutions to remove the mask structure of the part where the positive photoresist is not attached, making the mask structure patterned, so as to etch the diamond layer to form a porous two-dimensional network subsequently.

10. The manufacturing method of the IGBT chip structure according to claim 7, characterized in that, Before depositing the collector metal layer, the surface of the diamond layer is modified: First, the surface of the chip body is cleaned using a wet chemical cleaning process; A tungsten coating is deposited on the surface of the diamond layer using magnetron sputtering.

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