Method for improving breakdown resistance of device

Abstract

The invention provides a method for improving breakdown resistance of a device, which comprises the following steps of: providing a cellular region layout and a field limiting ring structure layout of a chip, and distributing groove type cellular structures in the cellular region of the chip; the field limiting ring structure layout is a multi-circle annular pattern surrounding the periphery of the cellular region layout from an overlook angle, the innermost circle of annular pattern is a field limiting ring main junction pattern, fan-shaped patterns are arranged at four corners of the field limiting ring main junction pattern, arcs of the fan-shaped patterns are attached to the four corners of the field limiting ring main junction pattern, and the arcs of the fan-shaped patterns are attached to the four corners of the field limiting ring main junction pattern. A region defined by two radiuses of the fan-shaped graph extends into the region of the cellular region layout; when the chip is manufactured, the field limiting ring structure layout is utilized to define a forming area of the field limiting ring structure, and the annular pattern and the fan-shaped pattern are subjected to ion implantation corresponding to the area on the substrate to form the field limiting ring structure. Different types of deep doping are formed at the corner position of the main junction of the field limiting ring, so that preferential breakdown at the corner position is avoided, and the avalanche breakdown capability of the device is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving the breakdown resistance of a device. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) has the characteristics of both field effect transistor and bipolar junction transistor, and has the advantages of easy driving, high breakdown voltage, large current, and low on-state voltage drop, and is widely used in many fields such as rail transit, urban power grid, automotive electronics, and industrial motors.

[0003] Trench Field Stop IGBT (FS-IGBT) has become the mainstream structure in the current development of IGBT due to its low-loss advantage, but it still has the problem of insufficient breakdown resistance, resulting in device failure. One of the electrical failure points is located in the cell area and the terminal transition area, especially at the local electric field concentration at the chip corner bend, which is prone to form a breakdown weak point.

[0004] To solve the above problems, a new method for improving the breakdown resistance of a device needs to be proposed. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for improving the breakdown resistance of a device, which is used to solve the problem that the electrical failure point exists in the cell area and the terminal transition area in the prior art, especially at the local electric field concentration at the chip corner bend, which is prone to form a breakdown weak point.

[0006] To achieve the above purpose and other related purposes, the present invention provides a method for improving the breakdown resistance of a device, including:

[0007] Step 1: Provide a layout of the cell area and a layout of the field limiting ring structure of the chip, and a trench cell structure is distributed in the chip cell area;

[0008] Viewed from the top, the layout of the field limiting ring structure is a multi-turn annular pattern surrounding the periphery of the cell area layout. Among them, the innermost annular pattern is the main junction pattern of the field limiting ring, and fan-shaped patterns are provided at the four corners of the main junction pattern of the field limiting ring. The arc of the fan-shaped pattern fits the four corners of the main junction pattern of the field limiting ring, and the area enclosed by the two radii of the fan-shaped pattern extends into the area of the cell area layout;

[0009] Step 2: When manufacturing the chip, use the layout of the field limiting ring structure to define the formation area of the field limiting ring structure, and perform ion implantation on the areas corresponding to the circular pattern and the fan-shaped pattern on the substrate to form the field limiting ring structure.

[0010] Preferably, when observed from a top view, the layout of the cell region in Step 1 is a rectangular area.

[0011] Preferably, when observed from a top view, the layout of the cell region in Step 1 is a rectangular area with rounded corners at the four corners.

[0012] Preferably, the radius of the fan-shaped pattern in Step 1 is 2 to 5 times the depletion region width at the breakdown of the parallel plane junction here.

[0013] Preferably, the corners of the fan-shaped pattern in Step 1 and the corners between the fan-shaped pattern and the main junction pattern of the field limiting ring are all rounded.

[0014] Preferably, the substrate in Step 2 is a silicon substrate.

[0015] Preferably, contact holes and trench structures are reserved in the area corresponding to the fan-shaped pattern on the substrate in Step 2.

[0016] Preferably, contact holes are reserved in the area corresponding to the fan-shaped pattern on the substrate in Step 2, and the trench structures are removed.

[0017] Preferably, the method is used for the manufacture of IGBT devices.

[0018] Preferably, the method is used for the manufacture of discrete devices.

[0019] As described above, the method for improving the breakdown resistance of a device according to the present invention has the following beneficial effects:

[0020] The present invention avoids the preferential breakdown at the corner position by forming deep different types of doping at the corner position of the main junction of the field limiting ring, thereby improving the avalanche breakdown ability of the device. Description of the Drawings

[0021] Figure 1 Schematic diagrams of the layout of the cell region and the field limiting ring structure shown as the prior art;

[0022] Figure 2 Shown as Figure 2 Schematic cross-sectional structure diagram of the device AA' cross-section obtained by the layout;

[0023] Figure 3 Schematic diagram of the process flow of the present invention;

[0024] Figure 4Shown is a schematic diagram of the layout of a single cell region and the layout of a field limiting ring structure according to the present invention;

[0025] Figure 5 Shown as Figure 4 Schematic cross-sectional structure diagram of the BB' cross-section of the device fabricated from the layout;

[0026] Figure 6 Shown is a schematic diagram of the layout of another cell region and the layout of a field limiting ring structure according to the present invention;

[0027] Figure 7 Shown as Figure 6 Schematic cross-sectional structure diagram of the CC' cross-section of the device fabricated from the layout;

[0028] Figure 8 Shown is a schematic diagram of the corner of the fan-shaped pattern and the corner between the fan-shaped pattern and the main junction pattern of the field limiting ring according to the present invention;

[0029] Figure 9 Shown is a schematic diagram of the corner between the fan-shaped pattern and the main junction pattern of the field limiting ring being rounded according to the present invention;

[0030] Figure 10 Shown is a schematic diagram of the corner of the fan-shaped pattern being rounded according to the present invention. Specific embodiments

[0031] The following illustrates the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] Please refer to Figure 3 , the present invention provides a method for improving the breakdown resistance of a device, including:

[0033] Step 1: Provide the layout of the cell region and the layout of the field limiting ring structure of the chip, and trench-type cell structures are distributed in the cell region of the chip;

[0034] Viewed from a top-down perspective, the layout of the field limiting ring structure is a multi-ring circular pattern surrounding the layout of the cell region. The innermost ring circular pattern is the main junction pattern of the field limiting ring. Four corners of the main junction pattern of the field limiting ring are each provided with a fan-shaped pattern. The arc of the fan-shaped pattern fits the four corners of the main junction pattern of the field limiting ring, and the region enclosed by the two radii of the fan-shaped pattern extends into the region of the layout of the cell region;

[0035] In some embodiments, viewed from a top-down perspective, the layout of the cell region in Step 1 is a rectangular region.

[0036] In some embodiments, when the cell region layout in Step 1 is observed from a top view, it is a rectangular region with rounded corners at the four corners.

[0037] In some embodiments, the radius of the fan-shaped pattern in Step 1 is 2 to 5 times the depletion region width at the breakdown of the parallel plane junction here. The depletion region refers to the interface region in a semiconductor pn junction, Schottky junction, or heterojunction where, due to the difference in the original chemical potential of the semiconductors on both sides of the interface, the energy band bends near the interface, resulting in a decrease in the electron or hole concentration. The formation of the depletion region is due to the diffusion and recombination of carriers (electrons and holes) after the contact of P-type and N-type semiconductors, resulting in almost no free carriers in the junction region. This region is characterized by the presence of space charges composed of fixed ionized donor or acceptor atoms, which generate a built-in electric field that prevents further carrier diffusion, thus forming a high-resistance region.

[0038] In some embodiments, the corners of the fan-shaped pattern in Step 1 (such as Figure 8 at ②) and the corners between the fan-shaped pattern and the field limiting ring main junction pattern (such as Figure 8 at ①) are all rounded, Figure 8 After the rounding treatment at ①, the structure shown in Figure 9 is formed, Figure 8 After the rounding treatment at ②, the structure shown in Figure 10 is formed to avoid the formation of a peak electric field here.

[0039] Step 2: When manufacturing the chip, use the field limiting ring structure layout to define the formation region of the field limiting ring structure. The annular pattern and the fan-shaped pattern correspond to the regions on the substrate for ion implantation to form the field limiting ring structure. By forming deep different-type dopings at the corner positions of the field limiting ring main junction, the preferential breakdown at the corner positions is avoided, thereby improving the avalanche breakdown ability of the device.

[0040] In some embodiments, the substrate in Step 2 is a silicon substrate.

[0041] In some embodiments, the region on the substrate corresponding to the fan-shaped pattern in Step 2 retains contact holes and trench structures. For example, please refer to Figure 4 , which shows a layout embodiment. Please refer to Figure 5 , which shows the cross-sectional structure of the device BB' obtained from the Figure 4 layout.

[0042] In some embodiments, the region on the substrate corresponding to the fan-shaped pattern in Step 2 retains contact holes, and the trench structures are removed, and the contact holes are retained for current conduction. For example, please refer to Figure 6 , which shows a layout embodiment. Please refer to Figure 7 , which shows the Figure 4Cross-sectional structure diagram of the BB' cross-section of the device fabricated by the layout.

[0043] In some embodiments, the method is used for the manufacture of IGBT devices. IGBT (Insulated Gate Bipolar Transistor), an insulated gate bipolar transistor, is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar junction transistor) and MOS (insulated gate field effect transistor), and has the advantages of both the high input impedance of MOSFET and the low on-state voltage drop of GTR.

[0044] In some embodiments, the method is used for the manufacture of discrete devices. A discrete device refers to an electronic device with a separate function and cannot be split, usually composed of one or more electronic devices, and can be used alone or in combination with other devices to complete specific circuit functions. Common discrete devices include diodes, transistors, field effect transistors, capacitors, resistors, and inductors, etc.

[0045] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0046] In summary, the present invention avoids the preferential breakdown at the corner position by forming deep different types of doping at the corner position of the field limiting ring main junction, thereby improving the avalanche breakdown ability of the device. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0047] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the breakdown resistance of a device, characterized in that: At least: Step 1: providing a cell region layout and a field limiting ring structure layout of the chip, wherein a grooved cell structure is distributed in the cell region of the chip; When viewed from a top view, the field limiting ring structure pattern is a multi-circle annular pattern surrounding the periphery of the cellular region pattern, wherein the innermost annular pattern is a field limiting ring main junction pattern, and fan-shaped patterns are arranged at the four corners of the field limiting ring main junction pattern, and the arcs of the fan-shaped patterns fit the four corners of the field limiting ring main junction pattern, and the area enclosed by the two radii of the fan-shaped patterns extends into the area of ​​the cellular region pattern; Step 2: When manufacturing the chip, the field limiting ring structure layout is used to define the formation area of ​​the field limiting ring structure, and the annular pattern and the fan-shaped pattern are ion-implanted into the area corresponding to the substrate to form the field limiting ring structure.

2. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The cell region layout in step 1 is a rectangular region when viewed from a top-down perspective.

3. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The cell area layout in step 1 is a rectangular area when viewed from a top-down perspective, with four arc-shaped corners.

4. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The radius of the fan-shaped figure in step 1 is 2 to 5 times the width of the depletion region when the parallel plane junction breaks down.

5. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The corners of the fan-shaped figure in step 1 and the corners between the fan-shaped figure and the field limiting ring main junction figure are rounded.

6. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The substrate in step 2 is a silicon substrate.

7. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The sector-shaped pattern in step 2 corresponds to a region on the substrate where contact holes and trench structures are retained.

8. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The sector-shaped pattern in step 2 corresponds to the area on the substrate where the contact hole is retained and the trench structure is removed.

9. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The method is used for manufacturing an IGBT device.

10. The method for improving the breakdown resistance of a device according to claim 1, characterized in that: The method is used for manufacturing discrete devices.

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