Hybrid imaging sensor with high sampling point distribution

Abstract

The invention relates to a hybrid imaging sensor with high sampling point distribution. The pixel circuit includes a pixel array and a color filter. The pixel array includes a plurality of pixels each including two photodiodes, a floating diffusion region coupled between the two photodiodes, and two transfer transistors coupled between the two photodiodes and the floating diffusion region. The color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each pixel is coupled to a first readout circuit. The pixels include a second subset of the pixels coupled to a second readout circuit and a first subset of the pixels not coupled to the second readout circuit. Each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of the pixels and a second pixel included in the first subset of the pixels and disposed below one of the color filters.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 608,150, filed on Dec. 8, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to image sensors, and more particularly (but not exclusively) to hybrid image sensors having a high sampling point distribution. Background Art

[0004] Image sensors have become ubiquitous and are now widely used in digital cameras, mobile phones, cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing. Technologies for manufacturing image sensors have been evolving rapidly. For example, the requirements for higher resolution and lower power consumption have driven further miniaturization and integration of these devices.

[0005] A typical image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge after absorbing the image light. The image charge generated by the pixels can be measured as an analog output image signal on column bitlines, which varies according to the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and the image light is read out as an analog image signal from the column bitlines and converted into a digital value to generate a digital image (e.g., image data) representing the external scene. The analog image signal on the bitlines is coupled to a readout circuit, which includes an input stage having an analog-to-digital conversion (ADC) circuit to convert these analog image signals from the pixel array into digital image signals. Summary of the Invention

[0006] On the one hand, the present application provides a pixel circuit, which includes: a pixel array including a plurality of pixels arranged in rows and columns, wherein each pixel includes: a first photodiode configured to generate a first image charge in response to incident light; a second photodiode configured to generate a second image charge in response to incident light; a floating diffusion region coupled to receive the first image charge from the first photodiode and receive the second image charge from the second photodiode; a first transfer transistor coupled between the first photodiode and the floating diffusion region to transfer the first image charge from the first photodiode to the floating diffusion region; and a second transfer transistor coupled between the second photodiode and the floating diffusion region to transfer the second image charge from the second photodiode to the floating diffusion region; and a color filter array disposed above the pixel array, wherein the color filter array includes a plurality of color filters each having one of a plurality of colors and disposed above at least one of the pixels, wherein each of the plurality of pixels is selectively coupled to a first readout circuit, wherein the plurality of pixels includes: a first subset of the pixels configured to be disconnected from a second readout circuit and connected to the first readout circuit to read a first set of data signals, and a second subset of the pixels selectively coupled to the second readout circuit to read a second set of data signals, wherein the second set of data signals is different from the first set of data signals, and wherein each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of the pixels and a second pixel included in the first subset of the pixels, and the first pixel and the second pixel are disposed below one of the color filters.

[0007] On the other hand, the present application provides an imaging system, which includes: a pixel circuit including a pixel array having a plurality of pixels arranged in rows and columns, wherein each pixel includes: a first photodiode configured to generate a first image charge in response to incident light; a second photodiode configured to generate a second image charge in response to incident light; a floating diffusion region coupled to receive the first image charge from the first photodiode and receive the second image charge from the second photodiode; a first transfer transistor coupled between the first photodiode and the floating diffusion region to transfer the first image charge from the first photodiode to the floating diffusion region; and a second transfer transistor coupled between the second photodiode and the floating diffusion region to transfer the second image charge from the second photodiode to the floating diffusion region; and a color filter array disposed above the pixel array, wherein the color filter array includes a plurality of color filters each having one of a plurality of colors and disposed above at least one of the pixels; a first readout circuit selectively coupled to each of the plurality of pixels to read out a first set of data signals; a second readout circuit, wherein the plurality of pixels include a first subset of the pixels configured to be disconnected from the second readout circuit while being coupled to the first readout circuit and a second subset of the pixels selectively coupled to the second readout circuit, wherein the second readout circuit is coupled to each of the pixels included in the second subset to read out a second set of data signals; and a mode selection switch circuit coupled to the pixels included in the second subset, wherein the pixels included in the second subset are configured to provide the first set of data signals to the first readout circuit or provide the second set of data signals to the second readout circuit in response to the mode selection circuit, wherein each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of the pixels and a second pixel included in the first subset of the pixels and disposed below one of the color filters. Description of the Drawings

[0008] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like components in the various views unless otherwise specified.

[0009] Figure 1 An example of a stacked hybrid complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) with an event-based vision sensor system according to the teachings of the present disclosure is illustrated.

[0010] Figure 2 An example of a pixel circuit with a four-Bayer color filter array and 1x2 microlenses according to the teachings of the present disclosure is illustrated.

[0011] Figure 3 Describe an example of a pixel circuit having a four-Bayer filter array and 2x2 microlenses according to the teachings of the present disclosure.

[0012] Figure 4 Describe an example of a pixel circuit having a four-RGBC filter array and 1x2 microlenses according to the teachings of the present disclosure.

[0013] Figure 5 Describe an example of a pixel circuit having an RGBC filter array and 2x2 microlenses according to the teachings of the present disclosure.

[0014] Figure 6 Describe an example of a pixel circuit having a four-Bayer filter array and 1x2 microlenses according to the teachings of the present disclosure.

[0015] Figure 7 Describe an example of a pixel circuit having a four-RGBC filter array and 1x2 microlenses according to the teachings of the present disclosure.

[0016] Figure 8 Describe an example of a pixel coupled to a mode selection switch circuit according to the teachings of the present disclosure.

[0017] Figure 9 Describe an example of a pixel array coupled to a mode selection switch circuit according to the teachings of the present disclosure.

[0018] Figure 10 Describe another example of a pixel array coupled to a mode selection switch circuit according to the teachings of the present disclosure.

[0019] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will appreciate that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to assist in improving understanding of the various embodiments of the present disclosure. Additionally, common but well-known elements that are useful or necessary in a commercially viable embodiment are typically not depicted so as not to obscure these various embodiments of the technology. Detailed Description

[0020] I. Overview

[0021] The disclosure relates to examples of imaging systems having pixel circuits that provide simultaneous hybrid functionality with a high sampling point distribution. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, those of ordinary skill in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0022] Reference throughout this specification to "one example" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present disclosure. Thus, the appearances of the phrases "in one example" or "in one embodiment" throughout the specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0023] For ease of description, spatial relative terms (e.g., "below", "beneath", "above", "below", "over", "on", "top", "bottom", "left", "right", "center", "middle", and the like) may be used herein to describe the relationship of one element or feature to another (additional) element or feature, as illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the figures is rotated or flipped, then an element described as "below" or "beneath" or "under" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "below" or "beneath" can cover both an above and a below orientation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly. Additionally, it should be understood that when an element is referred to as being "between" two other elements, the element may be the only element between the two other elements, or there may also be one or more intervening elements.

[0024] It should be further understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms and are not used to determine a process sequence or formation order of the associated elements. Unless otherwise indicated, these terms are only used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the disclosed embodiments.

[0025] Throughout this specification, several terms from the art are used. These terms have their ordinary meaning in the art, unless specifically defined herein or the context in which they are used otherwise clearly indicates. It should be noted that element names and symbols (e.g., Si and silicon) may be used interchangeably throughout this document; however, both have the same meaning.

[0026] As will be discussed, various examples of imaging systems are disclosed that have pixel circuits that provide simultaneous hybrid functionality (e.g., simultaneous image / video capture and event-driven sensing capabilities) with a high sampling point distribution. Although normal image / video sensors provide good image and / or video capture capabilities, one limitation of normal image / video sensors is that normal image sensors do not provide ultra-high frame rate and ultra-high speed capture capabilities, which can be useful in various applications such as machine vision, gaming, and artificial intelligence sensing. Attempts to provide such ultra-high frame rate and ultra-high speed capabilities to typical image / video sensors have resulted in compromised solutions that provide poorer quality image capture compared to their normal image sensor counterparts.

[0027] It should be appreciated that circuit designs in accordance with the teachings of the present disclosure address at least some of the problems discussed above. For example, the image sensors disclosed herein can operate in a hybrid mode, where for various event-driven (or other) applications, the image sensor simultaneously uses a first subset of pixels to provide good image and video capture capabilities and uses a second subset of pixels to sense events from the pixels at ultra-high frame rates and at ultra-high speeds. In addition, the first and second subsets of pixels can be arranged in a high sampling point distribution to provide improved contrast and / or modulation transfer function (MTF) compared to other image sensors.

[0028] Thus, as will be shown and described in the various examples below, an example pixel circuit includes a pixel array and a color filter. The pixel array includes a plurality of pixels, each of which includes two photodiodes, a floating diffusion region coupled between the two photodiodes, and two transfer transistors coupled between the two photodiodes and the floating diffusion region. The color filter array includes a plurality of color filters disposed over at least one of the pixels. Each pixel is coupled to a first readout circuit. As will be discussed in the various examples below, a pixel includes a first subset of pixels and a second subset of pixels. In various examples, the second subset of pixels is also coupled to a second readout circuit, and the first subset of pixels is the remaining subset of pixels that are not coupled to the second readout circuit. In other words, in accordance with the teachings of the present disclosure, the second subset of pixels is a subset of all pixels that includes some but not all of the pixels coupled to the first readout circuit. Each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of pixels and a second pixel included in the first subset of pixels, which are configured to be coupled to the first readout circuit and under one of the color filters but not coupled to the second readout circuit during a particular pixel operation (e.g., hybrid mode).

[0029] For illustration, Figure 1Describe an example of a stacked hybrid complementary metal oxide semiconductor (CMOS) image sensor (CIS) with an event-based vision sensor (EVS) system 100 according to the teachings of the present disclosure. As shown in the depicted example, the stacked CIS with the EVS system 100 includes a first die 102, a second die 104, and a third die 106 that are stacked and coupled together in a stacked chip scheme. In various examples, the first die 102, the second die 104, and the third die 106 are semiconductor dies comprising a suitable semiconductor material (e.g., silicon). In an example, the first die 102 (also referred to as the top die 102 of the stacked CIS with the EVS system 100) includes a pixel array 108. The third die 106 (also referred to as the bottom die 106 of the stacked CIS with the system 100) includes an image readout circuit 116 (also referred to as image readout mixed-signal circuitry). The image readout circuit 116 can be coupled to the pixel array 108 of the top die 102 through column-level connections 110 for normal image readout. In various examples, the column-level connections 110 for normal image readout are implemented from the column bit lines of the pixel array 108 using through-silicon vias (TSVs) that extend between the top die 102 and the bottom die 106 and are routed through the second die 104.

[0030] In various examples, the pixel array 108 is a two-dimensional (2D) array comprising a plurality of pixel units (also referred to as “pixels”), each pixel unit including a photodiode exposed to incident light. As illustrated in the depicted example, the pixels are arranged in rows and columns to acquire image data of a person, location, object, etc., which can then be used to reproduce an image and / or video of the person, location, object, etc. As further discussed herein, a first fraction of the pixels are configured as CMOS image sensor (CIS) pixels, and a second fraction of the pixels are configured as hybrid CIS / event-based vision sensor (EVS) pixels. In an example, each CIS pixel can be configured to photogenerate an image charge in response to incident light. After each CIS pixel has acquired its image charge, the corresponding analog image charge data is read out by the image readout circuit 116 in the bottom die 106 through the column bit lines. In various examples, the image charge from each row of the pixel array 108 can be read out in parallel by the image readout circuit 116 through the column bit lines.

[0031] In various examples, the image readout circuit 116 in the bottom die 106 includes amplifiers, analog-to-digital converter (ADC) circuitry, associated analog support circuitry, associated digital support circuitry, etc. for normal image readout and processing. In some examples, the image readout circuit 116 may also include event-driven readout circuitry, as will be described in more detail below. In operation, a photo-generated analog image charge signal is read out from the pixel cells of the pixel array 108, amplified, and converted to a digital value in the image readout circuit 116. In some examples, the image readout circuit 116 may read out one row of image data at a time. In other examples, the image readout circuit 116 may use various other techniques (not shown), such as serial readout or all-pixels simultaneous full-parallel readout, to read out the image data. The image data may be stored or even manipulated by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, etc.).

[0032] In the depicted example, the second die 104 (which may also be referred to as the middle die 104 of the stacked CIS with the EVS system 100) includes an event-driven sensing array 112 coupled to the pixel array 108 in the top die 102. In various examples, the event-driven sensing array 112 is coupled to the pixels of the pixel array 108 through corresponding hybrid bonding pad pairs between the top die 102 and the middle die 104. In one example, the event-driven sensing array 112 includes an event-driven circuit array. As will be discussed, in one example, in accordance with the teachings of the present disclosure, each of the event-driven circuits in the event-driven sensing array 112 is coupled to multiple pixels of the pixel array 108 through pixel-level connections between the top die 102 and the middle die 104 to asynchronously detect events occurring in the light incident on the pixel array 108.

[0033] In some embodiments, the pixels of the second fraction (i.e., hybrid CIS / EVS pixels) may be selectively coupled to the event-driven readout circuitry of the event-driven sensing array 112. When operating as an EVS pixel, the photosensor of the hybrid CIS / EVS pixel can be used to track changes in the intensity of light incident on the photosensor from an external scene. Specifically, the photosensor can generate image charge (electrons or holes) or photocurrent in response to incident light from the external scene. The generated image charge can then be provided to the coupled event-driven circuitry of the event-driven sensing array 112 via an EVS connection (e.g., a hybrid bond). In some embodiments, the event-driven circuitry includes: (i) a photocurrent-to-voltage converter coupled to the photosensor to convert the photocurrent generated by the photosensor into a voltage; and (ii) a filter amplifier coupled to the photocurrent-to-voltage converter to generate a filtered and amplified signal in response to the voltage received from the photocurrent-to-voltage converter. The event-driven circuitry may further include a threshold comparison circuit to determine and generate an event detection signal in response to an event detected asynchronously in the incident light received from the external scene. For example, the threshold comparison circuit can generate an event detection signal when the change in the pixel signal at the output of the filter amplifier relative to a reference pixel signal is greater than a predetermined voltage threshold. It should be understood that the described event-driven readout circuitry is one example implementation for reading out event signals. Various implementations of readout circuitry systems and readout schemes for event vision sensor pixels are well known. Therefore, for the sake of brevity and to clarify the aspects of the present technology, details regarding the circuitry systems and readout techniques for the event-driven circuitry are substantially omitted herein.

[0034] In various examples, a corresponding event detection signal is generated by the event-driven circuitry in the event-driven sensing array 112. The event detection signal can be coupled to be received and processed by the event-driven peripheral circuitry 114, which in one example is arranged around the periphery of the event-driven sensing array 112 in the intermediate die 104, as Figure 1 shown. The depicted example also illustrates the column-level connections 110 for normal image readout that route through the intermediate die 104 between the top die 102 and the bottom die 106.

[0035] II. Various Examples of Pixel Circuits

[0036] Figure 2 An example of a pixel circuit 207 including a pixel array 208 in accordance with the teachings of the present disclosure is illustrated. It should be understood that Figure 2 the pixel array 208 can be an example of the pixel array 108 in the stacked CIS with the EVS system 100 shown in Figure 1 and the similarly named and numbered elements above are coupled and operate similarly hereinafter.

[0037] In the illustrated example, the pixel array 208 includes a plurality of pixel units or pixels 219 arranged in Y rows and X columns. Each pixel 219 may include two sub-pixels 218 each including a photodiode. The two photodiodes in the two sub-pixels 218 are coupled together to share a floating diffusion region 220 (represented as a horizontal line extending between two adjacent sub-pixels 218), such that each pixel 219 includes one floating diffusion region 220. The two sub-pixels 218 are electrically isolated, for example, by a trench isolation structure and / or a junction isolation. An example circuit system of the pixel 219 is described in more detail below with reference to Figure 8 More detailed description.

[0038] The pixel circuit 207 may further include a color filter array 209 disposed on top of the pixel array 208. The color filter array 209 includes a plurality of color filters 230 each having one of a plurality of colors and disposed on top of at least one of the pixels 218. In Figure 2 In one example, the color filter array 209 includes a four-Bayer filter array such that (i) each color filter 230 is disposed on top of a pair of pixels 219 in two adjacent rows and (ii) color filters 230 of the same color are disposed on top of a 4x2 grouping of pixels 219 arranged in four adjacent rows and two adjacent columns. For example, the pixels 219 in rows 1 to 4 and columns 1 to 2 are disposed below a red color filter 230 (labeled "R"), (i) the pixels 219 in rows 1 to 4 and columns 3 to 4 and (ii) the pixels 219 in rows 5 to 8 and columns 1 to 2 are disposed below a green color filter 230 (labeled "G"), and the pixels 219 in rows 5 to 8 and columns 3 to 4 are disposed below a blue color filter 230 (labeled "B").

[0039] The pixel circuit 207 may further include a plurality of microlenses 240 disposed on top of the pixel array 208. Specifically, the microlenses 240 are 1x2 microlenses such that each microlens 240 is disposed on top of two sub-pixels 218 in the same row and two adjacent columns or on top of each pixel 219. The microlenses 240 may help to focus incident light onto the photodiodes included in the pixels 219, thereby improving the sensitivity of the pixel circuit 207 and the overall image quality. The microlenses 240 may also minimize crosstalk between adjacent pixels 219, thereby enhancing the ability of the pixel circuit 207 to accurately capture fine details and colors.

[0040] Each of the pixels 219 may be coupled to a first readout circuit, such as Figure 1 the image readout circuit 116 shown in Figure 2In the middle patterning) and a first subset 219a of the pixels 219. The second subset is a subset of a set that contains some but not all of the elements of the original set. In various examples, only the pixels included in the second subset 219b are configured to be selectively coupled to the second readout circuit depending on the operating mode of the corresponding pixel 219, such as the event-driven circuit in the event-driven sensing array 112 shown in Figure 1 In a particular pixel operating mode (e.g., hybrid mode), the pixels of the remaining subset or the first subset 219a are coupled to the first readout circuit but not to the second readout circuit. In Figure 2 In, the pixels included in the second subset 219b are arranged in a checkerboard pattern such that the second subset 219b includes (i) pixels 219 in odd rows and even columns and (ii) pixels 219 in even rows and odd columns. Thus, according to the teachings of the present disclosure, 50% of the pixels 219 in the pixel array 208 are included in the second subset 219b. Those of ordinary skill in the art will understand that in other examples, the positions of the pixels in the second subset 219b and the remaining subset or the first subset 219a may be flipped (e.g., the second subset 219b includes (i) pixels 219 in odd rows and odd columns and (ii) pixels 219 in even rows and even columns).

[0041] In various examples, the pixel circuit 207 can operate in a first mode, a second mode, and a third mode. In the first mode, all the pixels 219 are configured to be coupled to the first readout circuit to provide CIS information corresponding to the external scene, such that the pixel circuit 207 provides an image without loss of image quality compared to a conventional only-CIS pixel circuit. In the second mode, the pixels of the remaining subset or the first subset 219a are configured to be coupled to the first readout circuit to continue to provide CIS information, and the pixels of the second subset 219b are configured to be coupled to the second readout circuit to provide event detection signals (e.g., providing photocurrent for event detection functionality) and / or other non-CIS imaging information (e.g., intensity change or object motion information). Since the pixels in the second subset 219b are placed under the RGB filter 230, the non-CIS information can be provided in R+G+G+B or gray, which may result in reduced sensitivity of event detection (or other functionality) in the second mode but can provide improved image quality in the first mode. Thus, the second mode is a hybrid mode in which the pixel circuit 207 simultaneously provides CIS information and non-CIS information corresponding to the external scene. In the third mode, all the pixels 219 are configured to be coupled to the second readout circuit to provide non-CIS information.

[0042] It should be understood that according to the teachings of the present disclosure, in Figure 2In the example NxN (e.g., 8x4) pixel circuit 207 shown, when the pixels of the second subset 219b are configured to operate in the second mode and provide an event detection signal, there are also one or more pixels of the first subset 219a configured to provide CIS information under the color filter. Thus, it should be understood that in accordance with the teachings of the present disclosure, in the second or hybrid mode, all sampling sites of any particular color in the 8x4 example pixel circuit 207 are not sacrificed for EVS functionality at any time. In other words, in accordance with the teachings of the present disclosure, for each pixel of the second subset 219b that provides an event detection signal, there is a corresponding pixel of the first subset 219a that preserves color space information placed under the same color filter in the example 8x4 pixel circuit 207.

[0043] Figure 3 An example of a pixel circuit 307 including a pixel array 308 in accordance with the teachings of the present disclosure is illustrated. It should be understood that Figure 3 the pixel array 308 can be an example of the pixel array 108 in the stacked CIS with the EVS system 100 shown in Figure 1 and the similarly named and numbered elements are coupled and operate similarly hereinafter.

[0044] In the illustrated example, the pixel array 308 includes a plurality of pixel units or pixels 319 arranged in Y rows and X columns. Each pixel 319 can include two sub-pixels 318 each including a photodiode. The two photodiodes in the two sub-pixels 318 are coupled together to share a floating diffusion region 320 (represented as a horizontal line extending between two adjacent sub-pixels 318) such that each pixel 319 includes one floating diffusion region 320. The two sub-pixels 318 are electrically isolated, for example, by a trench isolation structure and / or a junction isolation. An example circuit system of the pixel 319 is described in more detail hereinafter with reference to Figure 8 More detailed description.

[0045] The pixel circuit 307 can also include a color filter array 309 disposed above the pixel array 308. The color filter array 309 includes a plurality of color filters 330 each having one of a plurality of colors and disposed above at least one of the pixels 318. In Figure 3In [the figure], the color filter array 309 includes a four-Bayer filter array such that (i) each color filter 330 is disposed over a pair of pixels 319 in two adjacent rows and (ii) color filters 330 of the same color are disposed over a 4x2 grouping of pixels 319 arranged in four adjacent rows and two adjacent columns. For example, the pixels 319 in rows 1 to 4 and columns 1 to 2 are disposed under a red color filter 330 (labeled "R"), (i) the pixels 319 in rows 1 to 4 and columns 3 to 4 and (ii) the pixels 319 in rows 5 to 8 and columns 1 to 2 are disposed under a green color filter 330 (labeled "G"), and the pixels 319 in rows 5 to 8 and columns 3 to 4 are disposed under a blue color filter 330 (labeled "B").

[0046] The pixel circuit 307 may further include a plurality of microlenses 340 disposed over the pixel array 308. Specifically, the microlenses 340 are 2x2 microlenses such that each microlens 340 is disposed over four sub-pixels 318 in adjacent rows and columns or over a pair of pixels 319 in adjacent rows. The microlenses 340 may help to focus incident light onto the photodiodes included in the pair of pixels 319, thereby improving the sensitivity of the pixel circuit 307 and the overall image quality. The microlenses 340 may also minimize crosstalk between adjacent pairs of pixels 319, thereby enhancing the ability of the pixel circuit 307 to accurately capture fine details and colors.

[0047] Each of the pixels 319 may be coupled to a first readout circuit, such as Figure 1 the image readout circuit 116 shown in [the figure]. Thus, all of the pixels 319 may be used to provide CIS information. Additionally, the pixels 319 may include a second subset 319b of the pixels 319 (patterned in Figure 3 [the figure]) and a first subset 319a of the pixels 319. The second subset is a subset of a set that contains some but not all of the elements of the original set. In various examples, only the pixels included in the second subset 319b are configured to selectively couple to a second readout circuit, such as the event-driven circuit included in the Figure 1 event-driven sensing array 112 shown in [the figure], depending on the operating mode of the corresponding pixel 319. In a particular pixel operating mode (e.g., hybrid mode), the pixels in the remaining subset or first subset 319a are thus coupled to the first readout circuit but not to the second readout circuit. In Figure 3In [the figure], the pixels included in the second subset 319b are arranged in a checkerboard pattern such that the second subset 319b includes (i) pixels 319 in odd rows and even columns and (ii) pixels 319 in even rows and odd columns. Thus, according to the teachings of the present disclosure, 50% of the pixels 319 in the pixel array 308 are included in the second subset 319b. Those of ordinary skill in the art will understand that in other examples, the positions of the pixels in the second subset 319b and the remaining subset or the first subset 319a may be flipped (e.g., the second subset 319b includes (i) pixels 319 in odd rows and odd columns and (ii) pixels 319 in even rows and even columns).

[0048] In various examples, the pixel circuit 307 can operate in a first mode, a second mode, and a third mode. In the first mode, all pixels 319 are configured to be coupled to a first readout circuit to provide CIS information corresponding to an external scene, such that compared with a conventional only-CIS pixel circuit, the pixel circuit 307 provides an image without image quality loss. In the second mode, the pixels in the remaining subset or the first subset 319a are configured to be coupled to a first readout circuit (e.g., an image readout circuit) to continue to provide CIS information, and the pixels in the second subset 319b are configured to be coupled to a second readout circuit (e.g., an event-driven circuit) to provide an event detection signal (e.g., providing a photocurrent for event detection functionality) and / or other non-CIS information. Since the pixels in the second subset 319b are disposed under the RGB filter 330, the non-CIS information can be provided corresponding to a combination of red, green, and blue (R+G+G+B) or gray, which may result in a reduced sensitivity of event detection (or other functionality) in the second mode, but can provide improved image quality in the first mode. Thus, the second mode is a hybrid mode in which the pixel circuit 307 simultaneously provides CIS information and non-CIS information corresponding to an external scene. In the third mode, all pixels 319 are configured to be coupled to the second readout circuit to provide non-CIS information.

[0049] It should be understood that according to the teachings of the present disclosure, in Figure 3In the example NxN (e.g., 8x4) pixel circuit 307 shown, when the pixels of the second subset 319b are configured to couple to a second readout circuit to operate in a second mode and provide an event detection signal, there are also one or more pixels of the first subset 319a configured to couple to a first readout circuit to provide CIS information under the color filter. Thus, it should be understood that in accordance with the teachings of the present disclosure, in the second or hybrid mode, all sampling sites of any particular color in the 8x4 example pixel circuit 307 are not sacrificed for EVS functionality at any time. In other words, in accordance with the teachings of the present disclosure, for each pixel of the second subset 319b that provides an event detection signal, there is a corresponding pixel of the first subset 319a disposed under the color filter in the example 8x4 pixel circuit 307.

[0050] Figure 4 An example of a pixel circuit 407 including a pixel array 408 in accordance with the teachings of the present disclosure is illustrated. It should be understood that Figure 4 the pixel array 408 can be an example of the pixel array 108 in the stacked CIS having the EVS system 100 shown in Figure 1 and the similarly named and numbered elements are similarly coupled and operative hereinafter.

[0051] In the illustrated example, the pixel array 408 includes a plurality of pixel units or pixels 419 arranged in Y rows and X columns. Each pixel 419 can include two sub-pixels 418 each including a photodiode. The two photodiodes in the two sub-pixels 418 are coupled together to share a floating diffusion region 420 (represented as a horizontal line extending between two adjacent sub-pixels 418) such that each pixel 419 includes one floating diffusion region 420. The two sub-pixels 418 are electrically isolated, for example, by a trench isolation structure and / or a junction isolation. An example circuit system of the pixel 419 is described in more detail hereinafter with reference to Figure 8 more details.

[0052] The pixel circuit 407 can also include a color filter array 409 disposed over the pixel array 408. The color filter array 409 includes a plurality of color filters each corresponding to one of a plurality of color spectra and disposed over at least one of the pixels 418. In Figure 4In [the figure], the color filter array 409 includes a four-color filter array (referred to as a four-RGBC color array) that includes red (R), green (G), blue (B), and clear (C) color filters, and the color filters are arranged in such a way that: (i) the RGB color filters 430 are disposed over the pixels 419 in the odd rows, (ii) the RGB color filters 430 of the same color are disposed over four pixels 419 in two adjacent columns and two adjacent odd rows (e.g., skipping the even rows), and (iii) non-RGB or clear color filters 432 (or no filter) are disposed over the pixels 419 in the even rows. For example, the pixels 419 in row 1 or 3 and column 1 or 2 are disposed under the red color filter 430 (labeled "R"), the pixels 419 in (i) row 1 or 3 and column 3 or 4 and (ii) row 5 or 7 and column 1 or 2 are disposed under the green color filter 430 (labeled "G"), the pixels 419 in row 5 or 7 and column 3 or 4 are disposed under the blue color filter 430 (labeled "B"), and the pixels 419 in the even rows are disposed under the non-RGB or clear color filter 432 (or no filter).

[0053] The pixel circuit 407 may further include a plurality of microlenses 440 disposed over the pixel array 408. Specifically, the microlenses 440 are 1x2 microlenses such that each microlens 440 is disposed over two sub-pixels 418 in the same row and two adjacent columns or over each pixel 419. The microlenses 440 may help to focus incident light onto the photodiodes included in the pixels 419, thereby improving the sensitivity of the pixel circuit 407 and the overall image quality. The microlenses 440 may also minimize crosstalk between adjacent pixels 419, thereby enhancing the ability of the pixel circuit 407 to accurately capture fine details and colors.

[0054] Each of the pixels 419 may be coupled to a first readout circuit, such as Figure 1 the image readout circuit 116 shown in [the figure]. Thus, all of the pixels 419 may be used to provide CIS information. Additionally, the pixels 419 may include a second subset 419b of the pixels 419 (patterned in Figure 4 [the figure]) and a first subset 419a of the pixels 419. The second subset is a subset of a set that contains some but not all of the elements of the original set. In various examples, only the pixels included in the second subset 419b are configured to selectively couple to a second readout circuit, such as the event-driven circuit included in Figure 1 the event-driven sensing array 112 shown in [the figure], depending on the operating mode of the corresponding pixel 419. In a particular pixel operating mode (e.g., a hybrid mode), the pixels of the remaining subset or first subset 419a are coupled to the first readout circuit but not to the second readout circuit. In Figure 4In this case, the second subset 419b and the first subset 419a are arranged in alternating rows such that the second subset 419b contains the pixels 419 in the even rows and the first subset 419a contains the pixels 419 in the odd rows. Thus, all the pixels included in the second subset 419b are placed under a non-RGB or transparent filter 432 (or no filter). Consequently, according to the teachings of the present disclosure, 50% of the pixels 419 in the pixel array 408 are included in the second subset 419b. Those of ordinary skill in the art will appreciate that in other instances, the positions of the pixels in the second subset 419b and the first subset 419a may be flipped (e.g., the second subset 419b contains the pixels 419 in the odd rows).

[0055] In various instances, the pixel circuit 407 can operate in a first mode, a second mode, and a third mode. In the first mode, all the pixels 419 are configured to couple to a first readout circuit to provide CIS information corresponding to an external scene, such that the pixel circuit 407 provides an image without loss of image quality compared to a conventional only-CIS pixel circuit. In the second mode, the pixels in the first subset 419a are configured to couple to the first readout circuit to continue providing CIS information, and the pixels in the second subset 419b are configured to couple to a second readout circuit to provide an event detection signal (e.g., providing a photocurrent for event detection functionality) and / or other non-CIS information. Placing the second subset 419b under a non-RGB or transparent filter 432 (or no filter) can help increase the generated photocurrent and / or reduce the latency associated with the pixels included in the second subset 419b. Thus, the second mode is a hybrid mode in which the pixel circuit 407 simultaneously provides CIS information and non-CIS information corresponding to an external scene. In the third mode, all the pixels 419 are configured to couple to the second readout circuit to provide non-CIS information.

[0056] It should be understood that according to the teachings of the present disclosure, in Figure 4 the NxN (e.g., 8x4) pixel circuit 407 shown in, when the pixels of the second subset 419b are configured to couple to the second readout circuit to operate in the second mode and provide an event detection signal, there is also one or more pixels of the first subset 419a configured to couple to the first readout circuit to provide CIS information under the color filter. Thus, it should be understood that according to the teachings of the present disclosure, in the second or hybrid mode, all the sampling sites of any particular color in the 8x4 example pixel circuit 407 are not sacrificed for EVS functionality at any time. In other words, according to the teachings of the present disclosure, for each pixel of the second subset 419b that provides an event detection signal, there is a corresponding pixel of the first subset 419a placed under the color filter in the example 8x4 pixel circuit 407.

[0057] Figure 5Describe an example of a pixel circuit 507 including a pixel array 508 in accordance with the teachings of the present disclosure. It should be understood that Figure 5 the pixel array 508 may be an example of the pixel array 108 in the stacked CIS having the EVS system 100 shown in Figure 1 , and the similarly named and numbered elements above are similarly coupled and operative hereinafter.

[0058] In the illustrated example, the pixel array 508 includes a plurality of pixel units or pixels 519 arranged in Y rows and X columns. Each pixel 519 may include two sub-pixels 518 each including a photodiode. The two photodiodes in the two sub-pixels 518 are coupled together to share a floating diffusion region 520 (represented as a horizontal line extending between two adjacent sub-pixels 518), such that each pixel 519 includes one floating diffusion region 520. The two sub-pixels 518 are electrically isolated, for example, by a trench isolation structure and / or a junction isolation. An example circuit system of the pixel 519 is described in more detail hereinafter with reference to Figure 8 more detail.

[0059] The pixel circuit 507 may further include a color filter array 509 disposed above the pixel array 508. The color filter array 509 includes a plurality of color filters each corresponding to one of a plurality of color spectra and disposed above at least one of the pixels 518. In Figure 5 , the color filter array 509 includes an RGBC filter array such that (i) the RGB color filters 530 are disposed above the pixels 519 in odd rows, (ii) the RGB color filters 530 of different colors are disposed above the pixels 519 in adjacent columns and adjacent odd rows (e.g., skipping even rows), and (iii) non-RGB or transparent filters 532 (or no filter) are disposed above the pixels 519 in even rows. For example, the pixels 519 in row 1 or 5 and column 1 or 3 are disposed below the red color filter 530 (labeled "R"), the pixels 519 in (i) odd rows and even columns and (ii) even rows and odd columns are disposed below the green color filter 530 (labeled "G"), the pixels 519 in row 3 or 7 and column 2 or 4 are disposed below the blue color filter 530 (labeled "B"), and the pixels 519 in even rows are disposed below the non-RGB or transparent filter 532 (or no filter).

[0060] The pixel circuit 507 may also include a plurality of microlenses 540 disposed over the pixel array 508. Specifically, the microlenses 540 are 2x2 microlenses such that each microlens 540 is disposed over four sub-pixels 518 in adjacent rows and columns or over a pair of pixels 519 in adjacent rows. The microlenses 540 may help to focus the incident light onto the photodiodes included in the pair of pixels 519, thereby improving the sensitivity of the pixel circuit 507 and the overall image quality. The microlenses 540 may also minimize crosstalk between adjacent pairs of pixels 519, thereby enhancing the ability of the pixel circuit 507 to accurately capture fine details and colors.

[0061] Each of the pixels 519 may be coupled to a first readout circuit, such as Figure 1 the image readout circuit 116 shown in Figure 5 . Thus, all of the pixels 519 may be used to provide CIS information. Additionally, the pixels 519 may include a second subset 519b of the pixels 519 (patterned in Figure 1 ) and a first subset 519a of the pixels 519. A subset is a set that contains some but not all of the elements of the original set. In various examples, only the pixels included in the second subset 519b are configured to selectively couple to a second readout circuit, such as the event-driven circuit included in the event-driven sensing array 112 shown in Figure 5 . In a particular pixel operating mode (e.g., hybrid mode), the pixels of the remaining subset or first subset 519a are coupled to the first readout circuit but not to the second readout circuit. In Figure 5 , the second subset 519b and the first subset 519a are arranged in alternating rows such that the second subset 519b includes the pixels 519 in the even rows and the first subset 519a includes the pixels 519 in the odd rows. Thus, according to the teachings of the present disclosure, 50% of the pixels 519 in the pixel array 508 are included in the second subset 519b. Therefore, all of the pixels included in the second subset 519b are disposed under a non-RGB or transparent color filter 532 (or no color filter). Those of ordinary skill in the art will appreciate that in other examples, the positions of the pixels in the second subset 519b and the first subset 519a may be flipped (e.g., the second subset 519b includes the pixels 519 in the odd rows).

[0062] In various examples, the pixel circuit 507 can operate in a first mode, a second mode, and a third mode. In the first mode, all the pixels 519 are configured to couple to a first readout circuit (e.g., an image readout circuit) to provide CIS information corresponding to an external scene, such that the pixel circuit 507 provides an image without loss of image quality compared to a conventional only-CIS pixel circuit. In the second mode, the pixels in the first subset 519a are configured to couple to the first readout circuit to continue to provide CIS information, and the pixels in the second subset 519b are configured to couple to a second readout circuit (e.g., an event-driven circuit) to provide an event detection signal (e.g., providing a photocurrent for event detection functionality) and / or other non-CIS information. Placing the second subset 519b under a non-RGB or transparent filter 532 (or no filter) can help increase the generated photocurrent and / or reduce the latency associated with the pixels included in the second subset 519b. Thus, the second mode is a hybrid mode in which the pixel circuit 507 simultaneously provides CIS information and non-CIS information corresponding to the external scene. In the third mode, all the pixels 519 are configured to couple to the second readout circuit to provide non-CIS information.

[0063] It should be understood that, according to the teachings of the present disclosure, in the Figure 5 illustrated example NxN (e.g., 8x4) pixel circuit 507, when the pixels of the second subset 519b are configured to couple to the second readout circuit to operate in the second mode and provide an event detection signal, there is also at least one pixel of the first subset 519a configured to couple to the first readout circuit to provide CIS information under the color filter. Thus, it should be understood that, according to the teachings of the present disclosure, in the second or hybrid mode, all the sampling sites of any particular color in the 8x4 example pixel circuit 507 are not sacrificed for EVS functionality at any time. In other words, according to the teachings of the present disclosure, for each pixel of the second subset 519b that provides an event detection signal, there is a corresponding pixel of the first subset 519a placed under the color filter in the example 8x4 pixel circuit 507.

[0064] Figure 6 Describe an example of a pixel circuit 607 including a pixel array 608 according to the teachings of the present disclosure. It should be understood that Figure 6 the pixel array 608 of Figure 1 can be an example of the pixel array 108 in the stacked CIS with an EVS system 100 shown in

[0065] In the illustrated example, the pixel array 608 includes a plurality of pixel units or pixels 619 arranged in Y rows and X columns. Each pixel 619 may include two sub-pixels 618 each including a photodiode. The two photodiodes in the two sub-pixels 618 are coupled together to share a floating diffusion region 620 (represented as a horizontal line extending between two adjacent sub-pixels 618), such that each pixel 619 includes one floating diffusion region 620. The two sub-pixels 618 are electrically isolated, for example, by a trench isolation structure and / or a junction isolation. An example circuit system of the pixel 619 is described in more detail below with reference to Figure 8 More detailed description.

[0066] The pixel circuit 607 may further include a color filter array 609 disposed on top of the pixel array 608. The color filter array 609 includes a plurality of color filters 630 each corresponding to one of a plurality of color spectra and disposed on top of at least one of the pixels 618. In Figure 6 In, the color filter array 609 includes a four-Bayer filter array such that (i) each color filter 630 is disposed on top of a pair of pixels 619 in two adjacent rows and (ii) color filters 630 of the same color are disposed on top of a 4x2 grouping of pixels 619 arranged in four adjacent rows and two adjacent columns. For example, the pixels 619 in rows 1 to 4 and columns 1 to 2 are disposed under a red color filter 630 (labeled "R"), (i) the pixels 619 in rows 1 to 4 and columns 3 to 4 and (ii) the pixels 619 in rows 5 to 8 and columns 1 to 2 are disposed under a green color filter 630 (labeled "G"), and the pixels 619 in rows 5 to 8 and columns 3 to 4 are disposed under a blue color filter 630 (labeled "B").

[0067] The pixel circuit 607 may further include a plurality of microlenses 640 disposed on top of the pixel array 608. Specifically, the microlenses 640 are 1x2 microlenses such that each microlens 640 is disposed on top of two sub-pixels 618 in the same row and two adjacent columns or on top of each pixel 619. The microlenses 640 may help focus incident light onto the photodiodes included in the pixels 619, thereby improving the sensitivity of the pixel circuit 607 and the overall image quality. The microlenses 640 may also minimize crosstalk between adjacent pixels 619, thereby enhancing the ability of the pixel circuit 607 to accurately capture fine details and colors.

[0068] Each of the pixels 619 may be coupled to a first readout circuit, such as Figure 1 The image readout circuit 116 shown in. Thus, all the pixels 619 can be used to provide CIS information. In addition, the pixels 619 may include a second subset 619b of the pixels 619 (in Figure 6In the middle patterning) and a first subset 619a of the pixels 619. A second subset is a subset of a set that contains some but not all of the elements of the original set. In various examples, only the pixels included in the second subset 619b are configured to be selectively coupled to the second readout circuit depending on the operating mode of the corresponding pixel 619, such as the event-driven circuit included in the event-driven sensing array 112 shown in Figure 1 In the event-driven sensing array 112 shown in Figure 6 In the example, the pixels included in the second subset 619b are arranged in alternating rows such that the second subset 619b includes the pixels 619 in the even rows and the first subset 619a includes the pixels 619 in the odd rows. Thus, according to the teachings of the present disclosure, 50% of the pixels 619 in the pixel array 608 are included in the second subset 619b. Therefore, all the pixels included in the second subset 619b are disposed under the RGB filter 630. Those of ordinary skill in the art should understand that in other examples, the positions of the pixels in the second subset 619b and the pixels in the first subset 619a may be flipped (e.g., the second subset 619b includes the pixels 619 in the odd rows).

[0069] In various examples, the pixel circuit 607 can operate in a first mode, a second mode, and a third mode. In the first mode, all the pixels 619 are configured to be coupled to the first readout circuit (e.g., an image readout circuit) to provide CIS information corresponding to an external scene, such that the pixel circuit 607 provides an image without loss of image quality compared to a conventional only-CIS pixel circuit. In the second mode, the pixels in the remaining subset or the first subset 619a are configured to be coupled to the first readout circuit to continue providing CIS information, and the pixels in the second subset 619b are configured to be coupled to the second readout circuit (e.g., an event-driven circuit) to provide an event detection signal (e.g., providing photocurrent for event detection functionality) and / or other non-CIS information. Since the pixels in the second subset 619b are disposed under the RGB filter 630, the non-CIS information can be provided in a combined color information of red, green, green, and blue information (e.g., R+G+G+B) or gray, which may result in a reduced sensitivity of event detection (or other functionality) in the second mode but can provide improved image quality in the first mode. Therefore, the second mode is a hybrid mode in which the pixel circuit 607 simultaneously provides CIS information and non-CIS information corresponding to an external scene. In the third mode, all the pixels 619 are configured to be coupled to the second readout circuit to provide non-CIS information.

[0070] It should be understood that according to the teachings of the present disclosure, in Figure 6In the example NxN (e.g., 8x4) pixel circuit 607 shown, when the pixels of the second subset 619b are configured to couple to the second readout circuit to operate in the second mode and provide an event detection signal, there are also one or more pixels of the first subset 619a configured to couple to the first readout circuit to provide CIS information under the color filter. Thus, it should be understood that in accordance with the teachings of the present disclosure, in the second or hybrid mode, all sampling sites of any particular color in the 8x4 example pixel circuit 607 are not sacrificed for EVS functionality at any time. In other words, in accordance with the teachings of the present disclosure, for each pixel of the second subset 619b that provides an event detection signal, there is a corresponding pixel of the first subset 619a disposed under the color filter in the example 8x4 pixel circuit 607.

[0071] Figure 7 Describes an example of a pixel circuit 707 including a pixel array 708 in accordance with the teachings of the present disclosure. It should be understood that Figure 7 the pixel array 708 of Figure 1 may be an example of the pixel array 108 in the stacked CIS having the EVS system 100 shown in

[0072] In the illustrated example, the pixel array 708 includes a plurality of pixel units or pixels 719 arranged in Y rows and X columns. Each pixel 719 may include two sub-pixels 718 each including a photodiode. The two photodiodes in the two sub-pixels 718 are coupled together to share a floating diffusion region 720 (represented as a horizontal line extending between two adjacent sub-pixels 718), such that each pixel 719 includes one floating diffusion region 720. The two sub-pixels 718 are electrically isolated, for example, by a trench isolation structure and / or a junction isolation. The example circuitry of the pixel 719 is described in more detail below with reference to Figure 8 More detailed description.

[0073] The pixel circuit 707 may also include a color filter array 709 disposed over the pixel array 708. The color filter array 709 includes a plurality of color filters each corresponding to one of a plurality of color spectra and disposed over at least one of the pixels 718. In Figure 7In [the figure], the color filter array 709 includes a four-RGBC color filter array including a red color filter, a green color filter, a blue color filter, and a transparent color filter, and the color filters are arranged in such a way that: (i) the RGB color filters 730 of the same color are disposed over four pixels 719 in (a) two adjacent odd rows (e.g., skipping even rows) and odd columns and (b) two adjacent even rows (e.g., skipping odd rows) and even columns, and (ii) the non-RGB or transparent color filters 732 (or no color filter) are disposed over the pixels 719 in (a) two adjacent odd rows (e.g., skipping even rows) and even columns and (b) two adjacent even rows (e.g., skipping odd rows) and odd columns. For example, the pixels 719 in (i) row 1 or 3 and column 1 and (ii) row 2 or 4 and column 2 are disposed under the red color filter 730 (labeled "R"), the pixels 719 in (i) row 1 or 3 and column 3, (ii) row 2 or 4 and column 4, (iii) row 5 or 7 and column 1, and (iv) row 6 or 8 and column 2 are disposed under the green color filter 730 (labeled "G"), the pixels 719 in (i) row 5 or 7 and column 3 and (ii) row 6 or 8 and column 4 are disposed under the blue color filter 730 (labeled "B"), and the pixels 719 in (i) even rows and odd columns and (ii) odd rows and even columns are disposed under the non-RGB or transparent color filter 732 (or no color filter).

[0074] The pixel circuit 707 may further include a plurality of microlenses 740 disposed over the pixel array 708. Specifically, the microlenses 740 are 1x2 microlenses such that each microlens 740 is disposed over two sub-pixels 718 in the same row and two adjacent columns or over each pixel 719. The microlenses 740 may help to focus incident light onto the photodiodes included in the pixels 719, thereby improving the sensitivity of the pixel circuit 707 and the overall image quality. The microlenses 740 may also minimize crosstalk between adjacent pixels 719, thereby enhancing the ability of the pixel circuit 707 to accurately capture fine details and colors.

[0075] Each of the pixels 719 may be coupled to a first readout circuit, such as Figure 1 the image readout circuit 116 shown in [the figure]. Thus, all of the pixels 719 may be used to provide CIS information. In addition, the pixels 719 may include a second subset 719b of the pixels 719 (patterned in Figure 7 [the figure]) and a first subset 719a of the pixels 719. The second subset is a subset of a set that contains some but not all of the elements of the original set. In various examples, only the pixels included in the second subset 719b are configured to selectively couple to a second readout circuit, such as included in Figure 1The event-driven circuitry in the event-driven sensing array 112 shown in. In a particular pixel operation mode (e.g., hybrid mode), the pixels of the remaining subset or first subset 719a are coupled to the first readout circuit but not to the second readout circuit. In Figure 7 , the second subset 719b and the first subset 719a are arranged in (i) even rows and odd columns and (ii) odd rows and even columns. Thus, all the pixels included in the second subset 719b are placed under a non-RGB or transparent filter 732 (or no filter). Accordingly, 50% of the pixels 719 in the pixel array 708 are included in the second subset 719b according to the teachings of the present disclosure. Those of ordinary skill in the art will appreciate that in other instances, the positions of the pixels in the second subset 719b and the pixels in the first subset 719a may be flipped (e.g., the second subset 719b includes the pixels 719 in the odd rows).

[0076] In various instances, the pixel circuit 707 can operate in a first mode, a second mode, and a third mode. In the first mode, all the pixels 719 are configured to be coupled to the first readout circuit (e.g., an image readout circuit) to provide CIS information such that, compared to a conventional only-CIS pixel circuit, the pixel circuit 707 provides an image without loss of image quality. In the second mode, the pixels in the first subset 719a are configured to be coupled to the first readout circuit to continue to provide CIS information, and the pixels in the second subset 719b are configured to be coupled to the second readout circuit (e.g., an event-driven circuit) to provide an event detection signal (e.g., providing a photocurrent for event detection functionality) and / or other non-CIS information. Placing the second subset 719b under a non-RGB or transparent filter 732 (or no filter) can help increase the generated photocurrent and / or reduce the latency associated with the pixels included in the second subset 719b. Thus, the second mode is a hybrid mode in which the pixel circuit 707 provides both CIS information and non-CIS information. In the third mode, all the pixels 719 are configured to be coupled to the second readout circuit to provide non-CIS information.

[0077] It should be understood that according to the teachings of the present disclosure, in Figure 7In the example NxN (e.g., 8x4) pixel circuit 707 shown, when the pixels of the second subset 719b are configured to couple to the second readout circuit to operate in the second mode and provide an event detection signal, there are also one or more pixels of the first subset 719a configured to couple to the first readout circuit to provide CIS information under the color filter. Thus, it should be understood that in accordance with the teachings of the present disclosure, in the second or hybrid mode, all sampling sites of any particular color in the 8x4 example pixel circuit 707 are not sacrificed for EVS functionality at any time. In other words, in accordance with the teachings of the present disclosure, for each pixel of the second subset 719b that provides an event detection signal, there is a corresponding pixel of the first subset 719a disposed under the color filter in the example 8x4 pixel circuit 707.

[0078] It should be understood that the pixel circuits described herein and above are merely examples illustrating certain features of the present disclosure, and other pixel circuits are within the scope of the present disclosure. For example, the pixel circuit may include pixels in a second subset arranged in a checkerboard pattern (e.g., as shown in Figure 2 , 3 and 7) and disposed under a non-RGB or transparent filter (or no filter) (e.g., as shown in Figure 4 , 5 and 7). In another example, the pixel circuit may include pixels in a second subset arranged in alternating rows (e.g., as shown in Figures 4 to 6 ) and disposed under a color filter (e.g., as shown in Figure 2 , 3 and 6). The pixels may be disposed under a Bayer filter array, a quad-Bayer filter array, an RGBC filter array, or a quad-RGBC filter array. In various examples, the pixel circuit may include pixels structured and arranged to provide phase detection information (e.g., half-shielded phase detection autofocus pixels (PDAF), dual PD, quad PD). The pixel circuit may also include a plurality of 1x2 microlenses disposed over the pixel array (e.g., as shown in Figure 2 , 4 , 6 and 7) or a plurality of 2x2 microlenses (e.g., as shown in Figure 3 and 5 ). In various examples, the second subset may include different proportions of the pixels in the pixel array, such as 1 / 16, 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, or other proportions. In other examples, all pixels are coupled to the second readout circuit without distinguishing between the second subset and the first subset of pixels.

[0079] As discussed above, an imaging system configured in accordance with the teachings of the present disclosure can be configured between a first mode that provides only CIS information, a second mode that provides hybrid (e.g., simultaneous CIS and non-CIS) information, and a third mode that provides only non-CIS information without loss of image quality. This enables the imaging system to selectively provide various types of information without sacrificing conventional imaging quality, which is different from many conventional imaging systems.

[0080] In some cases, due to the way most image sensor systems are used, it may be preferable to arrange the pixels included in the second subset in a checkerboard pattern. For example, an image sensor (e.g., a smartphone camera) is typically held horizontally or vertically such that horizontal lines or edges (e.g., of a wall, door, window, etc.) fall on a single row or column. If (i) the imaging system is operating in the second (e.g., hybrid) mode, (ii) the pixels included in the second subset cover an entire row or column, and (iii) incident light from a horizontal line or edge falls on the row or column that is fully occupied by the pixels included in the second subset, then the imaging system may not be able to clearly capture that horizontal line or edge due to the lack of CIS pixels in those rows or columns. On the other hand, the checkerboard pattern ensures that each row and column always contains CIS pixels to capture those horizontal lines or edges regardless of the mode in which the imaging system is operating.

[0081] In addition, in various examples of the pixel circuits disclosed herein (including pixel circuits 207, 307, 407, 507, 607, 707 and pixel circuits not fully illustrated but described above), each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of the pixels and a second pixel included in the first subset of the pixels and disposed below one of the color filters. Thus, when the pixel circuit is operating in the second (e.g., hybrid) mode described above, the arrangements described herein result in a high sampling point distribution for event detection, phase detection autofocus (PDAF), or other processing performed exclusively on signals from the pixels included in the second subset. Compared to other image sensors, the high sampling point distribution disclosed herein can result in improved contrast and / or modulation transfer function (MTF).

[0082] III. Various Examples of Pixel Array Layouts

[0083] Figure 8 An example of a pixel 819 coupled to a mode selection switch circuit 882 in accordance with the teachings of the present disclosure is illustrated, where the mode selection switch circuit 882 is coupled to a second readout circuit 880. It should be understood that Figure 8 the pixel 819 can be included in Figures 2 to 7Examples of pixels 219, 319, 419, 519, 619, 719 in pixel circuits 207, 307, 407, 507, 607, 707 shown in [description], and similarly named and numbered elements above are coupled and operate similarly hereinafter.

[0084] Pixel 819 may include a first photodiode 862a, a second photodiode 862b, a floating diffusion region (FD) 820, a first transfer transistor 864a, a second transfer transistor 864b, a source follower transistor 866, a row selection transistor 868, and a reset transistor 869. The first photodiode 862a corresponding to the first sub-pixel may be configured to photogenerate a first image charge in response to incident light. The second photodiode 862b corresponding to the second sub-pixel may be configured to photogenerate a second image charge in response to incident light. The FD 820 may be coupled to receive the first image charge from the first photodiode 862a and the second image charge from the second photodiode 862b. The first transfer transistor 864a may be coupled between the first photodiode 862a and the FD 820 to transfer the first image charge from the first photodiode 862a to the floating diffusion region FD 820. The second transfer transistor 864b may be coupled between the second photodiode 862b and the FD 820 to transfer the second image charge from the second photodiode 862b to the FD 820. The gate terminal of the source follower transistor 866 may be coupled to the FD 820, and the row selection transistor 868 may be coupled to the source follower transistor 866. The reset transistor 869 may be coupled to the FD 820 to selectively reset the FD 820 to a predetermined voltage level.

[0085] In the depicted example, the mode selection switch circuit 882 may include a first transistor 882a coupled between node N and the voltage source vpix. In the depicted example, node N is coupled to a second readout circuit 880, and in the example, the second readout circuit 880 is included in Figure 1Part of one of the event-driven circuits in the event-driven sensing array 112 shown in FIG. In the depicted example, the logarithmic amplifier stage portion of the second readout circuit 880 is illustrated, which includes a second transistor 884 coupled between node N and another voltage source and an inverter 886 coupled to node N. The gate of the second transistor 884 and the output of the inverter 886 may be coupled to other circuits, such as other stages of the second readout circuit 880 discussed above (e.g., one of the event-driven circuits included in the event-driven sensing array 112). In one example, pixel 819 is configured to provide CIS information or an event detection signal in response to the first transistor 882a. Specifically, in the depicted example, when pixel 819 is operating in the first mode configured to provide CIS information, the first transistor 882a of the mode selection switch circuit 882 may be turned on. In an example, when pixel 819 is operating in the second or third mode and is configured to provide an event detection signal (e.g., providing photocurrent for event detection functionality) and / or other non-CIS information, the first transistor 882a may be turned off. It should be understood that Figure 8 The illustrated embodiments of the mode selection switch circuit 882 and the logarithmic amplifier stage portion of the second readout circuit 880 are merely one example, and other circuitry may be implemented.

[0086] As shown, pixel 819 may be located on the top die 102, and the mode selection switch circuit 882 and the second readout circuit 880 may be located on the middle die 104 and coupled to one or more pixels 819. More specifically, in the illustrated example, the reset transistor 869 of pixel 819 is coupled to the mode selection switch circuit 882 through a hybrid bond 870 (or other type of bond) between the top die 102 and the middle die 104.

[0087] Figure 9 An example of a pixel array 908 coupled to the mode selection switch circuit 882 in accordance with the teachings of the present disclosure is illustrated. It should be understood that Figure 9 the pixel array 908 may be an example of half of the pixel arrays 408 and 508 included in the pixel circuits 407, 507, 607 shown in Figures 4 to 6 and the similarly named and numbered elements above are similarly coupled and operative hereinafter.

[0088] In the illustrated example, the pixel array 908 located on the top die 102 includes a plurality of pixels 819 arranged in rows and columns. The pixels included in the second subset 819b (one of which is boxed in a dashed line) include reset transistors coupled to the mode selection switch circuit 882. However, the pixels included in the remaining subset or the first subset 819a (one of which is boxed in a dashed line) are not coupled to the mode selection switch circuit 882. In Figure 9Among them, the pixels included in the second subset 819b are arranged in alternating rows (e.g., in the second and fourth rows) and in each column of those rows. This arrangement of the pixels included in the second subset 819b is the same as or substantially similar to the arrangement described in Figures 4 to 6 In addition, the pixel array 908 illustrates only four rows of pixels and is thus Figures 4 to 6 Half of the pixel arrays 408, 508, 608 shown in

[0089] Figure 10 Another example of a pixel array 1008 coupled to the mode selection switch circuit 882 in accordance with the teachings of the present disclosure is illustrated. It should be understood that Figure 10 The pixel array 1008 of Figure 2 can be an example of half of the pixel arrays 208, 308, 708 included in the pixel circuits 207, 307, 707 shown in 3 and 7, and the similarly named and numbered elements above are coupled and function similarly hereinafter.

[0090] In the illustrated example, the pixel array 1008 located on the top die 102 includes a plurality of pixels 819 arranged in rows and columns. The pixels included in the second subset 819b (one of which is framed by a dashed line) include reset transistors coupled to the mode selection switch circuit 882. However, the pixels included in the first subset 819a (one of which is framed by a dashed line) are not coupled to the mode selection switch circuit 882. In Figure 10 Among them, the pixels included in the second subset 819b are arranged in a checkerboard pattern (e.g., in a staggered manner). This arrangement of the pixels included in the second subset 819b is the same as or substantially similar to the arrangement described in Figure 2 、 3 and 7. In addition, the pixel array 1008 illustrates only four rows of pixels and is thus Figure 2 、 3 Half of the pixel arrays 208, 308, 708 shown in and 7.

[0091] Compared with the pixel array 908 of Figure 9 the pixel array 1008 of Figure 10 provides a more advanced sampling point distribution. For example, the pixel array 1008 includes at least two pixels in the second subset 819b included in each row and column, while the pixel array 908 does not include any pixels in the second subset 819b included in half of the rows.

[0092] In operation, the mode selection switch circuit 882 can be controlled to operate in a first mode in which all pixels 819 are connected through source follower transistors 866 and row selection transistors 868 ( Figure 8) Configuring the pixel arrays 908, 1008 and thus the imaging system including the pixel arrays 908, 1008 between a first mode (providing CIS information), a second mode (wherein the pixels included in the second subset 819b are connected to the second readout circuit 880 (e.g., one of the event-driven circuits) in response to the first transistor 882a of the mode selection switch circuit 882 being turned off (the reset transistor 869 may be turned on)), and a third mode (wherein all pixels are connected to the second readout circuit 880 to provide non-CIS information). In the second mode, the pixels included in the first pixel 819a continue to provide CIS information through the source follower transistor 866 and the row selection transistor 868. Thus, the imaging system operates in a hybrid state by providing both CIS and event detection (or other non-CIS) information simultaneously.

[0093] As discussed above, an imaging system configured in accordance with the teachings of the present disclosure can be configured between a first mode providing CIS information and a second mode providing hybrid information without loss of image quality. This enables the imaging system to provide additional information without sacrificing conventional imaging, unlike many conventional imaging systems. Additionally, because the pixels included in the second subset are arranged in a high sampling point distribution (e.g., for event detection, phase detection autofocus (PDAF), or other processing), the imaging system can provide improved contrast and / or modulation transfer function (MTF) compared to other image sensors.

[0094] IV. Conclusion

[0095] The foregoing description of the illustrative examples of the present disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific examples of the disclosure are described herein for illustrative purposes, those skilled in the relevant art will recognize that various modifications are possible within the scope of the disclosure.

[0096] These modifications can be made in light of the above detailed description. The terms used in the appended claims should not be construed as limiting the disclosure to the specific examples disclosed in the specification. Instead, the scope of the disclosure will be determined entirely by the appended claims, which are to be construed in accordance with the established principles of claim interpretation.

Claims

1. A pixel circuit, comprising: A pixel array comprising a plurality of pixels arranged in rows and columns, wherein each pixel comprises: a first photodiode configured to photogenerate a first image charge in response to incident light; a second photodiode configured to photogenerate a second image charge in response to incident light; a floating diffusion region coupled to receive the first image charge from the first photodiode and to receive the second image charge from the second photodiode; a first transfer transistor coupled between the first photodiode and the floating diffusion region to transfer the first image charge from the first photodiode to the floating diffusion region; and a second transfer transistor coupled between the second photodiode and the floating diffusion region to transfer the second image charge from the second photodiode to the floating diffusion region; and a color filter array disposed over the pixel array, wherein the color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels, wherein each of the plurality of pixels is selectively coupled to a first readout circuit, wherein the plurality of pixels include: a first subset of the pixels configured to be disconnected from a second readout circuit while being connected to the first readout circuit to read out a first set of data signals, and a second subset of the pixels selectively coupled to the second readout circuit to read out a second set of data signals, wherein the second set of data signals is different from the first set of data signals, and Wherein each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of the pixels and a second pixel included in the first subset of the pixels, and the first pixel and the second pixel are disposed under one of the color filters. 2 . The pixel circuit of claim 1 , wherein the second subset of the pixels comprises 50% of the pixels included in the pixel array. 3 . The pixel circuit of claim 1 , further comprising a plurality of microlenses disposed over the pixel array, wherein each microlens is disposed over each pixel. 4 . The pixel circuit of claim 1 , further comprising a plurality of microlenses disposed over the pixel array, wherein each microlens is disposed over a pair of pixels in two adjacent rows.

5. The pixel circuit of claim 1 , wherein the color filter array comprises a quad-Bayer filter array such that (i) each color filter is disposed over a pair of pixels in two adjacent rows and (ii) color filters of the same color are disposed over 4×2 pixel groups arranged in four adjacent rows and two adjacent columns, and wherein the pixels included in the second subset are arranged in a checkerboard pattern across the pixel array.

6. The pixel circuit of claim 1 , wherein the color filter array comprises a quad-Bayer filter array such that (i) each color filter is disposed over a pair of pixels in two adjacent rows and (ii) color filters of the same color are disposed over 4×2 pixel groups arranged in four adjacent rows and two adjacent columns, and wherein the pixels included in the second subset are arranged in alternating rows across the pixel array.

7. A pixel circuit according to claim 1, wherein the color filter array comprises a four-color filter array formed by a red filter, a green filter, a blue filter and a transparent filter array, so that (i) red, green and blue filters of the same color are placed on four pixels included in the first subset arranged in four adjacent rows and two adjacent columns in a staggered manner and (ii) transparent filters are placed on the pixels included in the second subset and arranged in a checkerboard pattern across the pixel array.

8. A pixel circuit according to claim 1, wherein the color filter array includes a four-red, green, and blue transparent filter array, which is formed by a red filter, a green filter, a blue filter and a transparent filter, so that (i) red, green, and blue filters of the same color are placed over four pixels included in the first subset arranged in two non-adjacent rows and two adjacent columns and (ii) transparent filters are placed over the pixels included in the second subset and arranged in alternating rows across the pixel array.

9. The pixel circuit of claim 1 , wherein the color filter array comprises a color filter array formed by a red filter, a green filter, a blue filter, and a transparent filter, such that (i) red, green, and blue filters of different colors are disposed over pixels included in the first subset arranged in adjacent columns and (ii) transparent filters are disposed over the pixels included in the second subset and arranged in alternating rows across the pixel array.

10. The pixel circuit of claim 1, wherein each 2x2 pixel grouping arranged in two adjacent rows and two adjacent columns includes a first pair of pixels included in the second subset of pixels and a second pair of pixels included in the first subset of pixels and disposed below both of the color filters.

11. An imaging system comprising: A pixel circuit comprising a pixel array having a plurality of pixels arranged in rows and columns, wherein each pixel comprises: a first photodiode configured to photogenerate a first image charge in response to incident light; a second photodiode configured to photogenerate a second image charge in response to incident light; a floating diffusion region coupled to receive the first image charge from the first photodiode and to receive the second image charge from the second photodiode; a first transfer transistor coupled between the first photodiode and the floating diffusion region to transfer the first image charge from the first photodiode to the floating diffusion region; and a second transfer transistor coupled between the second photodiode and the floating diffusion region to transfer the second image charge from the second photodiode to the floating diffusion region; and a color filter array disposed over the pixel array, wherein the color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels; a first readout circuit selectively coupled to each of the plurality of pixels to read out a first set of data signals; a second readout circuit, wherein the plurality of pixels includes a first subset of the pixels coupled to the first readout circuit and a second subset of the pixels selectively coupled to the second readout circuit configured to be disconnected from the second readout circuit, wherein the second readout circuit is coupled to each of the pixels included in the second subset to read out a second set of data signals; and A mode selection switch circuit is coupled to the pixels included in the second subset, wherein the pixels included in the second subset are configured to provide the first set of data signals to the first readout circuit or to provide the second set of data signals to the second readout circuit in response to the mode selection circuit, wherein each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of pixels and a second pixel included in the first subset of pixels and disposed under one of the color filters.

12. The imaging system of claim 11, wherein the second subset comprises 50% of the pixels contained in the pixel array.

13. The imaging system of claim 11, further comprising a plurality of microlenses disposed over the pixel array, wherein each microlens is disposed over each pixel.

14. The imaging system of claim 11, further comprising a plurality of microlenses disposed over the pixel array, wherein each microlens is disposed over a pair of pixels in two adjacent rows.

15. The imaging system of claim 11, wherein the color filter array comprises a quad-Bayer filter array such that (i) each color filter is disposed over a pair of pixels in two adjacent rows and (ii) color filters of the same color are disposed over 4x2 groups of pixels arranged in four adjacent rows and two adjacent columns, and wherein the pixels included in the second subset are arranged in a checkerboard pattern across the pixel array.

16. The imaging system of claim 11, wherein the color filter array comprises a quad-Bayer filter array such that (i) each color filter is disposed over a pair of pixels in two adjacent rows and (ii) color filters of the same color are disposed over 4x2 pixel groups arranged in four adjacent rows and two adjacent columns, and wherein the pixels included in the second subset are arranged in alternating rows across the pixel array.

17. The imaging system of claim 11 , wherein the color filter array comprises a four-color filter array formed by a red filter, a green filter, a blue filter, and a transparent filter array arranged in such a manner that: (i) red, green, and blue filters of the same color are disposed over four pixels included in the first subset arranged in four adjacent rows and two adjacent columns in a staggered manner and (ii) transparent filters are disposed over the pixels included in the second subset and arranged in a checkerboard pattern across the pixel array.

18. The imaging system of claim 11 , wherein the color filter array comprises a four-color filter array formed by a red filter, a green filter, a blue filter, and a clear filter array arranged in such a manner that (i) red, green, and blue filters of the same color are disposed over four pixels included in the first subset arranged in two non-adjacent rows and two adjacent columns and (ii) a clear filter is disposed over the pixels included in the second subset and arranged in alternating rows across the pixel array.

19. The imaging system of claim 11, wherein the color filter array comprises a color filter array formed of a red filter, a green filter, a blue filter, and a transparent filter, arranged in such a manner that: (i) red, green, and blue filters of different colors are placed over pixels included in the first subset arranged in adjacent columns and (ii) transparent filters are placed over the pixels included in the second subset and arranged in alternating rows across the pixel array.

20. The imaging system of claim 11, wherein each 2x2 grouping of pixels arranged in two adjacent rows and two adjacent columns includes a first pair of pixels included in the second subset of pixels and a second pair of pixels included in the first subset of pixels and disposed below both in the color filters.

Images