Monitoring circuit and semiconductor device

Abstract

An embodiment of the present disclosure relates to a monitoring circuit and a semiconductor device, and more particularly, to a monitoring circuit including an oscillation circuit generating an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter, and a semiconductor device including the monitoring circuit, the counter counts the number of times of rising or falling of the oscillation signal.

Description

[0001] This application is a divisional application of a patent application with an application number of 202010070215.6, a filing date of January 21, 2020, and an invention title of "Monitoring Circuit and Semiconductor Device".

[0002] Cross - reference to related applications

[0003] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0083760, filed with the Korean Intellectual Property Office on July 11, 2019, which is incorporated herein by reference in its entirety. Technical field

[0004] Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device. Background art

[0005] Semiconductor devices manufactured through semiconductor processing may not operate properly due to various factors or may have defects. Therefore, defects of semiconductor devices are inspected during semiconductor processing, but the inspection accuracy is not high, and it takes a long time to inspect semiconductor devices. In addition, so far, according to existing inspection methods, it is generally impractical to inspect defects of many semiconductor devices manufactured on a substrate one by one. Summary of the invention

[0006] The present invention generally relates to a monitoring circuit of a semiconductor device and a semiconductor device including the monitoring circuit. Various advantages of the monitoring circuit and semiconductor device of the present invention may include:

[0007] The monitoring circuit can accurately and quickly identify defects of the semiconductor device.

[0008] The monitoring circuit can accurately and quickly identify whether each individual semiconductor device is properly manufactured without defects through semiconductor processing.

[0009] The monitoring circuit can accurately monitor a semiconductor device in which transistors having respective threshold voltage levels are arranged.

[0010] The monitoring circuit can monitor the semiconductor device in a digital manner.

[0011] The semiconductor device can monitor its own state, performance, and characteristics.

[0012] When transistors arranged in the semiconductor device have respective threshold voltage levels, the semiconductor device can monitor its own performance, characteristics, or state.

[0013] The semiconductor device can monitor its own manufacturing process.

[0014] According to one aspect of the present invention, a monitoring circuit for monitoring a semiconductor device is provided. The monitoring circuit can monitor the state, characteristics or performance of the semiconductor device.

[0015] The monitoring circuit can be included in the semiconductor device.

[0016] The monitoring circuit can include an oscillation circuit and a counter. The oscillation circuit is configured to generate an oscillation signal having a rising characteristic and / or a falling characteristic according to a threshold voltage level, and the counter is configured to count the number of rising or falling times of the oscillation signal. The rising characteristic and / or the falling characteristic of the oscillation signal can represent the speed, slope, etc. of the voltage rise or fall in the oscillation signal, and can represent the interval between the rising section and the falling section, the number of rising sections or falling sections, the interval between rising sections (which can indicate a time period), the interval between falling sections (which can indicate a time period), etc.

[0017] The oscillation circuit can include one or more oscillators, and the one or more oscillators are configured to generate an oscillation signal according to an oscillation enable signal.

[0018] Each oscillator can be a digital-based ring oscillator.

[0019] Each oscillator can include a NAND gate and an odd number of inverters connected in series with the NAND gate.

[0020] If the oscillation circuit includes two or more oscillators, the two or more oscillators can generate oscillation signals at different timings respectively according to oscillation enable signals input at different timings.

[0021] If the oscillation circuit includes two or more oscillators, the monitoring circuit can further include a multiplexer configured to transmit the oscillation signal generated by one of the two or more oscillators to the counter according to a selection signal.

[0022] The two or more oscillators can generate oscillation signals having different rising characteristics and / or different falling characteristics respectively according to different threshold voltage levels.

[0023] The oscillation circuit can include a first oscillator and a second oscillator. The first oscillator is configured to generate a first oscillation signal according to a first threshold voltage level, and the second oscillator is configured to generate a second oscillation signal according to a second threshold voltage level, where the second threshold voltage level is different from the first threshold voltage level.

[0024] The second threshold voltage level can be greater than the first threshold voltage level.

[0025] The first oscillation signal can have a greater number of rising or falling times than the second oscillation signal.

[0026] The oscillation circuit may further include a third oscillator configured to generate a third oscillation signal according to a third threshold voltage level.

[0027] The third threshold voltage level may be greater than the second threshold voltage level.

[0028] The second oscillation signal may have a greater number of rising edges or falling edges than the third oscillation signal.

[0029] According to another embodiment of the present disclosure, a monitoring circuit may be included, the monitoring circuit including: an oscillation circuit including a first oscillator configured to generate a first oscillation signal according to an input of a first oscillation enable signal and a second oscillator configured to generate a second oscillation signal according to an input of a second oscillation enable signal; and a counter configured to count the number of rising edges or falling edges of each of the first oscillation signal and the second oscillation signal.

[0030] The first oscillator may generate the first oscillation signal according to a first threshold voltage level.

[0031] The second oscillator may generate the second oscillation signal according to a second threshold voltage level, where the second threshold voltage level is different from the first threshold voltage level and the second oscillation signal is different from the first oscillation signal.

[0032] According to another aspect, an embodiment of the present disclosure may provide a semiconductor device including: a substrate; and at least one monitoring circuit disposed on the substrate and configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and count the number of rising edges or falling edges of the oscillation signal when an input oscillation enable signal is received.

[0033] The rising characteristic and / or falling characteristic of the oscillation signal may represent the speed, slope, etc. of the voltage rise or fall in the oscillation signal, and may represent the interval between the rising section and the falling section, the number of rising sections or falling sections, the interval between rising sections (which may indicate a time period), the interval between falling sections (which may indicate a time period), etc.

[0034] A plurality of monitoring circuits may be disposed on the substrate, and the plurality of monitoring circuits may be distributed and arranged in a region of the semiconductor device different from the region where the memory cell array is arranged.

[0035] The monitoring circuit may include an oscillation circuit and a counter, the oscillation circuit being configured to generate an oscillation signal according to an input of an oscillation enable signal, and the counter being configured to count the number of rising edges or falling edges of the oscillation signal.

[0036] Transistors having a first threshold voltage level and transistors having a second threshold voltage level may be arranged in a region of a semiconductor device where a memory cell array is arranged.

[0037] According to another embodiment of the present disclosure, a monitoring circuit may be included, the monitoring circuit including: a first oscillation circuit adapted to generate a first oscillation signal corresponding to a first threshold voltage; a second oscillation circuit adapted to generate a second oscillation signal corresponding to a second threshold voltage, where the second threshold voltage is less than the first threshold voltage; a third oscillation circuit adapted to generate a third oscillation signal corresponding to a third threshold voltage, where the third threshold voltage is less than the second threshold voltage; a multiplexer adapted to select one of the first, second, and third oscillation signals in response to a selection signal; and a counter adapted to count the number of rising or falling times of the selected oscillation signal to generate a count value.

[0038] According to an embodiment of the present disclosure, defects of a semiconductor device can be accurately and quickly identified.

[0039] In addition, according to an embodiment of the present disclosure, a semiconductor device capable of self-monitoring its own state, performance, characteristics, etc. by the semiconductor device 100 itself can be provided.

[0040] In addition, according to an embodiment of the present disclosure, a semiconductor device capable of self-monitoring its own manufacturing process by the semiconductor device 100 itself can be provided.

[0041] In addition, according to an embodiment of the present disclosure, it can be accurately and quickly identified whether each individual semiconductor device is properly manufactured through semiconductor processing.

[0042] In addition, according to an embodiment of the present disclosure, a semiconductor device in which transistors having respective threshold voltage levels are arranged can be accurately monitored.

[0043] In addition, according to an embodiment of the present disclosure, a semiconductor device capable of self-monitoring its own performance, characteristics, or state by the semiconductor device 100 itself when the arranged transistors have respective threshold voltage levels can be provided.

[0044] In addition, according to an embodiment of the present disclosure, a monitoring circuit capable of digitally monitoring a semiconductor device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and other aspects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0046] Figure 1is a diagram schematically showing a semiconductor device including a monitoring circuit according to an embodiment of the present disclosure;

[0047] Figure 2 is a diagram schematically showing a monitoring circuit according to an embodiment of the present disclosure.

[0048] Figure 3 is a diagram showing the arrangement of a monitoring circuit in a planar structure semiconductor device according to an embodiment of the present disclosure;

[0049] Figure 4 and Figure 5 is a diagram showing the vertical structure of a semiconductor device according to an embodiment of the present disclosure;

[0050] Figure 6 and Figure 7 is a diagram showing the arrangement of a monitoring circuit in a vertical structure semiconductor device according to an embodiment of the present disclosure;

[0051] Figure 8 is a diagram showing the configuration of a monitoring circuit according to an embodiment of the present disclosure.

[0052] Figure 9 is a diagram showing the configuration of a monitoring circuit according to another embodiment of the present disclosure.

[0053] Figure 10 is a diagram showing the configuration of a monitoring circuit according to still another embodiment of the present disclosure.

[0054] Figure 11 is a diagram showing three oscillation signals in a monitoring circuit according to an embodiment of the present disclosure;

[0055] Figures 12 to 14 respectively are timing diagrams of ULVT monitoring, LVT monitoring, and SVT monitoring using a monitoring circuit using Figure 10 ;

[0056] Figure 15 is a diagram showing the state of implementing a semiconductor device including a monitoring circuit on a wafer according to an embodiment of the present disclosure;

[0057] Figure 16 is a diagram schematically showing a memory device according to an embodiment of the present disclosure.

[0058] Figure 17 is a diagram showing a memory system including a memory device and a memory controller according to an embodiment of the present disclosure.

[0059] Figure 18 is a diagram showing a computing system applying a semiconductor device according to an embodiment of the present disclosure; and

[0060] Figure 19 It is a flowchart showing a monitoring method according to an embodiment of the present disclosure. Detailed implementation manners

[0061] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0062] Figure 1 It is a diagram schematically showing a semiconductor device 100 including a monitoring circuit 200 according to an embodiment of the present disclosure. Figure 2 It shows the configuration of the monitoring circuit 200 according to an embodiment.

[0063] Now referring to Figure 1 and Figure 2 , the semiconductor device 100 may include at least one substrate (SUB), and the monitoring circuit 200 may be disposed on or in the at least one substrate (SUB). In an embodiment, the monitoring circuit 200 may be formed in the substrate (SUB), where the top surface of the monitoring circuit 200 is substantially coplanar with the top surface of the substrate (SUB). However, it should be noted that the present invention is not limited to the specific manner in which the monitoring circuit 200 can be disposed on or in the substrate (SUB). The monitoring circuit 200 can be enabled according to the input of an oscillation enable signal (EN_OSC). In response to the oscillation enable signal (EN_OSC), the monitoring circuit 200 can generate an oscillation signal (OSC) and count the number of rising or falling edges of the oscillation signal (OSC).

[0064] For example, the semiconductor device 100 can be a memory semiconductor (or non-system semiconductor) (also referred to as a memory, memory device, or storage device) that stores information or a memory controller that controls the operation of the memory semiconductor. In some cases, the semiconductor device 100 can be a non-memory semiconductor (or system semiconductor) for information processing (such as operation and inference).

[0065] For example, the memory semiconductor can include one of a random access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a video RAM (VRAM), a read-only memory (ROM), and a NAND flash memory. However, the memory semiconductor is not limited thereto and can be any one of various other types of semiconductors as long as the semiconductor can store information.

[0066] For example, according to the application scope, non-memory semiconductors may include a central processing unit (CPU), an application processor (AP) that can be used as a CPU in mobile terminals such as smartphones and tablet computers, a multimedia semiconductor, an application specific integrated circuit (ASIC), a merged DRAM logic (MDL) semiconductor, a power semiconductor, a microprocessor, an image sensor, and an artificial intelligence semiconductor. However, the non-memory semiconductors are not limited thereto, and may be any one of various types of semiconductors as long as the semiconductor has a function other than the function of storing information.

[0067] The monitoring circuit 200 may monitor the state and / or characteristics of the semiconductor device 100. For example, the monitoring circuit 200 may identify the state and / or characteristics of the semiconductor device 100 manufactured through semiconductor processing. The monitoring circuit 200 may determine whether the semiconductor device 100 is properly manufactured based on the identification result. The properly manufactured semiconductor device 100 may indicate that the semiconductor device 100 manufactured through semiconductor processing has a desired state or one or more desired characteristics. For example, the monitoring circuit 200 may identify the desired state or one or more characteristics of the semiconductor device 100 during an operation period and / or a non-operation period. The monitoring circuit 200 may determine whether the semiconductor device 100 has a normal state or characteristics, or whether the semiconductor device 100 is operating normally based on the identification result. The semiconductor device 100 having a normal state or characteristics may indicate that the state or characteristic information of the semiconductor device 100 (e.g., semiconductor processing state information, temperature, operation speed) is within a set reference range.

[0068] The number of the monitoring circuits 200 in the semiconductor device 100 may vary according to the design. For example, in an embodiment, the semiconductor device 100 may have only one monitoring circuit 200. In other embodiments, the semiconductor device 100 may have two or more monitoring circuits 200.

[0069] The oscillation signal (OSC) generated by the monitoring circuit 200 may have a variable voltage. For example, the oscillation signal (OSC) may have any one of various types of signal waveforms, and the various types of signal waveforms include a sine wave, a square wave, and a triangular wave.

[0070] The oscillation signal (OSC) may have at least one rising section with a voltage rising and at least one falling section with a voltage falling.

[0071] The number of the rising sections in the oscillation signal (OSC) may correspond to the number of times the oscillation signal (OSC) rises. The number of the falling sections in the oscillation signal (OSC) may correspond to the number of times the oscillation signal (OSC) falls.

[0072] The monitoring circuit 200 may generate an oscillation signal (OSC) having a rising characteristic and / or a falling characteristic based on a unique threshold voltage level.

[0073] The rising and / or falling characteristics of the oscillation signal may include the speed, slope, etc. of the voltage rise or fall in the oscillation signal. The rising characteristic and / or falling characteristic of the oscillation signal may include the interval between the rising section and the falling section, the number of rising sections or falling sections, the interval (or period) between the rising sections (which may indicate a period of time), and the interval (or period) between the falling sections.

[0074] As described above, since the rising characteristic and / or falling characteristic of the oscillation signal (OSC) may vary according to the unique threshold voltage level, the number of rising sections and the number of falling sections of the oscillation signal (OSC) may also vary within a predetermined time according to the unique threshold voltage level.

[0075] The monitoring circuit 200 may include an oscillation circuit 210 and at least one counter 220. The oscillation circuit 210 may generate an oscillation signal (OSC) in response to the input of an oscillation enable signal (EN_OSC). The counter 220 may count the number of rising or falling times of the oscillation signal (OSC) and output a count value (O_OSC_CNT).

[0076] Figures 3 to 7 FIG. is an example diagram showing the location of the monitoring circuit 200 in the semiconductor device 100 according to various embodiments of the present disclosure. Figure 3 FIG. is a diagram showing the arrangement of a plurality of monitoring circuits 200 in the planar semiconductor device 100. Figure 4 and Figure 5 FIG. is a diagram showing the vertical structure of the semiconductor device 100 according to an embodiment of the present disclosure. Figure 6 and Figure 7 FIG. is a diagram showing the arrangement of the monitoring circuit 200 in the vertical semiconductor device 100 according to an embodiment of the present disclosure.

[0077] As described above, the semiconductor device 100 may be implemented for various purposes and in any one of various types. Regardless of the purpose and type of the semiconductor device 100, the semiconductor device 100 may include a predefined core region (C / A) and a non-core region (P / A) other than the core region.

[0078] The core region (C / A) may be a region in which core circuits (including lines, electrodes, and elements such as transistors) that comply with the main purpose of the semiconductor device 100 are arranged. The non-core region (P / A) may be a region in which non-core circuits are arranged to assist or support the operation of the core circuits in the core region (C / A). The non-core region (P / A) may also be referred to as the "secondary region" or "peripheral region", and the non-core circuits may be referred to as "secondary circuits" or "peripheral circuits".

[0079] For example, the monitoring circuit 200 may be arranged in the core region (C / A).

[0080] For another example, the monitoring circuit 200 may be arranged in a non-core region (P / A) different from the core region (C / A). That is, the oscillation circuit 210 and the counter 220 may be arranged in the non-core region (P / A) in the semiconductor device 100, and the non-core region (P / A) is different from the predefined core region (C / A) in the semiconductor device 100.

[0081] For another example, the oscillation circuit 210 may be arranged inside the semiconductor device 100, and the counter 220 may be arranged outside the semiconductor device 100. The counter 220 may be connected to the semiconductor device 100 through the pins of the semiconductor device 100. The counter 220 may be directly or indirectly connected to the oscillation circuit 210. For example, the counter 220 may be directly or indirectly connected to the oscillation circuit 210 through the pins of the semiconductor device 100.

[0082] In this case, the oscillation circuit 210 included in the monitoring circuit 200 according to an embodiment of the present disclosure may be arranged in a non-core region (P / A) different from the predefined core region (C / A) of the semiconductor device 100.

[0083] For another example, the oscillation circuit 210 included in the monitoring circuit 200 according to an embodiment of the present disclosure may be arranged in the core region (C / A) of the semiconductor device 100, and the counter 200 may be arranged in the non-core region (P / A) of the semiconductor device 100.

[0084] For another example, the oscillation circuit 210 may be arranged in the non-core region (P / A) of the semiconductor device 100, and the counter 220 may be arranged in the core region (C / A) of the semiconductor device 100.

[0085] If the semiconductor device 100 is a memory semiconductor, the memory cell array may be arranged in the core region (C / A) of the semiconductor device 100, and the memory operation circuit for operating the memory cell array may be arranged in the non-core region (P / A) of the semiconductor device 100. In this case, the monitoring circuit 200 may be arranged in a region (i.e., the non-core region (P / A)) of the semiconductor device 100 that is different from the region (i.e., the core region (C / A)) where the memory cell array is arranged.

[0086] If the semiconductor device 100 is a non-memory semiconductor or a memory controller, a core circuit different from the monitoring circuit 200 and meeting the original purpose of the semiconductor device 100 may be arranged in the core region (C / A) of the semiconductor device 100, and a circuit for monitoring the interface between the monitoring circuit 200 and the peripheral devices may be arranged in the non-core region (P / A) of the semiconductor device 100. In this case, the monitoring circuit 200 may be arranged in a region (i.e., the non-core region (P / A)) of the semiconductor device 100 that is different from the region (i.e., the core region (C / A)) where the core circuit is arranged.

[0087] In the following description, by way of example, it is assumed that the monitoring circuit 200 is arranged inside the semiconductor device 100 and is arranged in the non-core region (P / A) of the semiconductor device 100.

[0088] According to an embodiment of the present disclosure, transistors having different threshold voltage levels may be arranged in the core region (C / A) of the semiconductor device 100.

[0089] For example, a transistor having a first threshold voltage level and a transistor having a second threshold voltage level may be arranged in the core region (C / A). The second threshold voltage level may be different from the first threshold voltage level. The memory cell array or the core circuit may be arranged in the core region (C / A) of the semiconductor device 100. The first threshold voltage level and the second threshold voltage level may be voltage levels that do not have overlapping voltage segments with each other. Alternatively, the first threshold voltage level and the second threshold voltage level may be voltage levels that have some overlapping voltage segments with each other.

[0090] For another example, a transistor having a first threshold voltage level, a transistor having a second threshold voltage level, and a transistor having a third threshold voltage level may be arranged in the core region (C / A) of the semiconductor device 100 where the memory cell array or the core circuit may be arranged. The first to third threshold voltage levels may be different. The first to third threshold voltage levels may be voltage levels that do not have overlapping voltage segments with each other. Alternatively, the first to third threshold voltage levels may be voltage levels that have some overlapping voltage segments with each other.

[0091] Referring to Figure 3 , when the semiconductor device 100 has a planar structure, the core region (C / A) and the non-core region (P / A) can exist in the same plane. The non-core region (P / A) is another region that does not overlap with the core region (C / A), and can be an external region of the core region (C / A). The non-core region (P / A) can be an outer edge region of the core region (C / A). The non-core region (P / A) can also be referred to as the "secondary region" or "peripheral region".

[0092] A plurality of monitoring circuits 200 can be arranged in the non-core region (P / A) on the substrate (SUB). For example, as Figure 3 shown, four monitoring circuits 200 can be arranged in the non-core region (P / A) on the substrate (SUB). However, the present invention is not limited to this manner, and generally at least one monitoring circuit 200 can be arranged in the non-core region (P / A) on the substrate (SUB).

[0093] Referring to Figure 4 , the semiconductor device 100 can have a first vertical structure, in which a first circuit layer (L1) is located on a first substrate (SUB1), a second substrate (SUB2) is located on the first circuit layer (L1), and a second circuit layer (L2) is located on the second substrate (SUB2).

[0094] The first vertical structure can be obtained by sequentially stacking the first substrate (SUB1), the first circuit layer (L1), the second substrate (SUB2), and the second circuit layer (L2) in semiconductor processing.

[0095] For an example of the first vertical structure, the first circuit layer (L1) on the first substrate (SUB1) can include one or more layers in which non-core circuits (e.g., secondary circuits or peripheral circuits) are arranged, and the second circuit layer (L2) on the second substrate (SUB2) can include one or more layers in which core circuits (e.g., memory cell arrays or main circuits) are arranged. In this case, the region on the first substrate (SUB1) where the first circuit layer (L1) is located can be the non-core region (P / A), and the region on the second substrate (SUB2) where the second circuit layer (L2) is located can be the core region (C / A).

[0096] For another example of the first vertical structure, the first circuit layer (L1) on the first substrate (SUB1) may include one or more layers on which core circuits (e.g., main circuits) are arranged, and the second circuit layer (L2) on the second substrate (SUB2) may include one or more layers on which non-core circuits (e.g., secondary circuits or peripheral circuits) are arranged. In this case, the region on the first substrate (SUB1) where the first circuit layer (L1) is located may be the core region (C / A), and the region on the second substrate (SUB2) where the second circuit layer (L2) is located may be the non-core region (P / A).

[0097] Referring Figure 5 , the semiconductor device 100 may have a second vertical structure, in which the first circuit layer (L1) is located on the first substrate (SUB1), the second circuit layer (L2) is located on the first circuit layer (L1), and the second substrate (SUB2) is located on the second circuit layer (L2).

[0098] In the second vertical structure, the vertical positions and manufacturing order of the first substrate (SUB1), the first circuit layer (L1), the second circuit layer (L2), and the second substrate (SUB2) may be changed.

[0099] The manufacturing process of the semiconductor device 100 having the second vertical structure may be as follows. In semiconductor processing, a first part and a second part may be manufactured. The first part may include forming the first circuit layer (L1) stacked on the first substrate (SUB1). The second part may include forming the second circuit layer (L2) stacked on the second substrate (SUB2). Thereafter, the second part may be inverted, and the inverted second part may be bonded to the first part, for example, by metal bonding, to manufacture the semiconductor device 100 having the second vertical structure.

[0100] For an example of the second vertical structure, the first circuit layer (L1) may include one or more layers on which core circuits (e.g., memory cell arrays, main circuits, etc.) are arranged, and the second circuit layer (L2) may include one or more layers on which non-core circuits (e.g., secondary circuits or peripheral circuits) are arranged. In this case, the region of the first circuit layer (L1) may be the core region (C / A), and the region of the second circuit layer (L2) may be the non-core region (P / A).

[0101] For another example of the second vertical structure, the first circuit layer (L1) may include one or more layers on which non-core circuits (e.g., secondary circuits or peripheral circuits) are arranged, and the second circuit layer (L2) may include one or more layers on which core circuits (e.g., main circuits) are arranged. In this case, the region of the first circuit layer (L1) may be the non-core region (P / A), and the region of the second circuit layer (L2) may be the core region (C / A).

[0102] Figure 6 and Figure 7 is a diagram showing the position where a monitoring circuit is arranged when a semiconductor device has a vertical structure according to an embodiment of the present disclosure.

[0103] Referring to Figure 6 when the semiconductor device 100 has a first vertical structure, as described above with reference to Figure 4 the region on the first substrate (SUB1) where the first circuit layer (L1) is located may be a non-core region (P / A), and the region on the second substrate (SUB2) where the second circuit layer (L2) is located may be a core region (C / A).

[0104] For example, a memory cell array (memory cells) or a core circuit may be arranged in the core region (C / A). The non-core region (P / A) may also be referred to as a "secondary region" or a "peripheral region", and the non-core region (P / A) is different from the core region (C / A), but may overlap with the core region (C / A).

[0105] In the case of the first vertical structure, one or more monitoring circuits 200 may be arranged in the non-core region (P / A) where the first circuit layer (L1) is located on the first substrate (SUB1). If there are two or more monitoring circuits 200, the two or more monitoring circuits 200 may be distributed and arranged in the non-core region (P / A) where the first circuit layer (L1) is located on the first substrate (SUB1). Since the two or more monitoring circuits 200 have a digital-based structure, the two or more monitoring circuits 200 can be distributed and arranged in the non-core region (P / A).

[0106] According to the first vertical structure, one or more monitoring circuits 200 arranged in the non-core region (P / A) may not overlap with the core circuits (such as a memory cell array, a main circuit, etc.) arranged in the core region (C / A) in the vertical direction. Optionally, as Figure 6 described, all or some of the one or more monitoring circuits 200 arranged in the non-core region (P / A) may overlap with the core circuits (such as a memory cell array, a main circuit, etc.) arranged in the core region (C / A) in the vertical direction.

[0107] Referring to Figure 7 when the semiconductor device 100 has a second vertical structure, as described above with reference to Figure 5 the region on the first substrate (SUB1) where the first circuit layer (L1) is located may be a core region (C / A), and the region where the second circuit layer (L2) is located under the second substrate (SUB2) may be a non-core region (P / A).

[0108] For example, a memory cell array (memory cells) or a core circuit may be arranged in a core region (C / A). A non-core region (P / A) may also be referred to as a "secondary region" or a "peripheral region", which is different from the core region (C / A) but may overlap with the core region (C / A).

[0109] In the case of the second vertical structure, one or more monitoring circuits 200 may be arranged in the non-core region (P / A) where the second circuit layer (L2) is located under the second substrate (SUB2). If there are two or more monitoring circuits 200, the two or more monitoring circuits 200 may be distributed and arranged in the non-core region (P / A) where the second circuit layer (L2) is located under the second substrate (SUB2). Since the two or more monitoring circuits 200 have a digital-based structure, the two or more monitoring circuits 200 can be distributed and arranged in the non-core region (P / A).

[0110] According to the second vertical structure, one or more monitoring circuits 200 arranged in the non-core region (P / A) may not overlap with the core circuits (e.g., memory cell array, main circuit, etc.) arranged in the core region (C / A) in the vertical direction. Optionally, as Figure 7 described, all or some of the monitoring circuits of one or more monitoring circuits 200 arranged in the non-core region (P / A) may overlap with the core circuits (e.g., memory cell array, main circuit, etc.) arranged in the core region (C / A) in the vertical direction.

[0111] Figure 8 is a diagram showing the configuration of the monitoring circuit 200 according to an embodiment of the present disclosure.

[0112] Referring to Figure 8 , the monitoring circuit 200 may include an oscillation circuit 210. The oscillation circuit 210 may include one or more oscillators (OSLT) that generate an oscillation signal (OSC) according to an input oscillation enable signal (EN_OSC).

[0113] As Figure 8 shown, each oscillator (OSLT) may be a digital-based ring oscillator.

[0114] Each oscillator (OSLT) may include a NAND gate (NAND) and an odd number of inverters (INV1 to INVn) (where n is an odd number of 1 or greater) connected in series with the NAND gate (NAND). The NAND gate (NAND) and the odd number of inverters (INV1 to INVn) may be implemented using transistors. For example, each of the odd number of inverters (INV1 to INVn) may be implemented using complementary metal oxide semiconductor (CMOS), which includes a p-channel transistor and an n-channel transistor.

[0115] Each oscillator (OSLT) may include an odd number of inverters (INV1 to INVn) to generate an oscillation signal (OSC).

[0116] The NAND gate (NAND) of each oscillator (OSLT) may include a first input terminal (IN1), a second input terminal (IN2), and an output terminal (OUT). The first input terminal (IN1) may be a terminal for inputting an oscillation enable signal (EN_OSC). The second input terminal (IN2) may be electrically connected to the output terminal of the last inverter (INVn) among the odd number of inverters (INV1 to INVn). The output terminal (OUT) may be electrically connected to the input terminal of the first inverter (INV1) among the odd number of inverters (INV1 to INVn).

[0117] The oscillation signal (OSC) generated by one or more oscillators (OSLT) in the oscillation circuit 210 may be input to the counter 220.

[0118] The counter 220 may receive various control signals to count the number of rising edges or falling edges of the input oscillation signal (OSC).

[0119] For example, the various control signals may include a count enable signal (I_EN) that enables the counting operation and a clock signal (I_CLK) that controls the counting operation time. The various control signals may further include a reset signal (I_RSTN) that resets the counting operation.

[0120] These various control signals may be generated inside the counter 220 or may be generated by a device external to the counter 220. The device external to the counter 220 may be a monitoring controller (not shown) provided inside or outside the monitoring circuit 200. For example, if the semiconductor device 100 is a memory device, the monitoring controller may be a memory controller that controls the memory device.

[0121] If the input count enable signal (I_EN) is received, the counter 220 may, at a time determined based on the clock signal (I_CLK) Figures 12 to 14During the Tm), the number of rising or falling edges of the oscillation signal (OSC) is counted.

[0122] Furthermore, the monitoring circuit 200 may include a determiner 800. The determiner 800 may output semiconductor processing state information of the semiconductor device 100 based on the difference between the count value (O_OSC_CNT) output from the counter 220 and a pre-stored reference value. When the semiconductor device 100 is in a desired state or has desired characteristics, the pre-stored reference value may correspond to the count value.

[0123] In some cases, the determiner 800 may be provided outside the semiconductor device 100. For example, if the semiconductor device 100 is a memory device, the determiner 800 may be included in a memory controller that controls the memory device.

[0124] As described above, the oscillation circuit 210 may include one oscillator (OSLT), or may include two or more oscillators (OSLT).

[0125] In the following description, the monitoring circuit 200 and its monitoring method will be described in conjunction with the case where the oscillation circuit 210 includes three oscillators (OSLT1), (OSLT2), and (OSLT3).

[0126] Figure 9 is a diagram showing the configuration of the monitoring circuit 200 according to an embodiment of the present disclosure. Figure 10 is a diagram showing the configuration of the monitoring circuit 200 according to an embodiment of the present disclosure, and this configuration may correspond to Figure 9 an example of Figure 11 is a diagram showing three oscillation signals (OSC1), (OSC2), and (OSC3) in the monitoring circuit 200 according to an embodiment of the present disclosure.

[0127] Referring to Figure 9 , the oscillation circuit 210 in the monitoring circuit 200 may include two or more oscillators (OSLT1), (OSLT2), and (OSLT3).

[0128] The two or more oscillators (OSLT1), (OSLT2), and (OSLT3) may have different threshold voltage levels. Therefore, the rising and falling characteristics of the oscillation signals (OSC1), (OSC2), and (OSC3) generated by each of the two or more oscillators (OSLT1), (OSLT2), and (OSLT3) may be different from each other.

[0129] Therefore, during the same time period, the number of rising edges and / or falling edges of the oscillation signals (OSC1), (OSC2), and (OSC3) generated by two or more oscillators (OSLT1), (OSLT2), and (OSLT3) may be different from each other.

[0130] Two or more oscillators (OSLT1), (OSLT2), and (OSLT3) in the oscillation circuit 210 may have the same odd number of inverters (INV1 to INVn). Optionally, the number of odd inverters (INV1 to INVn) in at least one of the two or more oscillators (OSLT1), (OSLT2), and (OSLT3) may be different from the number of odd inverters (INV1 to INVn) in other oscillators.

[0131] Two or more oscillators (OSLT1), (OSLT2), and (OSLT3) in the oscillation circuit 210 may generate two or more oscillation signals (OSC1), (OSC2), and (OSC3) at different timings according to the oscillation enable signals (EN_OSC_1), (EN_OSC_2), and (EN_OSC_3) input at different timings. That is, two or more oscillators (OSLT1), (OSLT2), and (OSLT3) may be enabled at different timings respectively to generate the oscillation signals (OSC1), (OSC2), and (OSC3).

[0132] Furthermore, the monitoring circuit 200 may include a multiplexer (MUX) that is configured to select one of the oscillation signals (OSC1), (OSC2), and (OSC3) according to a selection signal (I_SEL) and transmit the oscillation signal to the counter 220.

[0133] The multiplexer (MUX) may select one of the main output terminals (or oscillation signal output terminals) of two or more oscillators (OSLT1), (OSLT2), and (OSLT3) according to the selection signal (I_SEL). The multiplexer (MUX) may electrically connect the selected main output terminal to the input terminal of the counter 220.

[0134] For this multiplexing technique, the selection signal (I_SEL) may selectively indicate one of the two or more oscillators (OSLT1), (OSLT2), and (OSLT3).

[0135] The selection signal (I_SEL) is one of the various control signals described above. The selection signal (I_SEL) may be generated inside the counter 220, or may be generated by a device external to the counter 220. The device external to the counter 220 may be a monitoring controller (not shown) provided inside or outside the monitoring circuit 200. If the semiconductor device 100 is a memory device, the monitoring controller may be a memory controller that controls the memory device.

[0136] As described above, in order to enable two or more oscillators (OSLT1), (OSLT2), and (OSLT3) at different timings and generate two or more oscillation signals (OSC1), (OSC2), and (OSC3) at different timings, the input timings of the respective oscillation enable signals (EN_OSC_1), (EN_OSC_2), and (EN_OSC_3) must be controlled to be different from each other. For example, the first oscillator (OSLT1) may receive the first oscillation enable signal (EN_OSC_1) at the first input timing. The second oscillator (OSLT2) may receive the second oscillation enable signal (EN_OSC_2) at the second input timing. The third oscillator (OSLT3) may receive the third oscillation enable signal (EN_OSC_3) at the third input timing. The first to third input timings are different from each other.

[0137] Different from the case of enabling two or more oscillators (OSLT1), (OSLT2), and (OSLT3) at different timings to generate two or more oscillation signals (OSC1), (OSC2), and (OSC3) at different timings as described above, two or more oscillators (OSLT1), (OSLT2), and (OSLT3) may be enabled simultaneously to generate two or more oscillation signals (OSC1), (OSC2), and (OSC3) simultaneously. Optionally, two or more oscillators (OSLT1), (OSLT2), and (OSLT3) may be enabled independently to generate two or more oscillation signals (OSC1), (OSC2), and (OSC3) independently.

[0138] In this case, the monitoring circuit 200 does not need to include a multiplexer (MUX). Instead, the monitoring circuit 200 must include two or more counters 220 corresponding to two or more oscillators (OSLT1), (OSLT2), and (OSLT3).

[0139] The monitoring circuit 200 may include an oscillation circuit 210 and a counter 220. The oscillation circuit 210 may include a first oscillator (OSLT1) and a second oscillator (OSLT2), where the first oscillator (OSLT1) is configured to generate a first oscillation signal (OSC1) according to the input of a first oscillation enable signal (EN_OSC_1), and the second oscillator (OSLT2) is configured to generate a second oscillation signal (OSC2) according to the input of a second oscillation enable signal (EN_OSC_2). The counter 220 may count the number of rising edges or falling edges of each of the first oscillation signal (OSC1) and the second oscillation signal (OSC2).

[0140] Furthermore, the oscillation circuit 210 may include a third oscillator (OSLT3), and the third oscillator (OSLT3) is configured to generate a third oscillation signal (OSC3) according to the input of a third oscillation enable signal (EN_OSC_3).

[0141] In an embodiment of the present disclosure, the first oscillator (OSLT1) has a first threshold voltage level (VT1), which may indicate that the NAND gate (NAND) in the first oscillator (OSLT1) and the transistors constituting an odd number of inverters (INV1 to INVn) have the first threshold voltage level (VT1). The second oscillator (OSLT2) has a second threshold voltage level (VT2), which may indicate that the NAND gate (NAND) in the second oscillator (OSLT2) and the transistors constituting an odd number of inverters (INV1 to INVn) have the second threshold voltage level (VT2). The third oscillator (OSLT3) has a third threshold voltage level (VT3), which may indicate that the NAND gate (NAND) in the third oscillator (OSLT3) and the transistors constituting an odd number of inverters (INV1 to INVn) have the third threshold voltage level (VT3).

[0142] The first oscillator (OSLT1) may generate a first oscillation signal (OSC1) corresponding to the first threshold voltage level (VT1). The second oscillator (OSLT2) may generate a second oscillation signal (OSC2) corresponding to the second threshold voltage level (VT2). The third oscillator (OSLT3) may generate a third oscillation signal (OSC3) corresponding to the third threshold voltage level (VT3).

[0143] The first threshold voltage level (VT1), the second threshold voltage level (VT2), and the third threshold voltage level (VT3) may be different from each other.

[0144] Threshold voltage levels such as the first threshold voltage level (VT1), the second threshold voltage level (VT2), and the third threshold voltage level (VT3) may be within a voltage range between a lower limit value and an upper limit value.

[0145] The voltage range of the first threshold voltage level (VT1), the voltage range of the second threshold voltage level (VT2), and the voltage range of the third threshold voltage level (VT3) may not overlap with each other at all, or some of their voltage ranges may overlap with each other.

[0146] The second threshold voltage level (VT2) of the second oscillator (OSLT2) may be greater than the first threshold voltage level (VT1) of the first oscillator (OSLT1). The third threshold voltage level (VT3) of the third oscillator (OSLT3) may be greater than the second threshold voltage level (VT2) of the second oscillator (OSLT2).

[0147] That is to say, the third threshold voltage level (VT3) may be the highest, the second threshold voltage level (VT2) may be the second highest, and the first threshold voltage level (VT1) may be the lowest. Here, the low voltage range may indicate that the lower limit of the voltage range is the lowest.

[0148] In an embodiment, as Figure 11 shown, the number of rising edges or falling edges of the first oscillation signal (OSC1) may be greater than the number of rising edges or falling edges of the second oscillation signal (OSC2). The first oscillation signal (OSC1) may be generated by the first oscillator (OSLT1) having the first threshold voltage level (VT1). The second oscillation signal (OSC2) may be generated by the second oscillator (OSLT2) having the second threshold voltage level (VT2). That is to say, the first threshold voltage level (VT1) may be less than the second threshold voltage level (VT2), and the number of rising edges or falling edges of the first oscillation signal (OSC1) may be greater than the number of rising edges or falling edges of the second oscillation signal (OSC2).

[0149] The number of rising edges or falling edges of the second oscillation signal (OSC2) may be greater than the number of rising edges or falling edges of the third oscillation signal (OSC3). The third oscillation signal (OSC3) may be generated by the third oscillator (OSLT3) having the third threshold voltage level (VT3). That is to say, the second threshold voltage level (VT2) may be less than the third threshold voltage level (VT3), and the number of rising edges or falling edges of the second oscillation signal (OSC2) may be greater than the number of rising edges or falling edges of the third oscillation signal (OSC3).

[0150] According to the above description, with reference to Figure 11, the first oscillation signal (OSC1) can be generated by the first oscillator (OSLT1), the second oscillation signal (OSC2) can be generated by the second oscillator (OSLT2), and the third oscillation signal (OSC3) can be generated by the third oscillator (OSLT3). Among the first oscillation signal (OSC1), the second oscillation signal (OSC2), and the third oscillation signal (OSC3), the number of rising edges or falling edges of the first oscillation signal (OSC1) can be the largest, the number of rising edges or falling edges of the second oscillation signal (OSC2) can be the second largest, and the number of rising edges or falling edges of the third oscillation signal (OSC3) can be the smallest.

[0151] According to the above description, among two or more oscillators (OSLT1), (OSLT2), and (OSLT3), the oscillator with a higher threshold voltage level can generate an oscillation signal with a smaller number of rising or falling edges. Among two or more oscillators (OSLT1), (OSLT2), and (OSLT3), the oscillator with a lower threshold voltage level can generate an oscillation signal with a larger number of rising or falling edges. That is to say, the threshold voltage level and the number of rising or falling edges of the oscillation signal can be inversely proportional to each other.

[0152] Referring back Figure 8 , the determiner 800 can compare the first count value (O_OSC_CNT) of the number of rising edges or falling edges of the first oscillation signal (OSC1) generated by the first oscillator (OSLT1) with the corresponding reference value. Further, the determiner 800 can output the semiconductor processing status information of the semiconductor device 100 based on the difference corresponding to the comparison result.

[0153] If the difference is greater than or equal to a predetermined value, the determiner 800 can determine that there is a problem with the state or characteristics of the element (e.g., transistor, etc.) having the first threshold voltage level (VT1) in the semiconductor device 100, and can output the semiconductor processing status information indicating the determination result.

[0154] The determiner 800 can compare the second count value (O_OSC_CNT) of the number of rising edges or falling edges of the second oscillation signal (OSC2) generated by the second oscillator (OSLT2) with the corresponding reference value. Further, the determiner 800 can output the semiconductor processing status information of the semiconductor device 100 based on the difference corresponding to the comparison result.

[0155] If the difference is greater than or equal to a predetermined value, the determiner 800 can determine that there is a problem with the state or characteristics of the element (e.g., transistor, etc.) having the second threshold voltage level (VT2) in the semiconductor device 100. Further, the determiner 800 can output the semiconductor processing status information indicating the determination result.

[0156] The determiner 800 may compare a third count value (O_OSC_CNT) of the number of rising edges or falling edges of a third oscillation signal (OSC3) generated by a third oscillator (OSLT3) with a corresponding reference value. Further, the determiner 800 may output semiconductor processing status information of the semiconductor device 100 based on a difference corresponding to the comparison result.

[0157] If the difference is greater than or equal to a predetermined value, the determiner 800 may determine that there is a problem with the state or characteristics of an element (e.g., a transistor, etc.) having a third threshold voltage level (VT3) in the semiconductor device 100. Further, the determiner 800 may output semiconductor processing status information indicating the determination result.

[0158] In some embodiments, the first threshold voltage level (VT1), the second threshold voltage level (VT2), and the third threshold voltage level (VT3) may be three different threshold voltage levels among an ultra-low threshold voltage (ULVT) level, a low threshold voltage (LVT) level, a standard threshold voltage (SVT) level, and a high threshold voltage (HVT) level. The standard threshold voltage (SVT) level is referred to as a "conventional threshold voltage (RVT) level".

[0159] For example, as Figure 9 and Figure 10 shown, the first threshold voltage level (VT1) may be an ultra-low threshold voltage (ULVT) level, the second threshold voltage level (VT2) may be a low threshold voltage (LVT) level, and the third threshold voltage level (VT3) may be a standard threshold voltage (SVT) level. The monitoring circuit 200 in this case is the same as that Figure 10 shown.

[0160] The performance or characteristics of a transistor and the semiconductor device 100 including the transistor may vary according to a high threshold voltage level or a low threshold voltage level. For example, a transistor having a relatively high threshold voltage level has a low operating speed and low power consumption. A transistor having a relatively low threshold voltage level has a high operating speed and high power consumption.

[0161] Figures 12 to 14 Shows a timing diagram when ULVT monitoring, LVT monitoring, and SVT monitoring are performed using the Figure 10 shown monitoring circuit 200.

[0162] Refer to Figure 12, for the monitoring circuit 200 to perform ULVT monitoring, among the first oscillation enable signal (EN_OSC_1), the second oscillation enable signal (EN_OSC_2), and the third oscillation enable signal (EN_OSC_3), only the first oscillation enable signal (EN_OSC_1) has an enabled state, while the other signals have a disabled state. For example, the enabled state may correspond to the value 0 and the disabled state may correspond to the value 1, or the enabled state may correspond to the value 1 and the disabled state may correspond to the value 0.

[0163] Therefore, the first oscillator (OSLT1) in the oscillation circuit 210 is enabled to generate the first oscillation signal (OSC1).

[0164] The multiplexer (MUX) receives the selection signal (I_SEL) indicating the first oscillator (OSLT1), selects the first oscillation signal (OSC1) based on the selection signal (I_SEL), and transmits the first oscillation signal (OSC1) to the counter 220. The first oscillation signal (OSC1) is generated by the first oscillator (OSLT1) among the first to third oscillators (OSLT1), (OSLT2), and (OSLT3).

[0165] In Figure 12 In the example shown, the selection signal (I_SEL) indicating the first oscillator (OSLT1) or the first oscillation signal (OSC1) may have the value 2'b10.

[0166] If the reset signal (I_RSTN) is in the non-reset state and if the count enable signal (I_EN) is input in the count enable state, the counter 220 can count the number of rising or falling edges of the first oscillation signal (OSC1) during the time (Tm) determined based on the clock signal (I_CLK).

[0167] The non-reset state of the reset signal (I_RSTN) can be a high level, and the reset state of the reset signal (I_RSTN) can be a low level. In some cases, the non-reset state of the reset signal (I_RSTN) can be a low level, and the reset state of the reset signal (I_RSTN) can be a high level.

[0168] The count enable state of the count enable signal (I_EN) can be a high level, and the count disable state of the count enable signal (I_EN) can be a low level. In some cases, the count enable state of the count enable signal (I_EN) can be a low level, and the count disable state of the count enable signal (I_EN) can be a high level.

[0169] Referring to Figure 13, for the monitoring circuit 200 to perform LVT monitoring, among the first oscillation enable signal (EN_OSC_1), the second oscillation enable signal (EN_OSC_2), and the third oscillation enable signal (EN_OSC_3), only the second oscillation enable signal (EN_OSC_2) has an enabled state, while the other signals have a disabled state. For example, the enabled state may correspond to the value 0 and the disabled state may correspond to the value 1, or the enabled state may correspond to the value 1 and the disabled state may correspond to the value 0.

[0170] Therefore, the second oscillator (OSLT2) in the oscillation circuit 210 can be enabled to generate the second oscillation signal (OSC2).

[0171] The multiplexer (MUX) receives the selection signal (I_SEL) indicating the second oscillator (OSLT2), selects the second oscillation signal (OSC2) based on the selection signal (I_SEL), and transmits the second oscillation signal (OSC2) to the counter 220. The second oscillation signal (OSC2) is generated by the second oscillator (OSLT2) among the first to third oscillators (OSLT1), (OSLT2), and (OSLT3).

[0172] At Figure 13 In the example shown, the selection signal (I_SEL) indicating the second oscillator (OSLT2) or the second oscillation signal (OSC2) may have the value 2'b01.

[0173] If the reset signal (I_RSTN) is in a non-reset state and if the count enable signal (I_EN) is input in the count enable state, the counter 220 can count the number of rising or falling edges of the second oscillation signal (OSC2) during the time (Tm) determined based on the clock signal (I_CLK).

[0174] Referring to Figure 14 , for the monitoring circuit 200 to perform SVT monitoring, among the first oscillation enable signal (EN_OSC_1), the second oscillation enable signal (EN_OSC_2), and the third oscillation enable signal (EN_OSC_3), only the third oscillation enable signal (EN_OSC_3) has an enabled state, while the other signals have a disabled state. For example, the enabled state may correspond to the value 0 and the disabled state may correspond to the value 1, or the enabled state may correspond to the value 1 and the disabled state may correspond to the value 0.

[0175] Therefore, the third oscillator (OSLT3) in the oscillation circuit 210 is enabled to generate the third oscillation signal (OSC3).

[0176] The multiplexer (MUX) receives a selection signal (I_SEL) indicating the third oscillator (OSLT3), selects the third oscillation signal (OSC3) based on the selection signal (I_SEL), and transmits the third oscillation signal (OSC3) to the counter 220. The third oscillation signal (OSC3) is generated by the third oscillator (OSLT3) among the first to third oscillators (OSLT1), (OSLT2), and (OSLT3).

[0177] In Figure 14 the example shown, the selection signal (I_SEL) indicating the third oscillator (OSLT3) or the third oscillation signal (OSC3) may have a value of 2'b00.

[0178] If the reset signal (I_RSTN) is in a non-reset state and if the count enable signal (I_EN) is input in the count enable state, the counter 220 may count the number of rising or falling edges of the third oscillation signal (OSC3) during a time (Tm) determined based on the clock signal (I_CLK).

[0179] Figure 15 is a view showing the state of the semiconductor device 100 including the monitoring circuit 200 implemented on the wafer 1500 used as a substrate (SUB) according to an embodiment of the present disclosure.

[0180] Referring Figure 15 , in semiconductor processing, a circuit (i.e., an integrated circuit) is arranged on the surface of the wafer 1500. The wafer 1500 on which the integrated circuit is arranged is cut along a scribe line (SCL) into a predetermined size. As a result of the cutting, chips having a unit size are obtained. According to an embodiment of the present disclosure, each chip manufactured as described above may correspond to the semiconductor device 100 or the state before the semiconductor device 100 is manufactured.

[0181] Since the semiconductor device 100 must include the monitoring circuit 200, the monitoring circuit 200 may also be arranged when the integrated circuit is arranged on the wafer surface before the dicing process.

[0182] The monitoring circuit 200 may be provided in the chip area rather than at the scribe line (SCL) so as to be included in the semiconductor device 100 corresponding to one chip.

[0183] Therefore, the characteristics, performance, or state of each semiconductor device 100 can be accurately identified. In addition, it can be checked whether the overall semiconductor processing has been performed well for each semiconductor device 100.

[0184] The operation of the monitoring circuit 200 may be performed before and after the dicing process.

[0185] In addition, since the monitoring circuit 200 is included in the semiconductor device 100 corresponding to one chip, the monitoring function of the monitoring circuit 200 can be executed even when the semiconductor device 100 is mounted on various electronic devices such as a PC and a smart phone for operation after production is completed.

[0186] Since the monitoring circuit 200 uses the digital-based oscillation circuit 210 and the counter 220 to monitor the state, characteristics or performance of the semiconductor device 100, the monitoring circuit 200 is less affected by the environment compared with the analog-based monitoring, thereby obtaining more accurate monitoring results and performing faster monitoring.

[0187] Since the monitoring circuit 200 is made of transistors with a smaller size, the monitoring circuit 200 can be accurately arranged at various positions (e.g., corners) in the semiconductor device 100 without limitation.

[0188] Hereinafter, a memory device in which the semiconductor device 100 is a memory semiconductor will be described with reference to Figure 16 In addition, a memory controller for controlling the operation of the memory device will be described with reference to Figure 17 FIG.

[0189] Figure 16 FIG. 1600 is a diagram schematically showing a memory device 1600 according to an embodiment of the present disclosure. Figure 17 FIG. 1700 is a diagram showing a memory system including the memory device 1600 and the memory controller 1700 according to an embodiment of the present disclosure.

[0190] Referring to Figure 16 FIG. 1600, the memory device 1600 may include a memory cell array 1610, an address decoder 1620, a read and write circuit 1630, a control logic 1640, and a voltage generation circuit 1650.

[0191] The memory cell array 1610 may include a plurality of memory blocks (BLK1) to (BLKz) (where z is a natural number of 2 or more).

[0192] In the plurality of memory blocks (BLK1) to (BLKz), a plurality of word lines (WL) and a plurality of bit lines (BL) may be provided, and a plurality of memory cells (MC) may be arranged.

[0193] The plurality of memory blocks (BLK1) to (BLKz) may be connected to the address decoder 1620 through a plurality of word lines (WL). The plurality of memory blocks (BLK1) to (BLKz) may be connected to the read and write circuit 1630 through a plurality of bit lines (BL).

[0194] Each of the multiple memory blocks (BLK1) to (BLKz) may include multiple memory cells. For example, the multiple memory cells may be non-volatile memory cells having a vertical channel structure.

[0195] The memory cell array 1610 may be configured as a memory cell array having a two-dimensional structure. Optionally, in some cases, the memory cell array 1610 may be configured as a memory cell array having a three-dimensional structure.

[0196] Each of the multiple memory cells in the memory cell array 1610 may store at least one bit of data. For example, each of the multiple memory cells in the memory cell array 1610 may be a single-level cell (SLC) that stores one bit of data. As another example, each of the multiple memory cells in the memory cell array 1610 may be a multi-level cell (MLC) that stores two bits of data. As another example, each of the multiple memory cells in the memory cell array 1610 may be a triple-level cell (TLC) that stores three bits of data. As another example, each of the multiple memory cells in the memory cell array 1610 may be a quad-level cell (QLC) that stores four bits of data. As another example, the memory cell array 1610 may include multiple memory cells, each storing five or more bits of data.

[0197] The address decoder 1620, read and write circuit 1630, control logic 1640, and voltage generation circuit 1650 may operate as peripheral circuits for driving the memory cell array 1610.

[0198] The address decoder 1620 may be connected to the memory cell array 1610 through multiple word lines (WL).

[0199] The address decoder 1620 may be configured to operate in response to the control of the control logic 1640.

[0200] The address decoder 1620 may receive an address through an input / output buffer inside the memory device 1600. The address decoder 1620 may be configured to decode the block address among the received addresses. The address decoder 1620 may select at least one memory block according to the decoded block address.

[0201] The address decoder 1620 may receive a read voltage (Vread) and a pass voltage (Vpass) from the voltage generation circuit 1650.

[0202] When a read voltage is applied during a read operation, the address decoder 1620 may apply the read voltage (Vread) to the selected word line (WL) in the selected memory block and may apply the pass voltage (Vpass) to the remaining unselected word lines (WL).

[0203] In a program verification operation, the address decoder 1620 may apply the verification voltage generated by the pass voltage generation circuit 1650 to the selected word line (WL) in the selected memory block and may apply the pass voltage (Vpass) to the remaining unselected word lines (WL).

[0204] The address decoder 1620 may be configured to decode the column address in the received address. The address decoder 1620 may transfer the decoded column address to the read and write circuit 1630.

[0205] The read operation and the program operation of the memory device 1600 may be performed in units of pages. The address received when a read operation and a program operation are requested may include at least one of a block address, a row address, and a column address.

[0206] The address decoder 1620 may select one memory block and one word line according to the block address and the row address. The column address may be decoded by the address decoder 1620 so as to be provided to the read and write circuit 1630.

[0207] The address decoder 1620 may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

[0208] The read and write circuit 1630 may include a plurality of page buffers (PB). During a read operation of the memory cell array 1610, the read and write circuit 1630 may operate as a "read circuit", and during a write operation of the memory cell array 1610, the read and write circuit 1630 may operate as a "write circuit".

[0209] The read and write circuit 1630 may also be referred to as a "page buffer circuit" or a "data register circuit" including a plurality of page buffers (PB). Here, the read and write circuit 1630 may include a data buffer for data processing functions and may further include a cache buffer for cache functions in some cases.

[0210] Multiple page buffers PB can be connected to the memory cell array 1610 through multiple bit lines BL. In order to sense the threshold voltage (Vth) of memory cells during read operations and program verification operations, multiple page buffers (PB) can continuously supply sense current to the bit lines (BL) connected to the memory cells, and can detect changes in the flowing current amount according to the programmed state of the corresponding memory cells through the sense nodes, and then latch them as sense data.

[0211] The read and write circuit 1630 can operate in response to the page buffer control signal output from the control logic 1640.

[0212] In a read operation, the read and write circuit 1630 reads the data of the memory cells, temporarily stores the read data, and then outputs the data (DATA) to the input / output buffer of the memory device 1600. In an embodiment, the read and write circuit 1630 can include a column selection circuit, and a page buffer (PB) or a page register.

[0213] The control logic 1640 can be connected to the address decoder 1620, the read and write circuit 1630, and the voltage generation circuit 1650. The control logic 1640 can receive commands (CMD) and control signals (CTRL) through the input / output buffer (not shown) of the memory device 1600.

[0214] The control logic 1640 can be configured to control all operations of the memory device 1600 in response to the control signal (CTRL). The control logic 1640 can output a control signal for adjusting the precharge potential level of the sense nodes of multiple page buffers (PB).

[0215] The control logic 1640 can control the read and write circuit 1630 to perform a read operation on the memory cell array 1610. The voltage generation circuit 1650 can generate a read voltage (Vread) and a pass voltage (Vpass) used in the read operation in response to the voltage generation circuit control signal output from the control logic 1640.

[0216] Refer to Figure 17 The memory system can include a memory device 1600 for storing data and a memory controller 1700 for controlling the memory device 1600.

[0217] The memory device 1600 includes multiple memory blocks and operates in response to the control of the memory controller 1700. In this case, the operations of the memory device 1600 can include, for example, read operations, program operations (also referred to as "write operations"), and erase operations.

[0218] The memory device 1600 may include a memory cell array including a plurality of memory cells (hereinafter, simply referred to as "cells") that store data. Such a memory cell array may exist in a memory block.

[0219] For example, the memory device 1600 may be implemented as various types such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND, NOR flash memory, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin transfer torque random access memory (STT-RAM).

[0220] The memory device 1600 may be implemented as a three-dimensional array structure. Embodiments of the present disclosure may be applied to charge trap flash (CTF) in which a charge storage layer is formed of an insulating film, and to a flash memory device in which a charge storage layer is formed of a conductive floating gate.

[0221] The memory device 1600 is configured to receive commands and addresses from the memory controller 1700 and access a region selected by the address in the memory cell array. That is, the memory device 1600 may perform an operation corresponding to the command on the region selected by the address.

[0222] For example, the memory device 1600 may perform a programming operation, a read operation, and an erase operation. In this regard, during the programming operation, the memory device 1600 may program data in the region selected by the address. In the read operation, the memory device 1600 may read data from the region selected by the address. In the erase operation, the memory device 1600 may erase the data stored in the region selected by the address.

[0223] The memory controller 1700 may control write (or programming) operations, read operations, erase operations, and background operations on the memory device 1600. For example, the background operations may include at least one of garbage collection (GC), wear leveling (WL), and bad block management (BBM).

[0224] The memory controller 1700 may control the operation of the memory device 1600 according to a request from a host (HOST). Optionally, the memory controller 1700 may control the operation of the memory device 1600 independently of any request from the host (HOST).

[0225] The memory controller 1700 and the host (HOST) can be separate devices. In some cases, the memory controller 1700 and the host (HOST) can be integrated into one device. In the following description, the memory controller 1700 and the host (HOST) will be described as separate from each other.

[0226] In some embodiments, the memory controller 1700 may include a memory interface (I / F) 1720 and a control circuit 1730. Further, the memory controller 1700 may include a host interface (I / F) 1710.

[0227] The host interface 1710 provides an interface for communicating with the host (HOST).

[0228] The control circuit 1730 can receive commands from the host (HOST) through the host interface 1710 and can process the received commands.

[0229] The memory interface 1720 is connected to the memory device 1600 to provide an interface for communicating with the memory device 1600. That is, the memory interface 1720 can be configured to provide an interface between the memory device 1600 and the memory controller 1700 in response to the control of the control circuit 1730.

[0230] The control circuit 1730 performs all control operations of the memory controller 1700 to control the memory device 1600. The control circuit 1730 may include at least one of a processor 1731 and a working memory 1732. In some cases, the control circuit 1730 may further include an error detection and correction circuit (or ECC circuit) 1733.

[0231] The processor 1731 can control all operations of the memory controller 1700 and can perform logical operations. The processor 1731 can communicate with the host (HOST) through the host interface 1710 and can communicate with the memory device 1600 through the memory interface 1720.

[0232] The processor 1731 can perform the functions of the flash translation layer (FTL). The processor 1731 can convert the logical block address (LBA) provided by the host into a physical block address (PBA) through the flash translation layer (FTL). The flash translation layer (FTL) can receive the logical block address (LBA) and can convert the logical block address (LBA) into a physical block address (PBA) through a mapping table.

[0233] According to the mapping unit, there are several methods of mapping addresses through the flash translation layer. Typical address mapping methods include page mapping method, block mapping method, and hybrid mapping method.

[0234] The processor 1731 is configured to randomize the data received from a host. For example, the processor 1731 will use a randomization seed to randomize the data received from the host. The randomized data is provided as data to be stored to the memory device 1600 and programmed into the memory cell array.

[0235] The processor 1731 is configured to derandomize the data received from the memory device 1600 during a read operation. For example, the processor 1731 will use a derandomization seed to derandomize the data received from the memory device 1600. The derandomized data will be output to the host.

[0236] The processor 1731 can run firmware (FW) to control the operation of the memory controller 1700. In other words, when starting up, the processor 1731 can run (or drive) the firmware loaded in the working memory 1732 to control all operations of the memory controller 1700 and perform logical operations.

[0237] The firmware is a program running in the memory system 100 and can include various functional layers.

[0238] For example, the firmware can include at least one of a flash translation layer (FTL), a host interface layer (HIL), and a flash interface layer (FIL). The flash translation layer (FTL) performs the conversion between the logical address requested by the host to the memory system 100 and the physical address of the memory device 1600. The host interface layer (HIL) parses the commands requested by the host to the memory system 100 as a storage device and transfers the commands to the flash translation layer (FTL). The flash interface layer (FIL) transfers the commands indicated by the flash translation layer (FTL) to the memory device 1600.

[0239] The firmware can be stored, for example, in the memory device 1600 and then loaded into the working memory 1732.

[0240] The working memory 1732 can store the firmware, program code, commands, or data required to drive the memory controller 1700. As a volatile memory, the working memory 1732 can include, for example, at least one of static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM).

[0241] The error detection and correction circuit 1733 can be configured to use an error correction code to detect error bits of the data to be inspected and correct the detected error bits. For example, the data to be inspected can be the data stored in the working memory 1732 or the data read from the memory device 1600.

[0242] The error detection and correction circuit 1733 can be implemented to decode data using an error correction code. The error detection and correction circuit 1733 can be implemented as any one of various code decoders. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

[0243] The bus 1740 can be configured to provide a channel between the components 1710, 1720, 1731, 1732, and 1733 of the memory controller 1700. For example, the bus 1740 can include a control bus that transmits various control signals and commands, and a data bus that transmits various data.

[0244] The above components 1710, 1720, 1731, 1732, 1733, and 1740 of the memory controller 1700 are merely examples. Some of the foregoing components 1710, 1720, 1731, 1732, 1733, and 1740 of the memory controller 1700 can be excluded, or can be integrated into one element. In some cases, one or more other components can be added in addition to the foregoing components of the memory controller 1700.

[0245] The memory controller 1700 can be included in a host (HOST), or can be integrated with the memory device 1600.

[0246] According to an embodiment of the present disclosure, the memory device 1600 can be a semiconductor device 100 including a monitoring circuit 200. Additionally, according to an embodiment of the present disclosure, the memory controller 1700 that controls the operation of the memory device 1600 can also be a semiconductor device 100 including a monitoring circuit 200.

[0247] Figure 18 is a diagram showing a computing system 1800 to which a semiconductor device according to various embodiments of the present disclosure is applied.

[0248] Referring to Figure 18 , the computing system 1800 can include a central processing unit (CPU) 1810, a random access memory (RAM) 1820, a user interface / user experience (UI / UX) module 1830, a communication module 1840, and a power management module 1850 that are electrically connected to a system bus 1860. The central processing unit (CPU) 1810 can control all operations of the computing system 1800. The RAM 1820 can store data and information related to the operation of the computing system 1800. The user interface / user experience (UI / UX) module 1830 can provide a user environment to the user. The communication module 1840 can communicate with an external device through wired and / or wireless communication. The power management module 1850 can manage the power used by the computing system 1800.

[0249] The memory system 1870 may include a memory device 1600 implemented as a semiconductor device 100. In some cases, the memory system 1870 may further include a memory controller 1700.

[0250] The computing system 1800 may be a personal computer (PC), or may include mobile terminals such as smart phones and tablet computers, or various electronic devices.

[0251] The computing system 1800 may further include a battery that supplies an operating voltage, an application chipset, a graphics-related module, a camera image processor (CIS), and a DRAM. Additionally, the configuration of the computing system will be apparent to those skilled in the art.

[0252] In some embodiments, the memory system 1870 may include a device that stores data in a non-volatile memory such as a solid state drive (SSD), a universal flash storage (UFS) device, or an embedded MultiMediaCard (eMMC) device, and a device that stores data in a magnetic disk such as a hard disk drive (HDD). The non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Additionally, the memory system 1870 may be implemented as any one of various types of storage devices and may be installed in various electronic devices.

[0253] According to an embodiment of the present disclosure, the central processing unit 1810 and the RAM 1820 may be implemented as the semiconductor device 100 including the monitoring circuit 200. According to an embodiment of the present disclosure, if one or more of the UI / UX module 1830, the communication module 1840, and the power management module 1850 are implemented as an integrated circuit (IC), the integrated circuit may be implemented as the semiconductor device 100 including the monitoring circuit 200.

[0254] Hereinafter, the method of monitoring the state, characteristics, or performance of the above-described monitoring semiconductor device 100 will be briefly described again.

[0255] Figure 19 is a flowchart showing a monitoring method according to an embodiment of the present disclosure.

[0256] Refer to Figure 19, the monitoring method may include steps (S1910), (S1920), and (S1930). Step (S1910) may include generating an oscillation signal (OSC) having a rising section and a falling section according to a threshold voltage level when an oscillation enable signal is received. Step (S1920) may include counting the number of rising or falling times of the oscillation signal (OSC).

[0257] After step S1920, the monitoring method may include a determination step (S1930). The monitoring method may include outputting semiconductor processing status information (e.g., information indicating normal, abnormal, ULVT normal, ULVT abnormal, LVT normal, LVT abnormal, SVT normal, SVT abnormal) of the semiconductor device 100 based on the difference between a count value (O_OSC_CNT) obtained by counting the number of rising or falling times of the oscillation signal (OSC) and a pre-stored reference value.

[0258] After the manufacturing process of the semiconductor device 100 is completed and immediately before transporting the semiconductor device 100, the monitoring method may be executed to check whether the semiconductor processing is normal.

[0259] Optionally, after the semiconductor device 100 is transported and installed in the computing system 1800, the monitoring method may be executed in a specific event situation or at a periodic timing.

[0260] According to an embodiment of the present disclosure, the characteristics, performance, or state of the semiconductor device 100 can be accurately and quickly identified, thereby quickly and accurately identifying defects of the semiconductor device 100.

[0261] In addition, according to an embodiment of the present disclosure, a semiconductor device 100 capable of monitoring its own state, performance, or characteristics by itself can be provided.

[0262] In addition, according to an embodiment of the present disclosure, a semiconductor device 100 capable of monitoring its own manufacturing process by itself can be provided.

[0263] In addition, according to an embodiment of the present disclosure, it can be accurately and quickly identified whether each individual semiconductor device 100 is normally manufactured through semiconductor processing.

[0264] In addition, according to an embodiment of the present disclosure, the semiconductor device 100 in which transistors having respective threshold voltage levels are arranged can be accurately monitored.

[0265] In addition, according to an embodiment of the present disclosure, a semiconductor device 100 capable of monitoring its own performance, characteristics, or state by itself when the arranged transistors have respective threshold voltage levels can be provided.

[0266] In addition, according to an embodiment of the present disclosure, a monitoring circuit 200 capable of digitally monitoring a semiconductor device 100 may be provided.

[0267] Although specific embodiments of the present disclosure have been described for purposes of illustration, those skilled in the art will appreciate that various other embodiments, as well as modifications, additions, and substitutions thereof, are possible without departing from the scope and spirit of the disclosure as set forth in the appended claims.

Claims

1. A monitoring circuit for monitoring a semiconductor device, the monitoring circuit comprising: an oscillation circuit that generates an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level; and a counter that counts the number of rising edges or falling edges of the oscillation signal, wherein the semiconductor device includes a core region and a non-core region, wherein the oscillation circuit and the counter are disposed on one of the core region and the non-core region, wherein the core region is a region in which a core circuit including wires, electrodes, and transistor elements is disposed, wherein the non-core region is a region in which a non-core circuit is disposed to assist or support the operation of the core circuit in the core circuit region, wherein the oscillation circuit is disposed in the core region and the counter is disposed in the non-core region, wherein the rising characteristic is determined by at least one of a voltage rise in the oscillation signal, an interval between rising segments, a number of rising segments, and noise of the oscillation signal, wherein the falling characteristic is determined by at least one of a voltage drop in the oscillation signal, an interval between falling segments, a number of falling segments, and noise of the oscillation signal, wherein the semiconductor device has a vertical structure, a first circuit layer is located on a first substrate, wherein a second substrate is located on the first circuit layer, a second circuit layer is located on the second substrate, or the second circuit layer is located on the first circuit layer and the second substrate is located on the second circuit layer, wherein the region where the first circuit layer is located is the non-core region, the region where the second circuit layer is located is the core region, or the region where the first circuit layer is located is the core region and the region where the second circuit layer is located is the non-core region.

2. The monitoring circuit according to claim 1, wherein if a count enable signal is input, the counter counts the number of rising edges or falling edges of the oscillation signal during a set time based on a clock signal.

3. The monitoring circuit according to claim 1, wherein the oscillation circuit includes one or more oscillators that are enabled according to an oscillation enable signal to generate the oscillation signal.

4. The monitoring circuit according to claim 3, wherein each oscillator is a digital-based ring oscillator.

5. The monitoring circuit according to claim 3, wherein if the oscillation circuit includes two or more oscillators, each of the two or more oscillators includes a NAND gate and an odd number of inverters connected in series with the NAND gate, and wherein the number of odd number of inverters included in at least one of the two or more oscillators is different from the number of odd number of inverters included in other oscillators.

6. The monitoring circuit according to claim 3, wherein if the oscillation circuit includes two or more oscillators, the two or more oscillators generate the oscillation signal at different timings according to oscillation enable signals input at different timings.

7. The monitoring circuit according to claim 3, further comprising: If the oscillation circuit includes two or more oscillators, the multiplexer transmits, according to a selection signal, an oscillation signal generated by one of the two or more oscillators to the counter.

8. The monitoring circuit according to claim 7, wherein the two or more oscillators respectively generate oscillation signals having different rising characteristics or different falling characteristics according to different threshold voltage levels.

9. The monitoring circuit according to claim 8, wherein the oscillation circuit includes a first oscillator and a second oscillator, the first oscillator generates a first oscillation signal according to a first threshold voltage level, and the second oscillator generates a second oscillation signal according to a second threshold voltage level, wherein the second threshold voltage level is different from the first threshold voltage level, wherein the second threshold voltage level is greater than the first threshold voltage level, and wherein the first oscillation signal has a greater number of rising times or falling times than the second oscillation signal.

10. The monitoring circuit according to claim 9, wherein the oscillation circuit further includes a third oscillator, the third oscillator generates a third oscillation signal according to a third threshold voltage level, wherein the third threshold voltage level is greater than the second threshold voltage level, and wherein the second oscillation signal has a greater number of rising times or falling times than the third oscillation signal.

11. The monitoring circuit according to claim 1, further including a determiner, the determiner outputs semiconductor processing state information based on a difference between a count value output from the counter and a pre-stored reference value.

12. A monitoring circuit, comprising: an oscillation circuit including a first oscillator and a second oscillator, the first oscillator generates a first oscillation signal according to an input of a first oscillation enable signal, and the second oscillator generates a second oscillation signal according to an input of a second oscillation enable signal; and a counter that counts the number of rising times or falling times of each of the first oscillation signal and the second oscillation signal, wherein the first oscillator generates the first oscillation signal according to a first threshold voltage level, wherein the second oscillator generates the second oscillation signal according to a second threshold voltage level, the second threshold voltage level is different from the first threshold voltage level, and the second oscillation signal is different from the first oscillation signal, wherein the monitoring circuit is included in a semiconductor device, the semiconductor device includes a core region and a non-core region, wherein the oscillation circuit and the counter are disposed on one of the core region and the non-core region, wherein the core region is a region where a core circuit including lines, electrodes, and transistor elements is disposed, wherein the non-core region is a region where non-core circuits are disposed to assist or support the operation of the core circuit in the core circuit region, wherein the oscillation circuit is disposed in the core region and the counter is disposed in the non-core region, Wherein, the rising characteristic is determined by at least one of a voltage rise in the oscillation signal, an interval between rising sections, a number of rising sections, and noise of the oscillation signal. Wherein, the falling characteristic is determined by at least one of a voltage fall in the oscillation signal, an interval between falling sections, a number of falling sections, and noise of the oscillation signal. Wherein, the semiconductor device has a vertical structure, and a first circuit layer is located on a first substrate. Wherein, a second substrate is located on the first circuit layer, and a second circuit layer is located on the second substrate, or the second circuit layer is located on the first circuit layer, and the second substrate is located on the second circuit layer. Wherein, an area where the first circuit layer is located is a non-core area, an area where the second circuit layer is located is a core area, or an area where the first circuit layer is located is a core area, and an area where the second circuit layer is located is a non-core area.

13. A semiconductor device comprising: a substrate; and a monitoring circuit disposed on the substrate, generating an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level, and counting a number of rising times or falling times of the oscillation signal. Wherein the semiconductor device includes a core area and a non-core area. Wherein the monitoring circuit is disposed on one of the core area and the non-core area. Wherein the monitoring circuit includes an oscillation circuit and a counter. Wherein the core area is an area where a core circuit including lines, electrodes, and transistor elements is disposed. Wherein the non-core area is an area where a non-core circuit is disposed to assist or support the operation of the core circuit in the core circuit area. Wherein, the oscillation circuit is disposed in the core area, and the counter is disposed in the non-core area. Wherein, the rising characteristic is determined by at least one of a voltage rise in the oscillation signal, an interval between rising sections, a number of rising sections, and noise of the oscillation signal. Wherein, the falling characteristic is determined by at least one of a voltage fall in the oscillation signal, an interval between falling sections, a number of falling sections, and noise of the oscillation signal. Wherein, the semiconductor device has a vertical structure, and a first circuit layer is located on a first substrate. Wherein, a second substrate is located on the first circuit layer, and a second circuit layer is located on the second substrate, or the second circuit layer is located on the first circuit layer, and the second substrate is located on the second circuit layer. Wherein, an area where the first circuit layer is located is a non-core area, an area where the second circuit layer is located is a core area, or an area where the first circuit layer is located is a core area, and an area where the second circuit layer is located is a non-core area.

14. The semiconductor device according to claim 13, wherein a plurality of monitoring circuits are disposed on the substrate, and wherein the plurality of monitoring circuits are distributed and disposed in an area of the semiconductor device different from an area where a memory cell array is disposed.

15. The semiconductor device according to claim 13, wherein each of the monitoring circuits in the monitoring circuit includes an oscillation circuit and a counter, the oscillation circuit generates the oscillation signal, and the counter counts the number of rising edges or the number of falling edges of the oscillation signal.

16. The semiconductor device according to claim 15, wherein the oscillation circuit includes one or more oscillators, and the one or more oscillators are enabled according to an oscillation enable signal to generate the oscillation signal.

17. The semiconductor device according to claim 16, wherein if the oscillation circuit includes two or more oscillators, the monitoring circuit further includes a multiplexer, and the multiplexer transmits the oscillation signal generated by one of the two or more oscillators to the counter according to a selection signal.

18. The semiconductor device according to claim 17, wherein the two or more oscillators respectively generate oscillation signals having different rising characteristics or different falling characteristics according to different threshold voltage levels.

19. The semiconductor device according to claim 18, wherein the oscillation circuit includes a first oscillator and a second oscillator, the first oscillator generates a first oscillation signal according to a first threshold voltage level, and the second oscillator generates a second oscillation signal according to a second threshold voltage level, wherein the second threshold voltage level is different from the first threshold voltage level, wherein the second threshold voltage level is greater than the first threshold voltage level, and wherein the first oscillation signal has a greater number of rising edges or a greater number of falling edges than the second oscillation signal.

20. The semiconductor device according to claim 19, wherein the transistors having the first threshold voltage level and the transistors having the second threshold voltage level are arranged in the region of the semiconductor device where the memory cell array is arranged.

Images