Array substrate and display device

Abstract

The invention relates to an array substrate and a display device, the array substrate comprises a substrate, the substrate is provided with a display area and a non-display area, the non-display area is provided with a gate drive circuit, and the gate drive circuit further comprises a first redundant low-level signal line and a first sacrificial electrode located above the first redundant low-level signal line; one part of the first redundant low-level signal line is located in the circuit area and arranged around the driving circuit, and the other part of the first redundant low-level signal line extends to the bus area and is electrically connected with the two ends of the first low-level signal line or the pulse signal line in the bus area. And the first redundant low-level signal line is electrically connected with the first sacrificial electrode through the first layer conversion hole so as to consume ions around the electrolytic tank. The first sacrificial electrode on the first redundant low-level signal line is utilized to consume part of ions in the gate drive circuit, so that the connection position of the metal wire and the first signal wire is prevented from being corroded, and the signal smoothness and the normal display of the display panel are ensured.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to an array substrate and a display device. Background Art

[0002] With the continuous progress of technology, the application of the Gate Driver on array (GOA) technology for the array substrate has gradually increased. The GOA technology integrates the gate driver on the glass substrate to form a scan of the display panel. The GOA technology has advantages such as low cost, low power consumption, and narrow borders, and has gradually become a new research direction for each manufacturer.

[0003] The GOA technology simultaneously completes the functional units composed of Thin Film Transistor (TFT) devices and the manufacturing process of the array substrate to replace the traditional driver chip and complete the function of progressive scanning during the display of the picture.

[0004] However, for a display panel using the GOA technology, when operating in a high-temperature and high-humidity environment, the via holes for layer transfer will be corroded and burned, resulting in the inability to conduct signals. As a result, the display panel cannot display the picture normally, showing abnormalities and affecting the product yield. Summary of the Invention

[0005] The present application provides an array substrate and a display device, which can protect the circuit area from the influence of electrochemical corrosion caused by high temperature and high humidity, and improve the product yield.

[0006] In a first aspect, the present application provides an array substrate. The substrate has a display area and a non-display area. The non-display area is provided with a gate driving circuit. The gate driving circuit includes a circuit area and a bus area arranged in sequence along the direction away from the display area. The bus area includes a plurality of first signal traces. One end of the circuit area is connected to some of the plurality of first signal traces through a metal trace, and the other end of the circuit area is connected to the scan line of the display area through a metal trace; the plurality of first signal traces include a first high-level signal line, a first low-level signal line, and a pulse signal line; The gate driving circuit further includes a first redundant low-level signal line and a first sacrificial electrode located above it. A part of the first redundant low-level signal line is located in the circuit area and is arranged around the gate driving circuit. Another part of the first redundant low-level signal line extends to the bus area and is electrically connected to both ends of the first low-level signal line or the pulse signal line in the bus area. The first redundant low-level signal line is electrically connected to the first sacrificial electrode through a first via hole for layer transfer.

[0007] In a possible implementation, the first high-level signal line includes multiple clock signal lines; the first low-level signal line includes a gate-off signal line, and the pulse signal line includes a frame start signal line; the first signal trace further includes a low-frequency signal line; Multiple ones of the first signal traces are sequentially arranged in a direction away from the display area; Among them, the frame start signal line is located on one side away from the display area, the gate-off signal line is arranged close to the circuit area, the multiple clock signal lines are sequentially arranged at intervals in a direction from the frame start signal line to the gate-off signal line, and the low-frequency signal line is arranged between the clock signal line and the gate-off signal line.

[0008] In a possible implementation, the metal trace includes an output trace and an input trace. One end of the circuit area is electrically connected to multiple ones of the input traces, and the multiple input traces are respectively electrically connected to the corresponding first signal traces. The other end of the circuit area is electrically connected to one output trace.

[0009] In a possible implementation, the first sacrificial electrode at the position of the output trace is discontinuously arranged; or, the first redundant low-level signal line at the position of the output trace is discontinuously arranged.

[0010] In a possible implementation, the gate driving circuit further includes a second redundant low-level signal line and a second sacrificial electrode located above it. The second redundant low-level signal line is located on the outer peripheral side of the first redundant low-level signal line. A part of the second redundant low-level signal line is located in the circuit area and is arranged around the gate driving circuit. Another part of the second redundant low-level signal line extends to the bus area and is electrically connected to both ends of the first low-level signal line or the pulse signal line in the bus area. The second redundant low-level signal line is electrically connected to the second sacrificial electrode through the first via hole layer.

[0011] In a possible implementation, the gate driving circuit includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a first electrode layer sequentially arranged on the substrate. The first signal trace is located on the first metal layer, the metal trace is located on the second metal layer, the first via hole layer penetrates the first insulating layer and / or the second insulating layer, and the first sacrificial electrode and the second sacrificial electrode are both located on the first electrode layer; Among them, the first redundant low-level signal line is located on the first metal layer or the second metal layer, and the second redundant low-level signal line is located on the first metal layer or the second metal layer.

[0012] In a possible implementation, the gate driving circuit includes a circuit intermediate node located in the circuit region, and second signal lines are disposed around the circuit intermediate node; Wherein, a redundant signal line is disposed between the circuit intermediate node and the second signal lines, a third sacrificial electrode is disposed above the redundant signal line, and the redundant signal line is electrically connected to the third sacrificial electrode through a second transfer via hole.

[0013] In a possible implementation, the root mean square voltage of the second signal lines is greater than the root mean square voltage of the circuit intermediate node, and the root mean square voltage of the circuit intermediate node is greater than the root mean square voltage of the redundant signal line.

[0014] In a possible implementation, the redundant signal line includes a first sub-redundant trace and a second sub-redundant trace; The first sub-redundant trace extends along the outer peripheral side of the circuit intermediate node, and the second sub-redundant trace is disposed between the first sub-redundant trace and the second signal lines and extends along the outer peripheral side of the first sub-redundant trace.

[0015] In a second aspect, the present application provides a display device, including a display panel and a housing, the housing is connected to the display panel, and an array substrate as described in the first aspect is disposed in the display panel.

[0016] The above technical solutions provided by the embodiments of the present application have the following advantages compared with the prior art: The array substrate and the display device provided by the embodiments of the present application use a first redundant low-level signal line to surround the circuit region, and a first sacrificial electrode is disposed above the first redundant low-level signal line, which can consume part of the ions in the gate driving circuit, avoid corrosion of the connection positions such as the metal trace and the first signal trace, ensure signal smoothness and normal display of the display panel, effectively extend the service life of the display panel, and improve the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention and, together with the specification, are used to explain the principles of the present invention.

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0020] Figure 1 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 2 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 3 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 4 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 5 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 6 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 7 is Figure 1 The cross-sectional schematic diagram at the position d shown; Figure 8 is Figure 1 The cross-sectional schematic diagram at the position a shown; Figure 9 is Figure 2 The cross-sectional schematic diagram at the position b shown; Figure 10 It is a top view schematic diagram of an intermediate circuit node provided by an embodiment of the present application; Figure 11 It is a top view schematic diagram of an intermediate circuit node provided by an embodiment of the present application; Figure 12 is Figure 10 The cross-sectional schematic diagram at the position c shown; Figure 13 is Figure 10 The cross-sectional schematic diagram at the position e shown; Figure 14 It is a block diagram of a display device provided by an embodiment of the present application.

[0021] Explanation of reference numerals in the drawings: 1. Array substrate; 11. Substrate; 12. Gate driving circuit; 121. Circuit area; 1211. Driving circuit; 1212. Metal trace; 12121. Output trace; 12122. Input trace; 1213. Intermediate circuit node; 12131. Third via hole for layer transfer; 12132. Second electrode layer; 1214. Second signal line; 1215. Redundant signal line; 12151. First sub-redundant trace; 12152. Second sub-redundant trace; 1216. Third sacrificial electrode; 1217. Second via hole for layer transfer; 122. Bus area; 1221. First signal trace; 12211. First high-level signal line; 12212. First low-level signal line; 12213. Pulse signal line; 12214. Low-frequency signal line; 123. First metal layer; 124. First insulating layer; 125. Second metal layer; 1231 / 1251. First redundant low-level signal line; 1232 / 1252. Second redundant low-level signal line; 126. Second insulating layer; 127. First electrode layer; 1271 / 1272. First sacrificial electrode; 1273 / 1274. Second sacrificial electrode; 13. First via hole for layer transfer; 131. First sub-via hole for layer transfer; 132. Second sub-via hole for layer transfer; 14. Electrode trace; 141. First electrode trace; 142. Second electrode trace; 143. Second break; AA. Display area; IA. Non-display area; 2. Display panel. Detailed implementation manners

[0022] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0023] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or letters in different examples. Such repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0024] For ease of description, spatial relative relationship terms may be used in the text to describe the relative position relationship or movement of one element or feature shown in the figure with respect to another element or feature. These relative relationship terms are, for example, "inside", "outside", "inner side", "outer side", "below", "beneath", "above", "over", "front", "rear", etc. Such spatial relative relationship terms are intended to include different orientations of the device during use or operation other than the orientations depicted in the figure. For example, if the device in the figure undergoes a position flip, attitude change, or motion state change, then these directional indications will change accordingly. For example, an element described as "below other elements or features" or "beneath other elements or features" will then be oriented as "above other elements or features" or "over other elements or features". Therefore, the exemplary term "below" can include both the upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative relationship descriptors used in the text are interpreted accordingly.

[0025] In the related art, in a high-temperature and high-humidity environment, the display device is affected by the external environment, and water vapor will enter the liquid crystal cell in the display device, and then mix with ions to form a solvent for the electrolytic cell. At this time, the first electrode layer will be damaged and gradually reduced to In, eventually causing the first electrode layer to open circuit and fail, affecting the abnormal picture. To solve the technical problem of abnormal display pictures caused by the corrosion and burn of the transfer layer holes in the related art under high-temperature and high-humidity environments, the present application provides an array substrate. By using a first redundant low-level signal line to surround the circuit area, a first sacrificial electrode is arranged above the first redundant low-level signal line, which can consume some ions in the gate driving circuit, avoid corroding the connection position between the metal trace and the first signal trace, ensure the smooth signal transmission and the normal display of the display panel, effectively extend the service life of the display panel, and improve the product yield.

[0026] The first embodiment Figure 1 A top view schematic diagram of an array substrate provided by an embodiment of the present application is shown; Figure 7 For Figure 1 The cross-sectional schematic diagram at the d position shown; Figure 8 For Figure 1 The cross-sectional schematic diagram at the a position shown; Figure 14 A block diagram of a display device provided by an embodiment of the present application.

[0027] An embodiment of the present application provides an array substrate 1, which is applied to a display panel of a display device to implement the display function of the display panel. The array substrate 1 includes a substrate 11. The substrate 11 is, for example, a rigid substrate made of glass, or the substrate 11 can also be a flexible substrate made of materials such as polyimide (PI), etc., to form a transparent substrate 11. The display device of the present application is not limited to a rigid non-bendable display panel, but can also be a flexible bendable display panel.

[0028] The substrate 11 has a display area AA and a non-display area IA. The non-display area IA is provided with a gate driving circuit 12 (Gate Driver on array, abbreviated as GOA) to achieve low cost, low power consumption, narrow border, etc. of the array substrate 1. Among them, the gate driving circuit 12 includes a circuit area 121 and a bus area 122 (Busline) arranged in sequence along a direction away from the display area AA. The direction away from the display area AA is, for example, the first direction (refer to Figure 14 the X-axis shown).

[0029] There is at least one driving circuit 1211 in the circuit area 121, and each driving circuit 1211 is connected to the bus area 122 to facilitate signal transmission. Among them, the number of driving circuits 1211 depends on the actual situation, and can be one, two or more. The multiple driving circuits 1211 are arranged in sequence along the second direction (refer to Figure 14 the Y-axis shown). One end of the driving circuit 1211 in the circuit area 121 is connected to the bus area 122 through a metal trace 1212, and the other end of the driving circuit 1211 in the circuit area 121 is connected to a scan line (not shown in the figure) of the display area AA through a metal trace 1212.

[0030] The bus area 122 includes a plurality of first signal traces 1221, which are arranged in sequence along a direction away from the display area AA. Each first signal trace 1221 and the corresponding metal trace 1212 are respectively electrically connected to an electrode trace 14 above it through a first transfer layer hole 13 to form an electrolytic cell. Among them, the electrode trace 14 provides the anode and cathode for the electrolytic cell to achieve a complete circuit. The electrode trace 14 is made of, for example, indium tin oxide (ITO), and has relatively stable performance and good conductivity.

[0031] The multiple first signal traces 1221 include a first high-level signal line 12211, a first low-level signal line 12212, and a pulse signal line 12213. The first high-level signal line 12211 is not limited to one, and the first high-level signal line 12211 includes, for example, multiple clock signal lines. The multiple clock signal lines are, for example, CK1, CK2, CK3, and CK4 respectively, so as to facilitate synchronous data transmission, control the data exchange rate, and determine the data transmission timing, etc. The first low-level signal line 12212 includes, for example, a gate-off signal line (VSS), which is a DC voltage signal for turning off the driving circuit 1211 in the circuit area 121. The pulse signal line 12213 includes, for example, a frame start signal line (STV), which is a signal for triggering the start of scanning.

[0032] Among them, the first signal trace 1221 further includes a low-frequency signal line 12214, which provides a control signal for noise elimination in the driving circuit 1211 of the circuit area 121, etc. The low-frequency signal line 12214 can be set to one, two, etc. according to the situation, and can be, for example, LC1, LC2, etc.

[0033] The frame start signal line (STV) is located on one side away from the display area AA, the gate-off signal line (VSS) is arranged close to the circuit area 121, and CK1, CK2, CK3, and CK4 among the multiple clock signal lines are sequentially arranged at intervals in the direction from the frame start signal line (STV) to the gate-off signal line (VSS). The low-frequency signal line 12214 is arranged between the clock signal line and the gate-off signal line (VSS). Among them, for example, the LC1 low-frequency signal line is adjacent to the CK4 clock signal line, and the LC2 low-frequency signal line is adjacent to the gate-off signal line (VSS).

[0034] An electrolytic cell is formed between the first high-level signal line 12211 and the corresponding metal trace 1212 through the first electrode trace 141 or between the first low-level signal line 12212 and the corresponding metal trace 1212 through the second electrode trace 142.

[0035] In some examples, the metal trace 1212 includes, for example, an output trace 12121 and an input trace 12122. One end of the driving circuit 1211 in the circuit area 121 is electrically connected to an output trace 12121. The output trace 12121 is, for example, a gate line (Gate, abbreviated as G), which is connected to the scan line of the display area AA to achieve the scanning function. Among them, the output trace 12121 connected to the first driving circuit 1211 in the circuit area 121 can be marked as G1, the output trace 12121 connected to the second driving circuit 1211 in the circuit area 121 can be marked as G2, and so on. The output trace 12121 connected to the nth driving circuit 1211 can be marked as Gn, specifically subject to the actual situation.

[0036] The other end of the driving circuit 1211 in the circuit region 121 is electrically connected to, for example, a plurality of input traces 12122, and the plurality of input traces 12122 are respectively electrically connected to corresponding first signal traces 1221.

[0037] Exemplarily, taking the first driving circuit 1211 in the circuit region 121 as an example for further explanation, three input traces 12122 are provided, for example. The first input trace 12122 extends into the bus region 122 and is electrically connected to the first electrode trace 141 above it through the first sub-vias 131. The first electrode trace 141 is electrically connected to the CK1 clock signal line through the second sub-vias 132; the second input trace 12122 extends into the bus region 122 and is electrically connected to the second electrode trace 142 above it through another first sub-vias 131. The second electrode trace 142 is electrically connected to the gate-off signal line (VSS) through another second sub-vias 132; the third input trace 12122 extends into the bus region 122 and is electrically connected to the LC1 low-frequency signal line. The connection method is the same as that of the above-mentioned CK1 clock signal line and the gate-off signal line (VSS), and will not be repeated here.

[0038] It can be understood that the above only lists the connection situation of one driving circuit 1211, and the connection methods of other driving circuits 1211 are the same as that of the first driving circuit 1211. The second driving circuit 1211 is electrically connected to the CK2 clock signal line, for example, and it shall be subject to the actual situation.

[0039] In this embodiment, the gate driving circuit 12 further includes a first redundant low-level signal line 1231 and a first sacrificial electrode 1271 located above it. A part of the first redundant low-level signal line 1231 is located in the circuit region 121 and is arranged around the circuit region 121. Among them, the driving circuits 1211 in the circuit region 121 are arranged in sequence along the second direction, and the first redundant low-level signal line 1231 is arranged along the periphery of the arranged driving circuits 1211, that is, the periphery of the circuit region 121.

[0040] Another part of the first redundant low-level signal line 1231 extends into the bus region 122 and is connected to the first low-level signal line 12212 in the bus region 122. The first redundant low-level signal line 1231 is electrically connected to the first sacrificial electrode 1271 through the first vias 13, so as to consume ions around the electrolytic cell, thereby protecting the electrode traces 14 in the gate driving circuit 12 and avoiding their failure, which affects the normal display of the display panel.

[0041] It should be noted that when the first redundant low-level signal line 1231 and the first sacrificial electrode 1271 are arranged around the circuit region 121, at the intersection position with the output line 12121 of the metal trace 1212, if the output line 12121 is enclosed, a phenomenon of relatively large capacitance is likely to occur. Therefore, the output line 12121 can be avoided to reduce the capacitance.

[0042] First example The first redundant low-level signal line 1231 located at the position of the output line 12121 is set to be disconnected to reduce the capacitance at this position and avoid excessive capacitance, which may affect normal display and lifespan. Among them, the disconnection position can be, for example, the first break (not shown in the figure) to avoid the output line 12121.

[0043] Second example Since the output line 12121 is relatively thick, in order to minimize the capacitance of the output line 12121 and the capacitance of the first redundant low-level signal line 1231, the first sacrificial electrode 1271 located at the position of the output line 12121 can be set to be disconnected, that is, a second break 143 can be set at this position to avoid the output line 12121 and prevent the output line 12121 from being enclosed, which may affect normal use.

[0044] In this embodiment, the gate driving circuit 12 includes a first metal layer 123, a first insulating layer 124, a second metal layer 125, a second insulating layer 126, and a first electrode layer 127 that are sequentially arranged on the substrate 11. The first signal trace 1221 is located in the first metal layer 123, the metal trace 1212 is located in the second metal layer 125, the first transfer hole 13 penetrates through the first insulating layer 124 and / or the second insulating layer 126, the first electrode trace 141, the second electrode trace 142, and the first sacrificial electrode 1271 are located in the first electrode layer 127, and the first redundant low-level signal line 1231 is located in the first metal layer 123. The first insulating layer 124 is, for example, used to separate the first metal layer 123 and the second metal layer 125, and the second insulating layer 126 is, for example, used to protect the second metal layer 125, etc.

[0045] Since the layer stack structures are different at different positions, further examples will be given for different cutting points below.

[0046] First example As Figure 7 shown, a cross-sectional schematic diagram of the connection position between the CK2 clock signal line and the metal trace 1212 at position d is shown.

[0047] The first metal layer 123, the first insulating layer 124, the second metal layer 125, the second insulating layer 126, and the first electrode layer 127 are sequentially stacked on the substrate 11. The orthographic projection area of the second metal layer 125 on the substrate 11 is smaller than that of the first metal layer 123 on the substrate 11, so that the second insulating layer 126 partially covers the second metal layer 125, and the remaining part covers the first insulating layer 124. Moreover, the second insulating layer 126 can wrap the end of the second metal layer 125 and isolate the second metal layer 125.

[0048] The second insulating layer 126 is provided with a first sub-transfer hole 131 to expose the second metal layer 125. The first electrode layer 127 covers the second insulating layer 126 and the first sub-transfer hole 131 and is electrically connected to the second metal layer 125. The second sub-transfer hole 132 sequentially penetrates through the second insulating layer 126 and the first insulating layer 124 to expose the first metal layer 123. The first electrode layer 127 extends into the first sub-transfer hole 131 and is connected to the first metal layer 123 to realize the connection between the first metal layer 123 and the second metal layer 125.

[0049] Among them, the CK1 clock signal line is located in the first metal layer 123, the input trace 12122 in the metal trace 1212 is located in the second metal layer 125, and the first electrode trace 141 is located in the first electrode layer 127, realizing the trace connection.

[0050] Second example As Figure 8 shown, a cross-sectional schematic diagram of the position of the first redundant low-level signal line 1231 at a and the first sacrificial electrode 1271 above it is shown.

[0051] The first metal layer 123, the first insulating layer 124, the second insulating layer 126, and the first electrode layer 127 are sequentially stacked on the substrate 11. The first transfer hole 13 sequentially penetrates through the first insulating layer 124 and the second insulating layer 126. The first sacrificial electrode 1271 in the first electrode layer 127 covers the second insulating layer 126 and the first transfer hole 13 and is electrically connected to the first metal layer 123. Among them, the first redundant low-level signal line 1231 is located in the first metal layer 123.

[0052] The array substrate provided in this embodiment is provided with a first redundant low-level signal line on the first low-level signal line. The first redundant low-level signal line surrounds the circuit region. A first sacrificial electrode is disposed above the first redundant low-level signal line, and the metal layer and the first sacrificial electrode are connected by a first transfer layer hole, so that part of the ions in the gate driving circuit can be consumed by the first sacrificial electrode, that is, the ions outside the driving circuit, thereby protecting the first transfer layer hole, the metal trace, the first signal trace, the electrode trace, etc., so that their service life is not affected by the electrochemical corrosion caused by high temperature and high humidity within a certain period of time, ensuring that the display panel can display normally and extending the service life of the display panel.

[0053] Second Embodiment Figure 2 A top view schematic diagram of an array substrate provided by an embodiment of the present application is shown; Figure 9 is Figure 2 The cross-sectional schematic diagram at the position b shown; Figure 14 A block diagram of a display device provided by an embodiment of the present application.

[0054] The second embodiment of the present application further provides an array substrate, which has the same or similar structure as the array substrate provided in its first embodiment. The difference is that the gate driving circuit 12 in this embodiment further includes a first redundant low-level signal line 1251 and a first sacrificial electrode 1272 located above it. A part of the first redundant low-level signal line 1251 is located in the circuit region 121 and is arranged around the circuit region 121. Among them, the driving circuits 1211 in the circuit region 121 are arranged in sequence along the second direction, and the first redundant low-level signal line 1251 is, for example, arranged along the periphery of the arranged circuit region 121.

[0055] Another part of the first redundant low-level signal line 1251 extends into the bus region 122 and is electrically connected to both ends of the pulse signal line 12213 in the bus region 122. The first redundant low-level signal line 1251 is electrically connected to the first sacrificial electrode 1272 through the first transfer layer hole 13, so as to consume the ions around the electrolytic cell, thereby protecting the electrode trace 14 in the gate driving circuit 12 and preventing it from failing and affecting the normal display of the display panel.

[0056] In this embodiment, as Figure 9 shown, a cross-sectional schematic diagram of the position of the first redundant low-level signal line 1251 at the position b and the first sacrificial electrode 1272 located above it is shown.

[0057] The gate driving circuit 12 includes a first insulating layer 124, a second metal layer 125, a second insulating layer 126, and a first electrode layer 127 that are sequentially disposed on the substrate 11. The specific setting manner is the same as that in the first embodiment above, and will not be repeated here. The difference is that the first redundant low-level signal line 1251 is located in the second metal layer 125.

[0058] The second insulating layer 126 is provided with a first transfer hole 13. The first sacrificial electrode 1272 in the first electrode layer 127 covers the second insulating layer 126 and the first transfer hole 13 and is connected to the second metal layer 125. Among them, the first redundant low-level signal line 1251 is located in the second metal layer 125, and the first sacrificial electrode 1272 is located in the first electrode layer 127.

[0059] It should be noted that when the first redundant low-level signal line 1251 is connected to the pulse signal line 12213, the first sacrificial electrode 1272 is also required to achieve electrical connection. The film layer setting manner can refer to the cross-sectional schematic diagram at d in the first embodiment. The cross-sectional schematic diagram is the same as the cross-sectional schematic diagram at d in the first embodiment above, and will not be repeated here.

[0060] In the array substrate provided in this embodiment, a first redundant low-level signal line is provided on the pulse signal line. The first redundant low-level signal line surrounds the circuit region. A first sacrificial electrode is provided above the first redundant low-level signal line, and the metal layer and the first sacrificial electrode are connected by the first transfer hole, so that some ions in the gate driving circuit can be consumed by the first sacrificial electrode, that is, the ions outside the driving circuit, thereby protecting the first transfer hole, metal traces, first signal traces, electrode traces, etc., so that their service life is not affected by electrochemical corrosion caused by high temperature and high humidity within a certain period of time, ensuring that the display panel can display normally and extending the service life of the display panel.

[0061] Third Embodiment Figure 3 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 4 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 5 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 6 It is a top view schematic diagram of an array substrate provided by an embodiment of the present application; Figure 14 It is a block diagram of a display device provided by an embodiment of the present application.

[0062] The third embodiment of the present application further provides an array substrate, which has the same or similar structure as the array substrates provided in its first embodiment and / or second embodiment. The difference is that the gate driving circuit 12 in this embodiment further includes a second redundant low-level signal line and a second sacrificial electrode located above it to achieve double protection and further improve the protection effect.

[0063] First Example As Figure 3 shown, the second redundant low-level signal line 1232 is electrically connected to the first low-level signal line 12212 in the bus region 122. The second redundant low-level signal line 1232 is, for example, located on the outer peripheral side of the first redundant low-level signal line 1231. A part of the second redundant low-level signal line 1232 is located in the circuit region 121 and is disposed around the circuit region 121, and another part of the second redundant low-level signal line 1232 extends into the bus region 122 to facilitate electrical connection with the first low-level signal line 12212 in the bus region 122.

[0064] The second redundant low-level signal line 1232 is electrically connected to the second sacrificial electrode 1273 through the first transfer layer hole 13 for consuming ions around the electrolytic cell.

[0065] Among them, the connection manner between the second redundant low-level signal line 1232 and the first low-level signal line 12212 is the same as the connection manner between the first redundant low-level signal line 1231 and the first low-level signal line 12212 in the above-mentioned first embodiment, and thus will not be repeated here.

[0066] Second Example As Figure 4 shown, the second redundant low-level signal line 1252 is electrically connected to both ends of the pulse signal line 12213 in the bus region 122. The second redundant low-level signal line 1252 is electrically connected to the second sacrificial electrode 1274 through the first transfer layer hole 13 for consuming ions around the electrolytic cell.

[0067] The second redundant low-level signal line 1252 is, for example, located on the outer peripheral side of the first redundant low-level signal line 1251. A part of the second redundant low-level signal line 1252 is located in the circuit region 121 and is disposed around the circuit region 121, and another part of the second redundant low-level signal line 1252 extends into the bus region 122 to facilitate electrical connection with the pulse signal line 12213 in the bus region 122.

[0068] The second redundant low-level signal line 1252 is electrically connected to the second sacrificial electrode 1274 through the first transfer layer hole 13 for consuming ions around the electrolytic cell.

[0069] Among them, the connection manner of the second redundant low-level signal line 1252 and the pulse signal line 12213 is the same as that of the first redundant low-level signal line 1251 and the pulse signal line 12213 in the above-mentioned second embodiment, and thus will not be repeated here.

[0070] Third Example As Figure 5 shown, the second redundant low-level signal line 1232 is electrically connected to the first low-level signal line 12212 in the bus area 122. The second redundant low-level signal line 1232 is, for example, located on the outer peripheral side of the first redundant low-level signal line 1251 as in the second embodiment. A part of the second redundant low-level signal line 1232 is located in the circuit area 121 and is arranged around the circuit area 121, and another part of the second redundant low-level signal line 1232 extends into the bus area 122 to be electrically connected to the first low-level signal line 12212 in the bus area 122.

[0071] Among them, the connection manner of the second redundant low-level signal line 1232 and the first low-level signal line 12212 is the same as that of the first redundant low-level signal line 1231 and the first low-level signal line 12212 in the above-mentioned first embodiment, and thus will not be repeated here.

[0072] Fourth Example As Figure 6 shown, the second redundant low-level signal line 1252 is electrically connected to both ends of the pulse signal line 12213 in the bus area 122. The second redundant low-level signal line 1252 is, for example, located on the outer peripheral side of the first redundant low-level signal line 1231 as in the first embodiment. A part of the second redundant low-level signal line 1252 is located in the circuit area 121 and is arranged around the circuit area 121, and another part of the second redundant low-level signal line 1252 extends into the bus area 122 to be electrically connected to the pulse signal line 12213 in the bus area 122.

[0073] Among them, the connection manner of the second redundant low-level signal line 1252 and the pulse signal line 12213 is the same as that of the first redundant low-level signal line 1251 and the pulse signal line 12213 in the above-mentioned second embodiment, and thus will not be repeated here.

[0074] Among them, the above-mentioned second redundant low-level signal line is arranged on the first metal layer 123 or the second metal layer 125 according to circumstances. By selecting different setting manners for the second redundant low-level signal line, different purposes and effects are achieved, the flexibility of the setting manner of the second redundant low-level signal line is improved, and different requirements are met.

[0075] The array substrate provided in this embodiment is provided with a first redundant low-level signal line and a second redundant low-level signal line, which can consume some ions in the gate driving circuit, that is, ions outside the driving circuit, and is provided with a double layer, effectively improving the consumption effect, so that its service life is not affected by the electrochemical corrosion caused by high temperature and high humidity within a certain period of time, ensuring that the display panel can display normally and extending the service life of the display panel.

[0076] The fourth embodiment Figure 10 is a top view schematic diagram of a circuit intermediate node provided by an embodiment of the present application; Figure 12 is Figure 10 a cross-sectional schematic diagram at c shown in; Figure 13 is Figure 10 a cross-sectional schematic diagram at e shown in; Figure 14 is a block diagram of a display device provided by an embodiment of the present application.

[0077] The third embodiment of the present application also provides an array substrate, which has the same or similar structure as the array substrates provided by its first embodiment and / or second embodiment. The difference is that the gate driving circuit 12 includes a circuit intermediate node 1213 located in the circuit region 121. The circuit intermediate node 1213 is a node located between a TFT (Thin Film Transistor) and several circuits, and is used for connecting and transmitting signals. For example, the circuit intermediate node 1213 can be a certain node between the circuit region 121 and the bus region 122, and plays a role in signal transmission and conversion in the gate driving circuit 12 to ensure the normal operation of the GOA circuit.

[0078] The circuit intermediate node 1213 is, for example, a frame synchronization node (Fn), a burst control node (Qn), a polarity inversion node (Pn), an address enable node (An), a gate driving node (Gn), etc. They are connected to the TFT device or the bus region 122 through traces, and are used for receiving and sending signals to realize the line-by-line scanning function of the circuit. These nodes are key transfer stations for signal transmission, ensuring the accurate transmission of signals in complex circuits. Among them, the circuit intermediate node 1213 is taken as Qn for exemplary illustration below.

[0079] When there is a third transfer layer hole 12131 in the circuit region 121 for the circuit intermediate node 1213, a second electrode layer 12132 will be provided above the circuit intermediate node 1213. Among them, other signal lines will be provided around the circuit intermediate node 1213, such as the second signal line 1214. The root mean square voltage of the second signal line 1214 is greater than the root mean square voltage of the circuit intermediate node 1213. At this time, the second signal line 1214 may cause corrosion of the second electrode layer 12132.

[0080] In this embodiment, a redundant signal line 1215 is disposed between the circuit intermediate node 1213 and the second signal line 1214. A third sacrificial electrode 1216 is disposed above the redundant signal line 1215. The redundant signal line 1215 is electrically connected to the third sacrificial electrode 1216 through a second transfer via 1217. Among them, the root-mean-square voltage of the circuit intermediate node 1213 is greater than the root-mean-square voltage of the redundant signal line 1215.

[0081] At this time, when the second signal line 1214 causes electrochemical corrosion of the surrounding electrodes, it will preferentially corrode the redundant signal line 1215, thereby effectively protecting the second electrode layer 12132.

[0082] The second signal line 1214 can be, for example, a metal trace of signals such as An and Pn, or a TFT device, etc., and its root-mean-square voltage is relatively high. Among them, the second signal line 1214 can be one, two, or three, etc. When the second signal line 1214 is, for example, one, it can be in an L shape and semi-surround the circuit intermediate node 1213; or, when the second signal line 1214 is, for example, three, it can be arranged along the Figure 10 orientations shown, that is, a second signal line 1214 is provided on each of the upper side, upper right side, and right side, specifically subject to the actual situation.

[0083] A redundant signal line 1215 with a lower root-mean-square voltage is introduced between the second signal line 1214 and the circuit intermediate node 1213. When the second signal line 1214 forms electrochemical corrosion on the surrounding electrodes, the redundant signal line 1215 is preferentially corroded, thereby protecting the second electrode layer 12132 on the circuit intermediate node 1213.

[0084] Among them, the redundant signal line 1215 can be adjusted according to the actual situation, and one or two can be set. For example, as Figure 11 shown, the redundant signal line 1215 includes a first sub-redundant trace 12151 and a second sub-redundant trace 12152. The first sub-redundant trace 12151 extends along the outer peripheral side of the circuit intermediate node 1213, and the second sub-redundant trace 12152 is disposed between the first sub-redundant trace 12151 and the second signal line 1214 and extends along the outer peripheral side of the first sub-redundant trace 12151. The first sub-redundant trace 12151 can be, for example, in a Z shape to facilitate complete isolation between the circuit intermediate node 1213 and the second signal line 1214. The second sub-redundant trace can also be, for example, in a Z shape. The first sub-redundant trace 12151 and the second sub-redundant trace 12152 intercept doubly to further improve the protection ability.

[0085] In this embodiment, as Figure 12 shown, a cross-sectional schematic diagram of the position of the second electrode layer 12132 at c is shown.

[0086] The gate driving circuit 12 includes a first metal layer 123, a first insulating layer 124, a second metal layer 125, a second insulating layer 126, and a second electrode layer 12132 that are sequentially disposed on the substrate 11. The second insulating layer 126 is provided with a third transfer layer hole 12131, and the second electrode layer 12132 is electrically connected to the second metal layer 125 through the third transfer layer hole 12131. Among them, the circuit intermediate node 1213 is disposed, for example, on the first metal layer 123.

[0087] In this embodiment, as Figure 13 shown, a cross-sectional schematic diagram of the position of the circuit intermediate node 1213 at e is shown.

[0088] The gate driving circuit 12 includes a first metal layer 123, a first insulating layer 124, a second metal layer 125, a second insulating layer 126, and a third sacrificial electrode 1216 that are sequentially disposed on the substrate 11. The second insulating layer 126 is provided with a second transfer layer hole 1217, and the third sacrificial electrode 1216 is electrically connected to the second metal layer 125 through the second transfer layer hole 1217.

[0089] Among them, the redundant signal line 1215 and the circuit intermediate node 1213 are disposed, for example, on the first metal layer 123, the second signal line 1214 is disposed, for example, on the second metal layer 125, and the third sacrificial electrode 1216 is disposed on the second electrode layer 12132.

[0090] The redundant signal line 1215 is, for example, VSS. The circuit intermediate node 1213 can be, for example, an upward pulse wave STV, FN, Qn, Gn that occurs only once in a frame, or a downward pulse wave Pn, An that occurs only once in a frame. From the perspective of the root mean square voltage, the root mean square voltages in this application are sorted from high to low as An / Pn > CK1~CK4 / LC1 / LC2 > STV / Fn / Qn / Gn > VSS.

[0091] For the array substrate provided in this embodiment, a third sacrificial electrode is specifically disposed on the driving circuit to consume the excess ions in the circuit region, protect the internal structure of the circuit region, prevent its lifespan from being affected by the electrochemical corrosion caused by high temperature and high humidity within a certain period of time, extend its service life, and ensure the normal display of the display panel.

[0092] Fifth Embodiment Figure 14 A block diagram of a display device provided by an embodiment of the present application is shown.

[0093] The fifth embodiment of the present application further provides a display device, including a display panel 2 and a housing. The housing is connected to the display panel 2, and an array substrate 1 as in any one of the first to fourth embodiments is disposed in the display panel. The array substrate 1 is disposed in the display panel 2 to meet the requirements and functions of the display device and achieve normal display of the display panel.

[0094] It should be understood that the terms used herein are for the purpose of describing particular example embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" as used herein may also include the plural forms. The terms "comprises", "comprising", "includes", and "having" are inclusive and thus specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the particular order described or illustrated, unless the order of performance is explicitly stated. It should also be understood that additional or alternative steps may be used.

[0095] Although the terms first, second, third, etc. may be used herein to describe multiple elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as "first" and "second" and other numerical terms used herein do not imply an order or sequence. Thus, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings of the example embodiments.

[0096] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. An array substrate, comprising a base substrate, the base substrate having a display area and a non-display area, the non-display area being provided with a gate drive circuit, the gate drive circuit comprising a circuit area and a bus area sequentially arranged in a direction away from the display area, the bus area comprising a plurality of first signal traces, one end of the circuit area being connected to a portion of the plurality of first signal traces through a metal trace, and the other end of the circuit area being connected to a scan line of the display area through a metal trace; the plurality of first signal traces comprising a first high-level signal line, a first low-level signal line and a pulse signal line; characterized in that The gate drive circuit also includes a first redundant low-level signal line and a first sacrificial electrode located above the first redundant low-level signal line, a portion of the first redundant low-level signal line is located in the circuit area and is arranged around the gate drive circuit, another portion of the first redundant low-level signal line extends to the bus area and is electrically connected to both ends of the first low-level signal line or the pulse signal line in the bus area, and the first redundant low-level signal line is electrically connected to the first sacrificial electrode through a first transfer hole.

2. The array substrate according to claim 1, characterized in that: The first high-level signal line includes a plurality of clock signal lines; the first low-level signal line includes a gate-off signal line, and the pulse signal line includes a frame start signal line; the first signal routing line also includes a low-frequency signal line; A plurality of the first signal wirings are arranged in sequence in a direction away from the display area; Among them, the frame start signal line is located on a side away from the display area, the gate closing signal line is arranged close to the circuit area, the multiple clock signal lines are arranged in sequence from the frame start signal line to the gate closing signal line, and the low-frequency signal line is arranged between the clock signal line and the gate closing signal line.

3. The array substrate according to claim 1, characterized in that: The metal routing includes output routing and input routing, one end of the circuit area is electrically connected to a plurality of the input routings, and the plurality of the input routings are electrically connected to corresponding first signal routings, respectively, and the other end of the circuit area is electrically connected to one of the output routings.

4. The array substrate according to claim 3, characterized in that: The first sacrificial electrode located at the output wiring position is disconnected; or, The first redundant low-level signal line located at the output wiring position is disconnected.

5. The array substrate according to claim 1, characterized in that: The gate drive circuit also includes a second redundant low-level signal line and a second sacrificial electrode located above the second redundant low-level signal line, wherein the second redundant low-level signal line is located on the outer peripheral side of the first redundant low-level signal line, a portion of the second redundant low-level signal line is located in the circuit area and is arranged around the gate drive circuit, another portion of the second redundant low-level signal line extends to the bus area and is electrically connected to both ends of the first low-level signal line or the pulse signal line in the bus area, and the second redundant low-level signal line is electrically connected to the second sacrificial electrode through the first transfer hole.

6. The array substrate according to claim 5, characterized in that: The gate drive circuit comprises a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a first electrode layer which are sequentially arranged on the substrate, the first signal wiring is located in the first metal layer, the metal wiring is located in the second metal layer, the first transfer hole penetrates the first insulating layer and / or the second insulating layer, and the first sacrificial electrode and the second sacrificial electrode are both located in the first electrode layer; The first redundant low-level signal line is located in the first metal layer or the second metal layer, and the second redundant low-level signal line is located in the first metal layer or the second metal layer.

7. The array substrate according to claim 1, characterized in that: The gate driving circuit includes a circuit middle node located in the circuit area, and a second signal line is arranged around the circuit middle node; A redundant signal line is arranged between the middle node of the circuit and the second signal line, a third sacrificial electrode is arranged above the redundant signal line, and the redundant signal line is electrically connected to the third sacrificial electrode through a second transfer hole.

8. The array substrate according to claim 7, characterized in that: The root square voltage of the second signal line is greater than the root square voltage of the middle node of the circuit, and the root square voltage of the middle node of the circuit is greater than the root square voltage of the redundant signal line.

9. The array substrate according to claim 7, characterized in that: The redundant signal line includes a first sub-redundant routing line and a second sub-redundant routing line; The first sub-redundant routing line extends along the outer periphery of the middle node of the circuit, and the second sub-redundant routing line is arranged between the first sub-redundant routing line and the second signal line, and extends along the outer periphery of the first sub-redundant routing line.

10. A display device, characterized in that: It comprises a display panel and a shell, wherein the shell is connected to the display panel, and the array substrate according to any one of claims 1 to 9 is arranged in the display panel.

Images