Numerical control system based on FPGA

Abstract

The invention discloses an FPGA (Field Programmable Gate Array)-based numerical control system, which comprises an FPGA chip and a plurality of drivers, and is characterized in that the FPGA chip comprises a DMA (Direct Memory Access) core, a descriptor management module, a first bus management module, a second bus management module and a plurality of transmission channels; the DMA core is connected with the first bus management module, the second bus management module and the descriptor management module, the first end of the transmission channel is connected with the first bus management module and the second bus management module, and the second end of the transmission channel is connected with the driver; the descriptor management module is connected with the first bus management module and is used for generating a descriptor chain table; the DMA core is used for traversing the descriptor chain table to generate a data transmission request, and the second bus management module determines a driver based on the data transmission request and gates a transmission channel corresponding to the driver. The descriptor management module is configured in the FPGA chip, so that multiple times of data interaction between the CPU and the FPGA chip is avoided, the CPU load is remarkably reduced, and the communication efficiency of the numerical control system is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of numerical control systems, and particularly relates to a numerical control system based on FPGA. Background Art

[0002] At present, it has become normal to use numerical control systems for processing control in the manufacturing industry. During the processing control process, the numerical control system needs to process and calculate a large amount of processing data. Smooth throughput processing of a large amount of data is essential for the numerical control system. At the same time, since the numerical control system will adapt to various types of motors, considering the different numbers and types of different types of motors in actual use, the numerical control system should have good scalability to facilitate equipment function expansion.

[0003] In the prior art, the main control chip is connected to the motherboard CPU using the PCIE bus. The main control chip is used to implement the protocol conversion between the PCIe communication bus of the motherboard CPU and the communication bus of the driver, as well as the transmission of motor control data and motor motion data. Among them, the main control chip uses the Intel PCIe core to complete the conversion of PCIE protocol transactions to the internal bus protocol. The driver bus corresponds to a set of internal bus protocols. The CPU software program configures the internal function modules of the main control chip and the drivers of different communication buses through the driver bus. The main control chip determines which bus protocol conversion to run currently through the configuration register.

[0004] The deficiencies of the prior art are as follows: The FPGA initiates PCIE communication relying on the multiplexed Tx interface. Data multiplexing this interface with the driver communication bus may cause bus conflicts, and the PCIe communication rate is much higher than the rate of this bus, so the communication efficiency is reduced. In addition, the number of extended driver communication buses is limited.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a numerical control system based on FPGA. Summary of the Invention

[0006] The purpose of the present invention is to provide a numerical control system based on FPGA, which can reduce the CPU load while improving the expansion ability of the driver bus.

[0007] To achieve the above purpose, the technical solution provided by a specific embodiment of the present invention is as follows:

[0008] A numerical control system based on FPGA, the numerical control system includes an FPGA chip and a plurality of drivers, and the FPGA chip includes a DMA core, a descriptor management module, a first bus management module, a second bus management module, and a plurality of transmission channels;

[0009] The DMA core is connected to the first bus management module, the second bus management module, and the descriptor management module. The first end of the transmission channel is connected to the first bus management module and the second bus management module, and the second end is connected to the driver.

[0010] The descriptor management module is connected to the first bus management module and is used to generate a descriptor linked list.

[0011] The DMA core is used to traverse the descriptor linked list to generate data transmission requests, and the second bus management module determines the driver based on the data transmission requests and selects the corresponding transmission channel of the driver.

[0012] In one or more embodiments of the present invention, the numerical control system further includes a CPU, and the FPGA chip further includes a PCIE core.

[0013] The PCIE core is connected between the CPU and the DMA core. The CPU is used to issue driver configuration instructions, and the PCIE core and the DMA core are used to transmit the driver configuration instructions to the first bus management module. The first bus management module selects the corresponding transmission channel based on the driver configuration instructions and performs initial configuration on the driver.

[0014] In one or more embodiments of the present invention, the DMA core includes multiple DMA engines. The DMA engines are connected to the descriptor management module, and the DMA engines are used to receive and process the descriptor linked list in parallel.

[0015] In one or more embodiments of the present invention, the first bus management module is connected to the DMA core through the AXI_LITE bus, and the first bus management module is used to convert PCIE protocol data into AXI_LITE protocol data.

[0016] The second bus management module is connected to the DMA engine through the AXI_MM bus, and the second bus management module is used to convert PCIE protocol data into AXI_MM protocol data.

[0017] In one or more embodiments of the present invention, the descriptor management module is connected to the first bus management module through the AXI_LITE bus.

[0018] The first bus management module is used to obtain CPU commands, and the descriptor management module is used to generate a descriptor linked list based on the CPU commands. The descriptor linked list includes a source address, a target address, a transmission length, control information, the address of the next descriptor, and status information.

[0019] In one or more embodiments of the present invention, the FPGA chip further includes a board upgrade control module, which is connected to the second bus management module. The board upgrade control module is used to monitor the board upgrade data between the second bus management module and the FLASH chip, and determine whether the transmission of the board upgrade data is completed. Wherein, the FLASH chip is arranged outside the numerical control system, and the second bus management module is used to transmit a board upgrade command to the FLASH chip through the AXI_MM bus.

[0020] In one or more embodiments of the present invention, the FPGA chip further includes a power-down save control module, which is connected to the second bus management module. The power-down save control module is used to monitor the power-down save data between the second bus management module and the FRAM chip, and determine whether the transmission of the power-down save data is completed. Wherein, the FRAM chip is arranged outside the numerical control system, and the second bus management module is used to transmit a power-down save command to the FRAM chip through the AXI_MM bus.

[0021] In one or more embodiments of the present invention, the transmission channel includes a first protocol conversion module, an AXI_LITE bus interface, a second protocol conversion module, and an AXI_MM bus interface;

[0022] The AXI_LITE bus interface is arranged between the first bus management module and the first end of the first protocol conversion module. The second end of the first protocol conversion module is directly or indirectly connected to the driver through the driver bus. The first protocol conversion module is used to realize the mutual conversion between the AXI_LITE protocol data and the driver bus protocol data;

[0023] The AXI_MM bus interface is arranged between the second bus management module and the first end of the second protocol conversion module. The second end of the second protocol conversion module is directly or indirectly connected to the driver through the driver bus. The second protocol conversion module is used to realize the mutual conversion between the AXI_MM protocol data and the driver bus protocol data.

[0024] In one or more embodiments of the present invention, the transmission channel further includes an interface gating module;

[0025] The first input end of the interface gating module is connected to the first protocol conversion module, the second input end is connected to the second protocol conversion module, and the output end is connected to the driver through the driver bus;

[0026] The interface gating module is used to gate the first protocol conversion module and the driver or gate the second protocol conversion module and the driver based on the priority of the protocol data, wherein the priority of the AXI_MM protocol data is higher than that of the AXI_LITE protocol data.

[0027] In one or more embodiments of the present invention, the FPGA chip further includes a register, which is connected to the second bus management module and the transmission channel, and the register is used to store the transmission data between the second bus management module and the transmission channel; and / or,

[0028] The FPGA chip further includes a dynamic configuration module, which is connected to the second bus management module through the AXI_MM bus, and the dynamic configuration module is used to store dynamic configuration commands.

[0029] Compared with the prior art, in the FPGA-based numerical control system of the present invention, by configuring a descriptor management module in the FPGA chip and connecting it between the DMA core and the first bus management module, CPU commands or driver configuration instructions can be directly transmitted to the first bus management module, and the descriptor management module generates a descriptor linked list, avoiding multiple data interactions between the CPU and the FPGA chip. The DMA can automatically complete data reading, transmission, and writing according to the descriptor linked list without frequent intervention of the CPU, significantly reducing the CPU load and improving the system efficiency;

[0030] The second bus management module controls different data transmission requests to be transmitted through different buses, ensuring that the motor servo cycle synchronization is not damaged and avoiding bus access conflicts, further improving the communication efficiency between the CPU and the FPGA chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 It is a schematic structural diagram of an FPGA-based numerical control system according to an embodiment of the present invention;

[0033] Figure 2 It is an architecture diagram of an FPGA-based numerical control system according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0035] Unless otherwise clearly stated, in the whole specification and claims, the term "comprising" or its variations such as "including" or "having" etc. will be understood to include the stated elements or components, without excluding other elements or other components.

[0036] "Coupled" or "connected" or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connections through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as connections through circuits or components such as switches and follower circuits. Additionally, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0037] In the detailed description of the specification, reference is made to the accompanying drawings which form a part thereof, wherein the same reference numerals always represent the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. Therefore, the following detailed description should not be considered limiting.

[0038] The various operations in the specification can be described as a plurality of discrete actions or operations in a manner that is most helpful for understanding the claimed subject matter. However, the described order should not be construed as implying that these operations must be order-related. Specifically, these operations can be performed in an order different from the presented order. The described operations can be performed in an order different from that of the described embodiments. Various additional operations can be performed in additional embodiments and / or the described operations can be omitted.

[0039] For the purposes of the present application, the phrase "A and / or B" means (A), (B) or (A and B). For the purposes of the present application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0040] Various components and devices may be referred to or shown in the singular form in this document (e.g., "MOS transistor", "transistor", "switch", etc.), but this is merely for the convenience of discussion, and any element referred to in the singular form may include multiple such elements according to the teachings of this document.

[0041] The specification describes the use of phrases "in this embodiment", "in other embodiments", or "in some embodiments", which may each refer to one or more of the same or different embodiments. Additionally, the terms "comprising", "including", "having", etc. used with respect to the embodiments of this application are synonymous.

[0042] As Figure 1 shown, an embodiment of the present invention provides an FPGA-based numerical control system. Among them, the numerical control system includes an FPGA chip 10 and a driver 20. The FPGA chip includes a DMA core 11, a descriptor management module 12 (i.e., Figure 1 shown as Descriptor_manage), a first bus management module 13 (i.e., Figure 1 shown as AXI_LITE_BUS_manage), a second bus management module 14 (i.e., Figure 1 shown as AXI_MM_BUS_manage) and a plurality of transmission channels 15. Further, in this embodiment, the DMA core 11 (Direct Memory Access Core) is preferably an SGDMA core 11 (Scatter-Gather Direct Memory Access Core).

[0043] The DMA core 11 is connected to the first bus management module 13, the second bus management module 14, and the descriptor management module 12. The first end of the transmission channel 15 is connected to the first bus management module 13 and the second bus management module 14, and the second end is connected to the driver 20. Further, there is bidirectional communication between the DMA core 11 and the descriptor management module 12 through a bypass path. The DMA core 11 can directly read the descriptor linked list generated by the descriptor management module 12, not only without going through a complex processing flow or intermediate module, but also without occupying the CPU or FPGA logic resources, thereby reducing the transmission delay and improving the real-time performance and efficiency of the system.

[0044] The descriptor management module 12 is connected to the first bus management module 13 and is used to generate a descriptor linked list.

[0045] The DMA core 11 is used to traverse the descriptor linked list to generate a data transmission request. The second bus management module 14 determines the driver 20 based on the data transmission request and selects and enables the transmission channel 15 corresponding to the driver.

[0046] It should be noted that to improve the expansion ability of the numerical control system, the number of drivers 20 and transmission channels 15 is often multiple, and the number of drivers 20 and transmission channels 15 is the same and in one-to-one correspondence. The specific number depends on the specific application scenario of the numerical control system.

[0047] As Figure 2 shown, another embodiment of the present invention provides a numerical control system based on FPGA. The numerical control system further includes a CPU, and the CPU is used to issue driver configuration instructions and various CPU commands. The FPGA chip further includes a PCIE core 16 (Peripheral Component Interconnect Express Core), where the PCIE core 16 is connected between the CPU and the DMA core 11.

[0048] Furthermore, the communication connection between the PCIE core 16 and the CPU is realized through the PCIE bus, and the communication connection between the PCIE core 16 and the DMA core 11 is established. The PCIE core and the DMA core 11 are used to transmit the driver configuration instructions to the first bus management module 13.

[0049] Furthermore, the PCIE core 16 and the DMA core 11 are also connected through an interrupt signal bus DMA_INTERRUPT_BUS. The interrupt signal bus DMA_INTERRUPT_BUS is used to transmit the interrupt signals generated by the DMA core 11 to notify the CPU about the status or events of the DMA core 11 transmission. The interrupt signals include a transmission completion signal indicating the completion of the DMA transmission task and a transmission error signal indicating an error (such as address out-of-bounds, data verification error, etc.) occurring during the transmission process.

[0050] The first bus management module 13 selects the corresponding transmission channel 15 based on the driver configuration instruction and performs initial configuration on the driver 20. It should be noted that in this embodiment, the driver 20 is taken as an example of a motor for illustration. The transmission channel 15 and the motor 20 are in one-to-one correspondence, that is, if n motors are set in this embodiment, then n transmission channels 15 respectively connected to the motors are configured inside the FPGA chip. The motor is connected to the transmission channel 15 through the driver bus BUS, and the communication protocols of the driver buses BUS corresponding to each motor can be the same or different.

[0051] As Figure 1 and Figure 2 shown, the DMA core 11 includes multiple DMA engines 111. The DMA engines 111 are connected to the descriptor management module 12, and multiple DMA engines 111 receive and process the descriptor list in parallel. In one embodiment, the DMA engines 111 are in one-to-one correspondence with the transmission channels 15.

[0052] It should be noted that each DMA engine 111 in this embodiment independently corresponds to a group of transmission channels 15 and a bus respectively. Therefore, all the DMA engines 111 can work simultaneously without interference, thereby realizing data parallel transmission within the FPGA chip.

[0053] The first bus management module 13 is connected to the DMA core 11 through the AXI_LITE bus. The first bus management module 13 is used to convert PCIE protocol data into AXI_LITE protocol data.

[0054] The second bus management module 14 is connected to the DMA engine 111 through the AXI_MM bus. The second bus management module 14 is used to convert PCIE protocol data into AXI_MM protocol data. It can be understood that the driver configuration instructions issued by the CPU, various CPU commands, and the data transmission requests generated by the DMA core 11 traversing the descriptor list are all PCIE protocol data.

[0055] As Figure 1 and Figure 2 shown, the transmission channel 15 in one embodiment includes a first protocol conversion module 151 (i.e., Figure 1 and Figure 2 shown AXILITE_BUS_Bridge), an AXI_LITE bus interface 106, a second protocol conversion module 152 (i.e., Figure 1 and Figure 2 shown AXIMM_BUS_Bridge), an AXI_MM bus interface 105, and an interface gating module 153 (i.e., Figure 1 and Figure 2 shown Bridge_MUX).

[0056] The AXI_LITE bus interface 106 is disposed between the first bus management module 13 and the first end of the first protocol conversion module 151. And the AXI_LITE bus interface 106 and the first bus management module 13 are communicatively connected through the AXI_LITE bus. The second end of the first protocol conversion module 151 is connected to the first input end of the interface gating module 153, that is, indirectly connected to the driver through the driver bus BUS. The first protocol conversion module 151 is used to realize the mutual conversion between AXI_LITE protocol data and driver bus BUS protocol data.

[0057] The AXI_MM bus interface 105 is set between the second bus management module 14 and the first end of the second protocol conversion module 152. The AXI_MM bus interface 105 is communicatively connected to the second bus management module 14 via the AXI_MM bus. The second end of the second protocol conversion module 152 is connected to the second input end of the interface gating module 153, that is, indirectly connected to the driver 20 via the driver bus BUS. The second protocol conversion module 152 is used to realize the mutual conversion between the AXI_MM protocol data and the driver bus BUS protocol data. It should be noted that Figure 1 and Figure 2 the gray dotted lines shown in are all AXI_LITE buses, and the thick black solid lines are all AXI_MM buses.

[0058] The first input end of the interface gating module 153 is connected to the first protocol conversion module 151, the second input end is connected to the second protocol conversion module 152, and the output end is connected to the driver 20 via the driver bus BUS. The interface gating module 153 is used to gate the first protocol conversion module 151 and the driver or gate the second protocol conversion module 152 and the driver based on the priority of the protocol data, so as to complete data interaction. Among them, the priority of the AXI_MM protocol data is higher than that of the AXI_LITE protocol data.

[0059] The descriptor management module 12 is connected to the first bus management module 13 via the AXI_LITE bus. The first bus management module 13 is used to obtain CPU commands and driver configuration instructions. The descriptor management module 12 is used to generate a descriptor linked list based on the CPU commands and driver configuration instructions. The descriptor linked list is a linked list composed of multiple descriptors (Descriptor). The descriptor linked list includes source address, destination address, transfer length, control information, next descriptor address, and status information. Among them, the control information includes configurations such as transfer direction (read / write), transfer mode (single / loop), and interrupt enable. The CPU commands include motor control commands and motor motion feedback commands, etc.

[0060] It should be noted that in this embodiment, the CPU configures the driver 20 based on the driver configuration instruction before the driver 20 works. Specifically, the driver configuration instruction sent by the CPU is transmitted to the first bus management module 13 after passing through the PCIE core 16 and the DMA core 11. The first bus management module 13 selects the corresponding transmission channel 15 based on the driver configuration instruction and performs initial configuration on the driver (i.e., the motor). After the configuration is completed, the configuration information is sent back to the first bus management module 13 through the transmission channel 15. At this time, the descriptor management module 12 of the AXI_LITE bus that is communicatively connected to the first bus management module 13 can obtain the driver configuration information (including the address information of the driver, the communication protocol of the driver bus BUS, etc.) in the first bus management module 13.

[0061] After the driver configuration is completed, the controller can enter the working state. At this time, the data transmission between the driver and the FPGA chip is all realized through the first bus management module 13 and its corresponding transmission channel 15 and the AXI_MM bus. The AXI_MM bus has a high throughput rate and supports burst transmission and separation of read and write channels.

[0062] In an exemplary embodiment of the present invention, the CPU issues a motor control command. The motor control command is transmitted to the first bus management module 13 after passing through the PCIE core and the DMA core 11. The descriptor management module 12 obtains the motor control command in the first bus management module 13 through the AXI_LITE bus, and combines the motor control command and the driver configuration information (including the address information of the driver, the communication protocol of the driver bus BUS, etc.) to generate a corresponding descriptor linked list. The DMA core 11 is used to traverse the descriptor linked list to generate corresponding data transmission requests. The second bus management module 14 determines the driver based on the data transmission requests and selects the transmission channel 15 corresponding to the driver to implement the control of the motor, and the motor transmits back the motor control data through the transmission channel 15.

[0063] In an exemplary embodiment of the present invention, the CPU issues a motor motion feedback command. The motor motion feedback command is transmitted to the first bus management module 13 after passing through the PCIE core and the DMA core 11. The descriptor management module 12 obtains the motor motion feedback command in the first bus management module 13 through the AXI_LITE bus, and combines the motor motion feedback command and the driver configuration information (including the address information of the driver, the communication protocol of the driver bus BUS, etc.) to generate a corresponding descriptor linked list. The DMA core 11 is used to traverse the descriptor linked list to generate corresponding data transmission requests. The second bus management module 14 determines the driver based on the data transmission requests and selects the transmission channel 15 corresponding to the driver. The motor transmits back the motor motion feedback data through the transmission channel 15.

[0064] Such as Figure 1 andFigure 2 As shown, the FPGA chip in one embodiment further includes a board upgrade control module 18 (i.e., Update_ctrl). The board upgrade control module 18 is connected to the second bus management module 14. The board upgrade control module 18 is used to monitor the board upgrade data between the second bus management module 14 and the FLASH chip 40, and determine whether the board upgrade data transmission is completed. Among them, the FLASH chip 40 is arranged outside the numerical control system and is connected to the second bus management module 14 and the board upgrade control module 18 through the AXI_MM bus. The second bus management module 14 is used to transmit the board upgrade command to the FLASH chip 40 through the AXI_MM bus. It should be noted that the AXI_MM bus between the FLASH chip 40 and the second bus management module 14 corresponds to a DMA engine 111, that is, one of the DMA engines 111 in the DMA core 11 receives and processes the descriptor list associated with the board upgrade.

[0065] In an exemplary embodiment of the present invention, the CPU issues a board upgrade command. The board upgrade command is transmitted to the first bus management module 13 after passing through the PCIE core 16 and the DMA core 11. The descriptor management module 12 obtains the board upgrade command in the first bus management module 13 through the AXI_LITE bus, and generates a corresponding descriptor list in combination with the board upgrade command. The DMA engine 111 traverses the descriptor list to generate a corresponding data transmission request (including board upgrade data in this embodiment), and transmits the board upgrade data through the AXI_MM bus between the FLASH chip 40 and the second bus management module 14. At the same time, the board upgrade control module 18 monitors the board upgrade data flowing through this bus. When the board upgrade data transmission is completed, the board upgrade control module 18 generates a board upgrade completion signal, and transmits it to the second bus management module 14 through the AXI_MM bus, and then transmits it to the CPU through the DMA core 11 and the PCIE core.

[0066] As Figure 2As shown in the figure, the FPGA chip in one embodiment further includes a power-down save control module 17 (i.e., FRAM_ctrl). The power-down save control module 17 is connected to the second bus management module 14. The power-down save control module 17 is used to monitor the power-down save data between the second bus management module 14 and the FRAM chip 30, and determine whether the transmission of the power-down save data is completed. Among them, the FRAM chip 30 is arranged outside the numerical control system and is connected to the second bus management module 14 and the power-down save control module 17 through the AXI_MM bus. The second bus management module 14 is used to transmit the power-down save command to the FRAM chip 30 through the AXI_MM bus. It should be noted that the AXI_MM bus between the FRAM chip 30 and the second bus management module 14 corresponds to a DMA engine 111, that is, one of the DMA engines 111 in the DMA core 11 receives and processes the descriptor list associated with the power-down save.

[0067] In an exemplary embodiment of the present invention, the CPU issues a power-down save command. The power-down save command is transmitted to the first bus management module 13 after passing through the PCIE core and the DMA core 11. The descriptor management module 12 obtains the power-down save command in the first bus management module 13 through the AXI_LITE bus, and generates a corresponding descriptor list in combination with the power-down save command. The DMA engine 111 traverses the descriptor list to generate a corresponding data transmission request (including power-down save data in this embodiment), and transmits the power-down save data through the AXI_MM bus between the FRAM chip 30 and the second bus management module 14. At the same time, the power-down save control module 17 monitors the power-down save data flowing through this bus. When the transmission of the power-down save data is completed, the power-down save control module 17 generates a power-down save completion signal, and transmits it to the second bus management module 14 through the AXI_MM bus, and then transmits it to the CPU through the DMA core 11 and the PCIE core 16.

[0068] Taking the board upgrade command as an example, a large number of data transmission requests may be involved during the upgrade process. Therefore, in the prior art, the CPU needs to interact with the FPGA chip multiple times, occupying a large amount of CPU resources. In addition, due to the low communication efficiency of the PCIE bus between the CPU and the FPGA chip, the communication efficiency is further reduced.

[0069] The present invention configures a descriptor management module 12 within the FPGA chip, and the descriptor management module 12 is connected between the DMA core 11 and the first bus management module 13. CPU commands or driver configuration instructions are directly transmitted to the first bus management module 13, and the descriptor management module 12 obtains information from the first bus management module 13 and generates a descriptor linked list. It is equivalent to that the commands issued by the CPU can be "temporarily stored" in the first bus management module 13 at one time. During the board upgrade process, the CPU can send commands at least only once, and multiple data interactions are implemented by the AXI_MM bus, and the AXI_MM bus has the characteristics of high connectivity and high compatibility.

[0070] Furthermore, board upgrade data and corresponding data transfer requests, motor control data and corresponding data transfer requests, motion feedback data and corresponding data transfer requests, etc. are transmitted using different AXI_MM buses, but are all managed by the second bus management module 14, ensuring that the motor servo cycle synchronization is not damaged and avoiding bus access conflicts.

[0071] As Figure 2 shown, the FPGA chip in another embodiment further includes a register 101, and the register 101 is connected to the second bus management module 14 and the transmission channel 15. The register 101 is used to store the transmission data between the second bus management module 14 and the transmission channel 15.

[0072] As Figure 2 shown, the FPGA chip in another embodiment further includes a dynamic configuration module 102, and the dynamic configuration module 102 is connected to the second bus management module 14 through the AXI_MM bus. The dynamic configuration module 102 is used to store dynamic configuration commands.

[0073] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0074] By configuring the descriptor management module 12 within the FPGA chip and connecting it between the DMA core 11 and the first bus management module 13, the present invention enables CPU commands or driver configuration instructions to be directly transmitted to the first bus management module 13, and the descriptor management module 12 generates a descriptor linked list, avoiding multiple data interactions between the CPU and the FPGA chip. The DMA can automatically complete data reading, transmission, and writing according to the descriptor linked list without frequent intervention of the CPU, significantly reducing the CPU load and improving the system efficiency;

[0075] The present invention realizes data interaction and transmission through the AXI_MM bus, and utilizes its characteristics of high connectivity and high compatibility to further improve the communication efficiency between the CPU and the FPGA chip, avoiding the problem of low communication efficiency of the traditional PCIE bus.

[0076] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

[0077] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A numerical control system based on FPGA, characterized in that: The numerical control system includes an FPGA chip and a plurality of drivers, wherein the FPGA chip includes a DMA core, a descriptor management module, a first bus management module, a second bus management module and a plurality of transmission channels; The DMA core is connected to the first bus management module, the second bus management module and the descriptor management module, the first end of the transmission channel is connected to the first bus management module and the second bus management module, and the second end is connected to the driver; The descriptor management module is connected to the first bus management module and is used to generate a descriptor linked list; The DMA core is used to traverse the descriptor linked list to generate a data transmission request, and the second bus management module determines the driver based on the data transmission request and selects the transmission channel corresponding to the driver.

2. The FPGA-based numerical control system according to claim 1, characterized in that: The numerical control system also includes a CPU, and the FPGA chip also includes a PCIE core; The PCIE core is connected between the CPU and the DMA core. The CPU is used to issue driver configuration instructions. The PCIE core and the DMA core are used to transmit the driver configuration instructions to the first bus management module. The first bus management module selects the corresponding transmission channel based on the driver configuration instructions and performs initial configuration on the driver.

3. The FPGA-based numerical control system according to claim 2, characterized in that: The DMA core includes a plurality of DMA engines, wherein the DMA engines are connected to the descriptor management module, and the DMA engines are used for receiving and processing the descriptor linked list in parallel.

4. The FPGA-based numerical control system according to claim 3, characterized in that: The first bus management module is connected to the DMA core via an AXI_LITE bus, and the first bus management module is used to convert PCIE protocol data into AXI_LITE protocol data; The second bus management module is connected to the DMA engine via the AXI_MM bus, and the second bus management module is used to convert PCIE protocol data into AXI_MM protocol data.

5. The FPGA-based numerical control system according to claim 3, characterized in that: The descriptor management module is connected to the first bus management module via an AXI_LITE bus; The first bus management module is used to obtain CPU commands, and the descriptor management module is used to generate a descriptor linked list based on the CPU commands, wherein the descriptor linked list includes a source address, a target address, a transfer length, control information, a next descriptor address and status information.

6. The FPGA-based numerical control system according to claim 1, characterized in that: The FPGA chip also includes a board upgrade control module, which is connected to the second bus management module. The board upgrade control module is used to monitor the board upgrade data between the second bus management module and the FLASH chip, and determine whether the board upgrade data has been transmitted. The FLASH chip is arranged outside the numerical control system, and the second bus management module is used to transmit the board upgrade command to the FLASH chip through the AXI_MM bus.

7. The FPGA-based numerical control system according to claim 1, characterized in that: The FPGA chip also includes a power-off save control module, which is connected to the second bus management module. The power-off save control module is used to monitor the power-off save data between the second bus management module and the FRAM chip, and determine whether the power-off save data has been transmitted. The FRAM chip is arranged outside the numerical control system, and the second bus management module is used to transmit a power-off save command to the FRAM chip through the AXI_MM bus.

8. The FPGA-based numerical control system according to claim 4, characterized in that: The transmission channel includes a first protocol conversion module, an AXI_LITE bus interface, a second protocol conversion module and an AXI_MM bus interface; The AXI_LITE bus interface is arranged between the first bus management module and the first end of the first protocol conversion module, the second end of the first protocol conversion module is directly or indirectly connected to the driver through the driver bus, and the first protocol conversion module is used to realize the mutual conversion between AXI_LITE protocol data and driver bus protocol data; The AXI_MM bus interface is arranged between the second bus management module and the first end of the second protocol conversion module. The second end of the second protocol conversion module is directly or indirectly connected to the driver through a driver bus. The second protocol conversion module is used to realize mutual conversion between AXI_MM protocol data and driver bus protocol data.

9. The FPGA-based numerical control system according to claim 8, characterized in that: The transmission channel also includes an interface gating module; The first input end of the interface selection module is connected to the first protocol conversion module, the second input end is connected to the second protocol conversion module, and the output end is connected to the driver through the driver bus; The interface selection module is used to select the first protocol conversion module and the driver or the second protocol conversion module and the driver based on the priority of the protocol data, wherein the priority of the AXI_MM protocol data is greater than the priority of the AXI_LITE protocol data.

10. The FPGA-based numerical control system according to claim 1, characterized in that: The FPGA chip further includes a register, the register is connected to the second bus management module and the transmission channel, and the register is used to store transmission data between the second bus management module and the transmission channel; and / or, The FPGA chip also includes a dynamic configuration module, which is connected to the second bus management module via an AXI_MM bus, and is used to store dynamic configuration commands.

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