Adder, chip and electronic equipment

Abstract

The invention provides an adder, a chip and an electronic device, the adder comprises a redundancy coding unit, a decoder unit and a calculation unit, in the calculation process of a signed first target number and a non-signed second target number, the signed first target number is represented by a redundancy number in a differential pair form, and the non-signed second target number is represented by a redundancy number in a differential pair form; an efficient redundant number encoding and decoding process in a redundant encoding unit and a decoder unit can be realized; through the circuit design of the calculation unit, high-bit-width carry-free data processing can be realized, and the data calculation speed is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to an adder, a chip, and an electronic device. Background Art

[0002] In modern electronic computer systems, the adder plays a key role as the most basic computing unit, responsible for implementing the addition operation of data. Whether it is numerical calculation, logical operation, or data processing, the adder is an essential component. In fact, complex computing tasks can ultimately be decomposed into a series of addition operations, so the performance and efficiency of the adder are crucial to the performance of the entire computing system.

[0003] The efficiency of the adder is directly affected by the carry operation of the adder, which is one of the most critical steps in the addition process. Whether a carry occurs directly determines the overflow situation of the number, thereby affecting the accuracy of the calculation result. Traditional adders include ripple-carry adders, carry-lookahead adders, and carry-save adders, etc. However, when dealing with high-width data, the ripple-carry adder is prone to the problem of too long a carry chain, and the carry-lookahead adder is prone to the problem of large consumption of logical resources. Therefore, traditional adders require additional time and resources for carry operations, which limits the overall computing speed. Summary of the Invention

[0004] An adder, a chip, and an electronic device provided by an embodiment of this application can achieve carry-free data processing during data calculation, thereby improving the data calculation speed.

[0005] In a first aspect, this application provides an adder, including: a redundant encoding unit, a decoder unit, and a calculation unit; the redundant encoding unit is respectively connected to the decoder unit and the calculation unit, and the decoder unit is also connected to the calculation unit; the redundant encoding unit is configured to perform redundant encoding on a first target number and a second target number input to the adder respectively; when the first target number is a signed number and the second target number is an unsigned number, send the redundant encoding result of the first target number to the decoder unit, and send the redundant encoding result of the second target number to the calculation unit; the decoder unit is configured to decode the redundant encoding result of the first target number to obtain a first set of differential pairs; send the first set of differential pairs to the calculation unit; the calculation unit is configured to calculate and output the sum of the first target number and the second target number, or the difference between the first target number and the second target number based on the first set of differential pairs and the redundant encoding result of the second target number.

[0006] Compared with the prior art, in the process of calculating the first target number of signed numbers and the second target number of unsigned numbers, the present application uses redundant numbers in the form of differential pairs to represent the first target number of signed numbers, which can achieve an efficient redundant number encoding and decoding process. Through the circuit design of the calculation unit, data processing without carry for high bit widths can be achieved, improving the calculation speed of data. In a possible embodiment of the present application, the decoder unit includes a positive factor unit and a negative factor unit; the positive factor unit is used to decode the redundant encoding result of the first target number to obtain a plurality of first positive factors in the first differential pair set; the negative factor unit is used to decode the redundant encoding result of the first target number to obtain a plurality of first negative factors in the first differential pair set; wherein, each first positive factor and the corresponding first negative factor are determined according to the bits in the redundant encoding result of the first target number that are in the same position.

[0007] By designing the decoder unit to include a positive factor unit and a negative factor unit, the present application further uses the positive factor unit to determine a plurality of first positive factors in the first differential pair set, and uses the negative factor unit to determine a plurality of first negative factors in the first differential pair set, realizing an efficient redundant number encoding and decoding process.

[0008] In a possible embodiment of the present application, the positive factor unit includes a first inverter sub-unit and a first voltage regulation sub-unit, and the first inverter sub-unit is connected to the first voltage regulation sub-unit; the first inverter sub-unit is used to determine the output voltage value of the first inverter sub-unit based on the redundant encoding result of the first target number and the voltage value connected to the first inverter sub-unit; and send the output voltage value of the first inverter sub-unit to the first voltage regulation sub-unit; the first voltage regulation sub-unit is used to determine a plurality of first positive factors in the first differential pair set based on the output voltage value of the first inverter sub-unit.

[0009] By further designing the positive factor unit to include a first inverter sub-unit and a first voltage regulation sub-unit, the present application enables the first inverter sub-unit to adjust the voltage value connected to itself based on the redundant encoding result of the first target number. Furthermore, in the first voltage regulation sub-unit, a plurality of first positive factors in the first differential pair set can be determined according to the output voltage value of the first inverter sub-unit, realizing an efficient redundant number encoding and decoding process.

[0010] In a possible embodiment of the present application, the negative factor unit includes a second inverter subunit and a second voltage regulation subunit, and the second inverter subunit is connected to the second voltage regulation subunit; the second inverter subunit is configured to determine an output voltage value of the second inverter subunit based on a redundant coding result of the first target number and a voltage value connected to the second inverter subunit; and send the output voltage value of the second inverter subunit to the second voltage regulation subunit; the second voltage regulation subunit is configured to determine a plurality of first negative factors in the first differential pair set based on the output voltage value of the second inverter subunit.

[0011] In the present application, by further designing that the negative factor unit includes a second inverter subunit and a second voltage regulation subunit, the second inverter subunit can adjust the voltage value connected to itself based on the redundant coding result of the first target number. Furthermore, in the second voltage regulation subunit, a plurality of first negative factors in the first differential pair set can be determined according to the output voltage value of the second inverter subunit, thereby realizing an efficient redundant number encoding and decoding process.

[0012] In a possible embodiment of the present application, the calculation unit includes a first calculation subunit and a summation subunit. When the first target number is a signed number and the second target number is an unsigned number, the first calculation subunit is configured to determine a first intermediate value and a second intermediate value based on any one of the first positive factors in the first differential pair set, the first negative factor corresponding to the first positive factor, and a value corresponding to the first positive factor in the redundant coding result of the second target number; and send a plurality of first intermediate values and a plurality of second intermediate values to the summation subunit; the summation subunit is configured to calculate the sum of the first target number and the second target number based on the plurality of first intermediate values and the plurality of second intermediate values.

[0013] In the present application, by further designing that the calculation unit includes a first calculation subunit and a summation subunit, and using the plurality of first intermediate values and the plurality of second intermediate values obtained by the first calculation subunit, high-width carry-free data processing is realized, and the data calculation speed is improved.

[0014] In a possible embodiment of the present application, the first calculation subunit includes a first voltage regulation subunit and a third voltage regulation subunit; the third voltage regulation subunit is connected to the first voltage regulation subunit; the third voltage regulation subunit is configured to determine the output voltage value of the third voltage regulation subunit based on any one of the first positive factors in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant encoding result of the second target number, and the voltage value connected to the third voltage regulation subunit; and send the output voltage value of the third voltage regulation subunit to the first voltage regulation subunit; the first voltage regulation subunit is configured to determine the multiple first intermediate values based on the output voltage value of the third voltage regulation subunit.

[0015] By further designing the first calculation subunit, the present application can perform parallel calculations on the encoding and decoding results by combining different circuit modules to implement the encoding and decoding of the first target number and the second target number, obtain multiple first intermediate values, achieve high-width carry-free data processing, and improve the data calculation speed.

[0016] In a possible embodiment of the present application, the first calculation subunit further includes a second voltage regulation subunit and a fourth voltage regulation subunit; the fourth voltage regulation subunit is connected to the second voltage regulation subunit; the fourth voltage regulation subunit is configured to determine the output voltage value of the fourth voltage regulation subunit based on any one of the first positive factors in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant encoding result of the second target number, and the voltage value connected to the fourth voltage regulation subunit; and send the output voltage value of the fourth voltage regulation subunit to the second voltage regulation subunit; the second voltage regulation subunit is configured to determine the multiple second intermediate values based on the output voltage value of the fourth voltage regulation subunit.

[0017] By further designing the first calculation subunit, the present application can perform parallel calculations on the encoding and decoding results by combining different circuit modules to implement the encoding and decoding of the first target number and the second target number, obtain multiple second intermediate values, achieve high-width carry-free data processing, and improve the data calculation speed.

[0018] In a possible embodiment of the present application, the computing unit includes a second computing subunit and a summing subunit. When the first target number is a signed number and the second target number is an unsigned number, the second computing subunit is configured to determine a third intermediate value and a fourth intermediate value based on any one of the first positive factors in the first difference pair set, the first negative factor corresponding to the first positive factor, and the value corresponding to the first positive factor in the redundant encoding result of the second target number; and send a plurality of third intermediate values and a plurality of fourth intermediate values to the summing subunit. The summing subunit is configured to calculate the difference between the first target number and the second target number based on the plurality of third intermediate values and the plurality of fourth intermediate values.

[0019] By further designing the computing unit to include a second computing subunit and a summing subunit, and using the plurality of third intermediate values and the plurality of fourth intermediate values obtained by the second computing subunit, the present application realizes high-width carry-free data processing and improves the data calculation speed.

[0020] In a possible embodiment of the present application, the second computing subunit includes a second voltage regulation subunit and a fifth voltage regulation subunit; the second voltage regulation subunit is connected to the fifth voltage regulation subunit; the fifth voltage regulation subunit is configured to determine the output voltage value of the fifth voltage regulation subunit based on any one of the first positive factors in the first difference pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant encoding result of the second target number, and the voltage value connected to the fifth voltage regulation subunit; and send the output voltage value of the fifth voltage regulation subunit to the second voltage regulation subunit. The second voltage regulation subunit is configured to determine the plurality of third intermediate values based on the output voltage value of the fifth voltage regulation subunit.

[0021] By further designing the second computing subunit, the present application can calculate the encoding and decoding results in a parallel manner by using the combination of different circuit modules after encoding and decoding the first target number and the second target number, obtain a plurality of third intermediate values, realize high-width carry-free data processing, and improve the data calculation speed.

[0022] In a possible embodiment of the present application, the second calculation subunit further includes a first voltage regulation subunit and a sixth voltage regulation subunit; the sixth voltage regulation subunit is connected to the first voltage regulation subunit; the sixth voltage regulation subunit is configured to determine an output voltage value of the sixth voltage regulation subunit based on any one of the first positive factors in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant coding result of the second target number, and the voltage value connected to the sixth voltage regulation subunit; and send the output voltage value of the sixth voltage regulation subunit to the first voltage regulation subunit; the first voltage regulation subunit is configured to determine the plurality of fourth intermediate values based on the output voltage value of the sixth voltage regulation subunit.

[0023] By further designing the second calculation subunit in the present application, after encoding and decoding the first target number and the second target number by using the combination of different circuit modules, the encoding and decoding results can be calculated in a parallel manner to obtain a plurality of fourth intermediate values, realizing carry-free data processing with a high bit width and improving the data calculation speed.

[0024] In a second aspect, the present application further provides an adder, including: a redundant coding unit, a decoder unit, and a calculation unit; the redundant coding unit is respectively connected to the decoder unit and the calculation unit, and the decoder unit is further connected to the calculation unit; the redundant coding unit is configured to perform redundant coding on a first target number and a second target number input to the adder respectively; when both the first target number and the second target number are signed numbers, send the redundant coding result of the first target number and the redundant coding result of the second target number to the decoder unit; the decoder unit is configured to decode the redundant coding result of the first target number to obtain the first differential pair set; decode the redundant coding result of the second target number to obtain a second differential pair set; and send the first differential pair set and the second differential pair set to the calculation unit; the calculation unit is configured to calculate and output the sum of the first target number and the second target number, or the difference between the first target number and the second target number based on the first differential pair set and the second differential pair set.

[0025] In the process of calculating the signed first target number and the signed second target number in the present application, using redundant numbers in different differential pair forms to represent the signed first target number and the signed second target number respectively can realize an efficient redundant number encoding and decoding process. Through the circuit design of the calculation unit, carry-free data processing with a high bit width can be realized, and the data calculation speed can be improved.

[0026] In a possible embodiment of the present application, the decoder unit includes a positive factor unit and a negative factor unit; the positive factor unit is configured to decode the redundant coding result of the first target number to obtain a plurality of first positive factors in the first difference pair set; and decode the redundant coding result of the second target number to obtain a plurality of second positive factors in the second difference pair set; the negative factor unit is configured to decode the redundant coding result of the first target number to obtain a plurality of first negative factors in the first difference pair set; and decode the redundant coding result of the second target number to obtain a plurality of second negative factors in the second difference pair set; wherein, each first positive factor and the corresponding first negative factor are determined according to the bits at the same position in the redundant coding result of the first target number, and each second positive factor and the corresponding second negative factor are determined according to the bits at the same position in the redundant coding result of the second target number.

[0027] In a possible embodiment of the present application, the positive factor unit includes a first inverter subunit and a first voltage regulation subunit, and the first inverter subunit is connected to the first voltage regulation subunit; the first inverter subunit is configured to determine the first output voltage value of the first inverter subunit based on the redundant coding result of the first target number and the voltage value connected to the first inverter subunit; and send the first output voltage value of the first inverter subunit to the first voltage regulation subunit; the first voltage regulation subunit is configured to determine a plurality of first positive factors in the first difference pair set based on the first output voltage value of the first inverter subunit.

[0028] In a possible embodiment of the present application, the first inverter subunit is further configured to determine the second output voltage value of the first inverter subunit based on the redundant coding result of the second target number and the voltage value connected to the first inverter subunit; and send the second output voltage value of the first inverter subunit to the first voltage regulation subunit; the first voltage regulation subunit is configured to determine a plurality of second positive factors in the second difference pair set based on the second output voltage value of the first inverter subunit.

[0029] In a possible embodiment of the present application, the negative factor unit includes a second inverter sub-unit and a second voltage regulation sub-unit, and the second inverter sub-unit is connected to the second voltage regulation sub-unit; the second inverter sub-unit is configured to determine a first output voltage value of the second inverter sub-unit based on the redundant coding result of the first target number and the voltage value connected to the second inverter sub-unit; and send the first output voltage value of the second inverter sub-unit to the second voltage regulation sub-unit; the second voltage regulation sub-unit is configured to determine a plurality of first negative factors in the first differential pair set based on the first output voltage value of the second inverter sub-unit.

[0030] In a possible embodiment of the present application, the second inverter sub-unit is further configured to determine a second output voltage value of the second inverter sub-unit based on the redundant coding result of the second target number and the voltage value connected to the second inverter sub-unit; and send the second output voltage value of the second inverter sub-unit to the second voltage regulation sub-unit; the second voltage regulation sub-unit is configured to determine a plurality of second negative factors in the second differential pair set based on the second output voltage value of the second inverter sub-unit.

[0031] In a possible embodiment of the present application, the calculation unit includes a first calculation sub-unit, a second calculation sub-unit, and a summation sub-unit. When both the first target number and the second target number are signed numbers, the first calculation sub-unit is configured to determine a fifth intermediate value and a sixth intermediate value based on any one first positive factor in the first differential pair set, the first negative factor corresponding to the first positive factor, and the second positive factor corresponding to the first positive factor in the second differential pair set; and send a plurality of fifth intermediate values and a plurality of sixth intermediate values to the second calculation sub-unit; the second calculation sub-unit is configured to determine a seventh intermediate value and an eighth intermediate value based on any one second negative factor in the second differential pair set, the fifth intermediate value corresponding to the second negative factor, and the sixth intermediate value corresponding to the second negative factor; and send a plurality of seventh intermediate values and a plurality of eighth intermediate values to the summation sub-unit; the summation sub-unit is configured to calculate the sum of the first target number and the second target number based on the plurality of seventh intermediate values and the plurality of eighth intermediate values.

[0032] By further designing the calculation unit to include a first calculation sub-unit, a second calculation sub-unit, and a summation sub-unit, the present application can calculate the encoded and decoded results of the first target number and the second target number in a parallel manner by using the combination of different circuit modules, and then divide the encoded and decoded results by different calculation sub-units to achieve high-width carry-free data processing and improve the data calculation speed.

[0033] In a third aspect, the present application provides a chip, including the adder in any possible embodiment of the first aspect above; or the adder in any possible embodiment of the second aspect above.

[0034] In a fourth aspect, the present application provides an electronic device, including a circuit board and the chip in any possible embodiment of the third aspect above, and the chip is disposed on the circuit board. Description of the Drawings

[0035] Figure 1a Schematic diagram of the carry and sum circuits of a traditional half adder provided by the prior art;

[0036] Figure 1b Schematic diagram of the carry and sum circuits of a traditional full adder provided by the prior art;

[0037] Figure 2 Schematic diagram of the structure of an adder provided by an embodiment of the present application;

[0038] Figure 3a Schematic diagram of the structure of the positive factor unit 202-1 provided by an embodiment of the present application;

[0039] Figure 3b Schematic diagram of the structure of the negative factor unit 202-2 provided by an embodiment of the present application;

[0040] Figure 4 Schematic diagram of the structure of the calculation unit 203 provided by an embodiment of the present application;

[0041] Figure 5a Schematic diagram of the structure of the first calculation sub-unit 203-1 provided by an embodiment of the present application;

[0042] Figure 5b Schematic diagram of the structure of the first calculation sub-unit 203-1 provided by an embodiment of the present application;

[0043] Figure 6 Schematic diagram of the structure of the calculation unit 203 provided by an embodiment of the present application;

[0044] Figure 7a Schematic diagram of the structure of the second calculation sub-unit 203-3 provided by an embodiment of the present application;

[0045] Figure 7b Schematic diagram of the structure of the second calculation sub-unit 203-3 provided by an embodiment of the present application;

[0046] Figure 8 Schematic diagram of the structure of the calculation unit 203 provided by an embodiment of the present application;

[0047] Figure 9Schematic diagram of the structure of INT8 signed number + INT8 signed number provided by the embodiment of the present application;

[0048] Figure 10 Schematic diagram of the structure of INT8 signed number + INT8 unsigned number provided by the embodiment of the present application;

[0049] Figure 11 Schematic diagram of the structure of INT8 signed number - INT8 unsigned number provided by the embodiment of the present application;

[0050] Figure 12 Schematic diagram of the application scenario of the adder provided by the embodiment of the present application. Detailed implementation manners

[0051] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

[0052] In various embodiments of the present application, if there is no special description and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0053] In the present application, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural.

[0054] It can be understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. The magnitude of the serial numbers of the above processes does not mean the sequence of execution, and the execution sequence of each process should be determined according to its function and internal logic.

[0055] In modern electronic computer systems, the adder plays a key role as the most basic computing unit and is responsible for implementing the addition operation of data. Whether it is numerical calculation, logical operation, or data processing, the adder is an indispensable component. In fact, complex computing tasks can ultimately be decomposed into a series of addition operations, so the performance and efficiency of the adder are crucial to the performance of the entire computing system.

[0056] The efficiency of an adder is directly affected by the carry operation of the adder, which is one of the most critical steps in the addition process. Whether a carry occurs directly determines the overflow situation of the numbers, thereby affecting the accuracy of the calculation result. Traditional adders include ripple-carry adders, carry-lookahead adders, and carry-save adders, etc. However, when dealing with high-width data, ripple-carry adders are prone to the problem of too long carry chains, and carry-lookahead adders are prone to the problem of large consumption of logic resources. Therefore, traditional adders require additional time and resources for carry operations, which limits the overall calculation speed. For example, as Figure 1a shown, it is a schematic diagram of the carry and sum circuits of a traditional half adder, and Table 1 shows the truth table corresponding to the half adder; as Figure 1b shown, it is a schematic diagram of the carry and sum circuits of a traditional full adder, and Table 2 shows the truth table corresponding to the full adder. Here, the carry of the half adder = AB, and the carry of the full adder = AB + AC + BC.

[0057] Table 1

[0058] A B and carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

[0059] Table 2

[0060] A B C and carry 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0

[0061] With the continuous development of algorithms and chip technologies, it is becoming increasingly important to improve the performance, efficiency, and reliability of adders. This application discovers that redundant number coding (RNC) can improve the representation and calculation process of numbers by introducing redundant information, and thus can reduce or avoid frequent carry operations in traditional adders, improving the calculation speed. Based on redundant number coding, customized circuit design is further used to solve problems such as reducing the number of carry operations, improving the operation efficiency of the adder, and reducing power consumption.

[0062] As Figure 2 shown, an adder provided by an embodiment of this application includes: a redundant coding unit 201, a decoder unit 202, and a calculation unit 203. The redundant coding unit 201 is respectively connected to the decoder unit 202 and the calculation unit 203, and the decoder unit 202 is also connected to the calculation unit 203.

[0063] When the first target number input to the adder is a signed number and the second target number is an unsigned number, the redundant coding unit 201 performs redundant coding on the first target number and the second target number respectively, and then sends the redundant coding result of the first target number to the decoder unit 202, and sends the redundant coding result of the second target number to the calculation unit 203.

[0064] When the first target number input to the adder is a signed number and the second target number is a signed number, after the redundancy encoding unit 201 performs redundancy encoding on the first target number and the second target number respectively, it sends the redundancy encoding results of the first target number and the second target number to the decoder unit 202.

[0065] Optionally, during the process of performing redundancy encoding on the first target number and the second target number input to the adder respectively, the redundancy encoding unit 201 first needs to determine the redundancy encoding base number, and then obtains the redundancy encoding results of the first target number and the second target number respectively based on the determined redundancy encoding base number. For example, assuming that the redundancy encoding base number is 3, for the decimal number -3, since -1*4 + 0*2 + 1 = -3, the redundancy encoding result of -3 can be represented by (-1 0 1). For the decimal number 6, since 1*4 + 1*2 + 0 = 6, the redundancy encoding result of 6 can be represented by (1 1 0). Here, the redundancy encoding result of -3 can also be represented by (-1 -1 0), which is only an example here. In the actual application process, the representation of the redundancy encoding result can be determined by the redundancy characteristics of the redundant number system (RNS).

[0066] After determining the redundancy encoding results of the first target number and the second target number respectively, when the first target number input to the adder is a signed number and the second target number is an unsigned number, the decoder unit 202 decodes the redundancy encoding result of the first target number to obtain the first difference pair set. Here, the first difference pair set can include multiple groups of first factor pairs, and each group of first factor pairs can include a first positive factor and a first negative factor. Then the decoder unit 202 sends the first difference pair set to the calculation unit 203. When the first target number input to the adder is a signed number and the second target number is a signed number, the decoder unit 202 decodes the redundancy encoding result of the first target number to obtain the first difference pair set; decodes the redundancy encoding result of the second target number to obtain the second difference pair set. Here, the second difference pair set can include multiple groups of second factor pairs, and each group of second factor pairs can include a second positive factor and a second negative factor. Then the decoder unit 202 sends the first difference pair set and the second difference pair set to the calculation unit 203. It should be noted that this is only an example of the representation methods of the first difference pair set and the second difference pair set here, and the present application does not limit the specific representation methods of the first difference pair set and the second difference pair set.

[0067] As shown in Table 3, the redundant number in the form of a difference pair is represented by X = X + -X - For example, the signed number x i is represented as: x i = x i+ -x i - , where x i + and x i - ∈ {0, 1}, then x i ∈ {-1, 0, 1}. When x i = 0, x i + = x i - = 0 or 1. Or, the signed number x i can also be expressed as: x i = x i + + x i - , where x i + ∈ {0, 1}, x i - ∈ {0, -1}, x i ∈ {-1, 0, 1}. Taking the signed number -3 as an example, the differential pair form of -3 can be expressed as {x 2 + = 0, x 2 - = 1}, {x 1 + = 1, x 1 - = 1}, {x 0 + = 1, x 0 - = 0}. The redundant number of the unsigned number x i is represented by itself, that is, x i = x i + . When x i + ∈ {0, 1}, x i ∈ {0, 1}.

[0068] Table 3

[0069]

[0070] Exemplarily, in order to implement the signed numbers in Table 3 in the form of differential pairs, the decoder unit 202 may include a positive factor unit 202-1 and a negative factor unit 202-2. When the first target number is a signed number, the positive factor unit 202-1 decodes the redundant encoding result of the first target number to obtain a plurality of first positive factors in the first differential pair set. The negative factor unit 202-2 decodes the redundant encoding result of the first target number to obtain a plurality of first negative factors in the first differential pair set.

[0071] Similarly, when the second target number is a signed number, the positive factor unit 202-1 decodes the redundant encoding result of the second target number to obtain a plurality of second positive factors in the second differential pair set. The negative factor unit 202-2 decodes the redundant encoding result of the second target number to obtain a plurality of second negative factors in the second differential pair set.

[0072] Further, the positive factor unit 202-1 may include a first inverter sub-unit 204 and a first voltage regulation sub-unit 205, and the first inverter sub-unit 204 is connected to the first voltage regulation sub-unit 205. The first inverter sub-unit 204 determines the output voltage value of the first inverter sub-unit 204 based on the redundant encoding result of the first target number and the voltage value connected to the first inverter sub-unit 204, and then sends the output voltage value of the first inverter sub-unit 204 to the first voltage regulation sub-unit 205. The first voltage regulation sub-unit 205 determines a plurality of first positive factors in the first differential pair set based on the output voltage value of the first inverter sub-unit 204.

[0073] Exemplarily, a circuit module is constructed using multi-voltage threshold (MVT) transistors to implement the extraction of the differential positive factor x i + As Figure 3a shown, the first inverter sub-unit 204 includes a first low-threshold transistor M1, a second low-threshold transistor M2, and a negative ternary inverter (NTI) (not shown in the figure), and the first voltage regulation sub-unit 205 includes a first middle-threshold transistor M3 and a second middle-threshold transistor M4. Let x in Table 4 i be represented by A, and A N represents the output value of x i after passing through the NTI.

[0074] The input of the negative ternary inverter is the redundant encoding result of the first target number. The output terminal of the negative ternary inverter is connected to the first pole of M1 and the first pole of M2. The third pole of M1 is connected to the second pole of M2 and the second pole of M3. The third pole of M2 is grounded with the first pole of M3. The second pole of M1 is connected to the high voltage VDD with the first and third poles of M4. The third pole of M3 is connected to the second pole of M4 and is the output terminal of the positive factor unit 202-1. Among them, M1 and M3 can be positive channel metal oxide semiconductor (PMOS) transistors, and M2 and M4 can be negative channel metal oxide semiconductor (NMOS) transistors.

[0075] Here, the first poles of M1, M2, M3, and M4 are all the gates of the transistors. The second poles of M1, M2, M3, and M4 are all the drains of the transistors. The third poles of M1, M2, M3, and M4 are all the sources of the transistors.

[0076] Take Figure 3a the shown circuit diagram as an example for illustration. As shown in Table 4, assuming the redundant encoding result x i ∈{-1, 0, 1} of the first target number, when the input of the NTI is 0 or 1, the output of the positive factor unit 202-1 is 1, that is, the first positive factor x i + = 1. When the input of the NTI is -1, the output of the positive factor unit 202-1 is 0, that is, the first positive factor x i + = 0.

[0077] Table 4

[0078] <![CDATA[x i > <![CDATA[x i + > <![CDATA[x i - > -1 0 -1 0 1 -1 1 1 0

[0079] Similarly, the negative factor unit 202-2 includes a second inverter subunit 206 and a second voltage regulation subunit 207, and the second inverter subunit 206 and the second voltage regulation subunit 207 are connected. The second inverter subunit 206 determines the output voltage value of the second inverter subunit 206 based on the redundant encoding result of the first target number and the voltage value connected to the second inverter subunit 206, and then sends the output voltage value of the second inverter subunit 206 to the second voltage regulation subunit 207. The second voltage regulation subunit 207 determines a plurality of first negative factors in the first differential pair set based on the output voltage value of the second inverter subunit.

[0080] Exemplarily, a circuit module is constructed using multi-voltage threshold transistors to implement the extraction of the differential negative factor x. i - As shown in Figure 3b , the second inverter sub-unit 206 includes a third low-threshold transistor M5, a fourth low-threshold transistor M6, and a positive ternary inverter (PTI) (not shown in the figure). The second voltage regulation sub-unit 207 includes a third medium-threshold transistor M7 and a fourth medium-threshold transistor M8. Represent x in Table 4 i by A, and A P represents the output value of x i after passing through the PTI.

[0081] The input of the positive ternary inverter is the redundant coding result of the first target number. The output terminal of the positive ternary inverter is connected to the first pole of M5 and the first pole of M6. The second pole of M5 is connected to the first pole of M7 and a high voltage VDD. The third pole of M5 is connected to the second pole of M6 and the third pole of M7. The third pole of M6 is connected to the first pole and the second pole of M8 and grounded. The second pole of M7 is connected to the third pole of M8, and it is the output terminal of the negative factor unit 202-2. Among them, M5 and M7 can be PMOS transistors, and M6 and M8 can be NMOS transistors.

[0082] Here, the first pole of M5, the first pole of M6, the first pole of M7, and the first pole of M8 are all the gates of the transistors. The second pole of M5, the second pole of M6, the second pole of M7, and the second pole of M8 are all the drains of the transistors. The third pole of M5, the third pole of M6, the third pole of M7, and the third pole of M8 are all the sources of the transistors.

[0083] Taking the Figure 3b shown circuit diagram as an example for illustration, as shown in Table 4, assuming that the redundant coding result x of the first target number i ∈{-1, 0, 1}, then when the input of the PTI is 0 or -1, the output of the negative factor unit 202-2 is -1, that is, the first negative factor x i - = -1. When the input of the PTI is 1, the output of the negative factor unit 202-2 is 0, that is, the first negative factor x i - = 0.

[0084] As can be seen from the above description, the circuit scheme of the decoder unit 202 in the redundant number adder designed by using multi-voltage threshold transistors can reduce the hardware complexity. After the circuit scheme of the decoder unit 202 is designed by using multi-voltage threshold transistors, the differential pairs corresponding to the signed numbers can be obtained, and then the differential pairs are sent to the calculation unit 203. For example, when the first target number input to the adder is a signed number and the second target number is an unsigned number, the calculation unit 203 calculates and outputs the sum or difference between the first target number and the second target number based on the first set of differential pairs and the redundant coding result of the second target number. When the first target number input to the adder is a signed number and the second target number is a signed number, the calculation unit 203 calculates and outputs the sum or difference between the first target number and the second target number based on the first set of differential pairs and the second set of differential pairs.

[0085] In a possible embodiment, the calculation unit 203 includes a first calculation subunit 203-1 and a summation subunit 203-2. When the first target number is a signed number and the second target number is an unsigned number, the first calculation subunit 203-1 determines a first intermediate value and a second intermediate value based on any one of the first positive factors in the first set of differential pairs, the first negative factor corresponding to the first positive factor, and the value corresponding to the first positive factor in the redundant coding result of the second target number; and sends multiple first intermediate values and multiple second intermediate values to the summation subunit 203-2. The summation subunit 203-2 calculates and outputs the sum of the first target number and the second target number based on the multiple first intermediate values and the multiple second intermediate values.

[0086] Exemplarily, assume that the first target number x is -3 and the second target number y is 6. The first target number x is redundantly encoded according to the calculation form of x i =x i + -x i - to obtain x i ∈{-1, 0, 1}, and x i + ∈{0, 1}, x i - ∈{0, -1}. The second target number y is redundantly encoded according to the calculation form of y i =y i + to obtain y i ∈{0, 1}, and y i + ∈{0, 1}. As Figure 4 shown, each pair of first factors in the first set of differential pairs and the redundant coding result of the second target number are arranged according to x 2 +, x 2 - , y 2 , x 1 + , x 1 - , y 1 , x 0 + , x 0 - , y 0 are arranged, that is, the first calculation subunit 203-1 is based on the first positive factor x in the first difference pair set 2 + , the first positive factor x 2 + corresponding first negative factor x 2 - and the value y corresponding to the redundant coding result of the second target number and the first positive factor x 2 + to determine the first intermediate value t 2 and the second intermediate value u 2 ; the first calculation subunit 203-1 is based on the first positive factor x in the first difference pair set 2 ; the first positive factor x 1 + , the first positive factor x 1 + corresponding first negative factor x 1 - and the value y corresponding to the redundant coding result of the second target number and the first positive factor x 1 + to determine the first intermediate value t 1 and the second intermediate value u 1 ; the first calculation subunit 203-1 is based on the first positive factor x in the first difference pair set 1 ; the first positive factor x 0 + , the first positive factor x 0 + corresponding first negative factor x 0 - and the value y corresponding to the redundant coding result of the second target number and the first positive factor x 0 + to determine the first intermediate value t 0 and the second intermediate value u 0 0 ..

[0087] When calculating the sum of the first target number x and the second target number y, first, the redundant coding results of the first target number and the second target number are used to calculate the intermediate sum for each i in parallel: p i = xi +y i ∈ {-1, 0, 1, 2}, and the middle one and p i It can also be represented by 2t i +u i where t i is the first intermediate value, t i ∈ {0, 1}, u i is the second intermediate value, u i ∈ {0, -1}, so the sum corresponding to each i can be expressed as: s i = t i-1 + u i ∈ {-1, 0, 1}. Table 5 shows the truth table of a plus-plus-minus adder (PPM), that is, the truth table of x i + + x i - + y i . Here, the intermediate sum of each i can also be calculated in the target order. This is only an example, and the present application does not limit the specific calculation method of the intermediate sum.

[0088] Table 5

[0089] <![CDATA[x i + > 1 1 0 1 1 0 <![CDATA[x i - > 0 -1 -1 0 -1 -1 <![CDATA[y i > 1 1 1 0 0 0 <![CDATA[u i > 0 -1 0 -1 0 -1 <![CDATA[t i > 1 1 0 1 0 0 <![CDATA[s i > 2 1 0 1 0 -1

[0090] Optionally, as Figure 5a shown, each PPM in the first calculation subunit 203-1 may further include a first voltage regulation subunit 205 and a third voltage regulation subunit 208, and the third voltage regulation subunit 208 is connected to the first voltage regulation subunit 205. The third voltage regulation subunit 208 determines the output voltage value of the third voltage regulation subunit 208 based on any one of the first positive factors in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant coding result of the second target number, and the voltage value connected to the third voltage regulation subunit 208, and then sends the output voltage value of the third voltage regulation subunit 208 to the first voltage regulation subunit 205. The first voltage regulation subunit 205 determines a plurality of first intermediate values based on the output voltage value of the third voltage regulation subunit 208.

[0091] Exemplarily, as Figure 5aAs shown, the third voltage regulation subunit 208 includes a plurality of low-threshold transistors, PTI (not shown in the figure), and NTI (not shown in the figure). The first voltage regulation subunit 205 includes a first intermediate-threshold transistor M3 and a second intermediate-threshold transistor M4. Among them, some of the low-threshold transistors and M3 can be PMOS transistors, and some of the low-threshold transistors and M4 can be NMOS transistors. Here, it is only an example to illustrate the device composition of the third voltage regulation subunit 208 and the first voltage regulation subunit 205. It should be understood that any embodiment that can realize the respective functions of the third voltage regulation subunit 208 and the first voltage regulation subunit 205 after device expansion and combination is within the scope protected by this application.

[0092] Here, x in Table 5 i + is represented by A, and x in Table 5 i - is represented by B, and y in Table 5 i is represented by C. A P represents the output value of x i + after passing through PTI, and B N represents the output value of x i - after passing through NTI, and C P represents the output value of y i after passing through PTI.

[0093] Taking Figure 5a the shown circuit diagram as an example for illustration, as shown in Table 5, when the sum of the calculations of input x i + , x i - , and y i is 2 or 1, the first intermediate value t i is 1, that is, the output value of the first voltage regulation subunit 205 is 1. When the sum of the calculations of input x i + , x i - , and y i is 0 or -1, the first intermediate value t i is 0, that is, the output value of the first voltage regulation subunit 205 is 0.

[0094] Optionally, as Figure 5bAs shown, each PPM in the first calculation subunit 203-1 may further include a second voltage regulation subunit 207 and a fourth voltage regulation subunit 209, and the fourth voltage regulation subunit 209 is connected to the second voltage regulation subunit 207. The fourth voltage regulation subunit 209 determines the output voltage value of the fourth voltage regulation subunit 209 based on any one of the first positive factors in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant encoding result of the second target number, and the voltage value connected to the fourth voltage regulation subunit 209, and then sends the output voltage value of the fourth voltage regulation subunit 209 to the second voltage regulation subunit 207. The second voltage regulation subunit 207 determines a plurality of second intermediate values based on the output voltage value of the fourth voltage regulation subunit 209.

[0095] Exemplarily, as Figure 5b shown, the fourth voltage regulation subunit 209 includes a plurality of low-threshold transistors, a plurality of high-threshold transistors, PTI (not shown in the figure) and NTI (not shown in the figure). The second voltage regulation subunit 207 includes a third intermediate-threshold transistor M7 and a fourth intermediate-threshold transistor M8. Among them, some of the low-threshold transistors, some of the high-threshold transistors, and M7 may be PMOS transistors, and some of the low-threshold transistors, some of the high-threshold transistors, and M8 may be NMOS transistors. Here is only an example to illustrate the device composition of the fourth voltage regulation subunit 209 and the second voltage regulation subunit 207. It should be understood that any embodiment that can realize the respective functions of the fourth voltage regulation subunit 209 and the second voltage regulation subunit 207 after device expansion and combination is within the scope protected by this application.

[0096] Here, the x in Table 5 i + is represented by A, and the x in Table 5 i - is represented by B, and the y in Table 5 i is represented by C. A P represents the output value of x i + after passing through PTI, and A N represents the output value of x i + after passing through NTI. B P represents the output value of x i - after passing through PTI, and B N represents the output value of x i - after passing through NTI. C P represents the output value of y i after passing through PTI, and C N represents the output value of y iThe output value after NTI.

[0097] Taking Figure 5b the shown circuit diagram as an example, as shown in Table 5, when the calculation sum of input x i + , x i - , y i is -1 or 1, the second intermediate value u i is -1, that is, the output value of the second voltage regulation subunit 207 is -1. When the calculation sum of input x i + , x i - , y i is 0 or 2, the second intermediate value u i is 0, that is, the output value of the second voltage regulation subunit 207 is 0.

[0098] In a possible embodiment, the calculation unit 203 includes a second calculation subunit 203-3 and a summation subunit 203-2. When the first target number is a signed number and the second target number is an unsigned number, the second calculation subunit 203-3 determines a third intermediate value and a fourth intermediate value based on any one of the first positive factors in the first difference pair set, the first negative factor corresponding to the first positive factor, and the value corresponding to the first positive factor in the redundant encoding result of the second target number; and sends multiple third intermediate values and multiple fourth intermediate values to the summation subunit 203-2. The summation subunit 203-2 calculates the difference between the first target number and the second target number based on the multiple third intermediate values and the multiple fourth intermediate values.

[0099] Exemplarily, assume that the first target number x is -3 and the second target number y is 6. The first target number x is redundantly encoded according to the calculation form of x i =x i + -x i - to obtain x i ∈{-1, 0, 1}, and x i + ∈{0, 1}, x i - ∈{0, -1}. The second target number y is redundantly encoded according to the calculation form of y i =y i + to obtain y i ∈{0, 1}, and y i + ∈{0, 1}. As Figure 6 shown, each group of first factor pairs in the first difference pair set and the redundant encoding result of the second target number are arranged according to x2 + and x 2 - and y 2 and x 1 + and x 1 - and y 1 and x 0 + and x 0 - and y 0 are arranged, that is, the second calculation subunit 203-3 is based on the first positive factor x in the first difference pair set 2 + and the first positive factor x 2 + corresponding first negative factor x 2 - and the value y corresponding to the redundant encoding result of the second target number and the first positive factor x 2 + to determine the third intermediate value t 2 and the fourth intermediate value u 2 ; the second calculation subunit 203-3 is based on the first positive factor x in the first difference pair set 2 ; the second calculation subunit 203-3 is based on the first positive factor x in the first difference pair set 1 + and the first positive factor x 1 + corresponding first negative factor x 1 - and the value y corresponding to the redundant encoding result of the second target number and the first positive factor x 1 + to determine the third intermediate value t 1 and the fourth intermediate value u 1 ; the second calculation subunit 203-3 is based on the first positive factor x in the first difference pair set 1 ; the second calculation subunit 203-3 is based on the first positive factor x in the first difference pair set 0 + and the first positive factor x 0 + corresponding first negative factor x 0 - and the value y corresponding to the redundant encoding result of the second target number and the first positive factor x 0 + to determine the third intermediate value t 0 and the fourth intermediate value u 0 ; 0 .

[0100] When calculating the difference between the first target number x and the second target number y, first, the redundant encoding results of the first target number and the second target number are used to calculate the intermediate sum for each i in parallel: p i = x i - y i ∈{-2, -1, 0, 1}, and the intermediate sum p i can also be represented by 2t i + u i where t i is the third intermediate value, t i ∈{0, -1}, u i is the fourth intermediate value, u i ∈{0, 1}, so the sum corresponding to each i can be expressed as: s i = t i-1 + u i ∈{-1, 0, 1}. Table 6 shows the truth table of a minus-minus-plus adder (MMP), that is, the truth table of x i + + x i - - y i . Here, the intermediate sum for each i can also be calculated in the target order. This is just an example, and the present application does not limit the specific calculation method of the intermediate sum.

[0101] Table 6

[0102] <![CDATA[x i + > 1 1 0 1 1 0 <![CDATA[x i - > 0 -1 -1 0 -1 -1 <![CDATA[y i > 1 1 1 0 0 0 <![CDATA[u i > 0 1 0 1 0 1 <![CDATA[t i > 0 -1 -1 0 0 -1 <![CDATA[s i > 0 -1 -2 1 0 -1

[0103] Optionally, as shown in Figure 7a , each MMP in the second calculation subunit 203-3 may include a second voltage regulation subunit 207 and a fifth voltage regulation subunit 2010, and the second voltage regulation subunit 207 and the fifth voltage regulation subunit 2010 are connected. The fifth voltage regulation subunit 2010 determines the output voltage value of the fifth voltage regulation subunit 2010 based on any one of the first positive factors in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant encoding result of the second target number, and the voltage value connected to the fifth voltage regulation subunit 2010, and then sends the output voltage value of the fifth voltage regulation subunit 2010 to the second voltage regulation subunit 207. The second voltage regulation subunit 207 determines a plurality of third intermediate values based on the output voltage value of the fifth voltage regulation subunit 2010.

[0104] Exemplarily, as shown in Figure 7aAs shown, the fifth voltage regulation subunit 2010 includes a plurality of low-threshold transistors, a high-threshold transistor, PTI (not shown in the figure), and NTI (not shown in the figure). The second voltage regulation subunit 207 includes a third intermediate-threshold transistor M7 and a fourth intermediate-threshold transistor M8. Among them, some of the low-threshold transistors and M7 can be PMOS transistors, and some of the low-threshold transistors, a high-threshold transistor, and M8 can be NMOS transistors. Here, it is only an example to illustrate the device composition of the fifth voltage regulation subunit 2010 and the second voltage regulation subunit 207. It should be understood that any embodiment that can implement the respective functions of the fifth voltage regulation subunit 2010 and the second voltage regulation subunit 207 after device expansion and combination is within the scope protected by this application.

[0105] Here, let x in Table 6 i + be represented by A, and let x in Table 6 i - be represented by B, and let y in Table 6 i be represented by C. A P represents the output value of x i + after passing through PTI, B N represents the output value of x i - after passing through NTI, and C N represents the output value of y i after passing through NTI.

[0106] Taking Figure 7a the shown circuit diagram as an example for illustration, as shown in Table 6, when the sum of the calculations of the inputs x i + , x i - , and y i is -2 or -1, the third intermediate value t i is -1, that is, the output value of the second voltage regulation subunit 207 is 1. When the sum of the calculations of the inputs x i + , x i - , and y i is 0 or 1, the third intermediate value t i is 0, that is, the output value of the second voltage regulation subunit 207 is 0.

[0107] Optionally, as Figure 7bAs shown, each MMP in the second calculation subunit 203-3 may further include a first voltage regulation subunit 205 and a sixth voltage regulation subunit 2011, and the sixth voltage regulation subunit 2011 is connected to the first voltage regulation subunit 205. The sixth voltage regulation subunit 2011 determines the output voltage value of the sixth voltage regulation subunit 2011 based on any one of the first positive factors in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant coding result of the second target number, and the voltage value connected to the sixth voltage regulation subunit 2011, and then sends the output voltage value of the sixth voltage regulation subunit 2011 to the first voltage regulation subunit 205. The first voltage regulation subunit 205 determines a plurality of fourth intermediate values based on the output voltage value of the sixth voltage regulation subunit 2011.

[0108] Exemplarily, as Figure 7b shown, the sixth voltage regulation subunit 2011 includes a plurality of low-threshold transistors, a plurality of high-threshold transistors, PTI (not shown in the figure) and NTI (not shown in the figure). The first voltage regulation subunit 205 includes a first intermediate-threshold transistor M3 and a second intermediate-threshold transistor M4. Among them, some of the low-threshold transistors, some of the high-threshold transistors, and M3 may be PMOS transistors, and some of the low-threshold transistors, some of the high-threshold transistors, and M4 may be NMOS transistors. Here is only an example to illustrate the device composition of the sixth voltage regulation subunit 2011 and the first voltage regulation subunit 205. It should be understood that any embodiment that can implement the respective functions of the sixth voltage regulation subunit 2011 and the first voltage regulation subunit 205 after device expansion and combination is within the scope protected by this application.

[0109] Here, the x in Table 6 i + is represented by A, and the x in Table 6 i - is represented by B, and the y in Table 6 i is represented by C. A P represents the output value of x i + after passing through PTI, and A N represents the output value of x i + after passing through NTI. B P represents the output value of x i - after passing through PTI, and B N represents the output value of x i - after passing through NTI. C P represents the output value of y i after passing through PTI, and C N represents the output value of y iThe output value after NTI.

[0110] Taking Figure 7b the circuit diagram shown as an example for illustration, as shown in Table 6, when the sum of the calculations of the inputs x i + and x i - and y i is -1 or 1, the fourth intermediate value u i is 1, that is, the output value of the first voltage regulation sub-unit 205 is 1. When the sum of the calculations of the inputs x i + and x i - and y i is 0 or 2, the fourth intermediate value u i is 0, that is, the output value of the first voltage regulation sub-unit 205 is 0.

[0111] In a possible embodiment, the calculation unit 203 includes a first calculation sub-unit 203-1, a second calculation sub-unit 203-3, and a summation sub-unit 203-2. When both the first target number and the second target number are signed numbers, the first calculation sub-unit 203-1 determines a fifth intermediate value and a sixth intermediate value based on any one first positive factor in the first difference pair set, the first negative factor corresponding to the first positive factor, and the second positive factor corresponding to the first positive factor in the second difference pair set, and then sends multiple fifth intermediate values and multiple sixth intermediate values to the second calculation sub-unit 203-3. The second calculation sub-unit 203-3 determines a seventh intermediate value and an eighth intermediate value based on any one second negative factor in the second difference pair set, the fifth intermediate value corresponding to the second negative factor, and the sixth intermediate value corresponding to the second negative factor; and sends multiple seventh intermediate values and multiple eighth intermediate values to the summation sub-unit 203-2. The summation sub-unit 203-2 calculates the sum of the first target number and the second target number based on multiple seventh intermediate values and multiple eighth intermediate values.

[0112] Exemplarily, based on the above two embodiments, it can be known that, as Figure 8 shown, after the signed numbers X and Y are each redundantly encoded, based on their respective redundant encoding results, they respectively pass through the positive factor unit 202-1 ( Figure 8 denoted by PX in Figure 8 ) and the negative factor unit 202-2 ( 2 + denoted by NX in 2 - ) in the decoder unit 202 to obtain the first difference pair set and the second difference pair set. Each group of first factor pairs in the first difference pair set and each group of second factor pairs in the second difference pair set are arranged according to x 2+ , y 2 - , x 1 + , x 1 - , y 1 + , y 1 - , x 0 + , x 0 - , y 0 + , y 0 - Arrange them, that is, the first calculation subunit 203-1 is based on the first positive factor x in the first difference pair set 2 + , the first positive factor x 2 + corresponding first negative factor x 2 - and the first positive factor x in the second difference pair set 2 + corresponding second positive factor y 2 + , determine the fifth intermediate value t 2 and the sixth intermediate value u 2 ; The first calculation subunit 203-1 is based on the first positive factor x in the first difference pair set 1 + , the first positive factor x 1 + corresponding first negative factor x 1 - and the first positive factor x in the second difference pair set 1 + corresponding second positive factor y 1 + , determine the fifth intermediate value t 1 and the sixth intermediate value u 1 ; The first calculation subunit 203-1 is based on the first positive factor x in the first difference pair set 0 + , the first positive factor x 0 + corresponding first negative factor x 0 - and the first positive factor x in the second difference pair set 0 + corresponding second positive factor y 0 + , determine the fifth intermediate value t 0 and the sixth intermediate value u 0Here, the specific calculation method can refer to the embodiments described in Table 5, which will not be elaborated here.

[0113] The second calculation subunit 203-3 determines the seventh intermediate value t 2 - and the eighth intermediate value u 2 - corresponding to the fifth intermediate value t 1 and the sixth intermediate value u 2 corresponding to the second negative factor y 3 and the eighth intermediate value u 3 ; The second calculation subunit 203-3 determines the seventh intermediate value t 1 - and the eighth intermediate value u 1 - corresponding to the fifth intermediate value t 0 and the sixth intermediate value u 1 corresponding to the second negative factor y 4 and the eighth intermediate value u 4 ; The second calculation subunit 203-3 determines the seventh intermediate value t 0 - and the eighth intermediate value u 0 corresponding to the sixth intermediate value u 5 and the second negative factor and 0 5 Here, the specific calculation method can refer to the embodiments described in Table 6. Since the input of MMP has more combinations of input data than those in the embodiments described in Table 6, Table 7 is used as the truth table of MMP in this embodiment.

[0114] Table 7

[0115] <![CDATA[x i + > 1 1 0 1 1 0 0 0 <![CDATA[x i - > -0 -1 -1 -0 -1 -1 0 0 <![CDATA[y i > -1 -1 -1 0 0 0 -1 0 <![CDATA[u i > 0 1 0 1 0 1 1 0 <![CDATA[t i > 0 -1 -1 0 0 -1 -1 0

[0116] In summary, the present application realizes efficient encoding and decoding of redundant number systems through the representation of redundant numbers in the form of differential pairs, improving the encoding and decoding efficiency; designs various computing modules in the redundant number adder using multi-voltage threshold transistors, reducing the hardware complexity; and realizes the design of a high-bit-width carry-free adder through the combination and expansion of multiple computing sub-modules, such as signed number + unsigned number adder, signed number - unsigned number adder, and signed number + signed number adder. Additionally, in the redundant number system of the prior art, due to the existence of redundancy, the data bit width is large, and a relatively large circuit area / power consumption overhead is required to implement the computing function. For example, in the process of processing data such as -2, -1, 2, etc., at least a 2-bit data bit width and circuit overhead are required. However, the circuit scheme in the adder of the present application can implement the computing function with a 1-bit width, thus reducing the circuit complexity and power consumption. Moreover, the carry-free adder designed in the present application also has a fixed low transmission delay and is not affected by the bit width. As shown in Table 8, compared with the conventional redundant coding adder scheme, the present application can reduce the power consumption by 45%.

[0117] Table 8

[0118]

[0119] In one embodiment of the present application, Figure 9 shows the circuit scheme of INT8 signed number + INT8 signed number. After the signed numbers X and Y are respectively redundantly encoded, based on their respective redundant encoding results, they respectively pass through the positive factor unit 202-1 ( Figure 9 represented by PX in) and the negative factor unit 202-2 ( Figure 9 represented by NX in) in the decoder unit 202 to obtain the first differential pair set and the second differential pair set. Then, the first positive and negative factors of each bit of X and the second positive factor of each bit of Y are input into the corresponding bit of the PPM to calculate multiple fifth intermediate values and multiple sixth intermediate values. Next, the sixth intermediate value of any bit of the PPM, the second negative factor of the corresponding bit of Y, and the fifth intermediate value of the low 1-bit of the PPM are input into the corresponding bit of the MMP to calculate multiple seventh intermediate values and multiple eighth intermediate values. Finally, by performing an addition operation on the eighth intermediate value of any bit of the MMP and the seventh intermediate value of the low 1-bit of the MMP, the sum of the signed numbers X and Y is obtained. Here, during the calculation process, when there is no seventh intermediate value of the low 1-bit of the MMP, it is filled with 0. The highest bit output value is obtained by performing an addition operation on the fifth intermediate value of the highest bit of the PPM and the seventh intermediate value of the highest bit of the MMP.

[0120] In one embodiment of the present application, Figure 10The circuit scheme of INT8 signed number + INT8 unsigned number is shown. After the signed number X and the unsigned number Y are each redundantly encoded, based on the redundant encoding result of X, through the positive factor unit 202-1 ( Figure 10 represented by PX in Figure 10 ) and the negative factor unit 202-2 ( Figure 4 represented by NX in

[0121] ) in the decoder unit 202, a first set of differential pairs is obtained. For subsequent steps, reference can be made to Figure 11 the description of the corresponding embodiment, which will not be elaborated here. Figure 11 represented by PX in Figure 11 ) and the negative factor unit 202-2 ( Figure 5a and Figure 5b represented by NX in

[0122] The adder provided in the embodiments of the present application can be applied to application scenarios such as signed adder trees, signed multipliers, multiply-accumulators, accurate calculation circuits and chips, approximate calculation circuits and chips, neural network algorithm accelerated artificial intelligence (AI) chips, etc.

[0123] An embodiment of the present application further provides a chip, including: the adder described in any of the above embodiments.

[0124] An embodiment of the present application further provides an electronic device, including: a circuit board and the chip described in any of the above embodiments, and the chip is disposed on the circuit board. The chip including the adder provided in the above embodiments of the present application can be applied to various possible electronic devices. The present application does not limit the specific type of the electronic device. For example, the electronic device can be a computing device with computing power, or a terminal device or a server with data processing functions. As Figure 12 shown, taking the electronic device as a terminal computer with data processing functions as an example for illustration, the AI chip integrated with the adder in the above embodiments is disposed on the circuit board in the terminal computer, and the terminal computer can interact with at least one data acquisition device for data. After the terminal computer obtains the data collected by each data acquisition device, it can use the adder to perform data calculation on the collected data. Here, the data acquisition device can be products such as cameras, washing machines, refrigerators, and microwave ovens.

[0125] The above is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An adder, characterized in that, it includes: a redundant encoding unit, a decoder unit and a calculation unit; the redundant encoding unit is respectively connected to the decoder unit and the calculation unit, and the decoder unit is also connected to the calculation unit; the redundant encoding unit is used to perform redundant encoding on the first target number and the second target number input to the adder respectively; when the first target number is a signed number and the second target number is an unsigned number, the redundant encoding result of the first target number is sent to the decoding unit, and the redundant encoding result of the second target number is sent to the calculation unit; the decoder unit is used to decode the redundant encoding result of the first target number to obtain a first set of differential pairs; send the first set of differential pairs to the calculation unit; the calculation unit is used to calculate and output the sum of the first target number and the second target number, or the difference between the first target number and the second target number based on the first set of differential pairs and the redundant encoding result of the second target number.

2. The adder according to claim 1, characterized in that, the decoder unit includes a positive factor unit and a negative factor unit; the positive factor unit is used to decode the redundant encoding result of the first target number to obtain a plurality of first positive factors in the first set of differential pairs; the negative factor unit is used to decode the redundant encoding result of the first target number to obtain a plurality of first negative factors in the first set of differential pairs; wherein, each first positive factor and the corresponding first negative factor are determined according to the bits in the redundant encoding result of the first target number that are in the same position.

3. The adder according to claim 2, characterized in that, the positive factor unit includes a first inverter sub-unit and a first voltage regulation sub-unit, and the first inverter sub-unit is connected to the first voltage regulation sub-unit; the first inverter sub-unit is used to determine the output voltage value of the first inverter sub-unit based on the redundant encoding result of the first target number and the voltage value connected to the first inverter sub-unit; send the output voltage value of the first inverter sub-unit to the first voltage regulation sub-unit; the first voltage regulation sub-unit is used to determine a plurality of first positive factors in the first set of differential pairs based on the output voltage value of the first inverter sub-unit.

4. The adder according to claim 2 or 3, characterized in that, the negative factor unit includes a second inverter sub-unit and a second voltage regulation sub-unit, and the second inverter sub-unit is connected to the second voltage regulation sub-unit; the second inverter sub-unit is used to determine the output voltage value of the second inverter sub-unit based on the redundant encoding result of the first target number and the voltage value connected to the second inverter sub-unit; send the output voltage value of the second inverter sub-unit to the second voltage regulation sub-unit; the second voltage regulation sub-unit is used to determine a plurality of first negative factors in the first set of differential pairs based on the output voltage value of the second inverter sub-unit.

5. The adder according to any one of claims 1-4, characterized in that, the computing unit includes a first computing subunit and a summing subunit. When the first target number is a signed number and the second target number is an unsigned number, the first computing subunit is configured to determine a first intermediate value and a second intermediate value based on any one of the first positive factors in the first difference pair set, the first negative factor corresponding to the first positive factor, and the value corresponding to the first positive factor in the redundant coding result of the second target number; send a plurality of first intermediate values and a plurality of second intermediate values to the summing subunit; the summing subunit is configured to calculate the sum of the first target number and the second target number based on the plurality of first intermediate values and the plurality of second intermediate values.

6. The adder according to claim 5, characterized in that, the first computing subunit includes a first voltage regulation subunit and a third voltage regulation subunit; the third voltage regulation subunit is connected to the first voltage regulation subunit; the third voltage regulation subunit is configured to determine the output voltage value of the third voltage regulation subunit based on any one of the first positive factors in the first difference pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant coding result of the second target number, and the voltage value connected to the third voltage regulation subunit; send the output voltage value of the third voltage regulation subunit to the first voltage regulation subunit; the first voltage regulation subunit is configured to determine the plurality of first intermediate values based on the output voltage value of the third voltage regulation subunit.

7. The adder according to claim 5 or 6, characterized in that, the first computing subunit further includes a second voltage regulation subunit and a fourth voltage regulation subunit; the fourth voltage regulation subunit is connected to the second voltage regulation subunit; the fourth voltage regulation subunit is configured to determine the output voltage value of the fourth voltage regulation subunit based on any one of the first positive factors in the first difference pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant coding result of the second target number, and the voltage value connected to the fourth voltage regulation subunit; send the output voltage value of the fourth voltage regulation subunit to the second voltage regulation subunit; the second voltage regulation subunit is configured to determine the plurality of second intermediate values based on the output voltage value of the fourth voltage regulation subunit.

8. The adder according to any one of claims 1-4, characterized in that, the computing unit includes a second computing subunit and a summing subunit. When the first target number is a signed number and the second target number is an unsigned number, the second computing subunit is configured to determine a third intermediate value and a fourth intermediate value based on any one of the first positive factors in the first difference pair set, the first negative factor corresponding to the first positive factor, and the value corresponding to the first positive factor in the redundant coding result of the second target number; Send multiple third intermediate values and multiple fourth intermediate values to the summing subunit; The summing subunit is configured to calculate the difference between the first target number and the second target number based on the multiple third intermediate values and the multiple fourth intermediate values.

9. The adder according to claim 8, wherein, The second calculation subunit includes a second voltage regulation subunit and a fifth voltage regulation subunit; the second voltage regulation subunit is connected to the fifth voltage regulation subunit; The fifth voltage regulation subunit is configured to determine the output voltage value of the fifth voltage regulation subunit based on any first positive factor in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant encoding result of the second target number, and the voltage value connected to the fifth voltage regulation subunit; Send the output voltage value of the fifth voltage regulation subunit to the second voltage regulation subunit; The second voltage regulation subunit is configured to determine the multiple third intermediate values based on the output voltage value of the fifth voltage regulation subunit.

10. The adder according to claim 9, wherein, The second calculation subunit further includes a first voltage regulation subunit and a sixth voltage regulation subunit; the sixth voltage regulation subunit is connected to the first voltage regulation subunit; The sixth voltage regulation subunit is configured to determine the output voltage value of the sixth voltage regulation subunit based on any first positive factor in the first differential pair set, the first negative factor corresponding to the first positive factor, the value corresponding to the first positive factor in the redundant encoding result of the second target number, and the voltage value connected to the sixth voltage regulation subunit; Send the output voltage value of the sixth voltage regulation subunit to the first voltage regulation subunit; The first voltage regulation subunit is configured to determine the multiple fourth intermediate values based on the output voltage value of the sixth voltage regulation subunit.

11. An adder, wherein, Comprising: A redundant encoding unit, a decoder unit, and a calculation unit, the redundant encoding unit is respectively connected to the decoder unit and the calculation unit, and the decoder unit is further connected to the calculation unit; The redundant encoding unit is configured to perform redundant encoding on the first target number and the second target number input to the adder respectively; when both the first target number and the second target number are signed numbers, send the redundant encoding results of the first target number and the second target number to the decoder unit; The decoder unit is configured to decode the redundant encoding result of the first target number to obtain the first differential pair set; Decode the redundant encoding result of the second target number to obtain a second differential pair set; Send the first differential pair set and the second differential pair set to the calculation unit; The computing unit is configured to calculate and output the sum or the difference between the first target number and the second target number based on the first set of differential pairs and the second set of differential pairs.

12. The adder according to claim 11, wherein, the computing unit includes a first computing subunit, a second computing subunit, and a summing subunit. When both the first target number and the second target number are signed numbers, the first computing subunit is configured to determine a fifth intermediate value and a sixth intermediate value based on any one of the first positive factors in the first set of differential pairs, the first negative factor corresponding to the first positive factor, and the second positive factor in the second set of differential pairs corresponding to the first positive factor; send a plurality of fifth intermediate values and a plurality of sixth intermediate values to the second computing subunit; the second computing subunit is configured to determine a seventh intermediate value and an eighth intermediate value based on any one of the second negative factors in the second set of differential pairs, the fifth intermediate value corresponding to the second negative factor, and the sixth intermediate value corresponding to the second negative factor; send a plurality of seventh intermediate values and a plurality of eighth intermediate values to the summing subunit; the summing subunit is configured to calculate the sum of the first target number and the second target number based on a plurality of seventh intermediate values and a plurality of eighth intermediate values.

13. A chip, wherein, it includes: the adder according to any one of claims 1-10, or the adder according to any one of claims 11-12.

14. An electronic device, wherein, it includes: a circuit board and the chip according to claim 13, and the chip is disposed on the circuit board.

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