A starting control method and device, computer device and storage medium

Abstract

The application relates to a starting control method and device, computer equipment and a storage medium. The method comprises the following steps: in response to receiving a reset and release signal, controlling an XIP module to start a fetch operation; determining a starting stage according to the fetch operation, controlling a multi-piece selection module to obtain a timeout threshold corresponding to the starting stage through a system control module; when the starting stage does not run normally, receiving a reset and release signal generated by the multi-piece selection module based on the timeout threshold, and controlling the XIP module to fetch again based on the reset and release signal until all the starting stages run normally and the starting is completed. The method can be used for flexibly and efficiently completing XIP starting.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a startup control method and device, a computer device, and a storage medium. BACKGROUND

[0002] A system boot program is a small program that is run in advance before a CPU runs an operating system kernel, for initializing hardware devices and establishing a mapping of memory space, so as to bring the software and hardware environment of the system to a suitable state, and to prepare a correct environment for the CPU to finally invoke the operating system kernel.

[0003] In existing practical applications, a system boot program is usually stored on a non-volatile memory device that supports an eXecute In Place (XIP) operation, and a CPU can access the non-volatile memory device in the manner of accessing memory, so as to directly execute the system boot program stored in the non-volatile memory device. Therefore, the application field of XIP technology is wide, including but not limited to industrial control, transportation management, robot technology, national defense and military, medical instruments, and aerospace, etc.

[0004] In the process of conceiving and implementing the present application, the inventors have found that at least the following problems exist:

[0005] The access speed of a non-volatile memory is usually lower than that of a random access memory (RAM), resulting in a decline in execution efficiency; the access mode and data consistency of the memory are required to be high during the XIP startup process, and if not properly used, the system may become unstable or data may be damaged; and the existing XIP startup implementation often lacks flexibility and is difficult to adapt to the needs of different application scenarios.

[0006] The foregoing description is directed to providing general background information and does not necessarily constitute the prior art. SUMMARY

[0007] Therefore, it is necessary to provide a startup control method, device, computer device, and storage medium capable of efficiently and flexibly using XIP startup in view of the above technical problems.

[0008] In a first aspect, the present application provides a startup control method applied to a central processing unit, wherein the central processing unit is connected with a system control module and an XIP module respectively, the XIP module is connected with a plurality of chip select modules, and the system control module is connected with the plurality of chip select modules, and the method comprises the following steps:

[0009] S10: in response to receiving a reset position setting and release signal, controlling the XIP module to start a fetch operation;

[0010] S20: determining a start-up phase according to the instruction fetching operation, and controlling the multiple chip select modules to obtain a timeout threshold corresponding to the start-up phase by the system control module;

[0011] S30: when the start-up phase does not run normally, receiving the reset and release signals generated by the multiple chip select modules based on the timeout threshold, and controlling the XIP module to fetch instructions again based on the reset and release signals until all the start-up phases run normally and the start-up is completed.

[0012] In one embodiment, the timeout threshold includes a first timeout and a second timeout, and the step S20 includes:

[0013] when the start-up phase is a preset initial start-up phase, enabling a switch function enable in the multiple chip select modules by the system control module to obtain a first timeout preconfigured by the switch function;

[0014] when the start-up phase is a preset non-initial start-up phase, disabling the switch function enable in the multiple chip select modules by the system control module, and sending a second timeout corresponding to a chip select function to the multiple chip select modules.

[0015] In one embodiment, before the step S20, the method includes:

[0016] pre-dividing multiple start-up phases in a start-up flow according to the instruction fetching operation

[0017] In one embodiment, the multiple start-up phases include:

[0018] a BOOTROM phase of fetching instructions directly from a flash memory and actively moving programs from the flash memory to an internal static memory;

[0019] a UBOOT phase of verifying the moved programs;

[0020] a KERNEL phase of jumping to a new address to execute the moved programs.

[0021] In a second aspect, the application provides a start-up control method applied to a multiple chip select module, wherein the multiple chip select module is connected with a system control module and an XIP module, the system control module is connected with a central processing unit, and the XIP module is connected with the central processing unit, and the method includes:

[0022] S21, in response to triggering the reset and release signals, re-timing to obtain timing data, and obtaining a timeout threshold;

[0023] S22, when the timing data is greater than the timeout threshold, configuring the next instruction fetch operation chip select data in a preset order, and generating a new reset and release signal through the system control module to reset the management, so that the central processing unit controls the XIP module to fetch instructions again until the instruction fetch operation is completed.

[0024] In one embodiment, the timeout threshold includes a first timeout and a second timeout; and the step of obtaining the timeout threshold includes:

[0025] enabling the switching function of the multiple chip select module based on the system control module to obtain the first timeout pre-configured by the switching function;

[0026] disabling the switching function of the multiple chip select module based on the system control module, and receiving the second timeout sent by the central processing unit through the system control module.

[0027] In one embodiment, when the timing data is greater than the timeout threshold, the step of configuring the next instruction fetch operation chip select data in a preset order includes:

[0028] determining whether the switching function is enabled, if the switching function is enabled, comparing the timing data with the first timeout, and configuring the next instruction fetch operation chip select data in a chip select and configuration order when the timing data is greater than the first timeout;

[0029] if the switching function is disabled, comparing the timing data with the second timeout, and configuring the next instruction fetch operation chip select data in a chip select order when the timing data is greater than the second timeout.

[0030] In one embodiment, the step of configuring the next instruction fetch operation chip select data in a preset order includes:

[0031] determining the current instruction fetch operation chip select data;

[0032] when the switching function is enabled and the timing data is greater than the first timeout, determining the configuration value and / or chip select value of the chip select data required for the next instruction fetch operation;

[0033] or, when the switching function is disabled and the timing data is greater than the second timeout, determining the chip select value of the chip select data required for the next instruction fetch operation.

[0034] In one embodiment, the step of determining the configuration value and / or chip select value of the chip select data required for the next instruction fetch operation includes:

[0035] determining whether the chip select data is the last configuration value of the current chip select, if yes, determining whether the chip select data is the last chip select value, if yes, reading the abnormal state of the multi-chip select module through the system control module;

[0036] if the chip select data is not the last configuration value of the current chip select, determining the configuration value of the next chip select, and triggering new reset position setting and release signals;

[0037] if the chip select data is not the last chip select value, determining the chip select value of the next chip select, and triggering new reset position setting and release signals.

[0038] In a third aspect, the present application provides a starting control device, which comprises a signal receiving module, a threshold sending module and a pointer control module, wherein,

[0039] The signal receiving module is configured to control the XIP module to start a pointer operation in response to receiving reset position setting and release signals.

[0040] The threshold sending module is configured to determine a starting stage according to the pointer operation, and control the multi-chip select module to obtain a timeout threshold corresponding to the starting stage through the system control module.

[0041] The pointer control module is configured to obtain reset position setting and release signals generated by the multi-chip select module based on the timeout threshold when the starting stage does not run normally, so as to control the XIP module to re-take a pointer based on the reset position setting and release signals, until all the starting stages run normally.

[0042] In a fourth aspect, the present application provides a starting control device, which comprises a data obtaining module and a chip select configuration module, wherein,

[0043] The data obtaining module is configured to re-time to obtain timing data and obtain a timeout threshold in response to triggering reset position setting and release signals.

[0044] The chip select configuration module is configured to configure chip select data of a next pointer operation in a preset order and generate new reset position setting and release signals to reset management through the system control module when the timing data is greater than the timeout threshold, so as to control the XIP module to re-take a pointer until the pointer operation is completed.

[0045] In a fifth aspect, the present application provides a computer device, which comprises a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0046] S10: controlling the XIP module to start a pointer operation in response to receiving reset position setting and release signals.

[0047] S20: determining a start-up phase according to the instruction fetching operation, and controlling the plurality of chip select modules to acquire a time-out threshold corresponding to the start-up phase through the system control module;

[0048] S30: when the start-up phase does not run normally, receiving the reset and release signals generated by the plurality of chip select modules based on the time-out threshold, and controlling the XIP module to re-fetch instructions based on the reset and release signals until all the start-up phases run normally and the start-up is completed;

[0049] Alternatively, the computer program is executed by the processor to implement the following steps:

[0050] S21, in response to triggering the reset and release signals, re-timing to acquire timing data, and acquiring a time-out threshold;

[0051] S22, when the timing data is greater than the time-out threshold, configuring the chip select data of the next instruction fetching operation in a preset order, and generating new reset and release signals to reset the management through the system control module, so that the central processing unit controls the XIP module to re-fetch instructions until the instruction fetching operation is completed.

[0052] In a sixth aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the following steps:

[0053] S10: in response to receiving the reset and release signals, controlling the XIP module to start the instruction fetching operation;

[0054] S20: determining a start-up phase according to the instruction fetching operation, and controlling the plurality of chip select modules to acquire a time-out threshold corresponding to the start-up phase through the system control module;

[0055] S30: when the start-up phase does not run normally, receiving the reset and release signals generated by the plurality of chip select modules based on the time-out threshold, and controlling the XIP module to re-fetch instructions based on the reset and release signals until all the start-up phases run normally and the start-up is completed;

[0056] Alternatively, the computer program is executed by the processor to implement the following steps

[0057] S21, in response to triggering the reset and release signals, re-timing to acquire timing data, and acquiring a time-out threshold;

[0058] S22, when the timing data is greater than the timeout threshold, configuring the next instruction fetch operation of the chip select data in a preset order, and generating a new reset position and release signal through the system control module to reset the management, so that the central processing unit controls the XIP module to fetch instructions again until the instruction fetch operation is completed.

[0059] The starting control method, device, computer equipment and storage medium can support the XIP module to access the non-volatile memory based on the multi-chip selection module to complete the starting process, reduce the probability of starting failure of the existing non-volatile memory due to damage, and through the multi-chip selection design, each non-volatile memory will be reasonably traversed and configured as much as possible to ensure that the non-volatile memory can read data, so as to implement flexible and efficient use of XIP starting. Through the connection of the central processing unit, the system control module and the XIP module, the XIP module and the multi-chip selection module, and the system control module and the multi-chip selection module, efficient and simple communication interaction between the central processing unit and the hardware is supported, the switching function of the multi-chip selection module is configured to be disabled / enabled in different starting stages, and the chip selection threshold of the switching function and the chip selection function is configured to prevent unexpected central processing unit problems in each starting stage, such as hanging, running, and the like. The multi-chip selection module automatically generates a reset position and release signal based on the instruction fetch timeout caused by abnormal instruction fetch operation. The central processing unit quickly ends the current failed starting process and reenters a new starting process to start instruction fetch again according to the reset position and release signal generated by the multi-chip selection module. The multi-chip selection module cooperates with the XIP module to access the non-volatile memory to perform instruction fetch operation, thereby improving the XIP starting success rate, adapting to reading of different types of non-volatile memories, avoiding the risk of system hanging caused by abnormal central processing unit in each starting stage, and improving the reliability of the entire system starting. BRIEF DESCRIPTION OF DRAWINGS

[0060] Figure 1 The starting control system diagram of the starting control method in the first embodiment;

[0061] Figure 2 The flowchart of the starting control method in the second embodiment;

[0062] Figure 3 The address arrangement diagram in the storage space in the second embodiment;

[0063] Figure 4 The multi-starting stage processing flowchart in the second embodiment;

[0064] Figure 5 The flowchart of the starting control method in the third embodiment;

[0065] Figure 6Fig. 3 is a schematic diagram of a chip select flow for configuring a multi-chip mode selection module in the third embodiment;

[0066] Figure 7 Fig. 4 is a block diagram of a structure of a start control device in the fourth embodiment;

[0067] Figure 8 Fig. 5 is a block diagram of a structure of a start control device in the fifth embodiment;

[0068] Figure 9 Fig. 6 is a block diagram of an internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0069] The illustrative examples set forth in the following description have been presented for purposes of explanation and should not be construed as an exhaustive listing of all embodiments consistent with the present application. Rather, they are presented as examples to provide a description of the application as it can be practiced in one embodiment.

[0070] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. In the event of a contradiction, the specific disclosure of a particular embodiment supersedes any ambiguous implication arising from a description common to that embodiment and other embodiments.

[0071] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, may be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or," "and / or," "including at least one of the following," etc., as used in this application, may be interpreted as inclusive, or mean any one or any combination thereof. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C." Similarly, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C." Exceptions to this definition only occur when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0072] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0073] Depending on the context, the words “if” or “suppose” as used here can be interpreted as “when” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination” or “if detection (of the stated condition or event)” can be interpreted as “when determination” or “in response to determination” or “when detection (of the stated condition or event)” or “in response to detection (of the stated condition or event).”

[0074] It should be noted that in this paper, step codes such as S1, S2, etc. are used, the purpose is to express the corresponding content more clearly and simply, and it does not constitute a substantial limitation on the order. Those skilled in the art may perform S2 first and then perform S1 in specific implementation, etc., but these should be within the scope of protection of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application. In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only for the convenience of the description of the present application, and they have no specific meaning. Therefore, "module", "component" or "unit" can be mixedly used.

[0075] First embodiment

[0076] The starting control method provided by the present application can refer to the starting control system as shown in Figure 1 The starting control system includes a central processor 110, an XIP module 120, a system control module 130, a multi-chip selection module 140 and a non-volatile memory 150. The central processor 110 is connected with the XIP module 120 and the system control module 130 respectively, the XIP module 120 is connected with the multi-chip selection module 140 and the non-volatile memory 150, and the system control module 130 is connected with the multi-chip selection module 140. Among them, the central processor 110, the XIP module 120, the system control module 130 and the multi-chip selection module 140 are integrated on the same SOC chip.

[0077] The system control module 130 is responsible for coordinating and managing system-level configuration and control functions, such as clock gating, exception reset control. The system control module in the embodiment serves as a bridge for connecting the central processor 110 and the multi-chip selection module 140. The interaction between the system control module 130 and the multi-chip selection module 140 in the embodiment is relatively simple, and there is no need to use the amba bus communication additionally.

[0078] XIP module 120, with a simplified version of QSPI / SPI controller, has read function. XIP module 120 uses XIP technology to directly execute code on non-volatile memory 150, eliminating the need to copy code to RAM, thereby reducing boot time, memory occupation, improving system operation efficiency, reducing system cost and power consumption. XIP module 120 and central processor 110 can communicate with each other through any bus, such as AXI (Advanced eXtensible Interface) bus, AHB (Advanced High Performance Bus) bus or APB (Advanced Peripheral Bus) bus, so that central processor 110 can access XIP module 120 through any bus. XIP module 120 converts the read request access of central processor 110 into QSPI bus waveform to communicate with non-volatile memory 150 outside the chip, and receives the chip select configuration of the multi-chip select module to change the QSPI bus request form in real time. Optionally, XIP module 120 reads the chip select data of multi-chip select module 140 according to the instruction fetch instruction of central processor 110, and directly executes the instruction fetch operation on non-volatile memory 150. Optionally, central processor 110 generates an instruction fetch instruction according to the reset and release signal. Optionally, when central processor 110 receives the reset and release signal generated by the external start key operation, the chip select data of multi-chip select module 140 received by XIP module 120 is initial chip select data, such as chip select 0_ configuration 0; when central processor 110 receives the reset and release signal generated by the internal multi-chip select module, the chip select data of multi-chip select module 140 received by XIP module 120 is the chip select data of multi-chip select module 140 based on the timeout threshold configuration.

[0079] Non-volatile memory 150 uses a group of NorFlash chips, with common clock and data lines, and independent chip select (that is, in non-volatile memory, the selected state of each storage chip is controlled by a chip select signal (Chip Select, abbreviated as CS). Chip select signal is a low-level effective control signal, used to indicate which storage chip is selected for data read / write operation). Different norflash chips may be different manufacturers, with different specific parameters, such as supporting 16-bit, 24-bit, 32-bit address, such as only supporting mode0, mode1 clock / phase polarity, etc.

[0080] The central processor 110 can be a general processor, a digital signal processor or any other conventional processor. The central processor 110 interacts with the XIP module 120 to control the XIP module 120 to perform the instruction fetch operation. The central processor 110 interacts with the multiple chip select module 140 through the system control module 130 to control the multiple chip select module 140 to stop working by sending a stop command to the multiple chip select module 140, to send a timeout threshold to the multiple chip select module 140, to send a stop command to the multiple chip select module 140 to control the multiple chip select module 140 to stop timing and working, and to receive the reset set and release signals generated by the multiple chip select module 140 by using the reset management of the system control module 130, so that the central processor 110 controls the XIP module 120 to fetch instructions from zero according to the reset set and release signals.

[0081] Optionally, after the central processor 110 receives the external start key operation or the reset set and release signals generated by the internal multiple chip select module, the central processor 110 controls the XIP module 120 to perform the instruction fetch operation on the non-volatile memory 150 after reading the current chip select data of the multiple chip select module 140, and sends a stop command to the multiple chip select module 140 through the system control module 130 to control the multiple chip select module 140 to stop working when the instruction fetch is successful or fails. Optionally, the chip select data of the multiple chip select module 140 is initialized by the system control module 130 when the reset set and release signals come from the outside. Optionally, the central processor 110 sends an instruction fetch instruction to the XIP module 120 according to the reset set and release signals to control the XIP module 120 to perform the instruction fetch operation from zero. Optionally, the central processor 110 controls the multiple chip select module 140 to turn off / turn on the switch function enable through the system control module 130. Optionally, the central processor 110 sends a timeout threshold corresponding to the chip select function to the multiple chip select module 140 through the system control module 130.

[0082] The multiple chip select module 140 can be a general processor configured with a timing clock, a reset design and a multiple chip select design, wherein the multiple chip select design includes a plurality of chip select parameters and configuration parameters, and the internal clock of the multiple chip select module is cleared to restart timing when the reset set and release signals are generated. In this embodiment, the reset set and release signals generated by the multiple chip select module are a kind of reset set and release signals. Optionally, after the multiple chip select module 140 generates new reset set and release signals, the timing data is automatically cleared and restarted, and when the timing data is greater than the current acquired timeout threshold, the chip select data of the next instruction fetch operation is determined.

[0083] The startup control method of the startup control system supports the use of multiple chip select modules to access the non-volatile memory based on the XIP module to complete the startup process, reduces the probability of startup failure of the non-volatile memory due to damage, supports efficient and simple communication interaction between the central processor and the hardware, and in different startup stages of the software, based on the timeout threshold value transmitted by the central processor to the multiple chip select modules, the chip select data required for the instruction fetching operation is configured, so as to prevent unexpected central processor problems such as hanging and running away in each startup stage, the multiple chip select modules automatically configure the chip select data for the next instruction fetching after timeout, and generate a reset position and release signal feedback to the central processor, so that the central processor can quickly end the failed startup process and re-enter the startup process; the use of multiple chip select modules to assist the instruction fetching operation of the XIP module improves the startup success rate of the XIP module, adapts to the reading of different types of non-volatile memories, avoids the risk of system hanging due to abnormality of the central processor in each startup stage, and thus improves the reliability of the entire system startup.

[0084] Second embodiment

[0085] In one embodiment, as shown in Figure 2 , a startup control method is provided, which is applied to the central processor in Figure 1 for example. The central processor is connected with a system control module and an XIP module respectively, the XIP module is connected with a multiple chip select module, and the system control module is connected with the multiple chip select module. The startup control method provided in this embodiment includes:

[0086] S10, in response to receiving the reset position and release signal, controlling the XIP module to start the instruction fetching operation;

[0087] S20, determining the startup stage according to the instruction fetching operation, and controlling the multiple chip select module to obtain the timeout threshold value corresponding to the startup stage through the system control module;

[0088] S30, when the startup stage does not run normally, receiving the reset position and release signal generated by the multiple chip select module based on the timeout threshold value, and controlling the XIP module to fetch instructions again based on the reset position and release signal, until all startup stages run normally and the startup is completed.

[0089] Optionally, the reset position and release refers to the operation of restoring the state of certain hardware facilities or software programs to the initial state in the computer system. In short, the reset position and release is to restart certain devices to ensure normal operation. The reset position and release helps to solve system failure or ensure the necessary steps for normal operation of the system. The main functions of the reset position and release include: solving system failure, initializing hardware devices. For example, due to long running time, software bugs, hardware failure, etc., some devices or programs may appear abnormal state or deadlock, and the reset position and release can force them to restore the original state and thus remove the failure. For another example, in some application environments, the reset position and release can be used to initialize hardware devices or clear some temporary data to speed up system response speed. The implementation of the reset position and release usually includes: system command, software programming, physical switch. The system command refers to the system command issued by the operating system or hardware driver to realize the reset position and release. The software programming refers to the implementation of the reset position and release operation by specific code in software programming. The physical switch refers to the reset operation of some devices through the physical switch at the hardware level. Since the start control method in the embodiment is illustrated by taking the central processing unit as an example, when the received reset position and release signal comes from the outside, it can be one of the system command, software programming, and physical switch to trigger the reset position and release signal, and when the received reset position and release signal comes from the inside, it can be a preset trigger condition, such as exceeding a predetermined time.

[0090] Optionally, the instruction fetch operation refers to the process of fetching an instruction from the non-volatile memory to the instruction register. The instruction fetch operation in the embodiment uses the chip select data transmitted by the multiple chip select modules to determine the position of the instruction in the non-volatile memory, and then reads and executes the instruction from the non-volatile memory.

[0091] Optionally, the timeout threshold includes a first timeout and a second timeout. The first timeout is used to control the switching function to obtain the chip select data, and the second timeout is used to control the chip select function to obtain the chip select data.

[0092] Optionally, the step S20 of controlling the multiple chip select modules to obtain the timeout threshold corresponding to the start phase by the system control module includes:

[0093] S121, when the start phase is a preset initial start phase, enabling the switching function enable in the multiple chip select modules by the system control module to obtain the first timeout preconfigured by the switching function.

[0094] S122, when the startup stage is the preset non-initial startup stage, the system control module is used to close the switch function enable in the multi-chip selection module, and a second timeout corresponding to the chip selection function is sent to the multi-chip selection module.

[0095] The switch function is preconfigured with a first timeout, and when the switch function enable is enabled, the first timeout of the switch function is used to generate the reset position and release signals; the chip selection function is dynamically configured with a second timeout, and in different startup stages, the central processing unit assigns the chip selection function of the multi-chip selection module with a corresponding second timeout through the system control module, so that when the switch function enable is closed, the second timeout of the chip selection function is used to generate the reset position and release signals. Alternatively, the priority of the switch function is higher than that of the chip selection function, when the switch function and the chip selection function are both in the enabled state, the switch function is given priority, and when the switch function is disabled, the chip selection function is considered.

[0096] Alternatively, before step S10, the method further includes: pre-dividing a plurality of startup stages in the startup flow according to the instruction fetching operation. Alternatively, the plurality of startup stages includes: a BOOTROM stage, a UBOOT stage, and a KERNEL stage. Alternatively, the plurality of startup stages includes: a BOOTROM stage of fetching instructions directly from the flash memory and actively moving programs from the flash memory to the internal static memory; a UBOOT stage of verifying the moved programs; and a KERNEL stage of jumping to a new address to execute the moved programs.

[0097] Optionally, the embodiment sends different timeout thresholds to the multi-chip selection module by the system control module in different starting stages, such as a first timeout of 1s in the BOOTROM stage, a second timeout of 3s in the UBOOT stage, and a second timeout of 10s in the KERNEL stage. Further, when the instruction fetching operation in the BOOTROM stage does not run normally, i.e., after the instruction fetching operation fails, the new reset position setting and release signal transmitted by the multi-chip selection module is received, and a new instruction fetching operation is started. Optionally, the first timeout is preset to 1s or less to end the current starting process as soon as possible. If the instruction fetching operation in the BOOTROM stage is successfully completed, the instruction fetching operation enters the UBOOT stage. Further, the switching function is disabled by the system control module in the UBOOT stage (i.e., the switching function is disabled, and the first timeout cannot be used), and the second timeout corresponding to the UBOOT stage is sent to the multi-chip selection module by the system control module. Optionally, if the timeout occurs due to a failure in verification or other exceptions in the UBOOT stage, the reset position setting and release signal transmitted by the multi-chip selection module is received to end the current starting process. If the instruction fetching operation in the UBOOT stage is successfully executed, the instruction fetching operation enters the KERNEL stage. Further, the second timeout corresponding to the KERNEL stage is sent to the multi-chip selection module by the system control module in the KERNEL stage. Optionally, if the timeout occurs due to an error in program execution or other exceptions in the KERNEL stage, the reset position setting and release signal transmitted by the multi-chip selection module is received to end the current starting process.

[0098] Optionally, in any starting stage, when the central processor no longer needs the reset position setting and release signal generated by the multi-chip selection module, a stop command is sent to the multi-chip selection module by the system control module to control the multi-chip selection module to stop timing and stop working.

[0099] Optionally, all non-volatile memories need to be pre-solidified bin files, and the address arrangement in the storage space is shown in FIG. 8. Figure 3 Optionally, all non-volatile memories need to be pre-solidified bin files, and the address arrangement in the storage space is shown in FIG. 8.

[0100] Optionally, in the embodiment, the enable state of the switching function and the chip select function, the timeout threshold of the switching function and the chip select function are set in advance for each start stage. Optionally, in the BOOTROM stage, the switching function is enabled, and when the instruction fetch operation does not run normally after the timeout threshold, the reset and release signals transmitted by the multiple chip select module are received, and the timeout threshold of the next start stage (the UBOOT stage or the KERNEL stage) is sent to the multiple chip select module through the system control module, and the switching function is disabled. In the embodiment, the BOOTROM stage is taken as the initial start stage, and the UBOOT stage and the KERNEL stage are taken as the non-initial start stage. In actual application, more start stages can be subdivided.

[0101] In one embodiment, reference is made to the accompanying drawings Figure 4 Fig. 1 shows a flowchart of the instruction fetch operation of the multiple start stages of the central processor.

[0102] S101, the reset and release signals are received, the XIP module is controlled to start the instruction fetch operation, and the BOOTROM stage is entered. Optionally, the XIP module performs the instruction fetch operation on the non-volatile memory after reading the chip select data of the multiple chip select module; when the reset and release signals come from the outside, the chip select data of the multiple chip select module is initialized through the system control module; the switching function of the multiple chip select module is enabled through the system control module, so that the first timeout of the switching function is obtained, and the multiple chip select module generates new reset and release signals based on the first timeout.

[0103] S102, it is judged whether the instruction fetch operation of the BOOTROM stage runs normally, if yes, the switching function of the multiple chip select module is disabled through the system control module, and the second timeout of the next start stage (the UBOOT stage) is sent to the multiple chip select module through the system control module, and the UBOOT stage is entered; if not, the new reset and release signals generated by the multiple chip select module are received after the first timeout, so as to control the XIP module to fetch instructions again.

[0104] S103, it is judged whether the instruction fetch operation of the UBOOT stage runs normally, if yes, the second timeout of the next start stage (the KERNEL stage) is sent to the multiple chip select module through the system control module, and the KERNEL stage is entered; if not, the new reset and release signals generated by the multiple chip select module are received after the second timeout, so as to control the XIP module to fetch instructions again.

[0105] S104, judging whether the instruction fetching operation in the KERNEL stage is running normally, if yes, sending a stop command to the multi-chip selection module through the system control module, if not, receiving the new generated reset and release signals of the multi-chip selection module after the second timeout occurs, to control the XIP module to fetch instructions again. Alternatively, when the preset timeout condition is exceeded, the system control module reads the abnormal state of the multi-chip selection module, so that the central processing unit triggers a reminder to the implementer for debugging and checking according to the abnormal state.

[0106] In an embodiment, in the UBOOT stage, the second timeout of the chip selection function is set to 3 seconds, in the KERNEL stage, the second timeout of the chip selection function is set to 10 seconds, when the instruction fetching operation in the BOOTROM stage is completed, the switching function is disabled, and based on the next start stage being the UBOOT stage, the second timeout is configured to be 3 seconds; when the instruction fetching operation in the UBOOT stage is executed normally, the second timeout configured to be 3 seconds is updated to 10 seconds in the KERNEL stage, and then the multi-chip selection instruction fetching operation is executed based on the second timeout of 10 seconds.

[0107] Alternatively, when the reset and release signals come from the outside, the multi-chip selection module receives the externally triggered reset and release signals and feeds back to the system control module; the system control module controls the global reset according to the reset signal, so that the external reset, the multi-chip selection module reset, the system control module itself reset, the SOC bus reset, the central processing unit reset and the XIP module reset are released; the central processing unit controls the XIP module to start the instruction fetching operation based on the global reset triggered by the system control module.

[0108] The starting control method is applied to a central processor, and in response to receiving the reset and release signals, the XIP module starts the instruction fetching operation; the starting stage is determined according to the instruction fetching operation, and the system control module sends the timeout threshold corresponding to the starting stage to the multi-chip selection module; when the starting stage does not run normally, the reset and release signals generated by the multi-chip selection module based on the timeout threshold are received, and the XIP module is controlled to fetch instructions again based on the reset and release signals until all the starting stages run normally and the starting is completed. It can support the multi-chip selection module to access the non-volatile memory based on the XIP module to complete the starting process, reduce the probability of starting failure of the existing non-volatile memory due to damage, and through the multi-chip selection design, each piece of non-volatile memory will be reasonably traversed and configured as much as possible to ensure that the non-volatile memory can read data, so as to implement flexible and efficient XIP starting. The central processor is connected with the system control module and the XIP module, the XIP module is connected with the multi-chip selection module, the system control module is connected with the multi-chip selection module, the efficient and simple communication interaction between the central processor and the hardware is supported, the switching function of the multi-chip selection module is configured to be disabled / enabled in different starting stages, and the chip selection threshold of the switching function and the chip selection function is configured, to prevent unexpected central processor problems in each starting stage, such as hanging, running, and the like. The multi-chip selection module automatically generates the reset and release signals based on the timeout of the instruction fetching operation caused by the abnormal instruction fetching operation. The central processor quickly ends the current failed starting process and reenters a new starting process to start fetching instructions again according to the reset and release signals generated by the multi-chip selection module. The multi-chip selection module cooperates with the XIP module to access the non-volatile memory to perform the instruction fetching operation, thereby improving the XIP starting success rate, adapting to reading of different types of non-volatile memories, avoiding the risk of system hanging caused by abnormal central processor in each starting stage, and thereby improving the reliability of the entire system starting.

[0109] Third embodiment

[0110] In one embodiment, as shown in Figure 5 A starting control method is provided, and the multi-chip selection module in Figure 1 is taken as an example to illustrate the method. The multi-chip selection module is connected with the system control module and the XIP module, the system control module is connected with the central processor, and the XIP module is connected with the central processor.

[0111] S21, in response to triggering the reset and release signals, re-timing to obtain timing data, and obtaining a timeout threshold;

[0112] S22, when the timing data is greater than the timeout threshold, configuring the next instruction fetch operation chip select data in a preset order, and generating a new reset and release signal to feed back to the central processor through the system control module, so that the central processor controls the XIP module to fetch instructions again until the instruction fetch operation is completed.

[0113] Optionally, when the reset and release signal comes from the outside, the step S21 further comprises: resetting the chip select data to initialize the chip select data.

[0114] Optionally, the timeout threshold in step S21 comprises a first timeout and a second timeout; and the step of obtaining the timeout threshold in step S21 comprises:

[0115] based on the system control module enabling the switching function enable in the multi-chip select module to obtain the first timeout pre-configured by the switching function;

[0116] based on the system control module closing the switching function enable in the multi-chip select module, and receiving the second timeout sent by the central processor through the system control module.

[0117] Optionally, after the multi-chip select module generates the reset and release signal, the timeout threshold automatically returns to the first timeout.

[0118] Optionally, the timing data in step S21 is the data after the counter counting operation. The embodiment is used to measure the mechanism to be triggered. The timing data is compared with the timeout threshold to reserve a time of up to the timeout threshold for the instruction fetch operation. When the instruction fetch operation does not run normally within the timeout threshold, it indicates that the instruction fetch fails, and the chip select data required for the next instruction fetch operation is configured for the XIP module to read, and a new reset and release signal is generated to feed back to the central processor through the system control module after the reset management. Optionally, the central processor controls the XIP module to fetch instructions from zero after receiving the reset and release signal each time.

[0119] Optionally, the step S22 involves the switching function and the chip select function. The switching function in the multi-chip select module is pre-configured with the first timeout. After the multi-chip select module generates the reset and release signal, the timeout threshold returns to the first timeout. When the instruction fetch operation of the XIP module is not successful, and the timing data reaches the first timeout, the multi-chip select module generates a new reset and release signal, and determines the chip select data for the next instruction fetch operation. Further, the chip select value and / or configuration value in the chip select data for the next instruction fetch operation are modified in sequence by traversing the multi-chip select module.

[0120] Further, the priority of the switching function is higher than that of the chip select function. When the switching function is enabled, the chip select data is configured by using the switching function. When the switching function is disabled, the chip select data is configured by using the chip select function. The switching function of the multi-chip select module includes a plurality of chip select values, and each chip select value includes a plurality of configuration values. Alternatively, the chip select data of the multi-chip select module includes {chip select_0 configuration_0, chip select_0 configuration_1, chip select_0 configuration_2, chip select_1 configuration_0, chip select_1 configuration_1, chip select_1 configuration_2, chip select_2 configuration_0, chip select_2 configuration_1, chip select_2 configuration_2}. When the multi-chip select module is traversed, the configured chip select data is sent to the XIP module from chip select_0 configuration_0 to chip select_2 configuration_2, so that the XIP module performs the instruction fetching operation according to the chip select data.

[0121] The second timeout configured by the central processing unit for the chip select function. When the instruction fetching operation of the XIP module is not successful and the timing data reaches the second timeout, the multi-chip select module generates new reset and release signals and determines the chip select data for the next instruction fetching operation. Further, when the multi-chip select module is traversed, the chip select value of the chip select data for the next instruction fetching operation is modified in sequence. Alternatively, the chip select data of the multi-chip select module includes {chip select_0 configuration_0, chip select_0 configuration_1, chip select_0 configuration_2, chip select_1 configuration_0, chip select_1 configuration_1, chip select_1 configuration_2, chip select_2 configuration_0, chip select_2 configuration_1, chip select_2 configuration_2}. When the multi-chip select module is traversed, the chip select value is modified from chip select_0 configuration_0 to chip select_2 configuration_0, and the configured chip select data is read by the XIP module, so that the XIP module performs the instruction fetching operation on the non-volatile memory according to the chip select data.

[0122] The second timeout configured by the central processing unit for the chip select function. When the instruction fetching operation of the XIP module is not successful and the timing data reaches the second timeout, the multi-chip select module generates new reset and release signals and determines the chip select data for the next instruction fetching operation. Further, when the multi-chip select module is traversed, the chip select value of the chip select data for the next instruction fetching operation is modified in sequence. Alternatively, the chip select data of the multi-chip select module includes {chip select_0 configuration_0, chip select_0 configuration_1, chip select_0 configuration_2, chip select_1 configuration_0, chip select_1 configuration_1, chip select_1 configuration_2, chip select_2 configuration_0, chip select_2 configuration_1, chip select_2 configuration_2}. When the multi-chip select module is traversed, the chip select value is modified from chip select_0 configuration_0 to chip select_2 configuration_0, and the configured chip select data is read by the XIP module, so that the XIP module performs the instruction fetching operation on the non-volatile memory according to the chip select data.

[0123] Alternatively, in step S22, when the timing data is greater than the timeout threshold, the chip select data for the next instruction fetching operation is configured in a preset sequence, including:

[0124] S221, determining whether the switching function is enabled. If the switching function is enabled, the timing data is compared with the first timeout. When the timing data is greater than the first timeout, the chip select data for the next instruction fetching operation is configured in the chip select and configuration sequence.

[0125] S222, if the switching function is disabled, the timing data is compared with the second timeout. When the timing data is greater than the second timeout, the chip select data for the next instruction fetching operation is configured in the chip select sequence.

[0126] Alternatively, in step S221, the step of configuring the chip select data for the next instruction fetching operation in the preset sequence includes:

[0127] determining the chip select data for the current instruction fetching operation;

[0128] determining a configuration value and / or a chip select value of the chip select data for the next fetch operation when the toggle function is enabled and the timing data is greater than a first timeout;

[0129] or, determining a chip select value of the chip select data required for the next fetch operation when the toggle function is disabled and the timing data is greater than a second timeout.

[0130] wherein, when the reset and release signal comes from outside, the chip select data for the fetch operation is initial chip select data, such as chip select 0_configuration 0.

[0131] wherein, the step of determining the configuration value and / or the chip select value of the chip select data for the next fetch operation comprises:

[0132] judging whether the chip select data is the last configuration value of the current chip select, if yes, judging whether the chip select data is the last chip select value, if yes, reading the abnormal state of the multi-chip select module through the system control module, if the chip select data is not the last configuration value of the current chip select, determining the configuration value of the next chip select and triggering a new reset and release signal, if the chip select data is not the last chip select value, determining the chip select value of the next chip select and triggering a new reset and release signal.

[0133] Optionally, refer to the accompanying drawings Figure 6 for a schematic diagram of the operation flow of the multi-chip select module.

[0134] S41, generating a new reset and release signal, clearing the count, re-counting, and obtaining timing data; wherein, when the reset and release signal for the fetch operation comes from outside, initializing the chip select data;

[0135] S42, judging whether the toggle function is enabled, if yes, turning to S43, if not, turning to S44;

[0136] S43, waiting for the timing data to reach a first timeout, and then turning to S45;

[0137] S44, waiting for the timing data to reach a second timeout, and then turning to S46;

[0138] S45, judging whether the chip select data is the last configuration value of the current chip select, if yes, turning to S46, if not, turning to S48;

[0139] S46, judging whether the chip select data is the last chip select value, if yes, turning to S47, if not, turning to S49;

[0140] S47, controlling the multi-chip select module to stop abnormally;

[0141] S48, determine the next chip select configuration value, and go to S41;

[0142] S49, determine the next chip select value, and go to S41.

[0143] Optionally, for the central processor, each time the reset and release signal is received, it is a new starting point, and the fetch operation will be executed from zero. When the central processor receives the reset and release signal from the outside, the fetch operation is started through the XIP module, and the chip select data is initialized by the system control module to control the multi-chip select module, so that the XIP module reads the initial chip select data to start the fetch operation. Optionally, the initial chip select data is the first configuration of the first chip select, and when the reset and release signal comes from the outside, the chip select data is initialized by the system control module to control the multi-chip select module. The initial chip select data is chip select 0_configuration 0. When the reset and release signal comes from the inside, that is, the fetch operation fails to cause a timeout, at this time the multi-chip select module generates a new reset and release signal due to the timeout and feeds back to the central processor, and configures the chip select data for the next fetch operation for the XIP module to read.

[0144] Optionally, when the switching function is enabled, when the timing data exceeds the first timeout, the multi-chip select module generates a new reset and release signal to the central processor, and the central processor receives the reset and release signal generated by the multi-chip select module to execute the fetch operation from zero. For example, when configuring the chip select data for the next fetch operation, if the current chip select data (assuming that the chip select data includes: chip select (0, 1, 2)_configuration (0, 1, 2)) is the last configuration of the current chip select, then the next chip select (for example, the next chip select of chip select 0_configuration 2 is chip select 1_configuration 0) will be switched, otherwise the next configuration (for example, the next configuration of chip select 1_configuration 0 is chip select 1_configuration 1) will be switched.

[0145] Optionally, when the switching function is disabled, when the timing data exceeds the second timeout, the multi-chip select module generates a reset and release signal to the central processor, and the central processor executes the fetch operation from zero according to the reset and release signal generated by the multi-chip select module. For example, assuming that the current chip select data is the last chip select value, since there is no chip select value to select, a new reset and release signal will not be generated, otherwise the next chip select value will be determined.

[0146] Optionally, when the XIP module completes all the start stage of the instruction fetch operation, the central processor will send a stop command to the multi-chip select module through the system control module, the multi-chip select will stop counting in any case, and no new replacement position signal and release signal will be generated. When the multi-chip select module occurs a timeout condition when the chip select data is the last chip select value, the last configuration value, at this time, the counting will stop, and no replacement position signal and release signal will be generated, and the current state will be maintained, so that the central processor / system generates a corresponding reminder for the implementation personnel to debug and view.

[0147] Optionally, when the replacement position signal and the release signal come from the inside, that is, the replacement position signal and the release signal generated by the multi-chip select module, at this time, the timing data of the multi-chip select module reaches the timeout threshold; the system control module receives the replacement position signal and the release signal of the multi-chip select module, controls the preset global reset, so that the Soc bus, the multi-chip select module, the central processor and the XIP module enter the reset state according to the replacement position signal and the release signal; the multi-chip select module timing is cleared, and the timing is restarted; the central processor controls the XIP module to re-fetch the instruction.

[0148] In the above starting control method, the method is applied to the multi-chip select module, in response to the trigger reset and release signal, the timing data is obtained by re-timing, and the timeout threshold value transmitted by the central processing unit through the system control module is received; when the timing data is greater than the timeout threshold value, the chip select data of the next instruction fetching operation is configured in a preset order, and a new reset and release signal is generated to reset the management through the system control module, so that the central processing unit controls the XIP module to re-fetch instructions until the instruction fetching operation is completed. The XIP module can support the use of the multi-chip select module to access the non-volatile memory based on the XIP module to complete the starting process, reduce the probability of starting failure of the existing non-volatile memory due to damage, and through the multi-chip select design, each non-volatile memory will be reasonably and reasonably traversed and configured parameters to ensure that the non-volatile memory can read data, so as to implement flexible and efficient use of XIP starting. The central processing unit is connected with the system control module and the XIP module, the XIP module is connected with the multi-chip select module, the system control module is connected with the multi-chip select module, the efficient and simple communication interaction between the central processing unit and the hardware is supported, the switching function of the multi-chip select module is configured to be disabled / enabled in different starting stages, and the chip select threshold value of the switching function and the chip select function is configured, to prevent unexpected central processing unit problems in each starting stage, such as hanging, running, and the like. The multi-chip select module automatically generates the reset and release signal based on the non-normal instruction fetching operation caused by the instruction fetching timeout. The central processing unit quickly ends the current failed starting process and re-enters a new starting process to start instruction fetching again according to the reset and release signal generated by the multi-chip select module. The multi-chip select module cooperates with the XIP module to access the non-volatile memory to perform instruction fetching operation, thereby improving the XIP starting success rate, adapting to different types of non-volatile memory reading, avoiding the risk of system hanging caused by abnormal central processing unit in each starting stage, and improving the reliability of the entire system starting.

[0149] Fourth embodiment

[0150] In one embodiment, as shown in Figure 7 A starting control device is provided, comprising: a signal receiving module 110, a threshold sending module 120, and an instruction fetching control module 130, wherein:

[0151] The signal receiving module 110 is configured to control the XIP module to start instruction fetching operation in response to receiving the reset and release signal;

[0152] The threshold sending module 120 is configured to determine a starting stage according to the instruction fetching operation, and control the multi-chip select module to obtain a timeout threshold value corresponding to the starting stage through the system control module;

[0153] The fetch control module 130 is configured to fetch the reset and release signals generated by the chip select module based on the timeout threshold when the start-up phase does not run normally, so as to control the XIP module to re-fetch instructions based on the reset and release signals until all the start-up phases run normally.

[0154] The fifth embodiment

[0155] In one embodiment, as shown in Figure 8 A start-up control apparatus is provided, comprising a data acquisition module 210 and a chip select configuration module 220, wherein:

[0156] The data acquisition module 210 is configured to re-time to acquire timing data and acquire a timeout threshold in response to a trigger reset and release signal.

[0157] The chip select configuration module 220 is configured to configure chip select data of a next instruction fetching operation in a preset order and generate a new reset and release signal to reset management of the XIP module when the timing data is greater than the timeout threshold, so as to control the XIP module to re-fetch instructions by the central processing unit until the instruction fetching operation is completed.

[0158] The specific limitations of the start-up control apparatus can refer to the limitations of the start-up control method described above, which will not be repeated here. Each module in the above start-up control apparatus can be implemented by software, hardware, and combinations thereof, in whole or in part. Each module described above can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor invokes and executes the operations corresponding to each module.

[0159] In one embodiment, a computer device is provided, which can be a server, and an internal structure diagram thereof can be as shown in Figure 7 The computer device comprises a processor, a memory, a network interface, and a database connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the computer device is configured to store start-up control data. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement a start-up control method.

[0160] Those skilled in the art can understand, Figure 7The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0161] In one embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program:

[0162] In response to receiving the reset and release signal, the XIP module is controlled to start the instruction fetching operation; a start-up phase is determined according to the instruction fetching operation, and the system control module is used to control the plurality of chip select modules to obtain a timeout threshold corresponding to the start-up phase; when the start-up phase does not run normally, the reset and release signal generated by the plurality of chip select modules based on the timeout threshold is received, and the XIP module is controlled to fetch instructions again based on the reset and release signal until all the start-up phases run normally and the start-up is completed.

[0163] Alternatively, the processor implements the following steps when executing the computer program:

[0164] In response to triggering the reset and release signal, the timing data is obtained by re-timing, and the timeout threshold is obtained; when the timing data is greater than the timeout threshold, the chip select data of the next instruction fetching operation is configured in a preset order, and a new reset and release signal is generated to reset the management by the system control module, so that the central processing unit controls the XIP module to fetch instructions again until the instruction fetching operation is completed.

[0165] In one embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0166] In response to receiving the reset and release signal, the XIP module is controlled to start the instruction fetching operation; a start-up phase is determined according to the instruction fetching operation, and the system control module is used to control the plurality of chip select modules to obtain a timeout threshold corresponding to the start-up phase; when the start-up phase does not run normally, the reset and release signal generated by the plurality of chip select modules based on the timeout threshold is received, and the XIP module is controlled to fetch instructions again based on the reset and release signal until all the start-up phases run normally and the start-up is completed.

[0167] Alternatively, the computer program is executed by the processor to implement the following steps:

[0168] In response to the trigger reset and release signal, re-timing to obtain timing data, and obtaining a timeout threshold; when the timing data is greater than the timeout threshold, configuring the next read instruction operation with the chip select data in a preset order, and generating a new reset and release signal through the system control module reset management, so that the central processing unit controls the XIP module to re-read instructions until the read instruction operation is completed. Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments of each method. Any reference to memory, storage, databases, or other media in this application can include non-volatile and / or volatile storage. Non-volatile storage can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile storage can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0169] The technical features of the above embodiments can be combined in any way. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present disclosure.

[0170] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. A start-up control method applied to a central processing unit, wherein the central processing unit is connected with a system control module and an XIP module respectively, the XIP module is connected with a multi-chip selection module, the system control module is connected with the multi-chip selection module, and the XIP module is used to access a non-volatile memory to perform a fetch operation, characterized in that, The method comprises: S10: in response to a reception of a reset and release signal generated by an external start key operation, controlling the XIP module to start accessing the non-volatile memory to perform a fetch instruction operation; S20: determining a current start stage according to the fetch instruction operation, the start stage comprising a preset initial start stage and a non-initial start stage; and controlling the multi-chip select module to acquire a timeout threshold corresponding to the current start stage by the system control module, wherein when the current start stage is the initial start stage, the acquired timeout threshold is a first timeout, and when the current start stage is the non-initial start stage, the acquired timeout threshold is a second timeout; S30: when the start stage does not run normally, receiving a reset and release signal generated by the multi-chip select module based on the timeout threshold, and controlling the XIP module to re-access the non-volatile memory to perform a fetch instruction operation based on the reset and release signal until all the start stages run normally and the start is completed.

2. The method of claim 1, wherein, The step S20 comprises: when the start stage is a preset initial start stage, enabling a switch function enable in the multi-chip select module by the system control module to obtain the first timeout pre-configured by the switch function; when the start stage is a preset non-initial start stage, closing the switch function enable in the multi-chip select module by the system control module, and sending the second timeout corresponding to the chip select function to the multi-chip select module.

3. The method of claim 1, wherein, Before the step S20, the method comprises: pre-dividing a plurality of start stages in a start flow according to the fetch instruction operation, the plurality of start stages comprising a preset initial start stage and a non-initial start stage.

4. The method of claim 3, wherein, The plurality of start stages comprise: a BOOTROM stage of fetching an instruction directly from a flash memory and actively moving a program from the flash memory to an internal static memory; a UBOOT stage of verifying the moved program; a KERNEL stage of jumping to a new address to execute the moved program; wherein the BOOTROM stage is the initial start stage, and the UBOOT stage and the KERNEL stage are the non-initial start stages.

5. A starting control method applied to a multi-chip selection module, the multi-chip selection module being connected with a system control module and an XIP module, the system control module being connected with a central processing unit, the XIP module being connected with the central processing unit, the XIP module being used to access a non-volatile memory to perform a fetch operation, characterized in that, The method comprises: S21: in response to a reset and release signal generated by the multi-chip select module, re-timing to acquire timing data, and acquiring a timeout threshold, the timeout threshold comprising a first timeout for controlling a switch function to acquire chip select data and a second timeout for controlling a chip select function to acquire chip select data; S22, judging whether the switching function is enabled, if the switching function is enabled, comparing the timing data with the first timeout, when the timing data is greater than the first timeout, configuring the chip select data required for the next XIP module to access the non-volatile memory to perform the instruction fetching operation in the chip select and configuration sequence, generating new reset and release signals and resetting the management through the system control module; and / or, if the switching function is disabled, comparing the timing data with the second timeout, when the timing data is greater than the second timeout, configuring the chip select data required for the next XIP module to access the non-volatile memory to perform the instruction fetching operation in the chip select sequence, generating new reset and release signals and resetting the management through the system control module, so that the central processing unit controls the XIP module to re-access the non-volatile memory to perform the instruction fetching operation until the instruction fetching operation is completed.

6. The method of claim 5, wherein, The timeout threshold includes a first timeout and a second timeout. The step of obtaining the timeout threshold includes: enabling the switching function in the multi-chip select module based on the system control module, to obtain the first timeout pre-configured by the switching function; 7. The method of claim 5, wherein, disabling the switching function in the multi-chip select module based on the system control module, and receiving the second timeout sent by the central processing unit through the system control module. The step of configuring the chip select data required for the next XIP module to access the non-volatile memory to perform the instruction fetching operation in the chip select sequence or the configuration sequence includes: determining the chip select data of the current instruction fetching operation; when the switching function is enabled and the timing data is greater than the first timeout, determining the configuration value and / or the chip select value of the chip select data required for the next XIP module to access the non-volatile memory to perform the instruction fetching operation; 8. The method of claim 7, wherein, or, when the switching function is disabled and the timing data is greater than the second timeout, determining the chip select value of the chip select data required for the next XIP module to access the non-volatile memory to perform the instruction fetching operation. The step of determining the configuration value and / or the chip select value of the chip select data required for the next XIP module to access the non-volatile memory to perform the instruction fetching operation includes: judging whether the chip select data is the last configuration value of the current chip select, if yes, then judging whether the chip select data is the last chip select value, if yes, then reading the abnormal state of the multi-chip select module through the system control module; if the chip select data is not the last configuration value of the current chip select, then determining the configuration value of the next chip select and triggering new reset and release signals; 9. A starting control device applied to a central processing unit, the central processing unit being connected with a system control module and an XIP module respectively, the XIP module being connected with a multi-chip selection module, the system control module being connected with the multi-chip selection module, the XIP module being used to access a non-volatile memory to perform a fetch operation, characterized in that, if the chip select data is not the last chip select value, then determining the chip select value of the next chip select and triggering new reset and release signals. The device includes: a signal receiving module configured to generate reset and release signals in response to receiving an external start key operation, and control the XIP module to start accessing the non-volatile memory to perform the instruction fetching operation; The threshold sending module is configured to determine a current start stage according to the instruction fetching operation, the start stage including a preset initial start stage and a non-initial start stage; and control the multiple chip selection module to acquire a timeout threshold corresponding to the current start stage through the system control module, wherein when the current start stage is the initial start stage, the acquired timeout threshold is a first timeout, and when the current start stage is the non-initial start stage, the acquired timeout threshold is a second timeout. The instruction fetching control module is configured to acquire the reset and release signals generated by the multiple chip selection module based on the timeout threshold when the start stage does not run normally, so as to control the XIP module to re-access the non-volatile memory to perform the instruction fetching operation based on the reset and release signals until all the start stages run normally.

10. A start-up control device applied to a multi-chip selection module, the multi-chip selection module being connected with a system control module and an XIP module, the system control module being connected with a central processing unit, the XIP module being connected with the central processing unit, the XIP module being used to access a non-volatile memory to perform a fetch operation, characterized in that, The apparatus includes: The data acquisition module is configured to re-time to acquire timing data and acquire a timeout threshold in response to the reset and release signals generated by the multiple chip selection module, the timeout threshold including a first timeout for controlling the switching function to acquire the chip selection data and a second timeout for controlling the chip selection function to acquire the chip selection data. The chip selection configuration module is configured to determine whether a preset switching function is enabled, if the switching function is enabled, compare the timing data with the first timeout, and when the timing data is greater than the first timeout, configure chip selection data required for the XIP module to access the non-volatile memory to perform the instruction fetching operation in a next chip selection and configuration order, generate new reset and release signals, and reset the management through the system control module; and / or, if the switching function is disabled, compare the timing data with the second timeout, and when the timing data is greater than the second timeout, configure chip selection data required for the XIP module to access the non-volatile memory to perform the instruction fetching operation in a next chip selection order, generate new reset and release signals, and reset the management through the system control module, so that the central processing unit controls the XIP module to re-access the non-volatile memory to perform the instruction fetching operation until the instruction fetching operation is completed. 11.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-10. The processor executes the computer program to implement the steps of the method of any one of claims 1 to 8.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 8.

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