Template-driven test vector generation method

Abstract

The invention discloses a template-driven test vector generation method, which belongs to the technical field of integrated circuit testing and comprises the following steps: S1, acquiring a standard interface protocol of an integrated circuit to be processed; s2, based on a standard interface protocol, generating a standard interface test vector parameterization template; and S3, generating a comprehensive test vector by using the standard interface test vector parameterization template. According to the method, the generation of the test vector is more standard and consistent, the same design can be repeatedly used in different projects through parameterized design, only parameters need to be adjusted, and the repeatability of the test vector is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit testing, and particularly relates to a template-driven test vector generation method. Background Art

[0002] In the process of integrated circuit (IC) design and manufacturing, testing is an important link to ensure product quality and reliability. Traditional IC testing methods usually rely on manually writing test vectors, which are input signal sequences used to verify the circuit behavior. However, with the increase in IC complexity, this method becomes increasingly inefficient and error-prone. Manually written test vectors often require a large amount of time and labor costs, and when facing different types of ICs or different test requirements, these test vectors may need to be rewritten or substantially modified, which further increases the workload and may lead to more errors.

[0003] In addition, existing test vector generation methods lack flexibility and scalability, and it is difficult to quickly respond to changing requirements or adapt to new test scenarios. For specific hardware configurations, interface types, or protocols, test engineers must design test vectors from scratch, which not only takes time but also limits test efficiency and accuracy. At the same time, due to the lack of standardized and parameterized designs, the same or similar test tasks cannot be easily reused, resulting in waste of resources and insufficient technical accumulation. Summary of the Invention

[0004] In order to solve the above problems, the present invention proposes a template-driven test vector generation method.

[0005] The technical solution of the present invention is: a template-driven test vector generation method includes the following steps:

[0006] S1. Obtain the standard interface protocol of the integrated circuit to be processed;

[0007] S2. Generate a parameterized template for the standard interface test vector based on the standard interface protocol;

[0008] S3. Generate a comprehensive test vector using the parameterized template for the standard interface test vector.

[0009] Further, S2 includes the following sub-steps:

[0010] S21. Analyze the standard interface protocol;

[0011] S22. Generate a parameterized template for the standard interface test vector according to the analyzed standard interface protocol.

[0012] Further, in S21, the standard interface protocol includes protocol timing, data transfer format, and control signals.

[0013] Further, in S21, the analysis of the standard interface protocol specifically includes register reading and writing, state machine control, and interrupt handling.

[0014] Further, in S12, the standard interface test vector parameterization template includes a basic template module and a function module.

[0015] The basic template module is used to provide a standardized basic template;

[0016] The function module is used to process the basic template, decompose the function to be tested into several basic test vector sub-modules, and generate the standard interface test vector parameterization template.

[0017] Further, the basic template includes static objects, dynamic objects, and nested objects.

[0018] Further, the dynamic object is used to define the input sequence, expected output, clock, placeholder, and opcode as dynamic objects.

[0019] Further, the nested object is used to call the function module.

[0020] Further, the basic test vector module is specifically a register access sub-module, a state machine control sub-module, an interrupt handling sub-module, a parameterized configuration sub-module, and an interface adaptation sub-module;

[0021] The register access sub-module is used to generate test vectors for reading and writing registers;

[0022] The state machine control sub-module is used to generate test vectors for controlling the state transition of the state machine;

[0023] The interrupt handling sub-module is used to generate test vectors for triggering and handling interrupts;

[0024] The parameterized configuration sub-module is used to dynamically adjust the behavior of the basic template;

[0025] The interface adaptation sub-module is used to automatically adjust the data format and pin configuration.

[0026] The beneficial effects of the present invention are:

[0027] (1) The test vector template generation method proposed by the present invention covers common test scenarios, automatically generates test vectors by applying parametric design. This standardized template design makes the generation of test vectors more standardized and consistent. The parametric design enables the same design to be reused in different projects by simply adjusting the parameters, greatly improving the repeatability of test vectors;

[0028] (2) A test vector template generation method proposed by the present invention allows users to gradually add new functional modules or modify existing modules on the basis of existing templates without having to redesign the templates from scratch. This expansion mechanism makes the update and maintenance of templates simpler and more efficient, especially suitable for complex and changeable test environments. Description of the Drawings

[0029] Figure 1 It is a flowchart of a template-driven test vector generation method. Detailed Embodiments

[0030] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0031] As Figure 1 shown, the present invention provides a template-driven test vector generation method, including the following steps:

[0032] S1. Obtain the standard interface protocol of the integrated circuit to be processed;

[0033] S2. Generate a standard interface test vector parameterized template based on the standard interface protocol;

[0034] S3. Generate a comprehensive test vector by using the standard interface test vector parameterized template.

[0035] The present invention parses and selects different templates for different test requirements, and users can automatically generate test vectors that meet specific requirements by adjusting specific parameters, including template design and parameterization design.

[0036] Template design is to design a standardized template framework that covers all common test scenarios and fault types and contains the metadata of test vectors. Input sequence: Define a series of input signals to drive the device under test (DUT) into a specific state; Expected output: Define the expected output signals to verify whether the behavior of the DUT meets the expectations; Clock: Define the clock selection for each row of test vectors; Placeholder: Reserve placeholders for each variable parameter, and specific values can be filled in through parameterization design later; Opcode: Define vector fields, repetition, loop, and stop executing vectors.

[0037] Parameterization design allows users to customize the parameters in the template according to specific test requirements. Users can adjust the clock cycle, input signal combination, test conditions, etc. according to the actual hardware configuration to generate test vectors that meet specific requirements.

[0038] Through templatized design, the present invention supports flexible expansion of templates and real-time modification of generated vectors, enabling automatic generation from templates to specific test vectors. Module expansion is achieved through modular design, which supports flexible expansion of templates. Users can, based on existing templates, test a specific function by adding or deleting certain test modules without having to redesign the entire template. The templates support a multi-level nested structure. Users can embed multiple sub-templates in a general template to test different functional modules. For example, when a large number of various protocols are needed to modify certain registers multiple times in a certain chip function, the multi-level nested structure of the template can be utilized to nest different protocol test vector generation sub-templates in the functional test template. The templates support an inheritance mechanism. Users can derive a test template dedicated to a certain chip from a general test template, inheriting most of the content of the original template and only modifying a small number of specific parameters or test steps.

[0039] The present invention develops an automated tool that supports automatic generation from templates to specific test vectors. Users only need to input necessary parameters, and the tool can automatically generate test vectors according to the template format and simultaneously generate an interface adapter. When testing different interface types, the interface adapter can automatically adjust data formats, pin configurations, etc., to ensure that the test vectors can be correctly transmitted to the DUT.

[0040] In an embodiment of the present invention, S2 includes the following sub-steps:

[0041] S21. Analyze the standard interface protocol;

[0042] S22. Generate a parameterized template for standard interface test vectors according to the analyzed standard interface protocol.

[0043] In an embodiment of the present invention, in S21, the standard interface protocol includes protocol timing, data transfer format, and control signals.

[0044] In an embodiment of the present invention, in S21, analyzing the standard interface protocol specifically includes register read / write, state machine control, and interrupt handling.

[0045] In an embodiment of the present invention, in S12, the parameterized template for standard interface test vectors includes a basic template module and a functional module.

[0046] The basic template module is used to provide a standardized basic template;

[0047] The functional module is used to process the basic template, decompose the function to be tested into several basic test vector sub-modules, and generate a parameterized template for standard interface test vectors.

[0048] In an embodiment of the present invention, the basic template includes static objects, dynamic objects, and nested objects.

[0049] In an embodiment of the present invention, a dynamic object is used to define an input sequence, an expected output, a clock, a placeholder, and an opcode as dynamic objects.

[0050] In an embodiment of the present invention, a nested object is used to call a functional module.

[0051] In an embodiment of the present invention, the basic test vector module is specifically a register access sub-module, a state machine control sub-module, an interrupt processing sub-module, a parameterized configuration sub-module, and an interface adaptation sub-module;

[0052] The register access sub-module is used to generate test vectors for reading and writing registers;

[0053] The state machine control sub-module is used to generate test vectors for controlling state transitions of the state machine;

[0054] The interrupt processing sub-module is used to generate test vectors for triggering and processing interrupts;

[0055] The parameterized configuration sub-module is used to dynamically adjust the behavior of the basic template;

[0056] The interface adaptation sub-module is used to automatically adjust the data format and pin configuration.

[0057] In an embodiment of the present invention, first, the requirements analysis is carried out to clarify the functions, performance indicators, and specific test scenarios to be tested; according to the manual, the interface protocol is identified to determine the standard interface information used by the DUT and the constraint information is collected, and the factors that may affect the generation of test vectors, such as hardware configuration, clock frequency, and communication mode, are understood.

[0058] Analyze the principle of the standard interface protocol, including the timing, data transmission format, and control signals of the protocol. The parsing of the protocol is achieved by carefully reading the official documents and test specifications, and understanding the behaviors of the physical layer, data link layer, and transport layer of the protocol, including timing requirements, signal definitions, and command formats, etc.

[0059] Define a general standard interface test vector parameterized template according to the principle. The template production process includes designing a standardized module framework and implementing parameterized design. Select and develop a powerful template engine to implement the standardized module framework and parameterized design. The engine allows defining static content and dynamic parameter placeholders. Through the template engine, specific test vectors can be automatically generated according to the parameters provided by the user at runtime; and a set of standard template tags are defined to describe different parts of the test vectors, such as input sequences, expected outputs, and clock definitions, etc. These tags can be referenced in the template file and replaced with specific values during the generation process to obtain a standardized basic template covering common operations of the standard protocol, such as register reading and writing, state machine control, and interrupt processing, etc.

[0060] The template should contain necessary parameter placeholders, such as register address, data value, clock frequency, and communication mode. The template engine is designed based on the parameterized template, and an automated integration tool is designed to automatically generate test vectors through configuration files or graphical user interfaces to define specific different input parameters. Select the test vector template to be used according to the test requirements, and enter specific parameters to generate test vectors for specific requirements. For the copy function test, determine its functional execution steps and select to embed multiple different sub-template modules to generate a complex function test vector template, and enter specific parameters according to the constraints to generate the test vector. Finally, export the generated test vector to a format that can be used by the automatic test equipment.

[0061] Different submodule templates are responsible for generating a certain type of specific test vector or processing a specific function, such as register access module, state machine control module and interrupt processing module. These standardized basic templates can be combined and expanded according to test requirements to meet complex test scenarios. Constraints are obtained by parsing the test specification, including specifying which pins are used for input, output or bidirectional communication, specifying which pins are used for input, output or bidirectional communication, strictly following the standards of the interface protocol used, and specifying the data transmission format to ensure that the test vectors comply with the syntax and test specifications.

[0062] The present invention designs a universal test vector template, covering common operations of standard protocols (such as register reading and writing, state machine control and interrupt processing, etc.). The template should contain necessary parameter placeholders (such as register address, data value, clock frequency and communication mode, etc.). When the template is parsed, the data in the XML definition file is needed to complete the conversion from dynamic object to source code. All tags in the template belong to dynamic objects or nested objects. Different tag functions are specified to realize parameterized generation of test vectors. The parameter name is directly followed by the tag to realize the parameter replacement function, or to realize nesting other template files in one template file.

[0063] Basic template module: Provides standardized basic templates, including commonly used standard interface test vector templates, defines the basic structure of all test vectors, including header files, input sequences, expected outputs, clock definitions, placeholders, and opcodes, etc.; supports multiple standard interface protocols, and provides default test vector templates for each protocol. Parameter placeholders are reserved for common test scenarios, and users can enter specific parameter values ​​through configuration files or GUI.

[0064] Functional module: decomposes the function to be tested into multiple independent basic test vector generation modules. By combining these modules, they are responsible for generating specific types of test vectors. At the same time, users can select multiple functional modules to generate comprehensive test vectors.

[0065] Specifically, it includes a register access sub-module: which is used to generate test vectors for reading and writing registers, and supports configuring parameters such as register addresses, data values, access modes, etc.

[0066] A state machine control sub-module: which is used to generate test vectors for controlling the state transition of the state machine, and supports configuring parameters such as the initial state, target state, trigger conditions, etc.

[0067] An interrupt handling sub-module: which is used to generate test vectors for triggering and handling interrupts, and supports configuring parameters such as interrupt sources, priorities, enable / disable, interrupt service routines, etc. For modules like this, users can write scripts or code according to actual test requirements to customize various functional modules.

[0068] A parameterized configuration sub-module: allows users to dynamically adjust the behavior of the template by setting parameters, modify variable parameters such as register addresses, data values, clock frequencies, communication modes, etc. through a format configuration file, and develop a user-friendly GUI that allows users to input parameters through forms on the interface to meet different test requirements.

[0069] An interface adaptation sub-module: supports multiple standard interfaces. Users can set specific parameters of the interface, such as baud rate, frame format, handshake signals, etc. through a configuration file or GUI. The interface adapter can automatically adjust data formats, pin configurations, etc. according to the parameters set by users to ensure that the test vectors can be used correctly. Establish a standardized template library, record history to generate template types, and users can select suitable templates from the template library to quickly generate test vectors.

[0070] The template library also supports users to customize templates, combine and call historical modules, and classify the modules, such as by interface type, functional module, test scenario, etc., to facilitate users to quickly find the required templates. Users can create and share personalized templates according to their own needs to further enrich the content of the template library.

[0071] Those of ordinary skill in the art will realize that the embodiments described herein are for helping readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations that do not depart from the essence of the present invention based on the technical revelations disclosed in the present invention, and these deformations and combinations are still within the protection scope of the present invention.

Claims

1. A template-driven test vector generation method, characterized in that: The following steps are involved: S1. Obtaining a standard interface protocol for the integrated circuit to be processed; S2. Generate a standard interface test vector parameterization template based on the standard interface protocol; S3. Generate comprehensive test vectors using standard interface test vector parameterization templates.

2. The template-driven test vector generation method according to claim 1, characterized in that: The S2 comprises the following sub-steps: S21. Analyze the standard interface protocol; S22. Generate a standard interface test vector parameterization template according to the analyzed standard interface protocol.

3. The template-driven test vector generation method according to claim 2, characterized in that: In S21, the standard interface protocol includes protocol timing, data transmission format and control signals.

4. The template-driven test vector generation method according to claim 2, characterized in that: In S21, the analysis of the standard interface protocol specifically includes register reading and writing, state machine control and interrupt processing.

5. The template-driven test vector generation method according to claim 2, characterized in that: In S12, the standard interface test vector parameterized template includes a basic template module and a functional module. The basic template module is used to provide a standardized basic template; The functional module is used to process the basic template, decompose the function to be tested into a number of basic test vector sub-modules, and generate a standard interface test vector parameterized template.

6. The template-driven test vector generation method according to claim 5, characterized in that: The basic template includes static objects, dynamic objects and nested objects.

7. The template-driven test vector generation method according to claim 6, characterized in that: The dynamic object is used to define input sequences, expected outputs, clocks, placeholders, and opcodes as dynamic objects.

8. The template-driven test vector generation method according to claim 6, characterized in that: The nested object is used to call the function module.

9. The template-driven test vector generation method according to claim 5, characterized in that: The basic test vector module specifically includes a register access submodule, a state machine control submodule, an interrupt processing submodule, a parameterized configuration submodule and an interface adaptation submodule; The register access submodule is used to generate test vectors for reading and writing registers; The state machine control submodule is used to generate a test vector for controlling the state transition of the state machine; The interrupt processing submodule is used to generate test vectors for triggering and processing interrupts; The parameterized configuration submodule is used to dynamically adjust the behavior of the basic template; The interface adapter module is used to automatically adjust the data format and pin configuration.

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