Chip management method and device and PCIE (Peripheral Component Interface Express) equipment

Abstract

The invention provides a chip management method and device and PCIE (Peripheral Component Interface Express) equipment. The chip management method provided by the invention is applied to PCIE (Peripheral Component Interface Express) equipment, and the PCIE equipment is connected with a plurality of chips through an smbus. The method comprises the steps that when it is determined that initialization is needed, a unique identifier UDID of each chip is acquired; acquiring the equipment identifier of each chip according to a pre-acquired mapping relationship between the equipment identifier and the UDID; an smbus identifier is distributed to each chip; and recording the corresponding relationship between the equipment identifier and the smbus identifier of each chip. According to the chip management method and device and the PCIE equipment provided by the invention, automatic distribution and management of the smbus identifiers can be realized.

Description

Technical Field

[0001] This application relates to the technical field of chip management, and in particular, to a chip management method, apparatus, and PCIE device. Background Art

[0002] In recent years, in order to expand the performance and functions of PCIE devices, multiple chips are often connected to PCIE devices to provide additional processing capabilities, storage capacities, graphics processing capabilities, etc. based on these chips. When multiple chips are connected to a PCIE device simultaneously, the chips need to be managed to enable communication between the PCIE device and the chips. Summary of the Invention

[0003] In view of this, this application provides a chip management method, apparatus, and PCIE device for managing multiple chips connected to a PCIE device to enable communication between the PCIE device and the chips.

[0004] Specifically, this application is implemented through the following technical solutions:

[0005] In a first aspect of this application, a chip management method is provided. The method is applied to a PCIE device, and the PCIE device is connected with multiple chips through an smbus bus; the method includes:

[0006] When it is determined that initialization is required, obtain the unique identifier UDID of each chip;

[0007] According to the pre-obtained mapping relationship between the device identifier and the UDID, obtain the device identifier of each chip;

[0008] Assign an smbus identifier to each chip;

[0009] Record the corresponding relationship between the device identifier and the smbus identifier of each chip.

[0010] In a second aspect of this application, a chip management apparatus is provided. The apparatus is applied to a PCIE device, and the PCIE device is connected with multiple chips through an smbus bus; the apparatus includes: an obtaining module, an assigning module, and a recording module; wherein,

[0011] The obtaining module is configured to obtain the unique identifier UDID of each chip when it is determined that initialization is required;

[0012] The obtaining module is further configured to obtain the device identifier of each chip according to the pre-obtained mapping relationship between the device identifier and the UDID;

[0013] The assigning module is configured to assign an smbus identifier to each chip;

[0014] The recording module is configured to record the correspondence between the device identifier and the SMBus identifier of each of the chips.

[0015] A third aspect of the present application provides a PCIe device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of any of the methods provided in the first aspect of the present application are implemented.

[0016] A fourth aspect of the present application provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of any of the methods provided in the first aspect of the present application are implemented.

[0017] The chip management method, device, and PCIe device provided in the present application, when it is determined that initialization is required, obtain the unique identifier UDID of each chip, and obtain the device identifier of each chip according to the mapping relationship between the device identifier and the UDID obtained in advance, and then allocate an SMBus identifier to each chip, so as to record the correspondence between the device identifier and the SMBus identifier of each chip. In this way, an SMBus identifier management method is provided. Through this method, not only can the automatic allocation and management of SMBus identifiers be realized, but also the correspondence between the device identifier and the SMBus identifier of each chip can be established to meet the requirement of determining the SMBus identifier based on the device identifier or determining the device identifier based on the SMBus identifier, and the intelligent management of chips can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flowchart of the first embodiment of the chip management method provided in the present application;

[0019] Figure 2 It is a schematic structural diagram of a PCIe device shown in an exemplary embodiment of the present application;

[0020] Figure 3 It is a flowchart of the second embodiment of the chip management method provided in the present application;

[0021] Figure 4 It is a flowchart of the third embodiment of the chip management method provided in the present application;

[0022] Figure 5 It is a flowchart of the fourth embodiment of the chip management method provided in the present application;

[0023] Figure 6 It is a working principle diagram of a hot plug thread shown in an exemplary embodiment of the present application;

[0024] Figure 7A hardware structure diagram of the PCIE device where the chip management device provided by this application is located;

[0025] Figure 8 A schematic structural diagram of the first embodiment of the chip management device provided by this application. Detailed implementation manners

[0026] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0027] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms "a", "the", and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0028] It should be understood that although terms such as first, second, and third may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0029] This application provides a chip management method, device, and PCIE device for managing multiple chips connected to the PCIE device to achieve communication between the PCIE device and the chips.

[0030] The chip management method, device, and PCIE device provided by this application, when it is determined that initialization is required, obtain the unique identifier UDID of each chip, and based on the pre-obtained mapping relationship between the device identifier and the UDID, obtain the device identifier of each chip, and then allocate an smbus identifier for each chip, thereby recording the correspondence between the device identifier and the smbus identifier of each chip. In this way, a method for managing smbus identifiers is provided. Through this method, not only can the automatic allocation and management of smbus identifiers be realized, but also the correspondence between the device identifier and the smbus identifier of each chip can be established to meet the need to determine the smbus identifier based on the device identifier or determine the device identifier based on the smbus identifier, and the intelligent management of chips can be realized.

[0031] Specific embodiments are given below to introduce the technical solutions of this application in detail.

[0032] Figure 1 For the flowchart of the first embodiment of the chip management method provided by this application, please refer to Figure 1 In this embodiment, the method is applied to a PCIE device, and the PCIE device is connected with multiple chips through an smbus bus; the method includes:

[0033] S101. When it is determined that initialization is required, obtain the unique identifier UDID of each chip.

[0034] The method provided by this application is realized through the cooperation of multiple processes, and the multiple processes use a global lock to avoid conflicts. Specifically, when each process executes the method provided by this application, it needs to obtain the global lock first, and then release the global lock after execution.

[0035] Specifically, Figure 2 For the structural schematic diagram of a PCIE device shown in an exemplary embodiment of this application. Please refer to Figure 2 In Figure 2 In the shown example, a high-speed serial computer expansion bus standard PCIE (Peripheral Component Interconnect Express, abbreviated as PCIE) device is connected with 4 chips through an smbus (System Management Bus, abbreviated as smbus) bus.

[0036] It should be noted that after the PCIE device completes initialization, it will store an initialization completion flag. In this step, it can be determined whether initialization is required by judging whether there is an initialization completion flag, that is, when there is no initialization completion flag, it is determined that initialization operations are required, and when there is an initialization completion flag, it is determined that initialization operations are not required.

[0037] Further, when it is determined that initialization operations need to be performed, UDID (Unique Device Identifier) acquisition requests are continuously sent via broadcast until no UDID returned by any chip is received within a preset duration, at which point the UDID acquisition requests stop being sent. It should be noted that the UDID acquisition requests are used to instruct each chip that receives the UDID acquisition requests to return its unique identifier, the UDID.

[0038] It should be noted that in a possible implementation manner of this application, before sending the UDID acquisition requests via broadcast, an ARP request may be sent first based on the ARP protocol to instruct each chip that receives the ARP request to respond to the ARP request; further, for each chip that responds to the ARP request, a reset command is sent to the chip to instruct the chip to reset to the initial state.

[0039] S102. Obtain the device identifier of each of the chips according to the pre-obtained mapping relationship between the device identifier and the UDID.

[0040] Specifically, the pre-obtained mapping relationship between the device identifier and the UDID records the mapping relationships between the device identifiers and the UDIDs of the respective chips connected to the PCIE device.

[0041] In specific implementation, for each chip, after obtaining the UDID of the chip, the device identifier corresponding to the UDID can be searched from the pre-obtained mapping relationship between the device identifier and the UDID, and the found device identifier is the device identifier of the chip.

[0042] S103. Assign an smbus identifier to each of the chips.

[0043] Specifically, the smbus identifier refers to the identifier of the chip on the smbus bus.

[0044] It should be noted that a smbus identifier library is maintained on the PCIE device. The smbus identifier library records multiple smbus identifiers and the status information of each smbus identifier. The status information of each smbus identifier is used to represent the allocation status of the smbus identifier, and the status information may include allocated and unallocated.

[0045] When specifically implemented, when allocating an SMBus identifier for a certain chip, an unallocated SMBus identifier can be extracted from the SMBus identifier library and allocated to the chip. Specifically, when extracting an unallocated SMBus identifier from the SMBus identifier library, an unallocated SMBus identifier can be randomly extracted, or an unallocated SMBus identifier can be extracted in sequence. In this embodiment, no limitation is imposed on this.

[0046] It should be noted that after allocating an SMBus identifier for a certain chip, the status information of the allocated SMBus identifier is updated to allocated to indicate that this SMBus identifier cannot be allocated to other chips anymore.

[0047] S104. Record the correspondence between the device identifier of each chip and the SMBus identifier.

[0048] When specifically implemented, for each chip, after allocating an SMBus identifier for the chip, the device identifier and the SMBus identifier of the chip can be recorded as a group of correspondence.

[0049] It should be noted that after recording the correspondence between the device identifier and the SMBus identifier of each chip, when it is necessary to know the SMBus identifier of the chip subsequently, based on this correspondence, the corresponding SMBus identifier can be found through the device identifier of the chip; correspondingly, when it is necessary to know the device identifier of the chip, similarly, based on this correspondence, the corresponding device identifier can be found through the SMBus identifier of the chip to realize the communication between the PCIE device and the chip.

[0050] The chip management method provided in this embodiment, when it is determined that initialization is required, by obtaining the unique identifier UDID of each chip and according to the mapping relationship between the device identifier and the UDID obtained in advance, obtaining the device identifier of each chip, and then allocating an SMBus identifier for each chip, thereby recording the correspondence between the device identifier and the SMBus identifier of each chip. In this way, an SMBus identifier management method is provided. Through this method, not only can the automatic allocation and management of the SMBus identifier be realized, but also the correspondence between the device identifier and the SMBus identifier of each chip can be established to meet the requirement of determining the SMBus identifier based on the device identifier or determining the device identifier based on the SMBus identifier, and the intelligent management of the chip can be realized.

[0051] Figure 3 For the flowchart of the second embodiment of the chip management method provided in this application, please refer to Figure 3 , the method provided in this embodiment, on the basis of the above embodiment, after detecting a hot plug event, the method further includes:

[0052] S301. Obtain the device identifier of the inserted chip corresponding to the hot insertion event from the hot insertion event.

[0053] Specifically, a hot insertion event refers to an event of dynamically inserting a new chip (for the convenience of description, this chip is denoted as the inserted chip) during the operation of a PCIE device. It should be noted that the kernel-mode driver detects the operation of the inserted chip, and when detecting the operation of the inserted chip, reports a hot insertion event. The reported hot insertion event usually carries the device identifier of the currently inserted chip. In this step, the device identifier of the inserted chip corresponding to the hot insertion event can be obtained from the hot insertion event. For example, in one embodiment, the device identifier of the inserted chip corresponding to the obtained hot insertion event is device identifier 1.

[0054] S302. Allocate an smbus identifier for the inserted chip.

[0055] Specifically, referring to the previous description, there is an smbus identifier library maintained on the PCIE device. The smbus identifier library records multiple smbus identifiers and the status information of each smbus identifier. The status information of each smbus identifier is used to characterize the allocation status of the smbus identifier, and the status information can include allocated and unallocated.

[0056] In specific implementation, when allocating an smbus identifier for the inserted chip, an unallocated smbus identifier can be extracted from the smbus identifier library and allocated to the inserted chip. Specifically, when extracting an unallocated smbus identifier from the smbus identifier library, an unallocated smbus identifier can be randomly extracted, or an unallocated smbus identifier can be extracted in sequence. In this embodiment, it is not limited thereto.

[0057] For example, in one embodiment, the smbus identifier allocated for the inserted chip is smbus identifier 1.

[0058] S303. Record the corresponding relationship between the device identifier of the inserted chip and the smbus identifier.

[0059] In specific implementation, for the inserted chip, record the device identifier and the smbus identifier of the inserted chip as a group of corresponding relationships.

[0060] Combined with the above example, in one embodiment, the recorded corresponding relationship between the device identifier and the smbus identifier of the inserted chip is: device identifier 1 corresponds to smbus identifier 1.

[0061] The chip expansion method provided in this embodiment, after detecting a hot plug event, obtains the device identifier of the inserted chip corresponding to the hot plug event from the hot plug event, assigns an SMBus identifier to the inserted chip, and then records the correspondence between the device identifier and the SMBus identifier of the inserted chip. In this way, when a hot plug event occurs, the correspondence between the device identifier and the SMBus identifier of the inserted chip can be established, realizing the allocation and management of SMBus identifiers in the hot plug scenario.

[0062] Figure 4 The flowchart of the third embodiment of the chip management method provided in this application is shown in Figure 4 On the basis of the above embodiment, the method provided in this embodiment further includes, after detecting a hot unplug event:

[0063] S401. Obtain the target device identifier of the unplugged chip corresponding to the hot unplug event from the hot unplug event.

[0064] Specifically, a hot unplug event refers to an event of dynamically unplugging an inserted chip (for convenience of description, this chip is denoted as the unplugged chip) during the operation of a PCIE device. It should be noted that the kernel-mode driver detects the operation of unplugging the inserted chip, and when detecting the operation of unplugging the inserted chip, reports a hot unplug event, and the reported hot unplug event usually carries the device identifier of the currently unplugged inserted chip. In this step, the device identifier of the inserted chip corresponding to the hot unplug event can be obtained from the hot unplug event. For example, the device identifier of the inserted chip corresponding to the obtained hot unplug event is device identifier 2.

[0065] S402. Mark the correspondence in the recorded correspondence between the device identifier and the SMBus identifier that matches the target device identifier as disconnected.

[0066] In specific implementation, according to the target device identifier, in the recorded correspondence between the device identifier and the SMBus identifier, find the correspondence where the target device identifier is located, and mark the found correspondence as disconnected to indicate that it has become invalid.

[0067] It should be noted that after marking the found correspondence as disconnected, the status information of the SMBus identifier corresponding to the target device identifier in the SMBus identifier library can be updated to unallocated to indicate that this SMBus identifier can be re-allocated to a chip.

[0068] For example, in combination with the above example, if the currently unplugged inserted chip is the chip indicated by device identifier 2, at this time, the corresponding relationship where device identifier 2 is located is found: device identifier 2 corresponds to smbus identifier 2. In this step, this corresponding relationship is marked as disconnected. Further, the status information of smbus identifier 2 in the smbus identifier library is updated to unallocated.

[0069] The chip management method provided in this embodiment, after detecting a hot unplug event, obtains the target device identifier of the unplugged chip corresponding to the hot unplug event from the hot unplug event, and marks the corresponding relationship that matches the target device identifier in the recorded corresponding relationship between the device identifier and the smbus identifier as disconnected. In this way, the management of the smbus identifier in the hot unplug scenario can be realized.

[0070] Figure 5 For the flowchart of the fourth embodiment of the chip management method provided by this application, please refer to Figure 5 Based on the above embodiment, the method provided in this embodiment further includes:

[0071] S501. When creating a user-mode process, create a hotplug thread under the user-mode process and register the hotplug thread into the hotplug linked list.

[0072] Figure 6 For the working principle diagram of the hotplug thread shown in an exemplary embodiment of this application. Please refer to Figure 6 Specifically, when a user creates a new user-mode process through a kernel-mode call or a system call in the user mode, a hotplug thread will be automatically created under the user-mode process, and the created hotplug thread will be registered into the kernel-mode hotplug linked list.

[0073] It should be noted that the hotplug thread is used to handle hotplug events.

[0074] S502. After successfully registering the hotplug thread into the hotplug linked list, control the hotplug thread to enter the blocked state so that the hotplug thread stops executing and waits for a hotplug event to occur.

[0075] Specifically, the hotplug thread entering the blocked state indicates that the hotplug thread stops executing, it will not process the hotplug event, and it is waiting for a plug / unplug event to occur.

[0076] S503. After detecting a hotplug event, wake up the target hotplug thread in the hotplug linked list so that the target hotplug thread processes the hotplug event; where the target hotplug thread is the hotplug thread with the earliest registration time in the hotplug linked list.

[0077] Specifically, referring to the previous description, the hot plug and play event includes a hot plug event and a hot unplug event. When specifically implemented, when a PCIE device detects a hot plug and play event, it will find the hot plug and play thread with the earliest registration time from the hot plug and play linked list, and then wake up the hot plug and play thread for processing, so that the hot plug and play thread processes the hot plug and play event.

[0078] It should be noted that when the target hot plug and play thread is awakened, the target hot plug and play thread enters the awakened state. When the target hot plug and play thread enters the awakened state, it will process the hot plug and play event.

[0079] For example, in one embodiment, referring to Figure 6 , after detecting a hot plug and play event, the hot plug thread 1 will be awakened to enable the hot plug and play thread 1 to process the hot plug and play event.

[0080] S504. When it is detected that the target user-mode process in the created user-mode processes exits, delete the hot plug and play thread under the target user-mode process from the hot plug and play linked list; wherein, the target user-mode process is any one of the created user-mode processes.

[0081] For example, in one embodiment, in combination with Figure 6 , when it is detected that the user-mode process 1 exits, the hot plug and play thread 1 under the user-mode process 1 is deleted from the hot plug and play linked list. At this time, if a hot plug and play event is detected again, the hot plug and play thread with the earliest registration time in the hot plug and play linked list (at this time, the hot plug and play thread with the earliest registration time is the hot plug and play thread 2) will be awakened to enable the hot plug and play thread to process the hot plug and play event.

[0082] In the chip management method provided in this embodiment, when creating a user-mode process, by creating a hot plug and play thread under the user-mode process, registering the hot plug and play thread in the hot plug and play linked list, and after successfully registering the hot plug and play thread in the hot plug and play linked list, controlling the hot plug and play thread to enter the blocked state, and then waking up the target hot plug and play thread in the hot plug and play linked list after detecting a hot plug and play event, so that the target hot plug and play thread processes the hot plug and play event, and when it is detected that the target user-mode process exits, deleting the hot plug and play thread under the target user-mode process from the hot plug and play linked list. In this way, multi-thread management is realized and the processing efficiency is improved. In addition, when a hot plug and play event is detected, the hot plug and play thread with the earliest registration time is allowed to process the hot plug and play event, avoiding conflicts among multiple hot plug and play threads.

[0083] Optionally, in a possible implementation of the present application, the PCIE device communicates with each of the chips through a specified protocol; the specified protocol supports handshaking, and the specified protocol instructs the PCIE device to be responsible for the judgment and decision-making of the service logic and instructs the chip to be responsible for parsing and / or processing data.

[0084] Specifically, the specified protocol is set according to actual needs and is not limited in this embodiment. Among them, the specified protocol instructs the PCIE device to be responsible for the judgment and decision-making of the service logic. It should be noted that the service logic refers to specific calculations or operations, which may involve processing special data, executing special algorithms, or performing a certain decision-making process. For example, in a possible implementation, the service logic may include the logic of writing data to the chip, the logic of reading data from the chip, the data processing logic, etc. This is not limited in this embodiment.

[0085] Optionally, the specified protocol stipulates that the data packet formats when the PCIE device and the chip communicate include a first format and a second format. Among them, the first format includes a service operation code, an offset of the data written to the cache of the chip, the total data length, and valid data; the second format includes a service operation code, an error code, the total data length, and the valid data corresponding to the offset of the data written to the cache of the chip in the first format.

[0086] Specifically, the data packet in the first format can be the data packet sent by the PCIE device to the chip. Further, the data packet in the second format can be the data packet replied by the chip to the PCIE device. For example, in an embodiment, the data packet in the first format is used to indicate obtaining data from the chip. Correspondingly, after receiving the data packet, the chip replies a data packet in the second format to the PCIE device, and this data packet carries the corresponding actual data.

[0087] Referring to the previous description, the service operation code is used to indicate the specific operation or processing method of the data. Each service operation code corresponds to a specific operation or function. For example, in an embodiment, a service operation code is used to indicate reading data from the chip. For another example, in another embodiment, another service operation code is used to indicate writing data to the chip.

[0088] The offset of the data written to the cache of the chip is used to indicate the offset position when writing data to the cache of the chip, that is, the storage position of the data in the cache, or the offset position when reading data from the cache of the chip, that is, from which position to start reading the data.

[0089] The total data length is used to indicate the total length of the data to be written or the data to be read; and the valid data refers to the actual valid data.

[0090] Further, the error code is used to indicate errors or abnormal conditions that occur during program execution or system operations.

[0091] Further, the valid data corresponding to the offset where the data in the first format is written into the cache of the chip refers to the actual valid data corresponding to the offset where the data is written into the cache of the chip, that is, the actual valid data read from the cache of the chip. It should be noted that the cache area of the chip is only 8 bytes. Therefore, the first format and the second format stipulate that the length of the data packet is 8 bytes, so that it can be ensured that there will be no cache overflow during each communication.

[0092] Specifically, the first format is defined as follows:

[0093]

[0094] Further, the second format is defined as follows:

[0095]

[0096] It should be noted that the length of the valid data is 4 bytes.

[0097] In specific implementation, referring to the first format and the second format described above, when the PCIE device reads variable-length data in the chip from each of the chips through a specified protocol, first, a read request data packet is formed based on the first format (for example, the read request data packet is used to represent a data read request), and the read request data packet is sent to the chip; correspondingly, after receiving the read request data packet, the chip returns a corresponding response data packet according to the indication of the read request data packet (specifically, the data format of the response data packet can be the second format).

[0098] It should be noted that when forming the read request data packet based on the first format, first fill in the service operation code in the first format, and then set the offset written into the cache of the chip. When forming the read request data packet for the first time, the offset written into the cache of the chip is set to 0.

[0099] Further, after receiving the response data packet, the PCIE device determines whether it needs to continue receiving data (it can be determined whether to continue receiving data based on the difference between the total length of the data in the response data packet and the offset written to the cache in the chip in the read request data packet. Specifically, when the above difference is greater than zero, it is determined that data needs to be continued to be received, otherwise it is determined that data does not need to be continued to be received). When it is determined that data does not need to be continued to be received, the valid data in the unsigned char data in the response data packet (the valid data refers to the data indicated by the difference between the total length of the data in the response data packet and the offset written to the cache in the chip in the request data packet. For example, if the difference is 1, the data corresponding to the first byte in the response data packet is the valid data) is copied into the PCIE device. Similarly, when it is determined that data needs to be continued to be received, all the data in the unsigned char data in the response data packet is copied into the PCIE device, and a read request data packet is continued to be formed based on the first format to continue reading data. It should be noted that subsequently, when forming a read request data packet based on the first format, the offset written to the cache in the chip is equal to the sum of the offset value written to the cache in the chip when the previous read request data packet was formed and 4. For example, when forming the read request data packet for the second time, the offset written to the cache in the chip is 4.

[0100] When specifically implemented, for example, when the PCIE device reads data from each chip through a specified protocol, since at most 4 bytes of data can be read each time, if 9 bytes of data need to be read, then 3 read request data packets need to be sent. Among them, the first 2 read request data packets are respectively used to read 4 bytes of data, and the 3rd read request data packet is used to read 1 byte of data. The read pointer (used to point to the current position to be read) of the expansion device can be controlled by the offset written to the cache in the chip in the read request data packet. When the 9th byte is read, referring to the previous description, the valid data can be determined through the difference between the total length of the response data packet and the offset written to the cache in the chip in the read request data packet. At this time, the valid data is the data corresponding to the first byte of the response data packet, and the data corresponding to the last 3 bytes of the response data packet is invalid data. In this way, variable-length data reading can be achieved.

[0101] In addition, referring to the first format and the second format described above, when the PCIE device writes variable-length data to each chip through a specified protocol, first, a write request data packet is formed based on the first format (for example, the write request data packet is used to represent a data write request), and the write request data packet is sent to the chip; correspondingly, after receiving the write request data packet, the chip writes the corresponding data into the cache according to the indication of the write request data packet.

[0102] It should be noted that when constructing a write request data packet based on the first format, first fill in the service operation code in the first format, and then set the offset written to the cache of the chip. When constructing the write request data packet for the first time, the offset written to the cache of the chip is set to 0.

[0103] Furthermore, after the PCIE device sends a write request data packet, it will further determine whether there is still data to be sent (in specific implementation, it can be judged whether there is still data to be sent according to the difference between the total length of the data in the write request data packet and the offset written to the cache of the chip in the read / write request data packet. Specifically, when the above difference is greater than zero, it is determined that there is still data to be sent, otherwise it is determined that there is no data to be sent). When it is judged that there is still data to be sent, a write request data packet is constructed again. It should be noted that when constructing the write request data packet again, the offset written to the cache of the chip is equal to the sum of the offset value written to the cache of the chip when constructing the write request data packet last time and 4. For example, when constructing the write request data packet for the second time, the offset written to the cache of the chip is 4.

[0104] It should be noted that when constructing a write request data packet, valid data needs to be filled. The valid data is 4 bytes. If the length of the valid data is less than 4 bytes, it is filled with zeros.

[0105] For example, in one instance, when the PCIE device writes variable-length data to the chip through a specified protocol with each chip, since at most 4 bytes of data can be written each time, if 9 bytes of data need to be written, then 3 write request data packets need to be sent. Among them, the first 2 write request data packets sent are used to write 4 bytes of data respectively, and the third write request data packet sent is used to write 1 byte of data. The write pointer of the chip (used to point to the current position to be written) can be controlled by controlling the offset written to the cache of the chip in the write request data packet. When writing the 9th byte, the remaining 3 bytes are filled with 0 to achieve variable-length transmission.

[0106] The method provided in this embodiment can enable the PCIE device and the chip to communicate based on the communication protocol by stipulating the communication protocol between the PCIE device and the chip, thereby meeting the requirement of variable-length transmission.

[0107] Corresponding to the foregoing embodiment of a chip management method, the present application also provides an embodiment of a chip management device.

[0108] Embodiments of the chip management device provided by this application can be applied to PCIE devices. The device embodiments can be implemented through software, or through hardware or a combination of software and hardware. Taking software implementation as an example, as a logically meaningful device, it is formed by the processor of the PCIE device where it is located reading the corresponding computer program instructions in the non-volatile memory into the memory for operation. From a hardware perspective, as Figure 7 shown, it is a hardware structure diagram of the PCIE device where the chip management device provided by this application is located. In addition to Figure 7 the processor, memory, network interface, and non-volatile memory shown, the PCIE device where the device is located in the embodiment usually includes other hardware according to the actual functions of the chip management device, which will not be elaborated here.

[0109] Figure 8 Please refer to Figure 8 for the structural schematic diagram of Embodiment 1 of the chip management device provided by this application. The device provided in this embodiment is applied to a PCIE device, and the PCIE device is connected with multiple chips through an SMBus bus; the device includes: an acquisition module 810, an allocation module 820, and a processing module 830; where,

[0110] The acquisition module 810 is used to obtain the unique identifier UDID of each chip when it is determined that initialization is required;

[0111] The acquisition module 810 is further used to obtain the device identifier of each chip according to the mapping relationship between the device identifier and the UDID obtained in advance;

[0112] The allocation module 820 is used to allocate an SMBus identifier to each chip;

[0113] The processing module 830 is used to record the corresponding relationship between the device identifier and the SMBus identifier of each chip.

[0114] Optionally, the acquisition module 810 is further used to obtain the device identifier of the inserted chip corresponding to the hot plug event from the hot plug event after detecting the hot plug event;

[0115] The allocation module 820 is further used to allocate an SMBus identifier to the inserted chip;

[0116] The processing module 830 is further used to record the corresponding relationship between the device identifier and the SMBus identifier of the inserted chip.

[0117] Optionally, the acquisition module 810 is further used to obtain the target device identifier of the removed chip corresponding to the hot unplug event from the hot unplug event after detecting the hot unplug event;

[0118] The processing module 830 is further configured to mark the correspondence relationship in the recorded correspondence relationship between the device identifier and the SMBus identifier that matches the target device identifier as disconnected.

[0119] Optionally, the processing module 830 is further configured to:

[0120] When creating a user-mode process, create a hotplug thread under the user-mode process and register the hotplug thread in the hotplug linked list;

[0121] After successfully registering the hotplug thread in the hotplug linked list, control the hotplug thread to enter a blocked state so that the hotplug thread stops execution and waits for a hotplug event to occur;

[0122] After detecting a hotplug event, wake up the target hotplug thread in the hotplug linked list so that the target hotplug thread processes the hotplug event; wherein, the target hotplug thread is the hotplug thread with the earliest registration time in the hotplug linked list.

[0123] Optionally, the processing module 830 is further configured to:

[0124] When detecting the exit of a target user-mode process in the created user-mode processes, delete the hotplug thread under the target user-mode process from the hotplug linked list; wherein, the target user-mode process is any one of the created user-mode processes;

[0125] After detecting a hotplug event again, wake up the earliest-registered alternative hotplug thread in the hotplug linked list so that the alternative hotplug thread processes the hotplug event.

[0126] Optionally, the PCIE device communicates with each chip through a specified protocol; the specified protocol supports handshaking, and the specified protocol instructs the PCIE device to be responsible for the judgment and decision-making of business logic and instructs the chip to be responsible for parsing and / or processing data.

[0127] Optionally, the specified protocol stipulates that the data packet formats when the PCIE device and the chip communicate include a first format and a second format, wherein the first format includes a service operation code, an offset of the data written to the cache of the chip, a total data length, and valid data; the second format includes a service operation code, an error code, a total data length, and valid data corresponding to the offset of the data written to the cache of the chip in the first format.

[0128] Please continue to refer to Figure 7, this application also provides a PCIE device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of any of the methods provided in the first aspect of this application.

[0129] Furthermore, this application also provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the steps of any of the methods provided in the first aspect of this application.

[0130] For the specific implementation process of the functions and roles of each unit in the above device, please refer to the implementation process of the corresponding steps in the above method, which will not be elaborated here.

[0131] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the partial descriptions of the method embodiments. The device embodiments described above are only illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this application. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0132] The above are only the preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included within the scope of protection of this application.

Claims

1. A chip management method, characterized in that, the method is applied to a PCIE device, and the PCIE device is connected with multiple chips through an smbus bus; the method includes: when it is determined that initialization is required, obtaining the unique identifier UDID of each chip; obtaining the device identifier of each chip according to the pre-obtained mapping relationship between the device identifier and the UDID; allocating an smbus identifier to each chip; recording the corresponding relationship between the device identifier and the smbus identifier of each chip.

2. The method according to claim 1, characterized in that, after detecting a hot plug event, the method further includes: obtaining the device identifier of the inserted chip corresponding to the hot plug event from the hot plug event; allocating an smbus identifier to the inserted chip; recording the corresponding relationship between the device identifier and the smbus identifier of the inserted chip.

3. The method according to claim 1, characterized in that, after detecting a hot unplug event, the method further includes: obtaining the target device identifier of the unplugged chip corresponding to the hot unplug event from the hot unplug event; marking the corresponding relationship that matches the target device identifier in the recorded corresponding relationship between the device identifier and the smbus identifier as disconnected.

4. The method according to claim 1, characterized in that, the method further includes: when creating a user space process, creating a hot plug and unplug thread under the user space process, and registering the hot plug and unplug thread into a hot plug and unplug linked list; after successfully registering the hot plug and unplug thread into the hot plug and unplug linked list, controlling the hot plug and unplug thread to enter a blocked state, so that the hot plug and unplug thread stops executing and waits for a hot plug and unplug event to occur; after detecting a hot plug and unplug event, waking up the target hot plug and unplug thread in the hot plug and unplug linked list, so that the target hot plug and unplug thread processes the hot plug and unplug event; wherein, the target hot plug and unplug thread is the hot plug and unplug thread with the earliest registration time in the hot plug and unplug linked list.

5. The method according to claim 4, characterized in that, the method further includes: when detecting the exit of a target user space process in the created user space process, deleting the hot plug and unplug thread under the target user space process from the hot plug and unplug linked list; wherein, the target user space process is any user space process in the created user space process; after detecting a hot plug and unplug event again, waking up the target hot plug and unplug thread with the earliest registration time in the hot plug and unplug linked list, so that the target hot plug and unplug thread processes the hot plug and unplug event.

6. The method according to any one of claims 1 to 5, characterized in that, the PCIE device communicates with each chip through a specified protocol; the specified protocol supports handshaking, and the specified protocol indicates that the PCIE device is responsible for the judgment and decision of business logic, and indicates that the chip is responsible for parsing and / or processing data.

7. The method according to claim 6, characterized in that, The specified protocol stipulates that the data packet formats when the PCIE device communicates with the chip include a first format and a second format. Among them, the first format includes a service operation code, an offset of the data written to the cache of the chip, a total data length, and valid data; the second format includes a service operation code, an error code, a total data length, and valid data corresponding to the offset of the data written to the cache of the chip in the first format.

8. A chip management device, characterized in that, the device is applied to a PCIE device, and the PCIE device is connected with a plurality of chips through an smbus bus; the device includes: an acquisition module, an allocation module, and a recording module; among them, the acquisition module is used to obtain the unique identifier UDID of each chip when it is determined that initialization is required; the acquisition module is further used to obtain the device identifier of each chip according to the mapping relationship between the device identifier and the UDID obtained in advance; the allocation module is used to allocate an smbus identifier to each chip; the recording module is used to record the corresponding relationship between the device identifier and the smbus identifier of each chip.

9. A PCIE device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, when the processor executes the program, the steps of the method according to any one of claims 1-7 are implemented.

10. A computer-readable storage medium, on which a computer program is stored, characterized in that, when the program is executed by the processor, the steps of the method according to any one of claims 1-7 are implemented.

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