A system and method for verifying a bifurcation property of a PCIe switch

Abstract

The application provides a PCIe Switch bifurcation characteristic verification system and method, and relates to the technical field of PCIe. The PCIe Switch bifurcation characteristic verification system comprises a DUT module, a first EP verification agent component, a second EP verification agent component, a first RC verification agent component, a second RC verification agent component, a first PHY verification agent component, a second PHY verification agent component and a configuration module. The configuration module is used for configuring the bifurcation mode of the uplink port and the downlink port and the behavior of each verification agent component. The first protocol comparator is used for verifying the bifurcation characteristics of the uplink port, and the second protocol comparator is used for synchronously verifying the bifurcation characteristics of the downlink port. The application has the advantages of accelerating the verification convergence speed and improving the verification rate.

Description

Technical Field

[0001] This application relates to the field of PCIe technology, and more specifically, to a system and method for verifying the fork characteristics of a PCIe switch. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) is widely used. A PCIe Switch is a hardware device that provides expansion or aggregation capabilities and allows more devices to be connected to a PCIe port, thereby expanding the system's connectivity.

[0003] PCIe device forking refers to the ability of a PCIe device to simultaneously connect to multiple different PCIe devices. A PCIe device physically has multiple serial channels, which can be bundled together according to rules to connect to another PCIe device, enabling low-cost expansion of the PCIe device. How these channels are bundled corresponds to the forking characteristic of the device. PCIe switches need to connect PCIe devices with various channel widths, therefore, the forking characteristic is one of the most important features of PCIe switches.

[0004] A typical PCIe switch has multiple uplink ports and multiple downlink ports. Uplink ports can connect to host devices such as CPUs, while downlink ports connect to end devices. PCIe switches often require branching for both uplink and downlink ports.

[0005] Most existing PCIe switches support multiple fork scenarios, allowing connection of multiple devices with different channel widths depending on the configuration. The complex fork configurations present significant challenges for PCIe switch chip verification.

[0006] Currently, common PCIe Switch fork verification typically involves independently verifying the fork characteristics of the uplink or downlink ports on the PCIe Switch. However, this requires setting up two separate verification environments, which is labor-intensive and resource-intensive. It also fails to adequately cover the system configuration, resulting in low verification efficiency. Summary of the Invention

[0007] The purpose of this application is to provide a PCIe Switch fork feature verification system and method to solve the problem of low PCIe Switch fork verification efficiency in the prior art.

[0008] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0009] On one hand, embodiments of this application provide a PCIe Switch fork feature verification system, the PCIe Switch fork feature verification system comprising:

[0010] The DUT module includes multiple uplink ports and multiple downlink ports;

[0011] The system comprises a first EP verification proxy component, a second EP verification proxy component, a first RC verification proxy component, a second RC verification proxy component, a first PHY verification proxy component, and a second PHY verification proxy component. The first EP verification proxy component and the first PHY verification proxy component are both connected to the uplink port, and the first RC verification proxy component is connected to the first PHY verification proxy component. The second RC verification proxy component and the second PHY verification proxy component are both connected to the downlink port, and the second EP verification proxy component is connected to the second PHY verification proxy component. The first EP verification proxy component and the second EP verification proxy component are both used to simulate a terminal device controller, the first RC verification proxy component and the second RC verification proxy component are both used to simulate a master device controller, and the first PHY verification proxy component and the second PHY verification proxy component are both used to simulate PCIe PHY behavior.

[0012] A configuration module is connected to the DUT module and each verification proxy component, and is used to configure the fork pattern of the uplink port and the downlink port and the behavior of each verification proxy component;

[0013] A first protocol comparator and a second protocol comparator are connected. The first protocol comparator is connected to the first EP verification proxy component and the first RC verification proxy component. The second protocol comparator is connected to the second EP verification proxy component and the second RC verification proxy component. The first protocol comparator is used to verify the fork characteristics of the uplink port, and the second protocol comparator is used to synchronously verify the fork characteristics of the downlink port.

[0014] Optionally, the first EP verification proxy component, the second EP verification proxy component, the first RC verification proxy component, the second RC verification proxy component, the first PHY verification proxy component, and the second PHY verification proxy component are all simulation models implemented in Verilog or System Verilog code.

[0015] Optionally, the DUT module includes multiple physical links, and the configuration module is used to configure the number of uplink ports and downlink ports to be tested in the DUT module, and to configure the number of physical links connected to each uplink port and downlink port to be tested, so as to configure the fork pattern of the uplink port and the downlink port.

[0016] Optionally, each of the uplink ports to be tested, together with the corresponding first RC verification proxy component, the first PHY verification proxy component, the first EP verification proxy component, and the first protocol comparator, forms a first test unit, and the multiple first test units are independent of each other;

[0017] Each of the downlink ports to be tested, together with the corresponding second RC verification proxy component, second PHY verification proxy component, second EP verification proxy component, and second protocol comparator, forms a second test unit, and the multiple second test units are independent of each other.

[0018] Optionally, when verifying the fork characteristics of the uplink port, the first EP verification proxy component and the first RC verification proxy component simultaneously send test signals;

[0019] When verifying the fork characteristics of the downlink port, the second EP verification proxy component and the second RC verification proxy component simultaneously send test signals.

[0020] Optionally, the DUT module provides multiple pipe bus interfaces and multiple serial interfaces. Each uplink port is connected to the first EP verification proxy component through the pipe bus interface and to the first PHY verification proxy component through the serial interface.

[0021] Each of the downlink ports is connected to the second RC authentication proxy component via the pipe bus interface and to the second PHY authentication proxy component via the serial interface.

[0022] Optionally, when verifying the fork characteristics of the PCIe Switch, the verification test points include low-power mode, clock reset, register access, PCIe enumeration process, configuration of each fork scenario, pipe interface data transmission and reception path, and high-speed serial data transmission and reception path.

[0023] On the other hand, this application also provides a method for verifying the fork characteristics of a PCIe Switch, applied to the aforementioned PCIe Switch fork characteristic verification system, the method comprising:

[0024] Test points are extracted based on the protocol parameters of the DUT module and the fork configuration of the PCIe Switch, wherein the test points include test objects under different modes;

[0025] Based on the test points, generate test sequences and test cases; wherein each test case covers one or more functional points, and all test cases cover all functional points;

[0026] Configure the fork structure of the DUT module and control the operation of each verification proxy component;

[0027] Based on the test sequence and test cases, incentives are generated and sent to each verification agent component;

[0028] The fork characteristics of the uplink and downlink ports are verified by using the response data generated by the first and second protocol comparators based on the stimulus.

[0029] Optionally, after the step of verifying the response data generated based on the stimulus using the first protocol comparator and the second protocol comparator, the method further includes:

[0030] Perform regression testing with coverage on all test cases and collect code coverage and functional coverage data.

[0031] Optionally, the step of verifying the response data generated based on the stimulus using the first protocol comparator and the second protocol comparator includes:

[0032] The response data is compared with the standard data. If the comparison fails, the configuration of each verification agent component is debugged, the wiring of the PCIe Switch is debugged, or the code is debugged until all response data and standard data are successfully compared.

[0033] Compared with the prior art, this application has the following advantages:

[0034] This application provides a PCIe Switch fork feature verification system and method. The PCIe Switch fork feature verification system includes:

[0035] The DUT module includes multiple uplink ports and multiple downlink ports;

[0036] The system comprises a first EP verification proxy component, a second EP verification proxy component, a first RC verification proxy component, a second RC verification proxy component, a first PHY verification proxy component, and a second PHY verification proxy component. The first EP verification proxy component and the first PHY verification proxy component are both connected to the uplink port, and the first RC verification proxy component is connected to the first PHY verification proxy component. The second RC verification proxy component and the second PHY verification proxy component are both connected to the downlink port, and the second EP verification proxy component is connected to the second PHY verification proxy component. The first EP verification proxy component and the second EP verification proxy component are used to simulate a terminal device controller, the first RC verification proxy component and the second RC verification proxy component are used to simulate a master device controller, and the first PHY verification proxy component and the second PHY verification proxy component are used to simulate PCIe. PHY behavior; configuration module, connected to the DUT module and each verification proxy component, and used to configure the fork pattern of the uplink and downlink ports and the behavior of each verification proxy component; a first protocol comparator and a second protocol comparator, the first protocol comparator being connected to the first EP verification proxy component and the first RC verification proxy component, and the second protocol comparator being connected to the second EP verification proxy component and the second RC verification proxy component; the first protocol comparator is used to verify the fork characteristics of the uplink port, and the second protocol comparator is used to synchronously verify the fork characteristics of the downlink port.

[0037] On the one hand, the PCIe Switch fork feature verification system provided in this application includes a first protocol comparator and a second protocol comparator. The test unit, composed of the first protocol comparator, the first EP verification proxy component, the first PHY verification proxy component, and the first RC verification proxy component, can verify the fork feature of the uplink port. Meanwhile, the test unit, composed of the second protocol comparator, the second EP verification proxy component, the second PHY verification proxy component, and the second RC verification proxy component, can simultaneously verify the fork feature of the downlink port. Therefore, in the entire verification system, fork feature verification of both the uplink and downlink ports is achieved simultaneously through a single verification environment, reducing manpower and resource consumption while improving verification efficiency. On the other hand, since both the first EP verification proxy component and the second EP verification proxy component are used to simulate the terminal device controller, both the first RC verification proxy component and the second RC verification proxy component are used to simulate the master control device controller, and both the first PHY verification proxy component and the second PHY verification proxy component are used to simulate PCIe PHY behavior, each verification proxy component is a virtual functional component that replaces the traditional physical controller. This reduces the system setup cost, accelerates the verification convergence speed, and thus improves the overall system verification efficiency.

[0038] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is an interactive schematic diagram of the PCIe Switch fork feature verification system provided in an embodiment of this application.

[0041] Figure 2 A schematic diagram of the first test unit provided in an embodiment of this application.

[0042] Figure 3 An exemplary flowchart of a PCIe Switch fork feature verification method provided in the application embodiment.

[0043] In the picture:

[0044] 110 - DUT module; 120 - First EP verification proxy component; 130 - Second EP verification proxy component; 140 - First RC verification proxy component; 150 - Second RC verification proxy component; 160 - First PHY verification proxy component; 170 - Second PHY verification proxy component; 180 - Configuration module; 190 - First protocol comparator; 200 - Second protocol comparator. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0047] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0048] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0049] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0050] As described in the background section, most PCIe switches currently support multiple forking scenarios, allowing connection of multiple devices with different channel widths depending on the configuration. Given the complex forking patterns, it is necessary to verify the forking characteristics of the PCIe switch chip.

[0051] A typical PCIe switch has multiple upstream ports and multiple downstream ports. Upstream ports connect to the CPU or other controlling devices (Root Complex, RC), while downstream ports connect to end-point devices (Endpoint, EP). PCIe switches often require forking of both upstream and downstream ports. Therefore, verifying the forking characteristics of a PCIe switch requires verifying the forking characteristics of both its upstream and downstream ports.

[0052] In existing technologies, there are generally two methods for verifying the fork characteristics of PCIe switch chips:

[0053] One approach involves verifying the fork characteristics of either the uplink or downlink ports of a PCIe switch independently. However, this requires setting up two separate verification environments: one for verifying the uplink port's fork characteristics and the other for verifying the downlink port's fork characteristics. Ultimately, this method is labor-intensive and resource-intensive, doesn't adequately cover system configurations, and has low verification efficiency.

[0054] Another approach is to perform verification at the SOC (System on Chip) level. This method is direct and effective, but it requires the entire PCIe switch to be used as a DUT (Device Under Test). Due to the large amount of code in the SOC, the simulation speed is low and defects are exposed late.

[0055] In view of this, in order to solve the above problems, this application provides a PCIe Switch fork feature verification system. By building a verification environment, the fork features of the uplink port and downlink port can be verified simultaneously, which shortens the simulation time and speeds up the verification convergence.

[0056] The following is an exemplary description of the PCIe Switch fork feature verification system provided in this application:

[0057] Please see Figure 1 As an optional implementation, the PCIe Switch fork feature verification system includes a DUT module 110, a first EP (endpoint) verification proxy component, a second EP verification proxy component 130, a first RC (root complex) verification proxy component, a second RC verification proxy component 150, a first PHY (Physical Layer) verification proxy component, a second PHY verification proxy component 170, a configuration module 180, a first protocol comparator 190, and a second protocol comparator 200.

[0058] The first EP verification proxy component 120 and the first PHY verification proxy component 160 are both connected to the uplink port, and the first RC verification proxy component 140 is connected to the first PHY verification proxy component 160; the second RC verification proxy component 150 and the second PHY verification proxy component 170 are both connected to the downlink port, and the second EP verification proxy component 130 is connected to the second PHY verification proxy component 170; the first EP verification proxy component 120 and the second EP verification proxy component 130 are both used to simulate the terminal device controller, the first RC verification proxy component 140 and the second RC verification proxy component 150 are both used to simulate the master device controller, and the first PHY verification proxy component 160 and the second PHY verification proxy component 170 are both used to simulate PCIe PHY behavior;

[0059] The configuration module 180 is connected to the DUT module 110 and each verification proxy component, and is used to configure the fork pattern of the uplink and downlink ports and the behavior of each verification proxy component.

[0060] The first protocol comparator 190 is connected to the first EP verification proxy component 120 and the first RC verification proxy component 140, and the second protocol comparator 200 is connected to the second EP verification proxy component 130 and the second RC verification proxy component 150. The first protocol comparator 190 is used to verify the fork characteristics of the uplink port, and the second protocol comparator 200 is used to synchronously verify the fork characteristics of the downlink port.

[0061] The DUT module 110 is implemented by the PCIe Switch digital chip under test, which includes multiple uplink ports and multiple downlink ports, and can provide multiple pipe bus interfaces and multiple serial interfaces, and includes a configuration interface. Each uplink port is connected to the first EP verification proxy component 120 through the pipe bus interface and to the first PHY verification proxy component 160 through the serial interface; each downlink port is connected to the second RC verification proxy component 150 through the pipe bus interface and to the second PHY verification proxy component 170 through the serial interface.

[0062] The pipe bus interface is the interface signal of the PCIe controller. As an internal signal of the DUT, the simulation environment can force the connection between the pipe interface and the verification component through forced assignment. The pipe bus interface is defined in the physical layer and is a unified interface between the MAC (Media Access Layer) and PCS (Physical Coding Sub-layer), aiming to provide a unified industry standard. The serial interface is a full-duplex extension interface commonly used for communication between electronic devices.

[0063] In the DUT module 110, the number of uplink ports and multiple downlink ports can be configured, and the link width and serial number of the pipe interface corresponding to the uplink and downlink ports can also be flexibly configured. That is, the fork feature described in this application refers to configuring the number of uplink and downlink ports running in the current PCIe Switch, as well as the link width and other information corresponding to the ports.

[0064] As one implementation, the first EP verification proxy component 120, the second EP verification proxy component 130, the first RC verification proxy component 140, the second RC verification proxy component 150, the first PHY verification proxy component 160, and the second PHY verification proxy component 170 are all simulation models implemented using Verilog or System Verilog code. Specifically, the first PHY verification proxy component 160 and the second PHY verification proxy component 170 simulate real PCIe PHY behavior, the first EP verification proxy component 120 and the second EP verification proxy component 130 simulate the terminal device controller of the pipe interface, and the first RC verification proxy component 140 and the second RC verification proxy component 150 simulate the master device controller of the pipe interface. The first EP verification proxy component 120, the second EP verification proxy component 130, the first RC verification proxy component 140, and the second RC verification proxy component 150 can all generate and send stimuli, communicating with the uplink or downlink ports inside the DUT module 110 through the pipe interface or serial interface. The main control device described in this application can be a CPU or other similar device; the terminal device described in this application can be a PCIe node device.

[0065] Understandably, since the first EP verification proxy component 120 and the second EP verification proxy component 130 are both used to simulate the terminal device controller, the first RC verification proxy component 140 and the second RC verification proxy component 150 are both used to simulate the master control device controller, and the first PHY verification proxy component 160 and the second PHY verification proxy component 170 are both used to simulate PCIe PHY behavior, each verification proxy component is a virtual functional component that replaces the traditional physical controller. This reduces the system setup cost, accelerates the verification convergence speed, and thus improves the overall system verification efficiency.

[0066] Furthermore, the uplink port is connected to the first EP verification proxy component 120 through the internal pipe interface of the DUT module 110, and externally connected to the first PHY verification proxy component 160 through the serial interface. The first PHY verification proxy component 160 is in turn connected to the first RC verification proxy component 140. At the same time, the first protocol comparator 190 is connected to the first EP verification proxy component 120 and the first RC verification proxy component 140 respectively, forming a basic test unit. Meanwhile, the downlink port is connected to the second RC verification proxy component 150 through the internal pipe interface of the DUT module 110, and externally connected to the second PHY verification proxy component 170 through the serial interface. The second PHY verification proxy component 170 is in turn connected to the second EP verification proxy component 130. At the same time, the second protocol comparator 200 is connected to the second EP verification proxy component 130 and the second RC verification proxy component 150 respectively, forming another basic test unit.

[0067] Understandably, the two basic test units, consisting of the first protocol comparator 190 and the second protocol comparator 200, can perform fork characteristic verification relatively independently. Specifically, the test unit composed of the first protocol comparator 190, the first EP verification proxy component 120, the first PHY verification proxy component 160, and the first RC verification proxy component 140 can verify the fork characteristic of the uplink port; while the test unit composed of the second protocol comparator 200, the second EP verification proxy component 130, the second PHY verification proxy component 170, and the second RC verification proxy component 150 can simultaneously verify the fork characteristic of the downlink port. Therefore, in the entire verification system, fork characteristic verification of both the uplink and downlink ports is achieved simultaneously through a single verification environment, reducing manpower and resource consumption while improving verification efficiency.

[0068] Furthermore, the DUT module 110 includes multiple physical links. The configuration module 180 is used to configure the number of uplink and downlink ports under test in the DUT module 110, and to configure the number of physical links connecting each uplink and downlink port under test, so as to configure the fork configuration of the uplink and downlink ports. Specifically, the configuration module 180 can configure various PCIe Switch fork configurations, that is, it can configure the number of uplink or downlink ports, the width of the pipe bus interface of each uplink or downlink port, and the number of differential pairs contained in a set of serial interfaces.

[0069] For example, please combine Figure 1For uplink ports, when there are 4 uplink ports and 16 physical links (i.e., 16 pairs of differential lines), the number of first EP verification proxy components 120, first PHY verification proxy components 160, and first RC verification proxy components 140 are also 4, and the number of uplink ports to be tested is three. For example, if the uplink ports are P1, P2, P3, and P4, the first EP verification proxy components 120 are EP1, EP2, EP3, and EP4, and the first RC verification proxy components 140 are RC1, RC2, RC3, and RC4. If the uplink ports to be tested are P1, P2, and P3, then uplink port P4 is in standby mode. At this time, when the allocated physical links are X8+2X4, P1 is connected to EP1 through 8 physical links and also connected to the corresponding first EP verification proxy component 120 through 8 physical links; P2 is connected to EP2 through 4 physical links and also connected to the corresponding first EP verification proxy component 120 through 4 physical links; P3 is connected to EP3 through 4 physical links and also connected to the corresponding first EP verification proxy component 120 through 4 physical links.

[0070] Of course, the number of uplink ports to be tested and the allocation of physical links can also be configured according to actual needs. For example, the number of uplink ports to be tested can be 4, and each uplink port to be tested has 4 physical links; or, the number of uplink ports to be tested can be 2, and each uplink port to be tested has 8 physical links; or, the number of uplink ports to be tested can be 1, and each uplink port to be tested has 16 physical links.

[0071] Furthermore, each uplink port under test, together with the corresponding first RC verification proxy component 140, first PHY verification proxy component 160, first EP verification proxy component 120, and first protocol comparator 190, forms a first test unit, and the multiple first test units are independent of each other; at the same time, each downlink port under test, together with the corresponding second RC verification proxy component 150, second PHY verification proxy component 170, second EP verification proxy component 130, and second protocol comparator 200, forms a second test unit, and the multiple second test units are independent of each other.

[0072] By verifying the independent test units consisting of the proxy component and the protocol comparator, each test unit can perform independent simulation tests, thereby achieving parallel testing and significantly improving the verification efficiency of fork characteristics.

[0073] The verification test points for the PCIe Switch's forking characteristics include low-power mode, clock reset, register access, PCIe enumeration process, configuration of various forking scenarios, pipe interface data transmission and reception paths, and high-speed serial data transmission and reception paths. Therefore, by setting up independent test units, different test units can perform different test point verifications, improving the flexibility of the entire PCIe Switch forking characteristic verification system.

[0074] For example, please see Figure 2 The uplink ports are P1, P2, P3, and P4, the first EP verification proxy component 120 is EP1, EP2, EP3, and EP4, the first RC verification proxy component 140 is RC1, RC2, RC3, and RC4, and the first PHY verification proxy component 160 is PHY1, PHY2, PHY3, and PHY4. During the verification process, P1, EP1, RC1, PHY1, and the first protocol comparator 190 form a first test unit, denoted as C1; P2, EP2, RC2, PHY2, and the first protocol comparator 190 form a first test unit, denoted as C2; P3, EP3, RC3, PHY3, and the first protocol comparator 190 form a first test unit, denoted as C3; and P4, EP4, RC4, PHY4, and the first protocol comparator 190 form a first test unit, denoted as C4. C1, C2, C3, and C4 can operate independently. For example, C1 can perform low-power mode testing, C2 can perform register access testing, C3 can perform PCIe enumeration process testing, and C4 can perform clock reset testing. Of course, the four first test units can also perform the same type of verification test point testing simultaneously. For example, C1, C2, C3, and C4 can all perform PCIe enumeration process testing, which is not limited here.

[0075] During testing, the EP verification proxy component and the RC verification proxy component need to send test signals synchronously. Specifically, when verifying the fork characteristics of the uplink port, the first EP verification proxy component 120 and the first RC verification proxy component 140 send test signals synchronously. The test signal sent by the first EP verification proxy component 120 is processed by the uplink port and then sent to the first PHY verification proxy component 160, which in turn sends it to the first RC verification proxy component 140. Simultaneously, the test signal sent by the first RC verification proxy component 140 is processed by the first PHY verification proxy component 160 and then sent to the uplink port. After processing by the uplink port, the processed signal is sent to the first EP verification proxy component 120. Similarly, when verifying the fork characteristics of the downlink port, the second EP verification proxy component 130 and the second RC verification proxy component 150 send test signals synchronously.

[0076] The first protocol comparator 190 and the second protocol comparator 200 detect the protocol behavior of the PCIe Switch by receiving stimuli from the verification agent components and responses from the uplink and downlink ports inside the DUT module 110. They compare the behavior with the standard protocol specifications to complete the automatic check of the PCIe protocol. If there is any non-compliant behavior, the corresponding error message will be printed. At the same time, the fork characteristic verification system of the entire PCIe Switch is debugged, such as debugging the configuration of each verification agent component, debugging environmental wiring problems or code problems, etc.

[0077] As can be seen, in the PCIe Switch fork feature verification system provided in this application, the verification of uplink ports and downlink ports is relatively independent. That is, each uplink port and downlink port connects to a relatively independent test unit, and the tests between each uplink port and each downlink port are independent, allowing the system to determine the start and end of the tests, thus breaking free from the unified control of general verification frameworks. Through flexible configuration, the fork features of both uplink and downlink ports can be configured simultaneously, and the simulation test cases run by each test unit can be different, resulting in more thorough verification of various fork scenarios. Furthermore, the verification environment uses a verification proxy component instead of a real PCIe controller, accelerating the verification convergence speed.

[0078] Based on the above implementation, this application also provides a method for verifying the fork characteristics of a PCIe Switch. Please refer to [link to relevant documentation]. Figure 3 The method includes:

[0079] S102, extract test points based on the protocol parameters of the DUT module and the fork pattern of the PCIe Switch. The test points include test objects in different modes.

[0080] S104, Generate test sequences and test cases based on test points; where each test case covers one or more functional points, and all test cases cover all functional points.

[0081] S106 configures the fork structure of the DUT module and controls the operation of each verification proxy component.

[0082] S108 generates stimuli based on the test sequence and test cases, and sends the stimuli to each verification agent component.

[0083] S110, the first protocol comparator and the second protocol comparator are used to verify the response data generated by the stimulus, so as to realize the fork characteristics of the uplink port and the downlink port.

[0084] The protocol parameters of the DUT module 110 include the PCIe protocol and the PCIe interface protocol. The fork form of the PCIe Switch includes the PCIe Switch fork specification and design scheme, which includes the number of uplink ports and downlink ports to be tested.

[0085] In this application, based on the fork form of the PCIe Switch, the test points extracted include: low power mode, clock reset, register access, PCIe enumeration process, configuration of each fork scenario, pipe interface data transmission and reception path, and high-speed serial data transmission and reception path.

[0086] After developing the test sequence and test cases, set up the verification environment, instantiate each verification proxy component, verify the top-level interface, and connect each verification proxy component with the DUT module 110.

[0087] The test sequence, developed alongside the test cases, is a library used to generate test stimuli. Different test sequences are constructed based on different verification functionalities to generate different stimuli for verifying the design under test (DUT). A test case is a basic test scenario used to simulate the response of DUT module 110 under specific states. Test cases are executed in the order required by the verification components, with each case covering one or more functionalities. All test cases must cover all PCIe Switch fork functionalities to achieve complete verification.

[0088] After completing the above configuration, the verification environment can be initialized. Based on different configuration types, the branching pattern of the DUT module 110 and the operation of each verification proxy component can be configured, i.e., the startup and shutdown of each verification proxy component can be controlled. The number of downstream ports, the actual pipe width and serial width of each upstream and downstream port, and the capabilities supported by each verification proxy component must be determined.

[0089] Then, stimuli are generated based on the test sequence and test cases, and sent to each verification proxy component. Specifically, the test cases drive the verification proxy component to complete PCIe enumeration and send PCIe data packet stimuli. The data packets are processed by the DUT module 110, and the peer-driven verification proxy component receives the stimuli and sends a response data packet. It should be noted that the peer mentioned in this application refers to the port opposite to the verification proxy component that sends the stimuli. For example, for the first EP verification proxy component 120, its peer is the first RC verification proxy component 140; for the second RC verification proxy component 150, its peer is the second EP verification proxy component 130.

[0090] Finally, the first protocol comparator 190 and the second protocol comparator are used to verify the fork characteristics of the uplink and downlink ports based on the response data generated by the stimulus. Specifically, the first protocol comparator 190 and the second protocol comparator debug each test case one by one to ensure that each test case truly covers the verification test points extracted in step one. Furthermore, the first protocol comparator 190 and the second protocol comparator mainly compare the response data with standard data. If the comparison fails, the configuration of each verification agent component, the wiring of the PCIe Switch, or the code is debugged until all response data and standard data pass the comparison.

[0091] Furthermore, in one implementation, after step S110, the method further includes:

[0092] S112 performs regression testing with coverage on all test cases and collects code coverage and functional coverage data.

[0093] In practice, all test cases can undergo coverage regression to collect code coverage and functional coverage data. Coverage analysis is then performed, and for uncovered points, test cases are added or modified to cover them. Code coverage refers to the percentage of lines of code actually executed during software testing, usually expressed as a percentage. It is calculated by tracking execution during testing using specialized tools. Common calculation standards include line coverage, function coverage, statement coverage, branch coverage, and condition coverage, primarily used to measure the execution performance of design code. Functional coverage, on the other hand, involves writing covergroups and coverpoints based on the verification plan to cover specific data, addresses, or other control signals. Its purpose is to ensure that the design behaves as expected in a real-world environment, uncovering potentially missed functionalities through manually defined coverage scenarios. By determining code and functional coverage and covering uncovered points, the overall performance of the PCIe Switch fork feature verification system can be improved.

[0094] In summary, this application provides a PCIe Switch fork characteristic verification system and method. The PCIe Switch fork characteristic verification system includes: a DUT module, which includes multiple uplink ports and multiple downlink ports; a first EP verification proxy component, a second EP verification proxy component, a first RC verification proxy component, a second RC verification proxy component, a first PHY verification proxy component, and a second PHY verification proxy component; the first EP verification proxy component and the first PHY verification proxy component are both connected to the uplink ports, and the first RC verification proxy component is connected to the first PHY verification proxy component; the second RC verification proxy component and the second PHY verification proxy component are both connected to the downlink ports, and the second EP verification proxy component is connected to the second PHY verification proxy component; the first EP verification proxy component and the second EP verification proxy component are both used to simulate a terminal device controller, the first RC verification proxy component and the second RC verification proxy component are both used to simulate a master device controller, and the first PHY verification proxy component and the second PHY verification proxy component are both used to simulate a PCIe Switch fork characteristic verification system. PHY behavior; configuration module, connected to the DUT module and each verification proxy component, and used to configure the fork pattern of the uplink and downlink ports and the behavior of each verification proxy component; a first protocol comparator and a second protocol comparator, the first protocol comparator being connected to the first EP verification proxy component and the first RC verification proxy component, and the second protocol comparator being connected to the second EP verification proxy component and the second RC verification proxy component; the first protocol comparator is used to verify the fork characteristics of the uplink port, and the second protocol comparator is used to synchronously verify the fork characteristics of the downlink port.

[0095] On the one hand, the PCIe Switch fork feature verification system provided in this application includes a first protocol comparator and a second protocol comparator. The test unit, composed of the first protocol comparator, the first EP verification proxy component, the first PHY verification proxy component, and the first RC verification proxy component, can verify the fork feature of the uplink port. Meanwhile, the test unit, composed of the second protocol comparator, the second EP verification proxy component, the second PHY verification proxy component, and the second RC verification proxy component, can simultaneously verify the fork feature of the downlink port. Therefore, in the entire verification system, fork feature verification of both the uplink and downlink ports is achieved simultaneously through a single verification environment, reducing manpower and resource consumption while improving verification efficiency. On the other hand, since both the first EP verification proxy component and the second EP verification proxy component are used to simulate the terminal device controller, both the first RC verification proxy component and the second RC verification proxy component are used to simulate the master control device controller, and both the first PHY verification proxy component and the second PHY verification proxy component are used to simulate PCIe PHY behavior, each verification proxy component is a virtual functional component that replaces the traditional physical controller. This reduces the system setup cost, accelerates the verification convergence speed, and thus improves the overall system verification efficiency.

[0096] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0097] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A fork characteristic verification system for a PCIe switch, characterized in that, The PCIe Switch fork feature verification system includes: The DUT module includes multiple uplink ports and multiple downlink ports; The system comprises a first EP verification proxy component, a second EP verification proxy component, a first RC verification proxy component, a second RC verification proxy component, a first PHY verification proxy component, and a second PHY verification proxy component. The first EP verification proxy component and the first PHY verification proxy component are both connected to the uplink port, and the first RC verification proxy component is connected to the first PHY verification proxy component. The second RC verification proxy component and the second PHY verification proxy component are both connected to the downlink port, and the second EP verification proxy component is connected to the second PHY verification proxy component. The first EP verification proxy component and the second EP verification proxy component are both used to simulate a terminal device controller, the first RC verification proxy component and the second RC verification proxy component are both used to simulate a master device controller, and the first PHY verification proxy component and the second PHY verification proxy component are both used to simulate PCIe PHY behavior. A configuration module is connected to the DUT module and each verification proxy component, and is used to configure the fork pattern of the uplink port and the downlink port and the behavior of each verification proxy component; A first protocol comparator and a second protocol comparator are connected. The first protocol comparator is connected to the first EP verification proxy component and the first RC verification proxy component. The second protocol comparator is connected to the second EP verification proxy component and the second RC verification proxy component. The first protocol comparator is used to verify the fork characteristics of the uplink port, and the second protocol comparator is used to synchronously verify the fork characteristics of the downlink port.

2. The PCIe Switch fork characteristic verification system as described in claim 1, characterized in that, The first EP verification proxy component, the second EP verification proxy component, the first RC verification proxy component, the second RC verification proxy component, the first PHY verification proxy component, and the second PHY verification proxy component are all simulation models implemented in Verilog or SystermVerilog code.

3. The PCIe Switch fork characteristic verification system as described in claim 1, characterized in that, The DUT module includes multiple physical links. The configuration module is used to configure the number of uplink ports and downlink ports to be tested in the DUT module, and to configure the number of physical links connected to each uplink port and downlink port to be tested, so as to configure the fork pattern of the uplink port and the downlink port.

4. The PCIe Switch fork characteristic verification system as described in claim 3, characterized in that, Each of the uplink ports under test, together with the corresponding first RC verification proxy component, first PHY verification proxy component, first EP verification proxy component, and first protocol comparator, forms a first test unit, and the multiple first test units are independent of each other; Each of the downlink ports to be tested, together with the corresponding second RC verification proxy component, second PHY verification proxy component, second EP verification proxy component, and second protocol comparator, forms a second test unit, and the multiple second test units are independent of each other.

5. The PCIe Switch fork characteristic verification system as described in claim 1, characterized in that, When verifying the fork characteristics of the uplink port, the first EP verification proxy component and the first RC verification proxy component simultaneously send test signals. When verifying the fork characteristics of the downlink port, the second EP verification proxy component and the second RC verification proxy component simultaneously send test signals.

6. The PCIe Switch fork characteristic verification system as described in claim 1, characterized in that, The DUT module provides multiple pipe bus interfaces and multiple serial interfaces. Each uplink port is connected to the first EP verification proxy component through the pipe bus interface and to the first PHY verification proxy component through the serial interface. Each of the downlink ports is connected to the second RC authentication proxy component via the pipe bus interface and to the second PHY authentication proxy component via the serial interface.

7. The PCIe Switch fork characteristic verification system as described in claim 1, characterized in that, When verifying the forking characteristics of the PCIeSwitch, the verification test points include low power mode, clock reset, register access, PCIe enumeration process, configuration of various forking scenarios, pipe interface data transmission and reception path, and high-speed serial data transmission and reception path.

8. A method for verifying the fork characteristics of a PCIe switch, characterized in that, The method, applied to a fork characteristic verification system for a PCIe Switch as described in any one of claims 1 to 7, comprises: Test points are extracted based on the protocol parameters of the DUT module and the fork configuration of the PCIe Switch, wherein the test points include test objects under different modes; Based on the test points, generate test sequences and test cases; wherein each test case covers one or more functional points, and all test cases cover all functional points; Configure the fork structure of the DUT module and control the operation of each verification proxy component; Based on the test sequence and test cases, incentives are generated and sent to each verification agent component; The fork characteristics of the uplink and downlink ports are verified by using the response data generated by the first and second protocol comparators based on the stimulus.

9. The method for verifying the fork characteristics of a PCIe Switch as described in claim 8, characterized in that, After the step of verifying the response data generated based on the stimulus using the first protocol comparator and the second protocol comparator, the method further includes: Perform regression testing with coverage on all test cases and collect code coverage and functional coverage data.

10. The method for verifying the fork characteristics of a PCIe Switch as described in claim 8, characterized in that, The step of verifying the response data generated by the stimulus using the first protocol comparator and the second protocol comparator includes: The response data is compared with the standard data. If the comparison fails, the configuration of each verification agent component is debugged, the wiring of the PCIe Switch is debugged, or the code is debugged until all response data and standard data are successfully compared.

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