Method and device for self-adapting to different types of clock chips

Abstract

The invention discloses a method and a device for self-adapting to different types of clock chips, and belongs to the technical field of servers. The method is executed by a CPLD, and the CPLD is connected with an upper chip through a first IIC bus and connected with a clock chip through a second IIC bus. Detecting a slave device address of the connected clock chip through a second IIC bus, and determining a clock type of the currently connected clock chip according to the slave device address and a pre-stored analysis mode of register contents corresponding to different types of clock chips; and according to the clock type of the connected clock chip and the analysis mode of the register content corresponding to the type, converting the register content of the clock chip into time information in a set format so as to respond to a clock request of an upper chip by utilizing the time information in the set format. In the invention, even if different types of clock chips are replaced, the CPLD can adaptively identify the clock type of the connected clock chip, and manual identification is not needed, so that the manual maintenance cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and particularly to a method and device for adapting to different types of clock chips. Background Art

[0002] Different types of Real - Time Clock (RTC) chips have different clock formats. Currently, servers do not have the function of identifying the clock format in the clock chip. If the clock chip in the server is replaced, the server cannot automatically identify the clock format of the RTC.

[0003] In the related art, it is necessary to manually adapt BMC, BIOS, and the operating system to ensure that the server can correctly identify the clock format after replacing the clock chip.

[0004] It can be seen that this method has a high manual maintenance cost, and there is an urgent need to provide a method for adapting to different types of clock chips. Summary of the Invention

[0005] The present invention provides a method and device for adapting to different types of clock chips, which can solve the problem of high manual maintenance cost in the related art. The technical solutions are as follows:

[0006] On the one hand, a method for adapting to different types of clock chips is provided. The method is executed by a CPLD. The CPLD is connected to an upper - layer chip through a first IIC bus and is connected to a clock chip through a second IIC bus. The method includes:

[0007] Detect the slave device address of the connected clock chip through the second IIC bus, and determine the clock type of the currently connected clock chip according to the slave device address and the parsing method of the register content corresponding to different types of clock chips stored in advance.

[0008] Convert the register content of the clock chip into time information in a set format according to the clock type of the connected clock chip and the parsing method of the register content corresponding to this type, so as to respond to the clock request of the upper - layer chip using the time information in the set format.

[0009] On the other hand, a device for adapting to different types of clock chips is provided. The device is located in the CPLD. The CPLD is connected to an upper - layer chip through a first IIC bus and is connected to a clock chip through a second IIC bus. The device includes:

[0010] A detection unit, configured to detect the slave device address of the connected clock chip through the second IIC bus, and determine the clock type of the currently connected clock chip according to the slave device address and the parsing method of the register content corresponding to different types of clock chips stored in advance.

[0011] A conversion unit, configured to convert the register content of a clock chip into time information in a set format according to the clock type of the connected clock chip and the parsing method corresponding to the register content of this type, so as to use the time information in the set format to respond to the clock request of the upper-layer chip.

[0012] On the other hand, a server is provided, which is characterized by including: an upper-layer chip, a clock chip, and a CPLD; the CPLD is connected to the upper-layer chip through a first IIC bus and connected to the clock chip through a second IIC bus; and the CPLD is configured to execute the steps of the method for adapting to different types of clock chips described above.

[0013] On the other hand, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method for adapting to different types of clock chips described above are implemented.

[0014] The technical solution provided by the present invention can at least bring the following beneficial effects:

[0015] As a connection bridge between the upper-layer chip and the clock chip, the CPLD detects the slave device address of the connected clock chip, and determines the clock type of the currently connected clock chip according to the slave device address and the parsing method corresponding to the register content of different types of clock chips stored in advance. After determining the clock type of the clock chip, the parsing method corresponding to the register content of this clock type is used to convert the register content of the clock chip into time information in a set format, and then the time information in the set format is used to respond to the clock request of the upper-layer chip. It can be seen that even if different types of clock chips are replaced in this solution, the CPLD can adaptively identify the clock type of the connected clock chip, and then provide time information in a fixed format for the upper-layer chip through time conversion, without manual identification, reducing the manual maintenance cost. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 is a flowchart of a method for adapting to different types of clock chips provided by an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of the connection between a CPLD, an upper-layer chip, and a clock chip provided by an embodiment of the present invention;

[0019] Figure 3 It is a structural diagram of a device for adapting to different types of clock chips provided by an embodiment of the present invention. Specific Embodiments

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] The clock types of clock chips produced by different manufacturers may be different, and the parsing rules for time parsing of different clock types are also different. After determining the type of the clock chip replaced in the server, manual adaptation is performed on upper-layer chips such as BMC and CPU (which may include BIOS and operating system). However, this increases the manual maintenance cost. If the server can adapt to different types of clock chips, the manual cost will be greatly reduced.

[0022] By analyzing current different types of clock chips, it can be known that the slave device addresses corresponding to different types of clock chips may be different. Coupled with the fact that the register contents corresponding to different types of clock chips are different, it is possible to consider using the slave device address and register contents together to implement the determination of the clock type. This determination process is implemented by CPLD to provide time information in a fixed format for upper-layer chips as an intermediate bridge.

[0023] The following describes the specific implementation manners of the above concepts.

[0024] A method for adapting to different types of clock chips provided by an embodiment of the present invention is executed by CPLD. CPLD is connected to an upper-layer chip through a first IIC bus and connected to a clock chip through a second IIC bus; please refer to Figure 1 and Figure 2 , Figure 1 is a flowchart of the method for adapting to different types of clock chips, Figure 2 is a schematic diagram of the connection between CPLD and an upper-layer chip and a clock chip; the method includes:

[0025] Step 100, detecting the slave device address of the connected clock chip through the second IIC bus, and determining the clock type of the currently connected clock chip according to the slave device address and the register contents corresponding to different types of clock chips stored in advance;

[0026] Step 102: According to the clock type of the connected clock chip and the parsing method of the register content corresponding to this type, convert the register content of the clock chip into time information in a set format, so as to use the time information in the set format to respond to the clock request of the upper-layer chip.

[0027] In the embodiment of the present invention, the CPLD serves as the connection bridge between the upper-layer chip and the clock chip. The CPLD detects the slave device address of the connected clock chip, and determines the clock type of the currently connected clock chip according to the slave device address and the parsing method of the register content corresponding to different types of clock chips stored in advance. After determining the clock type of the clock chip, use the parsing method of the register content corresponding to this clock type to convert the register content of the clock chip into time information in a set format, and then use the time information in the set format to respond to the clock request of the upper-layer chip. It can be seen that in this solution, even if different types of clock chips are replaced, the CPLD can adaptively identify the clock type of the connected clock chip, and then provide time information in a fixed format for the upper-layer chip through time conversion, without manual identification, reducing the manual maintenance cost.

[0028] The following describes Figure 1 The execution methods of the steps shown.

[0029] First, for step 100, detect the slave device address of the connected clock chip through the second IIC bus, and determine the clock type of the currently connected clock chip according to the slave device address and the parsing method of the register content corresponding to different types of clock chips stored in advance.

[0030] In the embodiment of the present invention, clock chips produced by different manufacturers may have specific different clock types, and the slave device addresses and the parsing methods of the register content of different types of clock chips are also different. When connecting the clock chip to the IIC bus, it needs to be connected according to the corresponding slave device address (IIC_Slaver) of the clock chip.

[0031] In order to be able to adapt to different types of clock chips and enable the clock chip to quickly identify and determine the clock type of the clock chip and the parsing method of the register content after the clock type is switched, the corresponding relationship between the slave device address and the clock type can be stored in advance.

[0032] It should be noted that for clock chips of the same clock type, the parsing method of their register content is the same.

[0033] After the server is powered on, the CPLD needs to determine the clock type of the currently connected clock chip to provide accurate time information for the upper-layer chip. The upper-layer chip can at least include a CPU and a BMC. In the CPU, at least the BIOS and the operating system need to obtain time information.

[0034] In the embodiments of the present invention, the clock type of the currently connected clock chip can be determined in the following manner: Based on the correspondence relationship between the slave device address and the clock type stored in advance, determine whether the slave device address corresponds to a single clock type; if so, determine the corresponding single clock type as the clock type of the currently connected clock chip; if not, determine the clock type of the currently connected clock chip according to the register content of each clock type corresponding to the slave device address.

[0035] Among them, in this correspondence relationship, a slave device address may correspond to one clock type or multiple clock types. When the CPLD detects that the slave device address of the currently connected clock chip corresponds to a single clock type, it can directly determine that this single clock type is the clock type of the currently connected clock chip. Otherwise, it is necessary to further confirm the clock type of this clock chip from the corresponding multiple clock types.

[0036] It can be understood that regardless of the type of clock chip, its register content at least includes the following time types: seconds, minutes, hours, week, day, month, year. The register content of some types of clock chips may also include the time type of time zone. For example, Beijing time is in the eighth time zone. Since the same register address of different types of clock chips may correspond to different time types, and for each clock type of clock chip, which time types correspond to each register address are known, therefore, the embodiments of the present invention can use the register content at the same register address to determine which time type this register address corresponds to, so as to determine which clock type the clock chip belongs to.

[0037] Specifically, determining the clock type of the currently connected clock chip according to the register content of each clock type corresponding to the slave device address at the same time may include:

[0038] Based on the parsing method of the register content in these multiple types, select the same register address with different time types;

[0039] Based on the set duration determined by the time type corresponding to this same register address;

[0040] Read the value from the same register address and read the value again after the set duration;

[0041] Determine the type of the clock chip based on the difference between the two read values.

[0042] After the server is powered on, the CPLD needs to determine the clock type of the clock chip to ensure that the upper-layer chip can use the clock information normally. Therefore, it is necessary to complete the determination of the clock type as soon as possible. In the embodiment of the present invention, when selecting the same register address with different time types, the same register address corresponds to at least one time type that is the address with the shortest time among the corresponding multiple time types.

[0043] For example, the slave device address corresponds to two clock types at the same time (such as type A and type B). Among the parsing methods of the register contents corresponding to the clock chips of the two clock types, type A has register addresses from 00H to 06H, and type B has register addresses from 03H to 09H. That is, for 03H, 04H, 05H, and 06H, they are the same register addresses of type A and type B. The time types corresponding to the addresses 03H, 04H, 05H, and 06H of type A are second, minute, hour, and week in sequence, and the time types corresponding to the addresses 03H, 04H, 05H, and 06H of type B are hour, week, day, and month in sequence. Then, when selecting the same register address with different time types, it is necessary to ensure that the selected same register address corresponds to at least one time type that is the address with the shortest time among the corresponding multiple time types (second, minute, hour, week, day, month). The time type with the shortest time among the multiple time types is second, so 03H is used as the same register address for selecting different time types. Since the 03H address of type A corresponds to the time type of second and the 03H address of type B corresponds to the time type of hour, when determining the set duration, it is necessary to ensure that the difference between the values read twice after the set duration can distinguish between second and hour. That is to say, the set duration is a value that can distinguish the different time types corresponding to the same register address.

[0044] The following takes the clock chips of three different clock types as an example to illustrate this step.

[0045] The first clock type is PCF8523. The slave device address of this type of clock chip is 0x68. For the parsing method of the corresponding register contents, please refer to Table 1 below:

[0046] Table 1 PCF8523 clock chip register parsing format:

[0047]

[0048] According to Table 1, its register addresses are from 03H to 09H, and the corresponding time types are second, minute, hour, day, week, month, and day in sequence, and there is a corresponding numerical range noted after each time type.

[0049] The second type of clock is DS3231. The slave device address of this type of clock chip is 0x68. For the parsing method of the corresponding register content, please refer to Table 2 below:

[0050] Table 2 DS3231 Clock Chip Register Parsing Format:

[0051]

[0052] According to Table 2, its register addresses are 00H - 06H, and they correspond to time types of seconds, minutes, hours, days, date, month, and year in sequence. And there is a corresponding numerical range noted after each time type.

[0053] The third type of clock is SD2068. The slave device address of this type of clock chip is 0x32. For the parsing method of the corresponding register content, please refer to Table 3 below:

[0054] Table 3 SD2068 Clock Chip Register Parsing Format:

[0055]

[0056] According to Table 3, its register addresses are 00H - 06H, and they correspond to time types of seconds, minutes, hours, week, date, month, and year in sequence. And there is a corresponding numerical range noted after each time type.

[0057] The parsing methods of the above three types of clocks, slave device addresses, and register contents are all pre - stored in the CPLD. The CPLD detects the slave device address of the connected clock chip through the second IIC bus:

[0058] If the slave device address is 0x32, then directly using the correspondence between the clock type and the slave device address, it can be determined that the clock type of the currently connected clock chip is SD2068. Different from PCF8523 and DS3231, the register addresses 14 - 1FH in its RTC chip are a custom storage area composed of 12 bytes, which can store time zone information for convenient compatibility design. Then, use the parsing method of the register content corresponding to this clock type to parse the register content;

[0059] If the slave device address is 0x68, according to the correspondence between the clock type and the slave device address, it can be determined that this slave device address corresponds to two clock types, namely PCF8523 and DS3231. Therefore, it is necessary to further determine which one of PCF8523 and DS3231 this clock chip is;

[0060] Specifically, based on the parsing method of the register content corresponding to the PCF8523 and DS3231 clock types, the same register address with different time types is selected, that is, it is selected from the addresses 03H to 06H. Among them, the time type corresponding to the 03H address in the PCF8523 clock type is seconds, which is the time type of the shortest time. Therefore, the 03H address is selected as the same register address with different time types. Then, the 03H register address of the PCF8523 clock type corresponds to the time type of seconds, and the 03H register address of the DS3231 clock type corresponds to the time type of days (day of the week). Next, the set duration needs to be determined. When determining the set duration, it is necessary to adhere to the principle that the shorter the time of the determined clock type, the better. If it is 1 second, there may be a situation where the day also jumps, such as from Monday to Tuesday. Therefore, the set duration is at least 2 seconds.

[0061] Taking the set duration of 5 seconds as an example for illustration, then, the value can be read from the 03H register address of the clock chip, and then after 5 seconds, the value is read again from the 03H register address, and the difference between the two read values is calculated. If the difference is within the range of [-6, 1], it is determined that the time type corresponding to the 03H register address is not seconds but days, and then it is determined that the clock type of the clock chip is DS3231; if the difference is greater than or equal to 3 or less than or equal to -50, then it can be determined that the time type corresponding to the 03H register address is seconds, and then it is determined that the clock type of the clock chip is PCF8523.

[0062] It should be noted that the timing between the two readings can be implemented through the internal timing of the CPLD.

[0063] Then, for step 102, according to the clock type of the connected clock chip and the parsing method of the register content corresponding to this type, the register content of the clock chip is converted into time information in a set format to respond to the clock request of the upper-layer chip using the time information in the set format.

[0064] After determining the clock type of the connected clock chip, the register content of the clock chip can be directly parsed using the parsing method of the register content corresponding to this clock type, and then the time information of the clock chip can be obtained.

[0065] In order to enable the upper-layer chip to still obtain time information even after replacing the clock chip with a different clock type, the CPLD can convert the register content of the clock chip into time information in a set format. This set format is a fixed format, which is already configured in the upper-layer chip, and the upper-layer chip can obtain accurate time information based on the parsing method of this set format.

[0066] In one embodiment, please refer to Table 4 below for the parsing method of the register content in the CPLD;

[0067] Table 4 CPLD register parsing format:

[0068]

[0069] According to Table 4, the register addresses in the CPLD are 00H to 09H, and the corresponding time types are seconds, minutes, hours, week, day, month, year, spare, spare, and time zone respectively. The upper-layer chip can parse the register content in the CPLD according to this parsing method.

[0070] In one embodiment of the present invention, in order to ensure the accuracy of the time information obtained by the upper-layer chip, whenever the register value in the clock chip changes, the CPLD immediately performs time conversion.

[0071] Furthermore, since the server can also set the time zone information, some types of clock chips have storage addresses for time zone information, and some types of clock chips do not have storage addresses for time zone information. In the embodiment of the present invention, the CPLD can provide the time zone information for the upper-layer chip. That is to say, the register address in the CPLD can correspond to the time type of the time zone, that is, the 09H address in Table 4.

[0072] Furthermore, the upper-layer chip can also set the time zone information. In a specific implementation, the CPLD is also connected to a flash memory through a second IIC bus; then, the CPLD can receive the time zone information sent by the upper-layer chip and store the time zone information in the flash memory, so as to complete the setting of the time zone information by the upper-layer chip.

[0073] Correspondingly, when the time zone information is stored in the flash memory or the time zone information in the flash memory is updated, the CPLD can also read the stored time zone information from the flash memory and write the time zone information to its corresponding register address. In this way, the upper-layer chip can directly obtain the time zone information according to the register content when obtaining the time information.

[0074] Please refer to Figure 3 , the embodiment of the present invention provides a device for adapting to different types of clock chips. The device is located in the CPLD. The CPLD is connected to the upper-layer chip through a first IIC bus and connected to the clock chip through a second IIC bus; the device includes:

[0075] A detection unit 300, configured to detect the slave device address of the connected clock chip through the second IIC bus, and determine the clock type of the currently connected clock chip according to the slave device address and the parsing method of the register content corresponding to different types of clock chips stored in advance;

[0076] A conversion unit 302, configured to convert the register content of a clock chip into time information in a set format according to the clock type of the connected clock chip and the parsing method corresponding to the register content of this type, so as to use the time information in the set format to respond to the clock request of the upper-layer chip.

[0077] In an embodiment of the present invention, when the detection unit executes determining the clock type of the currently connected clock chip according to the address and the parsing methods corresponding to the register contents of different types of clock chips stored in advance, it specifically includes:

[0078] Based on the correspondence between the slave device address and the clock type stored in advance, determine whether the slave device address corresponds to a single clock type; if so, determine the corresponding single clock type as the clock type of the currently connected clock chip; if not, determine the clock type of the currently connected clock chip according to the register contents of each clock type corresponding to the slave device address at the same time.

[0079] In an embodiment of the present invention, when the detection unit executes determining the type of the currently connected clock chip according to the register contents of each of the multiple types corresponding to the slave device address at the same time, it specifically includes:

[0080] Based on the parsing methods of the register contents of these multiple types, select the same register address with different time types; based on the set duration determined by the time type corresponding to this same register address; read the value from the same register address, and read the value again after the set duration; determine the type of the clock chip based on the difference between the two read values.

[0081] In an embodiment of the present invention, when selecting the same register address with different time types, this same register address corresponds to at least one time type that is the address with the shortest time among the multiple corresponding time types.

[0082] In an embodiment of the present invention, the CPLD is further connected to a flash memory through a second IIC bus; the device further includes:

[0083] A receiving unit, configured to receive the time zone information sent by the upper-layer chip and store the time zone information in the flash memory.

[0084] In an embodiment of the present invention, the conversion unit is further configured to read the stored time zone information from the flash memory and write the time zone information to its corresponding register address.

[0085] In an embodiment of the present invention, whenever the register value in the clock chip changes, the conversion unit immediately executes converting the register content of the clock chip into time information in a set format.

[0086] It should be noted that: For the device for adapting to different types of clock chips provided in the above embodiments, only the division of the above functional modules is used for illustration. In actual applications, the above functions can be allocated to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device for adapting to different types of clock chips provided in the above embodiments and the method embodiments for adapting to different types of clock chips belong to the same concept. For the specific implementation process, please refer to the method embodiments and will not be elaborated here.

[0087] An embodiment of the present application further provides a server, including: an upper-layer chip, a clock chip, and a CPLD; the CPLD is connected to the upper-layer chip through a first IIC bus and connected to the clock chip through a second IIC bus; and the CPLD is configured to execute the steps of the method for adapting to different types of clock chips described above.

[0088] An embodiment of the present application further provides a computer-readable storage medium, on which at least one instruction, at least one program segment, a code set, or an instruction set is stored. The at least one instruction, at least one program segment, the code set, or the instruction set is loaded and executed by a processor to implement the method for adapting to different types of clock chips provided in each of the above method embodiments.

[0089] An embodiment of the present application further provides a computer program product, which includes a computer program. The processor of the computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the steps of the method for adapting to different types of clock chips described in any one of the above embodiments.

[0090] For the convenience of description, when describing the above system or device, various modules or units are described separately according to functions. Of course, when implementing the present application, the functions of each unit can be implemented in one or more software and / or hardware.

[0091] From the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments of the present application.

[0092] Finally, it should also be noted that in this text, relational terms such as first, second, third, and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the said element.

[0093] The above are only the preferred embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A method for adaptively adapting to different types of clock chips, characterized in that: The method is performed by a CPLD, the CPLD is connected to an upper chip via a first IIC bus, and is connected to a clock chip via a second IIC bus; the method comprises: Detecting the slave device address of the connected clock chip through the second IIC bus, and determining the clock type of the currently connected clock chip according to the slave device address and the pre-stored parsing method of the register contents corresponding to the different types of clock chips; According to the clock type of the connected clock chip and the parsing method of the register content corresponding to the type, the register content of the clock chip is converted into time information in a set format, so as to respond to the clock request of the upper chip using the time information in the set format.

2. The method according to claim 1, characterized in that The method of determining the clock type of the currently connected clock chip according to the address and the pre-stored parsing method of the register contents corresponding to the different types of clock chips comprises: Based on the pre-stored correspondence between the slave device address and the clock type, determine whether the slave device address corresponds to a single clock type; if so, determine the corresponding single clock type as the clock type of the currently connected clock chip; if not, determine the clock type of the currently connected clock chip based on the register content of each clock type in the multiple clock types that the slave device address simultaneously corresponds to.

3. The method according to claim 2, characterized in that The method of determining the type of the currently connected clock chip according to the register content of each type of multiple types corresponding to the slave device address at the same time includes: Selecting the same register address with different time types based on the way the register contents in the multiple types are parsed; A set duration determined based on the time type corresponding to the same register address; Read the value from the same register address and read the value again after a set time. The type of clock chip is determined based on the difference in the two read values.

4. The method according to claim 3, characterized in that When selecting the same register address with different time types, the same register address corresponds to at least one time type which is the address with the shortest time among the corresponding multiple time types.

5. The method according to claim 1, characterized in that The CPLD is also connected to a flash memory via a second IIC bus; Also includes: Receive the time zone information sent by the upper chip, and store the time zone information in the flash memory.

6. The method according to claim 5, characterized in that Also includes: The stored time zone information is read from the flash memory, and the time zone information is written into the corresponding register address.

7. The method according to claim 1, characterized in that Whenever the register value in the clock chip changes, the process of converting the register content of the clock chip into time information in a set format is immediately executed.

8. A device that adapts to different types of clock chips, characterized in that: The device is located in the CPLD, the CPLD is connected to the upper chip through the first IIC bus, and is connected to the clock chip through the second IIC bus; the device includes: A detection unit, used to detect the slave device address of the connected clock chip through the second IIC bus, and determine the clock type of the currently connected clock chip according to the slave device address and the pre-stored parsing method of the register contents corresponding to the different types of clock chips; The conversion unit is used to convert the register content of the clock chip into time information of a set format according to the clock type of the connected clock chip and the parsing method of the register content corresponding to the type, so as to respond to the clock request of the upper chip using the time information of the set format.

9. A server, characterized in that: include: Upper chip, clock chip and CPLD; The CPLD is connected to the upper chip via the first IIC bus and is connected to the clock chip via the second IIC bus; And the CPLD is used to execute the steps of any one of the methods described in claims 1-7.

10. A computer program product, characterized in that The invention comprises a computer program, wherein when the computer program is executed by the CPLD, the steps of any method according to claim 1 to claim 7 are implemented.

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