Automatic layer allocation method for complex PCB topology pre-evaluation and optimization

Abstract

The invention discloses an automatic layer allocation method for complex PCB topology pre-evaluation and optimization, and the method comprises the steps: splitting a multi-end wire net into a two-end wire net, and dividing wiring resources into an escape region and a channel region based on the boundary of a device; constructing a minimum spanning tree around the angular points of the device; expanding around the minimum spanning tree to form a channel area topological disc model, mapping pins to corresponding arc sections of a disc, generating a disc sequence, and forming chords in the disc by connecting lines of corresponding wire nets; optionally selecting a boundary of two arc sections to vertically cut and flatten the disc so as to convert all the line net connection relations into interval sequences on line sequence boundaries to be represented; based on an improved left edge algorithm, sorting the interval sequence of the net according to a right value, and selecting a maximum topological compatible net set to be distributed to the same layer; meanwhile, the escape sequence of pins in the device is dynamically adjusted in combination with a simulated annealing algorithm, and the number of single-layer topology compatible nets is optimized by disturbing a disc sequence. According to the invention, the wiring quality is obviously improved.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB design, and particularly relates to an automatic layer assignment method for pre-evaluating and optimizing complex PCB topologies. Background Art

[0002] With the increasing diverse demands of the market for the functions of electronic products, electronic products have become more intelligent and miniaturized, resulting in a significant increase in the number of pins on a PCB (Printed Circuit Board) while the manufacturing area remains unchanged or even decreases, leading to extremely serious topological intersections between wire nets. Therefore, with the sharp increase in the complexity of PCB design, the requirements for the number of layers in PCB routing have gradually become strict, and the routing time has become very time-consuming. Traditional PCB routing algorithms have difficulty meeting the growing design complexity and the need to shorten the development cycle of electronic products. Therefore, an effective and efficient PCB layer assignment method is needed to handle the topological intersections between various wire nets, maximize the number of topologically compatible wire nets on a single layer, reduce the time overhead in the PCB routing process, and improve the performance of the entire circuit system.

[0003] The routing process of a PCB consists of two main processes, namely escape zone routing and channel zone routing. Escape zone routing is to route the pins inside the device to the boundary of the device to ensure that signals can be transmitted from the pins to other parts of the PCB for subsequent routing, as Figure 1 shown. Channel zone routing refers to, after the escape zone routing is completed, transmitting and routing signals in a specific routing channel outside the PCB device to achieve the connection between various devices. Generally speaking, the topological intersection in the channel zone is much more complex than that in the escape zone, and the escape order at the device boundary determines the number of topological intersections of the wire nets in the channel zone, thereby affecting the final routing success rate. Therefore, when dealing with the PCB routing of large-scale designs in finite layers with strict capacity constraints, the escape order at the boundary needs to be considered emphatically.

[0004] Although the topological intersection situation in the channel zone is closely related to the escape order, previous work usually evaluated the topological intersection in the channel zone based on a fixed escape order at the boundary. These methods often only obtain local optimal solutions, resulting in the need to use more layers in routing, thereby increasing the cost of PCB design. There are also some studies that reduce the number of layers used by inserting additional vias, but punching holes destroys the signal integrity and reduces the system performance. Therefore, there is an urgent need for a dynamic topology evaluation and optimization model to increase the number of topologically compatible wire nets on the same layer, reduce the number of layers used, and reduce the number of vias to a certain extent.

[0005] By implementing the automatic layer assignment technology for PCBs, the complexity of wiring can be effectively reduced, the design cycle can be shortened, enabling electronic products to iterate and innovate more quickly, and enhancing market competitiveness. At the same time, the number of layers used in the PCB can be effectively reduced, and the number of drilled holes can be decreased, reducing the production cost of electronic products and improving product performance, which is particularly important in large-scale production of electronic products.

[0006] In summary, with the continuous increase in the complexity of PCB wiring and limited wiring resources, the current layer assignment algorithms are difficult to handle wiring scenarios with complex topologies under the premise of limited layers, which will additionally increase time overhead and via consumption. To improve the processing ability of the layer assignment algorithm for PCB wiring scenarios with limited layers, it is necessary to dynamically consider the wiring in the PCB channel area.

[0007] Regarding the layer assignment problem for PCBs with limited layers, there are still the following problems waiting for further research:

[0008] (1) Existing research is too rigid in determining the order of escape points on the boundary of the escape area. Most are based on fixed escape points and perform layer assignment based on the topology of the channel area, without considering that the positions of the escape points can be modified. These locally optimized methods often only obtain locally optimal solutions, resulting in the inability to complete wiring under limited layers.

[0009] (2) In PCB design, the number of layers will increase the design cost. Therefore, current PCB designs impose restrictions on the number of wiring layers. However, if simply minimizing the number of layers is used as the optimization goal, it will lead to frequent drilling of single wire nets, thereby increasing the number of vias and affecting signal integrity. Therefore, finding the maximum topologically compatible wire nets per layer based on the given number of layers can effectively reduce the number of vias. Summary of the Invention

[0010] The purpose of the present invention is to provide an automatic layer assignment method for pre-evaluating and optimizing complex PCB topologies, to solve the problems that the determination of the order of escape points on the boundary of the escape area is too rigid and that simply minimizing the number of layers as the optimization goal affects signal integrity.

[0011] Next, in the first aspect of the present invention, an automatic layer assignment method for pre-evaluating and optimizing complex PCB topologies is provided. The method includes:

[0012] Split the multi-terminal wire nets of the PCB into two-terminal wire nets, and divide the routable resources of the PCB into an escape area and a channel area based on the device boundary; among them, the area inside the device is the escape area, and the area outside the device is the channel area;

[0013] Use the corner points of the devices to represent each device, construct a minimum spanning tree around the corner points of the devices, and characterize the relative position relationship of each device through the minimum spanning tree. The edges of the minimum spanning tree represent the possible routing channels in the channel area;

[0014] Expand around the minimum spanning tree into a topological disk model of the channel area, map the pins to the corresponding arc segments of the disk, generate a disk order, and the connections of the corresponding nets form chords within the disk, thus presenting the topological crossing relationship of each net in the channel area;

[0015] Based on the disk order and the net connection relationship, arbitrarily select the boundary between two arc segments to vertically cut and flatten the disk, so as to convert all net connection relationships into an interval sequence on the line order boundary for representation, presenting the inclusion and crossing states of the corresponding nets;

[0016] Based on the improved left-edge algorithm, sort the interval sequence of the nets by the right value and select the maximum set of topologically compatible nets to be assigned to the same layer; at the same time, combine the simulated annealing algorithm to dynamically adjust the escape order of the pins within the device, and optimize the number of topologically compatible nets in a single layer by perturbing the disk order.

[0017] In some embodiments, a minimum spanning tree is constructed based on the Kruskal algorithm to split multi-terminal nets, including:

[0018] (1) Use the pins as vertices, construct a connected graph around each pin of the multi-terminal net, and use the Euclidean distance between two pins of the net to estimate the routing wire length as the cost of the edge in the connected graph;

[0019] (2) Select the edge with the minimum cost, and ensure that the two vertices of the edge are not on the same tree, and then merge the two trees connected by the edge into one tree;

[0020] (3) Repeat step (2) until all vertices are on the same tree;

[0021] (4) Take out all the edges on the tree, and each edge corresponds to a two-terminal net.

[0022] In some embodiments, use the corner points of the devices to represent each device, and construct a minimum spanning tree around the corner points of the devices, including:

[0023] Use the four corner points of the device to represent the device, and use the device as the vertex and the minimum distance between the corner points of the device as the weight of the edge to construct the minimum spanning tree.

[0024] In some embodiments, expand around the minimum spanning tree into a topological disk model of the channel area, including:

[0025] (a) Sort the nodes connected to the nodes with degrees not equal to 1 on the minimum spanning tree in a fixed order; wherein, the sorting order includes clockwise and counterclockwise;

[0026] (b) Select any leaf node of the minimum spanning tree as the starting point of traversal, and traverse according to the node connection relationship and the node sorting in (a) to go around the nodes of the minimum spanning tree in a circle, forming a closed area, and expand the closed area into a circular shape to obtain the channel area topological disk model; wherein, the escape areas of different devices correspond to different arc segments on the disk, the area inside the circle represents the channel area, and different arc segments on the circle represent the escape areas of the devices to which they belong.

[0027] In some embodiments, map the pins to the corresponding arc segments of the disk to generate a disk order, and the connections of the corresponding nets form chords inside the disk, thereby presenting the topological crossing relationship of each net in the channel area, including:

[0028] Map the pins belonging to the same device to the same arc segment, and the sorting of the pins on the disk is the disk order;

[0029] According to the mapping relationship between the pins and the disk, connect the pins of the same net, and correspondingly pull out a chord on the disk; since the area inside the disk represents the channel area, the topological crossing of different chords represents the topological incompatibility of the nets corresponding to the two chords in the channel area. In this way, pull all the pins into chords according to the net relationship, that is, realize the establishment of the channel area topological disk model.

[0030] In some embodiments, based on the improved left-edge algorithm, sort the interval sequences of the nets by the right value and select the maximum topological compatible net set to be assigned to the same layer, including:

[0031] (1) Sorting stage: Sort all the intervals of the nets in ascending order according to their right values to obtain an interval list;

[0032] (2) Selection stage: Select the first interval after sorting, traverse the remaining interval list, and continuously select non-overlapping intervals until the list traversal ends, and place the selected intervals in the same set;

[0033] (3) Iteration stage: Repeat the sorting and selection until all intervals are selected;

[0034] The set with the largest number of intervals is the maximum topological compatible net set, and the nets in it are assigned to the same layer to maximize the number of nets that can be accommodated in a single layer.

[0035] In some embodiments, combine the simulated annealing algorithm to dynamically adjust the escape order of the pins in the device, and optimize the number of single-layer topological compatible nets by perturbing the disk order, including:

[0036] (1) Obtain an initial disk order based on the initial order in which the pins within the device are mapped to the arc segments corresponding to the disk;

[0037] (2) Vertically cut the disk and flatten it into a linear sequence, sequentially traverse the nets and the line order sequence, and obtain the interval of each net in the line order sequence;

[0038] (3) Based on the improved left-edge algorithm, find the set of maximum topological compatible intervals, i.e., the set of topologically compatible nets, and calculate the objective function according to the number of topologically compatible nets;

[0039] (4) Perturb the pin mapping order to generate a new disk order, repeat steps (2) and (3), and determine whether to accept the new disk order based on the simulated annealing algorithm; until after multiple repetitions, the set of maximum topologically compatible nets does not change or the objective function is optimal, and the iteration ends.

[0040] In some embodiments, the objective function is as follows:

[0041]

[0042] In the formula, n represents the total number of nets, T cn (area) represents the number of nets that are topologically compatible in the channel area, corresponding to the crossing situation inside the disk; only when the escape order satisfies no topological crossing in the channel area, T cn (area) is equal to n, and at this time, Assign Cost = 0, reaching the optimum.

[0043] According to the second aspect of the present invention, there is provided a computer device, including: a processor and a memory, the memory stores a program or instruction that can run on the processor, and when the program or instruction is executed by the processor, the steps of the automatic layer assignment method for pre-evaluating and optimizing complex PCB topologies described in any item of the first aspect are implemented.

[0044] According to the third aspect of the present invention, there is provided a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by the processor, the steps of the automatic layer assignment method for pre-evaluating and optimizing complex PCB topologies described in any item of the first aspect are implemented.

[0045] Generally speaking, compared with the prior art by the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0046] The present invention proposes an automatic layer assignment technology for complex PCB topology pre-evaluation and optimization, aiming to solve the problems of unreasonable layer assignment and time-consuming wiring in traditional PCB wiring layer assignment algorithms for limited layers. By establishing a topology evaluation model, the topology problem in the channel area is converted into a linear sequence multi-segment resource allocation problem. The left-edge algorithm is used to find the maximum single-layer topology compatible netlist, and the SA algorithm is used to optimize the problem results. Finally, the layer assignment of all netlists is completed, reducing the wiring complexity and significantly improving the wiring quality. Through actual wiring results, it is verified that this technology can reasonably allocate wiring resources, ensure the wiring rate under the condition of limited layers, and reduce the running time of wiring at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 FIG. is a schematic diagram of an ideal PCB channel area and escape area provided by an embodiment of the present application;

[0048] Figure 2 FIG. is a schematic diagram of the overall process of an automatic layer assignment method for complex PCB topology pre-evaluation and optimization provided by an embodiment of the present application;

[0049] Figure 3 FIG. is a comparison diagram of splitting a multi-terminal netlist considering wire length provided by an embodiment of the present application; where, Figure 3 (a) in FIG. is the result diagram of splitting in any order, Figure 3 (b) in FIG. is the result diagram of splitting using the minimum spanning tree considering wire length;

[0050] Figure 4 FIG. is an example diagram of dividing routable resources of a PCB provided by an embodiment of the present application;

[0051] Figure 5 FIG. is a schematic diagram of establishing a disk model provided by an embodiment of the present application;

[0052] Figure 6 FIG. is a schematic diagram of constructing a closed area around the minimum spanning tree provided by an embodiment of the present application;

[0053] Figure 7 FIG. is a schematic diagram of establishing a topology model provided by an embodiment of the present application; where, Figure 7 (a) in FIG. is a schematic diagram of mapping pins to the topology disk model, Figure 7 (b) in FIG. is a schematic diagram of constructing the topology intersection model of the channel area;

[0054] Figure 8 FIG. is a schematic diagram of establishing a topology model provided by an embodiment of the present application;

[0055] Figure 9 FIG. is a comparison diagram of the topology model before and after perturbation provided by an embodiment of the present application;

[0056] Figure 10 A schematic diagram of the operation result of layer allocation provided by an embodiment of the present application; wherein, Figure 10 In (a), it is a schematic diagram of all net free wires, Figure 10 In (b), it is a schematic diagram of the maximum topological compatible net free wires, Figure 10 In (c), it is an actual topological schematic diagram;

[0057] Figure 11 A schematic diagram of the hardware structure of a computer device provided by an embodiment of the present application. Specific embodiments

[0058] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Based on the embodiments provided in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0059] Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without making creative efforts, the present application can also be applied to other similar scenarios based on these drawings. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be understood as the content disclosed in the present application being insufficient.

[0060] Referring to "embodiment" in the present application means that the specific features, structures or characteristics described in combination with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0061] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. The words such as "a", "an", "one kind", "the" and the like involved in this application do not indicate a quantity limitation and may represent a singular or plural number. The terms "comprising", "including", "having" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include steps or units not listed, or may further include other steps or units inherent to these processes, methods, products or devices. The words such as "connected", "linked", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0062] This application designs a global routing planning for PCB, which can maximize the proportion of single-layer topology compatible nets based on the limited routing layers, thereby improving the routing completion rate and reducing the running time.

[0063] As Figure 2 shown, this application proposes an automatic layer assignment method for pre-evaluating and optimizing complex PCB topologies, which is specifically as follows:

[0064] 1. Overall framework

[0065] The overall framework of the technical solution is divided into three parts: preprocessing of PCB routing data, establishment of a topology model, and layer assignment. First, convert the routing data of the PCB into a data form suitable for the topology model, then establish the topology model, optimize it through the simulated annealing (SA) algorithm, select the set of nets with the largest topological compatibility based on the improved Left-Edge algorithm, and assign them to the same layer. For the unassigned nets, repeat the establishment of the topology model and SA optimization, and layer by layer with the Left-Edge algorithm until all nets are assigned.

[0066] 1.1 Preprocessing

[0067] In the preprocessing stage, in order to simplify the calculation of the subsequent topology model, the multi-terminal netlist is first split into two-terminal netlists. On the other hand, in the PCB routing scenario of multiple devices, most topological crossovers occur outside the devices. Therefore, the main area of topological crossover needs to be converted into a topology model, which is a necessary preparation for subsequent topological evaluation. The main process is as follows:

[0068] (1) Netlist splitting;

[0069] (2) Routable resource partitioning and processing.

[0070] 1.2 Topology model establishment

[0071] Considering the limited number of layers, this application focuses on topological compatibility, that is, there is no topological crossover between the netlists assigned to the same layer. In this way, the allocated netlists can be maximized, and the number of used layers can be effectively reduced. Generally speaking, the main part of PCB routing is in the channel area. Therefore, based on the given number of layers, the larger the proportion of topologically compatible netlists in the channel area participating in layer assignment, the more beneficial it is to reduce the number of used layers. This application represents the relative position relationship of each device based on the minimum spanning tree. The edges of the spanning tree represent the possible routing channels in the channel area, and then a topological disk model of the channel area is constructed. Finally, the pins are mapped onto the topological disk, and the connections of the corresponding netlists form chords within the disk, presenting the topological crossover relationship of each netlist in the channel area. The main process is as follows:

[0072] (1) Establish a topological disk model of the channel area;

[0073] (2) Establish the mapping relationship between pins and the topological disk model.

[0074] 1.3 Layer assignment

[0075] In the layer assignment stage, the points belonging to the same device on the disk can exchange positions. By adjusting the escape order of the pins within the device, the crossover relationship between the corresponding chords within the disk will change, and the topological relationship of the netlists in the corresponding channel area will also change accordingly. In this way, by sacrificing the wire length of some netlists in the escape area, more netlists can be accommodated on a single layer, and the number of used layers can be compressed. Then, based on the improved left-edge algorithm, the corresponding netlist subsets with only inclusion relationships are solved in turn. Among these subsets, the one with the largest number of inclusions is the largest netlist subset sought by this application, that is, the largest topologically compatible netlist set on a single layer. Finally, the layer assignment of all netlists is completed through continuous iteration. The main process is as follows:

[0076] (1) Perturb each pin within the device range;

[0077] (2) Obtain the largest topologically compatible netlist set based on the left-edge algorithm and the topological disk order.

[0078] 2. Algorithm design

[0079] The method flow of automatic layer assignment for PCB in the embodiments of this application is as follows Figure 2 shown

[0080] 2.1 Net splitting

[0081] Before performing the layer assignment algorithm, the multi-terminal net needs to be split first. The goal is to ensure the shortest wire length of the overall connection. Therefore, the Kruskal algorithm is used to construct a minimum spanning tree to split the multi-terminal net. In this method, the Euclidean distance between two pins of the net is selected to estimate the wire length. Assume that the coordinates of pin A in the net are x a , y a , and the coordinates of pin B in the net are x b , y b . Then the Euclidean distance between the two pins is as follows

[0082]

[0083] The specific steps are as follows

[0084] (1) Construct a connected graph around each Pin point of the multi-terminal net, and the cost of the edge is d(A, B);

[0085] (2) Select the edge with the minimum cost, and ensure that the two vertices of the edge are not on the same tree, and then merge them into one tree;

[0086] (3) Repeat step 2 until all vertices are on the same tree;

[0087] (4) Take out all the edges on the tree, and each edge corresponds to a two-terminal net.

[0088] Figure 3 Figure for comparison before and after splitting the multi-terminal net using the minimum spanning tree. Among them Figure 3 (a) in is the result graph of splitting in any order, Figure 3 (b) in is the result graph of splitting using the minimum spanning tree considering the wire length. It can be seen that the wire length is significantly reduced.

[0089] 2.1 Dividing routable resources

[0090] After splitting the routing main body, it is necessary to divide the routable resources. Generally speaking, the routable resources of the PCB can be divided into an escape area and a channel area based on the device boundary. The area inside the device is the escape area, and the area outside the device is the channel area. Escape routing is to escape the pins inside the component to the component boundary, and the points on the component boundary are called escape points; Area routing is to connect the pins between the components that have escaped to the boundary as shown Figure 4 shown

[0091] 2.2 Topology Model Establishment

[0092] After the wiring main body and wiring area are processed in the preprocessing stage, in order to construct a topology model of the channel area to present the topological cross-relationship between each net, and then guide the layer assignment in the next stage. In this application, the four corner points of the device are used to represent the device, and the disk model is used to represent the routable resources.

[0093] The specific steps are as follows:

[0094] (1) Construct a minimum spanning tree around the corner points of the device;

[0095] (2) Expand the minimum spanning tree into a disk.

[0096] Through step (1), the escape areas of each device are connected into one body, and the relative position relationship between the devices is characterized by the minimum spanning tree. In step (2), any leaf node of the spanning tree is selected, and a circle is formed by going around the nodes of the minimum spanning tree once. The closed area is expanded into a circular shape. The escape areas of different devices correspond to different arc segments on the disk. As Figure 5 shown, the area inside the circle represents the channel area, and different arc segments on the circle represent the escape areas of the affiliated devices.

[0097] Among them, the minimum spanning tree is expanded into a disk, and the steps are as follows:

[0098] (a) Sort the nodes connected to the nodes with a degree not equal to 1 on the spanning tree in a fixed order, such as clockwise / counterclockwise;

[0099] (b) Select any leaf node of the spanning tree as the starting point of traversal, and traverse according to the connection relationship of the nodes and the node sorting in (a).

[0100] As Figure 6 shown, the sorting of node 2 is 1, 3, 6; the sorting of node 3 is 2, 4, 5; starting from node 1, traversing to node 2, according to the sorting order of node 2, 3 comes after 1, so node 2 traverses to node 3, and so on, node 3 traverses to node 4, and the final traversal result is 1, 2, 3, 4, 5, 6.

[0101] After the disk model is established, the mapping relationship between the pins and the disk model can be established, so that the pins belonging to the same device are mapped to the same arc segment, as Figure 7 shown in (a). According to the mapping relationship between the pins and the disk, the pins of the same net are connected, and a chord is pulled out on the disk accordingly. Since the area inside the disk represents the channel area, the topological cross of different chords represents the topological incompatibility of the nets corresponding to the two chords in the channel area. Pull all the pins into chords according to the net relationship, and the establishment of the topology model of the channel area is realized, asFigure 7 as shown in (b) of

[0102] The pseudo-code for establishing the topological model is shown in Table 1.

[0103] Table 1 Pseudo-code for Establishing Topological Model

[0104]

[0105]

[0106] 2.3 Layer Assignment

[0107] After the establishment of the topological model, based on the improved left-edge algorithm, find a disk order with the largest number of topologically compatible nets. Based on the disk order and the net connection relationship, arbitrarily select the boundary of two arcs to vertically cut and flatten the disk, and convert all net connection relationships into an interval sequence on the line order boundary to represent, presenting the inclusion and crossing states of the corresponding nets. As Figure 8 shown, for example, the subscripts corresponding to Net 2 in the interval sequence are 1 and 14, and the interval is (1, 14). The subscripts corresponding to Net 6 in the interval sequence are (5, 18). The two intervals overlap, indicating that the two nets are topologically crossed.

[0108] Then, based on the improved Left-Edge algorithm, convert the problem of finding the maximum number of topologically compatible nets into a problem of processing multi-interval resource allocation. The implementation process of the ordinary left-edge algorithm is divided into two stages: sorting and selection. The optimization goal is to minimize the number of layers of interval allocation. The following details its implementation process:

[0109] (1) Sorting stage (Sort): First, sort all intervals in ascending order according to their left values. For example, assume there is a set of nets {1, 2, 3, 4, 5, 6, 7}, and their intervals are: (0, 3), (3, 5), (6, 8), (1, 7), (7, 8), (0, 1), (2, 6). After sorting according to the left values of the intervals, the order is {1, 6, 4, 7, 2, 3, 5}. The purpose of this sorting is to facilitate finding non-conflicting intervals and accelerating the implementation of the algorithm.

[0110] (2) Selection stage (Selection): Select the first interval after sorting, traverse the interval list, and continuously select non-overlapping intervals until the list traversal ends, and place the selected intervals in the same set.

[0111] Repeat the sorting and selection until all intervals are selected. For example, in the example of step (1), the set list of intervals is {1, 2, 3}; {6, 7, 5}; {4}. At this time, the number of layers used by the intervals is the actual number of layers used by the nets.

[0112] Although the ordinary left-edge algorithm can solve the layer assignment problem of multi-nets, in the case of layer constraints, it is very likely to result in a large amount of available routing resources remaining on a certain layer, thus causing waste of layers. Therefore, the optimization goal of the improved left-edge algorithm proposed in this application is to maximize the number of non-crossing intervals on a single layer, so as to maximize the number of nets assigned to the same layer. The pseudo-code of the improved left-edge algorithm is shown in Table 2.

[0113] Table 2 Pseudo-code table of the improved left-edge algorithm

[0114]

[0115]

[0116] After the topological model is established and the corresponding maximum topological compatible nets are obtained, it may only be a feasible solution, not an optimal solution. Because the escape order is actually flexible and variable. When adjusting the escape order of the pins inside the device, the crossing relationship between the chords in the corresponding topological disk model will also change accordingly. By perturbing the pins on the same arc segment and swapping their positions, that is, the escape order on the device boundary, and then changing the number of topological crossing nets in the channel area, as Figure 9 shown. By continuously perturbing the positions of the pins, and then finding a disk order with the largest number of topological compatible nets based on the improved left-edge algorithm.

[0117] In order to achieve global topological non-crossing of the network under layer constraints, this application proposes a dynamic disk model based on SA. By continuously iterating to determine the reasonable escape points of each pin, and then finding the maximum number of topological compatible nets on a single layer, the layer assignment under the limited layer is completed. Therefore, this application defines the objective function as follows:

[0118]

[0119] Among them, the parameter n represents the total number of nets, and T cn (area) represents the number of nets that are topologically compatible in the channel area, corresponding to the crossing situation inside the disk. Only when the escape order satisfies no topological crossing in the channel area, T cn (area) is equal to n, and at this time AssignCost = 0.

[0120] As shown in Table 3, the specific steps are as follows:

[0121] (1) Specify the initial positions of the pins inside the device escaping to the virtual boundary to obtain the initial disk order;

[0122] (2) Vertically cut the disk from the device gap and expand it into a linear sequence. Traverse the nets and the line order sequence in turn to obtain the interval of each net in the line order sequence;

[0123] (3) Based on the left-edge algorithm, find the set of maximum topological compatible intervals, i.e., the topological compatible netlist set, and calculate AssignCost;

[0124] (4) Perturb the disks, and based on the SA algorithm, obtain a new disk order. Repeat steps (2) and (3). Until after multiple repetitions, the maximum topological compatible netlist set does not change or AssignCost = 0, then end the iteration.

[0125] Table 3 Pseudo-code table of the annealing-based netlist layer assignment algorithm

[0126]

[0127] 2.4 Final effect display

[0128] The layer assignment operation result based on this method is as Figure 10 shown. Figure 10 In (a) of , it is a fanout wire diagram. It can be seen that the contradictions of topological intersections mainly occur in the channel area. Figure 10 In (b) of , it is the obtained maximum topological compatible netlist of a single layer. Although the fanout wires cross each other, the actual topology is compatible, as shown in (c) of . Figure 10 In (c) of .

[0129] In addition, the automatic layer assignment method for complex PCB topology pre-evaluation and optimization described in of this application embodiment can be implemented by a computer device. Figure 2 The hardware structure schematic diagram of the computer device of this application embodiment is as shown in . As shown in , the device may include a processor 201 and a memory 202 storing computer program instructions. Figure 11 The hardware structure schematic diagram of the computer device of this application embodiment is as shown in . As shown in , the device may include a processor 201 and a memory 202 storing computer program instructions. Figure 11 Specifically, the above-mentioned processor 201 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0130] Specifically, the above-mentioned processor 201 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0131] Among them, the memory 202 may include a mass storage for data or instructions. By way of example and not limitation, the memory 202 may include a hard disk drive (HDD), a floppy disk drive, a solid state drive (SSD), a flash memory, an optical disc, a magneto-optical disc, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. In appropriate cases, the memory 202 may include removable or non-removable (or fixed) media. In appropriate cases, the memory 202 may be internal or external to the data processing device. In a particular embodiment, the memory 202 is a non-volatile memory. In a particular embodiment, the memory 202 includes a read-only memory (ROM) and a random access memory (RAM). In appropriate cases, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically alterable ROM (EAROM), or a flash memory, or a combination of two or more of these. In appropriate cases, the RAM may be a static random access memory (SRAM) or a dynamic random access memory (DRAM), where the DRAM may be a fast page mode dynamic random access memory (FPMDRAM), an extended date out dynamic random access memory (EDODRAM), a synchronous dynamic random access memory (SDRAM), etc.

[0132] The memory 202 can be used to store or cache various data files required for processing and / or communication, as well as possible computer program instructions executed by the processor 201.

[0133] By reading and executing the computer program instructions stored in the memory 202, the processor 201 implements any one of the automatic layer assignment methods for pre-evaluating and optimizing complex PCB topologies in the above embodiments.

[0134] In some embodiments, the point cloud generation device may further include a communication interface 203 and a bus 200. Among them, as Figure 11 shown, the processor 201, the memory 202, and the communication interface 203 are connected through the bus 200 and complete communication with each other.

[0135] The communication interface 203 is used to implement communication between various modules, devices, units, and / or devices in the embodiments of the present application. The communication interface 203 can also implement data communication with other components, such as external devices, image / data acquisition devices, databases, external storage, and image / data processing workstations.

[0136] The bus 200 includes hardware, software, or both, and couples components of the point cloud generation device to each other. The bus 200 includes, but is not limited to, at least one of the following: Data Bus, Address Bus, Control Bus, Expansion Bus, Local Bus. By way of example and not limitation, the bus 200 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable bus or a combination of two or more of these. In a suitable case, the bus 200 may include one or more buses. Although embodiments of the present application describe and illustrate specific buses, the present application contemplates any suitable bus or interconnect.

[0137] The computer device can execute the automatic layer assignment method for pre-evaluating and optimizing complex PCB topologies in the embodiments of the present application based on the rendering device, so as to implement the combination Figure 2 with the described automatic layer assignment method for pre-evaluating and optimizing complex PCB topologies.

[0138] In addition, in combination with the automatic layer assignment method for pre-evaluation and optimization of complex PCB topologies in the above embodiments, an embodiment of the present application can provide a computer-readable storage medium to implement. Computer program instructions are stored on the computer-readable storage medium; when the computer program instructions are executed by a processor, any one of the automatic layer assignment methods for pre-evaluation and optimization of complex PCB topologies in the above embodiments is implemented.

[0139] In summary, the automatic layer assignment technology for pre-evaluation and optimization of complex PCB topologies proposed in the present application aims to solve the problems of unreasonable layer assignment for limited layers and time-consuming wiring in traditional PCB wiring layer assignment algorithms. By establishing a topology evaluation model, converting the topology problem in the channel area into a linear sequence multi-segment resource allocation problem, using the left-edge algorithm to find the maximum single-layer topology compatible netlist, and optimizing the problem results based on the SA algorithm, the layer assignment of all netlists is finally completed, reducing the complexity of wiring and significantly improving the wiring quality. Through the actual wiring results, it is verified that this technology can reasonably allocate wiring resources, ensure the wiring rate under the condition of limited layers, and at the same time reduce the running time of wiring.

[0140] It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification. In addition, according to the needs of implementation, each step / component described in the present application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present application.

[0141] Those skilled in the art can easily understand that the above embodiments only represent several implementation manners of the present application, and the description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An automatic layer allocation method for pre-evaluation and optimization of complex PCB topology, characterized in that: The method includes: Split the multi-terminal net of the PCB into two-terminal nets, and divide the PCB's routable resources into an escape area and a channel area based on the device boundary; the inside of the device is the escape area, and the outside of the device is the channel area; Use the corner points of the device to represent each device, and construct a minimum spanning tree around the corner points of the device. The minimum spanning tree is used to represent the relative position relationship of each device. The edges of the minimum spanning tree represent possible wiring channels in the channel area. The minimum spanning tree is expanded into a channel area topological disk model, and the pins are mapped to the corresponding arc segments of the disk to generate a disk sequence. The corresponding lines of the network form the chords in the disk, thus presenting the topological intersection relationship of each network in the channel area. Based on the disk sequence and the line network connection relationship, the disk is cut vertically and flattened at the boundary of any two arc segments to convert all the line network connection relationships into interval sequences on the line sequence boundary to show the inclusion and intersection status of the corresponding line network; Based on the improved left edge algorithm, the interval sequence of the wire nets is sorted according to the right value and the largest topologically compatible wire net set is selected and allocated to the same layer. At the same time, the escape order of the pins in the device is dynamically adjusted in combination with the simulated annealing algorithm, and the number of single-layer topologically compatible wire nets is optimized by perturbing the disk sequence.

2. The automatic layer allocation method for complex PCB topology pre-evaluation and optimization according to claim 1 is characterized in that: The multi-terminal network is split by constructing a minimum spanning tree based on the Kruskal algorithm, including: (1) Taking the pins as vertices, a connectivity graph is constructed around each pin of the multi-terminal wire net, and the Euclidean distance between two pins of the wire net is used to estimate the wiring length as the cost of the edge in the connectivity graph; (2) Select the edge with the smallest cost and ensure that the two vertices of the edge are not on the same tree, and then merge the two trees connected by the edge into one tree; (3) Repeat step (2) until all vertices are on the same tree; (4) Take out all the edges in the tree, each edge corresponds to a two-terminal line network.

3. The automatic layer allocation method for complex PCB topology pre-evaluation and optimization according to claim 1 is characterized in that: Use the corner points of the device to represent each device, and construct a minimum spanning tree around the corner points of the device, including: The four corner points of a device are used to represent the device, and the device is used as a vertex. The minimum distance between the device corner points is used as the weight of the edge to construct a minimum spanning tree.

4. The automatic layer allocation method for complex PCB topology pre-evaluation and optimization according to claim 1 is characterized in that: The minimum spanning tree is expanded into a channel area topological disk model, including: (a) sorting the nodes connected to the nodes whose degree is not 1 on the minimum spanning tree in a fixed order; wherein the sorting order includes clockwise and counterclockwise; (b) Select any leaf node of the minimum spanning tree as the starting point of the traversal, and traverse according to the node connection relationship and the node order of (a) to circle around the minimum spanning tree node to form a closed area, and then expand the closed area into a circle to obtain a channel area topological disk model; wherein, the escape areas of different devices correspond to different arc segments on the disk, the area inside the circle represents the channel area, and the different arc segments on the circle represent the escape areas of the devices to which they belong.

5. The automatic layer allocation method for complex PCB topology pre-evaluation and optimization according to claim 1 is characterized in that: Map the pins to the arcs corresponding to the disk to generate a disk sequence. The corresponding lines of the network form the chords in the disk, thus presenting the topological intersection relationship of each network in the channel area, including: Map the pins belonging to the same device to the same arc segment, and the order of the pins on the disk is the disk sequence; According to the mapping relationship between pins and disks, the pins of the same wire network are connected, and a string is pulled out on the disk. Since the inner area of ​​the disk represents the channel area, the topological intersection of different strings represents that the wire network topologies corresponding to the two strings in the channel area are incompatible. In this way, all pins are pulled into strings according to the wire network relationship, thereby realizing the establishment of a topological disk model of the channel area.

6. The automatic layer allocation method for complex PCB topology pre-evaluation and optimization according to claim 1 is characterized in that: Based on the improved left edge algorithm, the interval sequence of the network is sorted by right value and the largest topologically compatible network set is selected and assigned to the same layer, including: (1) Sorting stage: Arrange the intervals of all network segments in ascending order according to their right values ​​to obtain an interval list; (2) Selection phase: Select the first interval after sorting, traverse the remaining interval list, and continue to select non-overlapping intervals until the list traversal is completed, and put the selected intervals in the same set; (3) Iteration phase: sorting and selection are repeated until all intervals are selected; The set with the largest number of intervals in each set is the maximum topologically compatible network set, and the networks within it are allocated to the same layer to maximize the number of networks that can be accommodated in a single layer.

7. The automatic layer allocation method for complex PCB topology pre-evaluation and optimization according to claim 6, characterized in that: Combined with the simulated annealing algorithm, the escape order of the pins in the device is dynamically adjusted, and the number of single-layer topology compatible wire nets is optimized by perturbing the disk order, including: (1) Based on the initial order of the arc segments corresponding to the disk mapped to the pins in the device, an initial disk sequence is obtained; (2) Cut the disk vertically and flatten it into a linear sequence, traverse the line net and line sequence in turn, and obtain the interval of each line net in the line sequence; (3) Based on the improved left edge algorithm, the maximum topological compatible interval set, that is, the topological compatible network set, is obtained, and the objective function is calculated according to the number of topological compatible networks; (4) Perturb the pin mapping order to generate a new disk sequence, repeat steps (2) and (3), and determine whether to accept the new disk sequence based on the simulated annealing algorithm; end the iteration until the maximum topologically compatible network set does not change or the objective function is optimal after multiple repetitions.

8. The automatic layer allocation method for complex PCB topology pre-evaluation and optimization according to claim 7, characterized in that: The objective function is as follows: In the formula, n represents the total number of wire nets, T cn (area) represents the number of topologically compatible wire networks in the channel area, corresponding to the intersection inside the disk; T is only when the escape sequence satisfies the condition that there is no topological intersection in the channel area. cn (area) is equal to n, at this time AssignCost = 0, reaching the optimal value.

9. A computer device, characterized in that: include: A processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the automatic layer allocation method for complex PCB topology pre-evaluation and optimization as described in any one of claims 1 to 8 are implemented.

10. A readable storage medium, characterized in that: Programs or instructions are stored thereon, and when the programs or instructions are executed by the processor, the steps of the automatic layer allocation method for complex PCB topology pre-evaluation and optimization as described in any one of claims 1 to 8 are implemented.

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