Integrated circuit layout matching module layout method and system

Abstract

The invention discloses an integrated circuit layout matching module layout method and system, and the method comprises the steps: obtaining the attribute information of a component module of an integrated circuit netlist and the attribute information of a component module of an integrated circuit layout, and carrying out the matching and grouping processing, and obtaining grouped component modules; obtaining relative layout position information of the grouped component modules, and carrying out merging operation to obtain merged component modules; and obtaining the minimum distance between the central points of the adjacent combined component modules, and carrying out layout on the combined component modules to obtain an integrated circuit layout matching module layout result. According to the method, the most compact layout can be achieved through a module port merging method, a large amount of memory occupation is saved, and the layout flexibility is improved. The integrated circuit layout matching module layout method and system can be widely applied to the technical field of integrated circuit layout matching.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit layout matching, and particularly to a method and system for laying out an integrated circuit layout matching module. Background Art

[0002] The diverse requirements for the functions of integrated circuits have led to an increasing proportion of mixed circuits of analog circuits and digital circuits in the system-on-chip. Since analog circuits and digital circuits are very different, the automatic design method of digital circuits cannot be applied. The automation level of analog circuits lags behind relatively, which slows down the development speed of analog integrated circuit design. At present, the design of analog circuits is still mainly manual design, which has problems such as long cycle and high cost. Currently, the mainstream layout methods for analog integrated circuit layouts include manual layout, automatic layout based on machine learning, automatic layout based on constraint conditions, automatic layout based on templates, etc. Manual layout is a traditional layout method, which can achieve good layout effects in small-scale analog integrated circuits, but the layout difficulty increases sharply in large-scale analog integrated circuits, and a large amount of manpower and time are required to achieve a satisfactory layout. The performance of automatic layout based on machine learning is limited by the quality and quantity of the data used. The method of automatic layout based on constraint conditions has a high complexity and a slow layout speed, while the automatic layout based on templates has the problem of poor flexibility. Summary of the Invention

[0003] In order to solve the above technical problems, the purpose of the present invention is to provide a method and system for laying out an integrated circuit layout matching module, which can achieve the most compact layout and save a large amount of memory occupancy by merging module ports, and improve the flexibility of the layout.

[0004] The first technical solution adopted by the present invention is: a method for laying out an integrated circuit layout matching module, including the following steps:

[0005] Obtain the attribute information of the component modules of the integrated circuit netlist and the attribute information of the component modules of the integrated circuit layout, and perform matching grouping processing to obtain the grouped component modules;

[0006] Obtain the relative layout position information of the grouped component modules and perform a merging operation to obtain the merged component modules;

[0007] Obtain the minimum center point distance between adjacent merged component modules and perform layout on the merged component modules to obtain the layout result of the integrated circuit layout matching module.

[0008] Further, the step of obtaining the attribute information of the component modules in the integrated circuit netlist and the attribute information of the component modules in the integrated circuit layout and performing matching grouping processing to obtain the grouped component modules specifically includes:

[0009] Read the netlist information of the integrated circuit to obtain the attribute information of the component modules in the integrated circuit netlist. The attribute information of the component modules in the integrated circuit netlist includes the netlist name of the component module, the device type of the component module, the netlist port name information of the component module, the parameter information of the component module, and the connection relationship between the ports of the component module.

[0010] Read the layout information of the integrated circuit to obtain the attribute information of the component modules in the integrated circuit layout. The attribute information of the component modules in the integrated circuit layout includes the layout name of the component module, the layout port name information of the component module, the size information of the component module, the layout position information of the component module, the layout rotation information of the component module, the layout mirror information of the component module, and the geometric parameter information of the component module.

[0011] Determine the matching relationship and matching type between the component modules according to the attribute information of the component modules in the integrated circuit netlist and the attribute information of the component modules in the integrated circuit layout. The matching types include differential pair matching type, current mirror matching type, resistor array matching type, and capacitor array matching type.

[0012] Group the component modules according to the matching relationship and matching type between the component modules to obtain the grouped component modules.

[0013] Further, the step of reading the layout information of the integrated circuit to obtain the attribute information of the component modules in the integrated circuit layout specifically includes:

[0014] Determine the layout name of the component module and the layout port name information of the component module according to the label information of the component modules in the integrated circuit layout.

[0015] Determine the layout position information and the geometric parameter information of the component module according to the label position information of the component modules in the integrated circuit layout.

[0016] Determine the size information of the component module according to the rectangular bounding box size information of the component modules in the integrated circuit layout.

[0017] Combine the label information of the component module and the layout port name information of the component module to determine the layout rotation information and the layout mirror information of the component module.

[0018] Integrate the layout name of the component module, the layout port name information of the component module, the size information of the component module, the layout position information of the component module, the layout rotation information of the component module, the layout mirror information of the component module, and the geometric parameter information of the component module to obtain the attribute information of the component module in the integrated circuit layout.

[0019] Further, the step of grouping the component modules according to the matching relationship and matching type between the component modules to obtain the grouped component modules specifically includes:

[0020] Determine the matching relationship between the component modules according to the netlist name of the component module and the layout name of the component module;

[0021] Through the path search algorithm, regard the component modules as nodes and the matching relationship between the component modules as connection edges, and search from the common nodes of the component modules to construct the connected graph structure of the component modules;

[0022] Determine the matching type of the component modules according to the connected graph structure of the component modules;

[0023] Group the component modules according to the matching type of the component modules to obtain the grouped component modules.

[0024] Further, the step of obtaining the relative layout position information of the grouped component modules and performing a merging operation to obtain the merged component modules specifically includes:

[0025] According to the preset matching principle, perform a preliminary layout on the grouped component modules to obtain the relative layout position information of the grouped component modules, and the preset matching principle includes the same direction, common centroid, and symmetry;

[0026] Construct a preset merging operation behavior, and combine the relative layout position information of the grouped component modules to perform a merging operation to obtain the merged component modules.

[0027] Further, the preset merging operation behaviors include a non-allowable merging operation behavior, an allowable well merging operation behavior, and an allowable well and port merging operation behavior, where:

[0028] The non-allowable merging operation behavior represents the default operation behavior for adjacent grouped component modules;

[0029] The allowable well merging operation behavior means that if the well types of adjacent grouped component modules are the same, the allowable well merging operation behavior is adopted;

[0030] The described allowable well and port merging operation behavior means that if the well types of adjacent grouped component modules are the same and they have at least one port with the same node information, and the port sizes are the same and the directions are opposite, then the allowable well and port merging operation behavior is adopted.

[0031] Further, the step of obtaining the minimum center point distance between adjacent merged component modules and performing layout on the merged component modules to obtain the layout result of the integrated circuit layout matching module specifically includes:

[0032] Obtain the minimum center point distance between adjacent merged component modules;

[0033] According to the minimum center point distance, combined with the preset merging operation behavior, determine the layout information of the component modules;

[0034] Set the origin position of the layout information of the integrated circuit as the coordinate origin, and the total centroid position of the grouped component modules as the layout center point. Combined with the layout information of the component modules, perform layout on the merged component modules to obtain the layout result of the integrated circuit layout matching module.

[0035] Further, the step of obtaining the minimum center point distance between adjacent merged component modules specifically includes:

[0036] If the adjacent merged component modules adopt the non - allowable merging operation behavior, the minimum center point distance between the centers of the adjacent merged component modules is the minimum DRC distance between the adjacent merged component modules without overlap;

[0037] If the adjacent merged component modules adopt the allowable well merging operation behavior, the minimum center point distance between the centers of the adjacent merged component modules is the minimum DRC distance between the adjacent merged component modules without overlap under the condition of ignoring the well;

[0038] If the adjacent merged component modules adopt the allowable well and port merging operation behavior, the minimum center point distance between the centers of the adjacent merged component modules is the center point distance between the adjacent merged component modules when the ports are completely overlapped.

[0039] The second technical solution adopted by the present invention is: An integrated circuit layout matching module layout system, including:

[0040] The first module is used to obtain the attribute information of the component modules in the integrated circuit netlist and the attribute information of the component modules in the integrated circuit layout and perform matching grouping processing to obtain the grouped component modules;

[0041] The second module is used to obtain the relative layout position information of the grouped component modules for merging operations to obtain the merged component modules;

[0042] The third module is used to obtain the minimum center point distance between adjacent merged component modules and layout the merged component modules to obtain the layout result of the integrated circuit layout matching module.

[0043] The beneficial effects of the method and system of the present invention are as follows: By obtaining the attribute information of the component modules of the integrated circuit netlist and the attribute information of the component modules of the integrated circuit layout and performing matching grouping processing, the present invention does not require consuming the memory for constructing a grid, can save a large amount of memory occupancy, further obtains the relative layout position information of the grouped component modules for merging operations, can process DRC rules (physical design rules), and achieves the most compact layout by merging module ports. Finally, by obtaining the minimum center point distance between adjacent merged component modules and laying out the merged component modules, the matching relationship and matching type between modules can be identified, and different layout methods can also be designed according to various matching types and the attribute information of various matching modules, improving the flexibility of the layout. Brief Description of the Drawings

[0044] Figure 1 is the step flow chart of a method for laying out an integrated circuit layout matching module of the present invention;

[0045] Figure 2 is the circuit structure schematic diagram provided by a specific embodiment of the present invention;

[0046] Figure 3 is the schematic diagram of an example for reading circuit netlist information provided by a specific embodiment of the present invention;

[0047] Figure 4 is the schematic diagram of an example for reading circuit layout information provided by a specific embodiment of the present invention;

[0048] Figure 5 is the schematic diagram of an example for establishing a connectivity graph according to netlist information provided by a specific embodiment of the present invention;

[0049] Figure 6 is the schematic diagram of an example for identifying matching relationships and matching types through a connectivity graph provided by a specific embodiment of the present invention;

[0050] Figure 7 is the schematic diagram of a rough layout example provided by a specific embodiment of the present invention;

[0051] Figure 8 is the schematic diagram of an example of an allowable merging operation provided by a specific embodiment of the present invention;

[0052] Figure 9It is a schematic diagram of the layout result of the final integrated circuit layout matching module provided by a specific embodiment of the present invention;

[0053] Figure 10 It is a schematic framework diagram of the layout of the integrated circuit layout matching module provided by a specific embodiment of the present invention;

[0054] Figure 11 It is a structural block diagram of a layout system for an integrated circuit layout matching module of the present invention. Specific embodiments

[0055] The following further elaborates on the present invention in detail in conjunction with the accompanying drawings and specific embodiments. For the step numbers in the following embodiments, they are only set for the convenience of elaboration and explanation, and no limitation is imposed on the order between steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0056] Digital circuits and their automatic design technologies have become increasingly mature, enabling large-scale and highly complex layout automation design. However, the diverse requirements for integrated circuit functions have led to an increasing proportion of mixed circuits of analog and digital circuits in the system-on-chip. Since analog circuits and digital circuits are very different, the automatic design methods of digital circuits cannot be applied. Moreover, the relatively lagging automation level of analog circuits has slowed down the development speed of analog integrated circuit design. Currently, the design of analog circuits still mainly relies on manual design, and factors such as its long cycle and high cost have attracted much attention in the academic and industrial circles.

[0057] The layout method of digital integrated circuit layouts is generally a layout method based on routing channel allocation. Since the component sizes in digital integrated circuit layouts are smaller, composed of various repetitive units, and the parasitic parameters of the traces do not need to be considered in digital integrated circuit layouts, and the traces can use a uniform line width, in terms of layout, a grid-based or standardized layout method is usually adopted, leaving sufficient spacing between units for routing. This layout method requires reserving space for the routing channels in advance, and in order to meet the DRC requirements (physical design rule requirements) between the traces, the lanes in the channels are spaced far apart from each other, resulting in the layout occupying additional layout area, which is not applicable in analog integrated circuits.

[0058] Currently, the mainstream layout methods for analog integrated circuit layouts include manual layout, automatic layout based on machine learning, automatic layout based on constraint conditions, automatic layout based on templates, etc.

[0059] Manual layout is a traditional layout method, which can achieve good layout results in small-scale analog integrated circuits, but the layout difficulty increases sharply in large-scale analog integrated circuits, and a large amount of manpower and time are required to achieve a satisfactory layout.

[0060] Machine learning-based automatic placement is an emerging automatic placement technology that has received much attention in recent years. By using a large amount of instance placement data and corresponding labels, the machine learning model can learn the rules and characteristics of placement, so as to achieve efficient placement of complex analog integrated circuits. The advantage of this method is that it can significantly reduce the human input and show better results in the placement of large-scale integrated circuits, but its performance is limited by the quality and quantity of the data used.

[0061] Constraint-based automatic placement is another common automatic placement method. It guides the placement process by introducing various physical and electrical constraints during the placement process, such as circuit performance, power consumption, wiring length, etc., to ensure that the placement result meets the design requirements. This method usually uses heuristic algorithms or optimization algorithms to search for the optimal placement scheme. Therefore, this method has a high complexity and a slow placement speed, but it has been proven to be an effective placement method in practice.

[0062] Template-based automatic placement realizes automatic placement through pre-designed placement templates. Designers can create a series of placement templates according to the characteristics and requirements of the circuit and select the appropriate template for application when placement is needed. This method can improve the placement efficiency and consistency to a certain extent, especially suitable for circuit placement tasks with high repeatability. The main disadvantage of this placement method is its poor flexibility.

[0063] Based on this, with reference to Figure 1 , the present invention provides a layout method for an integrated circuit layout matching module, and the method includes the following steps:

[0064] S100. Obtain the attribute information of the component modules of the integrated circuit netlist and the attribute information of the component modules of the integrated circuit layout, and perform matching grouping processing to obtain the grouped component modules;

[0065] Specifically, read the netlist information of the integrated circuit to obtain the attribute information of the component modules of the integrated circuit netlist. The attribute information of the component modules of the integrated circuit netlist includes the netlist name of the component module, the device type of the component module, the netlist port name information of the component module, the parameter information of the component module, and the connection relationship between the ports of the component module;

[0066] Read the layout information of the integrated circuit to obtain the attribute information of the component modules of the integrated circuit layout. The attribute information of the component modules of the integrated circuit layout includes the layout name of the component module, the layout port name information of the component module, the size information of the component module, the layout position information of the component module, the layout rotation information of the component module, the layout mirror information of the component module, and the geometric parameter information of the component module;

[0067] In this embodiment, the netlist and layout of the integrated circuit are input. All module connection relationships and corresponding attribute information are obtained by reading the circuit netlist and layout. Among them, the node information connected to all ports of all modules can be read from the netlist. By traversing, all connection ports of the same node can be found, and then all connected modules can be found to obtain all module connection relationships. The input netlist of the integrated circuit supports the input of netlists in multiple mainstream formats such as CDL, SPICE, and VERILOG. The input layout of the integrated circuit supports the input of layouts in multiple mainstream formats such as GDSII, CIF, and OASAS.

[0068] Among them, it should be noted that according to the label information of the component modules in the integrated circuit layout, the layout name of the component module and the layout port name information of the component module are determined; according to the label position information of the component modules in the integrated circuit layout, the layout position information and the geometric parameter information of the component module are determined; according to the rectangular bounding box size information of the component modules in the integrated circuit layout, the size information of the component module is determined; by combining the label information of the component module and the layout port name information of the component module, the layout rotation information and the layout mirror information of the component module are determined; the layout name of the component module, the layout port name information of the component module, the size information of the component module, the layout position information of the component module, the layout rotation information of the component module, the layout mirror information of the component module, and the geometric parameter information of the component module are integrated to obtain the attribute information of the component module in the integrated circuit layout.

[0069] In this embodiment, the name of the module is obtained through the label information above the module in the layout. The label position above the module represents the layout position of the module. The geometric shape composition of the module can also be identified through the label position. The size of the module is equal to the rectangular bounding box size of all geometric shapes of the module. The port information of the module is identified through the label information above the module port. The layout rotation and layout mirror information of the module can be obtained by analyzing the module label information and port information. Thus, all attribute information of the module in the layout is obtained.

[0070] The matching relationship and matching type between component modules are determined according to the attribute information of the component modules in the integrated circuit netlist and the attribute information of the component modules in the integrated circuit layout. The matching types include differential pair matching type, current mirror matching type, resistor array matching type, and capacitor array matching type.

[0071] Furthermore, it should be noted that the name of the module is unique. The binding relationship between the module in the integrated circuit netlist information and the module in the layout is established according to the name of the module. The module attribute information addresses in the integrated circuit netlist and the integrated circuit layout can be obtained according to the name of the module, and the attribute information of the module can be called and modified according to the module attribute information address.

[0072] Group the component modules according to the matching relationship and matching type between the component modules to obtain the grouped component modules.

[0073] Among them, it should be noted that the matching relationship between the component modules is determined according to the netlist name and layout name of the component modules; through the path search algorithm, the component modules are regarded as nodes, and the matching relationship between the component modules is regarded as connection edges, and the search is carried out from the common nodes of the component modules to construct the connected graph structure of the component modules; the matching type of the component modules is determined according to the connected graph structure of the component modules; the component modules are grouped according to the matching type of the component modules to obtain the grouped component modules.

[0074] In this embodiment, when the method of identifying from the circuit netlist is adopted, starting from common nodes such as ground or power supply, each module is searched through the path search algorithm. Each module is used as a node, and the connection relationship between the modules is used as the connection edge between the nodes to establish a connected graph structure. Among them, the edge not only stores the module information it connects, but also stores the port name information of the module it connects. By parsing the graph structure, around the essential connection relationship of each matching type, the relevant modules corresponding to this matching type are searched. When the method of identifying from the circuit layout is adopted, the matching relationship between the modules is obtained by identifying the modules in a specific range, and then the attribute information of the modules in the netlist and layout is obtained according to the module name. According to the above information, the matching type between the modules is identified, and the modules are grouped according to the principle of whether there is a matching relationship. The modules with a matching relationship between them will be classified as the same group of matching modules.

[0075] More specifically, the netlist recognition method starts from common nodes such as ground or power supply, searches for each module through a path search algorithm, takes each module as a node, and the connection relationship between modules as the connection edge between nodes to establish a connected graph structure. Among them, the connection edge between nodes not only stores the module information corresponding to the node, but also stores the information of the module port name connected to it. Iterate each matching type, search for all matching modules of this matching type by parsing the graph structure and the essential connection relationship of this matching type, and group them according to their matching relationship; while the layout recognition method identifies and groups the matching types of modules within a specific range. The matching modules in the same group only include the relevant modules with a matching relationship between them. The path search algorithm includes graph search algorithms such as DFS, BFS, GBFS, and algorithms improved based on these graph search algorithms.

[0076] In summary, according to the matching type to be recognized, find the corresponding essential connection relationship, and then further identify through graph search. Generally speaking, the essential connection relationship of a differential pair is that the source electrodes are connected and the connected node is a non-common node, the substrates are connected, the gate electrodes are not connected, the drain electrodes are not connected. In addition, the differential pair also has the characteristic of the same size; the essential connection relationship of a current mirror is that the gate electrodes are connected and the gate electrode of one of them is connected to the drain electrode, the substrates are connected, the source electrodes are connected and the connected node is a common node, and the drain electrodes are not connected. However, some special structures such as the cascode current mirror structure still need to be identified by an additional mechanism. The matching types include differential pair matching types, current mirror matching types, resistor array matching types, capacitor array matching types, etc., which are matching types that need to be noted in the integrated circuit design process. Whether there is a matching relationship between modules is obtained by parsing the graph structure or extracting the layout information. The modules with a matching relationship belong to the same group of matching modules and have the same matching type. For the rough layout, only the relative position relationship between modules needs to be determined, and operations such as rotating, mirroring, or port transformation of the modules are performed to make the port directions of the modules in the same row / column the same, and the placement centroids of all ports with the same node are the same.

[0077] S200. Obtain the relative layout position information of the grouped component modules and perform a merging operation to obtain the merged component modules;

[0078] Specifically, according to the preset matching principles, perform a preliminary layout on the grouped component modules to obtain the relative layout position information of the grouped component modules. The preset matching principles include same direction, common centroid, and symmetry;

[0079] More specifically, according to the matching type and matching principles such as in the same direction, common centroid, symmetry, etc., the number of modules in each row and each column of the module is calculated, and then the accurate relative position of the module in which row and which column is calculated, that is, starting from the lower left corner, it is calculated which row and which column the module will be laid out in. At the same time, the rotation and mirror properties of the module in the layout are adjusted so that the modules in the same row / column have the same direction. The specific direction of the modules in the same row / column is determined by the matching type, and at the same time, the ports of the modules that need to be merged are adjacent.

[0080] Further, it should be noted that the preset merge operation behaviors include not allowing merge operation behavior, allowing well merge operation behavior, and allowing well and port merge operation behavior. Among them, the not allowing merge operation behavior means the default operation behavior of adjacent grouped component modules; the allowing well merge operation behavior means that if the well types of adjacent grouped component modules are the same, the allowing well merge operation behavior is adopted; the allowing well and port merge operation behavior means that if the well types of adjacent grouped component modules are the same and there are at least one port with the same node information, and the port sizes are the same and the directions are opposite, the allowing well and port merge operation behavior is adopted.

[0081] Among them, for all adjacent module pairs, a merge judgment is made. The first time, the allowable merge operations of all adjacent modules are judged, that is, three operations: not allowing merge, allowing well merge, and allowing well and port merge. This judgment needs to be comprehensively judged according to the module type, module port node information, etc. According to the first judgment information, the result of the first judgment is unified as the second merge judgment information, and its feature is that the merge between all modules is to improve the merge degree as much as possible on the basis of legal merge to achieve the effect of compacting and saving the layout area.

[0082] In this embodiment, the same group of matching modules are laid out together. According to the matching principles such as in the same direction, common centroid, symmetry, etc., the number of modules in each row and each column of the module is calculated. Then, according to the best matching principle, the same group of modules are roughly laid out to determine the relative layout position of the modules in each row and each column. The default merge operation for adjacent modules is not allowing merge. When the well types of adjacent modules are the same, the merge operation adopted is allowing well merge. On this basis, if there are at least one port with the same node information in adjacent modules respectively, and the port sizes are the same and the directions are opposite, the merge operation adopted is allowing well and port merge.

[0083] The layout of the Dummy module is the last step of the rough layout. If there is a Dummy module in the group of matching modules, after the rough layout of other modules is completed, the Dummy module is evenly distributed to the outermost side of the existing rough layout according to the matching principle. The Dummy module is an additional module added to ensure the consistency and good matching of the matching modules.

[0084] Construct a preset merging operation behavior, perform a merging operation in combination with the relative layout position information of the grouped component modules, and obtain the merged component modules.

[0085] Further, if there is information that does not allow merging in the module merging information, all the module merging information is set to not allow merging; otherwise, if there is information that allows well merging in the module merging information, all the module merging information is set to allow well merging; if neither of the above conditions is met, all the same-row / column module merging information is set to allow well and port merging, and all the same-column / row module merging information is set to allow well merging.

[0086] Among them, well merging includes the same-region merging of regions such as the N+ region, P+ region, NWell region, and PWell region between two modules. Port merging is to move the modules so that the M1 metals of the adjacent ports of the same nodes of the two modules completely overlap. If well merging is used between adjacent modules, the calculation of the center point spacing of the modules needs to be calculated based on the DRC rules to ensure that no other DRC problems are triggered after ignoring the well DRC problems between adjacent modules; if port merging is used between adjacent modules, there is no need to consider the DRC rules, and only the center point spacing between the modules in the case of port merging needs to be calculated.

[0087] S300. Obtain the minimum center point spacing between adjacent merged component modules and perform layout on the merged component modules to obtain the layout result of the integrated circuit layout matching module.

[0088] Specifically, obtain the minimum center point spacing between adjacent merged component modules.

[0089] It should be noted that if the adjacent merged component modules adopt the operation behavior that does not allow merging, the minimum center point spacing of the adjacent merged component modules is the minimum DRC distance between the adjacent merged component modules without overlap; if the adjacent merged component modules adopt the operation behavior that allows well merging, the minimum center point spacing of the adjacent merged component modules is the minimum DRC distance between the adjacent merged component modules without overlap under the condition of ignoring the well; if the adjacent merged component modules adopt the operation behavior that allows well and port merging, the minimum center point spacing of the adjacent merged component modules is the center point spacing of the adjacent merged component modules when the ports completely overlap.

[0090] In this embodiment, when the final merging operation adopted by the module does not allow merging, the minimum distance between the centers of adjacent modules is the minimum DRC distance between the modules without overlap; when the final merging operation adopted by the module allows well merging, the minimum distance between the centers of adjacent modules is determined by the minimum DRC distance between the modules without overlap when wells are ignored; when the final merging operation adopted by the module allows well and port merging, the minimum distance between the centers of adjacent modules is the center point distance of the modules when the ports completely overlap.

[0091] Determine the layout information of the component modules according to the minimum center point distance and in combination with the preset merging operation behavior;

[0092] Set the origin position of the layout information of the integrated circuit as the coordinate origin, and the total centroid position of the grouped component modules as the layout center point. In combination with the layout information of the component modules, layout the merged component modules to obtain the layout result of the integrated circuit layout matching module.

[0093] In this embodiment, the layout information of the modules in the integrated circuit layout includes the layout position information, rotation information, and mirror image information of the modules. Taking the origin position of the integrated circuit layout as the coordinate origin and the total centroid position of the matching modules in the same group as the layout center point of the matching modules in this group, calculate the layout information of the modules in sequence according to the module center point distance and the merging operation adopted by adjacent modules, so that the arrangement of the modules in each row / column is compact and meets the matching principle.

[0094] In summary, calculate the minimum value between the centers of adjacent modules after the above merging step, thereby obtaining all the adjacent distances of the modules in each row / column. Taking the central module in the rough layout as the center, its layout position remains unchanged, while the layout positions of the remaining modules need to be calculated according to the adjacent distances between the modules. Through the above calculation process, the detailed layout positions of all the modules can be obtained. According to the detailed layout position information of the modules obtained in the previous step, call the design tool to find the attribute information of each module in the layout, and modify the layout attribute information of the corresponding module, thereby generating the final layout layout.

[0095] To sum up, refer to Figure 10, in the embodiment of the present invention, the netlist information of the integrated circuit is read to obtain the attribute information of the module in the integrated circuit netlist; and the layout information of the integrated circuit is read to obtain the attribute information of the module in the integrated circuit layout. Furthermore, the matching relationship between the modules is identified according to the module attribute information in the circuit netlist and the layout, and the matching type between the modules is identified, and the modules are grouped. In the layout, the modules are roughly laid out according to the module attribute information to obtain the relative layout position information of the modules. Then, the allowed merging operations of the adjacent modules are sequentially judged, and the final merging operation adopted by the modules is judged according to the allowed merging information of the modules. Further, according to the merging operation adopted by the modules, the minimum distance between the central points of the adjacent modules is calculated, and the layout information of the modules in the integrated circuit layout is calculated according to the central point distance information of the modules. Finally, an integrated circuit design tool is called to modify the attribute information of the modules in the layout to generate the layout of the modules in the integrated circuit layout.

[0096] Therefore, the embodiment of the present invention has the following improvement points compared with the prior art:

[0097] 1) In terms of memory occupancy, compared with the automatic layout based on machine learning, since there is no need to train and store large models, the embodiment of the present invention saves a large amount of memory occupancy; compared with the automatic layout with a grid model, the present invention does not require the memory for constructing the grid.

[0098] 2) In terms of running efficiency, compared with the automatic layout based on machine learning or based on constraint conditions, the embodiment of the present invention saves a large amount of time for model calculation and iterative optimization; compared with the automatic layout with a grid model, its step length depends on the size of the grid block, and the calculation time is also limited by the number of grids passed. In a large-area layout, the running efficiency of the layout with a grid model decreases significantly. In the layout of the present invention, the distance between modules is an exact value and is not restricted, and the result can be obtained only by one calculation, and the running efficiency is significantly better than that of the layout with a grid model.

[0099] 3) In terms of layout area, the embodiment of the present invention can handle DRC rules (physical design rules), and achieves the most compact layout by merging module ports. Compared with other automatic layout algorithms, the present invention has significant advantages in dealing with complex DRC rules (physical design rules) and increasing the layout compactness.

[0100] 4) In terms of layout performance, the embodiments of the present invention can identify the matching relationships and matching types between modules, and can also design different layout methods according to various matching types and the attribute information of various matching modules. In the detection of module merging, the present invention makes a judgment by detecting the module attribute information and the adjacent module port node information, and unifies all module merging schemes in the final judgment. In terms of layout flexibility and layout performance, the present invention can achieve a refinement degree approaching or even reaching that of manual layout.

[0101] Finally, taking the Figure 2 OTA circuit shown as an example, the embodiments of the present invention will be described in conjunction with the accompanying drawings:

[0102] 1) Read the netlist information of the integrated circuit;

[0103] The input netlist contains various information including modules, such as Figure 3 shown. Region 300 shows the source information of the netlist, region 301 shows the input / output node information of the netlist, region 302 shows the name information of the modules, region 303 shows the node information connected to each port of the modules, region 304 shows the module type information, and region 305 shows various size and parameter information of the modules.

[0104] 2) Read the layout information of the integrated circuit;

[0105] In Figure 4 (a), the input layout contains the physical information of the modules. Through preprocessing of the layout, there will be no overlapping situation between the modules in the input layout, and each module as shown in region 403 will be placed loosely, and each group of modules is allowed to be divided into a region for identifying matching relationships, such as regions 400, 401, and 402. There are two adjacent ways, horizontal and vertical, for adjacent modules in regions 404 and 405.

[0106] In Figure 4 (b), the module 403 is further analyzed. Point 406 is the midpoint of the module, and the layout attribute information of the module is recorded here using a label. Points 408, 409, and 410 are the centers of the three ports of the module respectively, and the port information of the module is recorded here using a label, and it can be recognized that regions 410, 411, and 412 are the port regions of the module.

[0107] 3) Identification of module matching relationships and matching types;

[0108] Establish a Figure 5 connected graph structure as shown according to the connection relationship information between the modules, where each node corresponds to Figure 2Each part shown, such as node 200 represents the GND node, node 201 represents the VDD node, and module 100 represents the module with the gate node as VB. Edges 500 - 509 represent the connection relationship between the ports of two modules, and the edge information includes the connection ports and the node information of this connection. As Figure 6 shown, after establishing the connected graph structure, starting from the common node, through path search, it is found that there is a matching relationship between group 600 and group 601, and through the connecting edges 503 - 505, it is identified that the matching group 600 is of the current mirror matching type, and through the connecting edges 501, 508, 509, it is identified that the matching group 601 is of the differential pair matching type.

[0109] If the method of identifying the match from the layout is adopted, then it is identified from the designated regions 400, 401, 402, excluding region 402 with only one module. The modules in region 400 are equivalent to the modules in matching group 600, and the modules in region 401 are equivalent to the modules in matching group 601.

[0110] 4) Roughly layout the modules according to the existing information;

[0111] According to the known matching information, following the matching principle of common centroid, roughly layout the scattered modules so that the placement of the modules meets the matching requirements. At the same time, the port positions of the modules also need to be adjusted so that the port positions also meet the matching principle of common centroid, and try to make the adjacent port nodes the same so that adjacent ports can be smoothly merged when the port merging operation is adopted. Compared with Figure 4 the original layout of a, after the rough layout Figure 7 already meets the rough matching placement, where the modules in region 700 correspond to the modules in region 400, the modules in region 701 correspond to the modules in region 401, and the modules in region 702 correspond to the modules in region 402.

[0112] 5) Merge and compress adjacent modules;

[0113] According to the allowed merge operations, merge and compress adjacent modules. As Figure 8 shown, if adjacent module merging is not allowed, then place the adjacent modules in manner 800. If adjacent module well merging is allowed, then place the adjacent modules in manner 801. If adjacent module well and port merging is allowed, then place the adjacent modules in manner 802. If the adopted merge method is not allowing merging or allowing well merging, then compress the distance between adjacent modules to the optimal without changing the merge operation.

[0114] 6) Output the layout of the modules after layout;

[0115] After the above steps are completed, call the integrated circuit design tool to modify the attribute information of the module in the layout, and output the modified layout. For example, Figure 9 As shown, the final layout result of the module in area 700 is the style shown in area S0, and the final layout result of the module in area 701 is the style shown in area S1.

[0116] Refer to Figure 11 , an integrated circuit layout matching module layout system, including:

[0117] The first module 1101 is used to obtain the attribute information of the component modules in the integrated circuit netlist and the attribute information of the component modules in the integrated circuit layout, and perform matching grouping processing to obtain the grouped component modules;

[0118] The second module 1102 is used to obtain the relative layout position information of the grouped component modules and perform a merging operation to obtain the merged component modules;

[0119] The third module 1103 is used to obtain the minimum center point distance between adjacent merged component modules and layout the merged component modules to obtain the integrated circuit layout matching module layout result.

[0120] The content in the above method embodiments is applicable to the system embodiments. The functions specifically implemented by the system embodiments are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0121] The above is a specific description of the preferred embodiments of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A method for layout matching module of integrated circuit, characterized in that: The following steps are involved: Acquire the attribute information of the component module of the integrated circuit netlist and the attribute information of the component module of the integrated circuit layout and perform matching and grouping processing to obtain the grouped component module; Obtaining relative layout position information of the grouped component modules and performing a merging operation to obtain a merged component module; The minimum center point spacing between adjacent merged component modules is obtained and the merged component modules are laid out to obtain the integrated circuit layout matching module layout result.

2. The integrated circuit layout matching module layout method according to claim 1, characterized in that: The step of obtaining the attribute information of the component modules of the integrated circuit netlist and the attribute information of the component modules of the integrated circuit layout and performing matching and grouping processing to obtain the grouped component modules specifically includes: Reading the netlist information of the integrated circuit to obtain the attribute information of the component module of the integrated circuit netlist, wherein the attribute information of the component module of the integrated circuit netlist includes the netlist name of the component module, the device type of the component module, the netlist port name information of the component module, the parameter information of the component module, and the connection relationship between the ports of the component module; Reading the layout information of the integrated circuit, obtaining the attribute information of the component module of the integrated circuit layout, wherein the attribute information of the component module of the integrated circuit layout includes the layout name of the component module, the layout port name information of the component module, the size information of the component module, the layout position information of the component module, the layout rotation information of the component module, the layout mirror information of the component module and the geometric parameter information of the component module; Determine the matching relationship and matching type between the component modules according to the attribute information of the component modules in the integrated circuit netlist and the attribute information of the component modules in the integrated circuit layout, wherein the matching type includes a differential pair matching type, a current mirror matching type, a resistor array matching type, and a capacitor array matching type; The component modules are grouped according to the matching relationship and matching type between the component modules to obtain grouped component modules.

3. The integrated circuit layout matching module layout method according to claim 2, characterized in that: The step of reading the layout information of the integrated circuit and obtaining the attribute information of the component module of the integrated circuit layout specifically includes: Determine the layout name of the component module and the layout port name information of the component module according to the label information of the component module of the integrated circuit layout; Determine the layout position information and geometric parameter information of the component module according to the label position information of the component module of the integrated circuit layout; Determine the size information of the component module according to the rectangular bounding box size information of the component module of the integrated circuit layout; Combining the label information of the component module with the layout port name information of the component module, determining the layout rotation information of the component module and the layout mirror information of the component module; The layout name of the component module, the layout port name information of the component module, the size information of the component module, the layout position information of the component module, the layout rotation information of the component module, the layout mirror information of the component module and the geometric parameter information of the component module are integrated to obtain the attribute information of the component module of the integrated circuit layout.

4. The integrated circuit layout matching module layout method according to claim 3, characterized in that: The step of grouping the component modules according to the matching relationship and matching type between the component modules to obtain the grouped component modules specifically includes: Determine the matching relationship between component modules according to the netlist name of the component module and the layout name of the component module; Through the path search algorithm, the component modules are regarded as nodes, the matching relationship between the component modules is regarded as the connection edge, and the common nodes of the component modules are searched to build the connected graph structure of the component modules; Determine the matching type of the component module according to the connectivity graph structure of the component module; The component modules are grouped according to the matching types of the component modules to obtain grouped component modules.

5. The integrated circuit layout matching module layout method according to claim 4, characterized in that: The step of obtaining the relative layout position information of the grouped component modules and performing a merging operation to obtain the merged component modules specifically includes: Preliminarily layout the grouped component modules according to preset matching principles to obtain relative layout position information of the grouped component modules, wherein the preset matching principles include same direction, common centroid and symmetry; Construct a preset merging operation behavior, perform a merging operation based on the relative layout position information of the grouped component modules, and obtain a merged component module.

6. The integrated circuit layout matching module layout method according to claim 5, characterized in that: The preset merging operation behavior includes a not allowing merging operation behavior, a allowing well merging operation behavior, and a allowing well and port merging operation behavior, wherein: The not-allowed-merge operation behavior indicates the default operation behavior of adjacent grouped component modules; The well merging operation behavior allowed means that if the well types of adjacent grouped component modules are the same, the well merging operation behavior allowed is adopted; The allowing well and port merging operation behavior indicates that if the well types of adjacent grouped component modules are the same and have at least one port with the same node information, and the ports are the same size and opposite directions, the allowing well and port merging operation behavior is adopted.

7. The integrated circuit layout matching module layout method according to claim 6, characterized in that: The step of obtaining the minimum center point spacing between adjacent merged component modules and laying out the merged component modules to obtain the layout result of the integrated circuit layout matching module specifically includes: Get the minimum center point spacing between adjacent merged component modules; Determine the layout information of the component module based on the minimum center point spacing and the preset merging operation behavior; The origin position of the integrated circuit layout information is set as the coordinate origin, and the total centroid position of the grouped component module is set as the layout center point. Combined with the layout information of the component module, the merged component module is laid out to obtain the integrated circuit layout matching module layout result.

8. The integrated circuit layout matching module layout method according to claim 7, characterized in that: The step of obtaining the minimum center point spacing between adjacent merged component modules specifically includes: If the adjacent merged component modules adopt the behavior of not allowing the merge operation, the minimum spacing between the center points of the adjacent merged component modules is the minimum DRC distance between the adjacent merged component modules without overlapping; If the adjacent merged component modules adopt the behavior of allowing well merging operation, the minimum spacing between the center points of the adjacent merged component modules is the minimum DRC distance between the adjacent merged component modules without overlapping when the wells are ignored; If the adjacent merged component modules adopt the behavior of allowing well and port merging operations, the minimum spacing between the center points of the adjacent merged component modules is the spacing between the center points of the adjacent merged component modules when the ports completely overlap.

9. An integrated circuit layout matching module layout system, characterized in that: Includes the following modules: The first module is used to obtain the attribute information of the component module of the integrated circuit netlist and the attribute information of the component module of the integrated circuit layout and perform matching and grouping processing to obtain the grouped component module; The second module is used to obtain the relative layout position information of the grouped component modules and perform a merging operation to obtain a merged component module; The third module is used to obtain the minimum center point spacing between adjacent merged component modules and layout the merged component modules to obtain the integrated circuit layout matching module layout result.

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