Heterogeneous integrated sensing and computing integrated circuit, chip and manufacturing method thereof

Abstract

The present disclosure relates to a heterogeneously integrated sensing, storage and computing integrated circuit, chip and its manufacturing method, wherein the sensing, storage and computing integrated circuit includes: a scanning signal line, a data signal line and a photoelectric detection module. The data signal line is used to provide a resistance conversion signal; the photoelectric detection module includes a first switch unit, a resistive storage unit and a photoelectric detection unit. In the first functional mode, the photoelectric detection unit generates a photocurrent according to the intensity of the image optical signal; in the second functional mode, the resistive storage unit stores the weighted resistance state based on the resistance conversion signal; in the third functional mode, the second common node provides a second total current; the first common node is used to provide a first total current, and the first total current and the second total current are used for image recognition. The sensing, storage and computing integrated circuit provided by the present disclosure can realize image acquisition, weight storage and calculation functions, and the first switch unit is bonded to the photoelectric detection unit, so that the sensing, storage and computing integrated circuit can realize photoelectric detection units compatible with multiple materials.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a heterogeneously integrated sensing, storage, and computing circuit, a chip, and a manufacturing method thereof. Background Art

[0002] With the rapid development of network information and artificial intelligence technology, the number of edge sensing devices has grown exponentially. The large amount of data transmission, storage and processing processes have brought huge challenges to the energy consumption and computing speed of the entire Internet of Things system. Therefore, it is necessary to produce integrated sensing, storage and computing chips.

[0003] In the field of image sensing, complementary metal oxide semiconductor (CMOS) sensors typically use silicon photodetectors. However, numerous other material systems exist, such as those based on mercury cadmium telluride (HgCdTe), indium antimonide (InSb), and aluminum gallium nitride (AlGaN). These photodetectors are incompatible with CMOS manufacturing processes. Therefore, developing integrated sensing, storage, and computing circuits compatible with multi-material photodetectors has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a heterogeneously integrated sensing, storage and computing integrated circuit, chip and its manufacturing method.

[0005] The present disclosure provides a heterogeneously integrated sensing, storage and computing integrated circuit, comprising: a plurality of scanning signal lines, a plurality of data signal lines and a plurality of photoelectric detection modules arranged in an array;

[0006] The scanning signal line is used to provide a conduction control signal;

[0007] The data signal line is used to provide a resistance conversion signal;

[0008] The photoelectric detection module includes a first switch unit, a resistive storage unit and a photoelectric detection unit;

[0009] The control end of the first switch unit in the same column is connected to the corresponding scan signal line, and the first end of the first switch unit in the same row is connected to the corresponding data signal line; the conduction control signal is used to control the on-off state of the first switch unit; the resistance state conversion signal is used to adjust the resistance state of the resistive memory unit;

[0010] The second end of the first switch unit is bonded to the first end of the photodetection unit, and the second end of the photodetection unit is electrically connected to the first common node; the first end of the resistive memory unit is connected to the second end of the first switch unit, and the second end of the resistive memory unit is electrically connected to the second common node; the first common node and the second common node are used to be electrically connected to an external control module;

[0011] In the first functional mode, the photoelectric detection module is used to turn on the first switch unit, so that the photoelectric detection unit generates a photocurrent according to the intensity of the optical signal of the detected image, and the first common node is used to output the photocurrent;

[0012] In the second functional mode, the photoelectric detection module is used to turn on the first switch unit so that the resistive memory unit is adjusted to the corresponding weighted resistance state based on the written resistance state conversion signal;

[0013] In the third functional mode, the photodetection module is used to turn on the first switch unit so that the resistive storage unit converts the photocurrent of the image into a resistive current based on the corresponding weighted resistance state;

[0014] Among them, the first common node is also used to provide a first total current, which is the sum of all photocurrents; the second common node is used to provide a second total current, which is the sum of all resistive currents; the first total current and the second total current are used to generate image recognition results under a preset algorithm.

[0015] Optionally, the sensing, storage and computing integrated circuit further includes: a first output module and a second output module; the first common node is connected to the first output module, and the second common node is connected to the second output module;

[0016] The first output module is used to convert the first total current into a first total voltage, and the second output module is used to convert the second total current into a second total voltage.

[0017] Optionally, the first output module includes a second switching unit and a first amplifying unit;

[0018] A control end of the second switch unit is connected to the external control module, a first end of the second switch unit is connected to the first common node, a second end of the second switch unit is connected to the first amplifying unit, and an output end of the first amplifying unit is connected to the external control module;

[0019] The first amplifying unit is used to convert the first total current into a first total voltage; the second switching unit is used to be turned on in the first functional mode to output the first total voltage to the external control module.

[0020] Optionally, the second output module includes a third switching unit and a second amplifying unit;

[0021] A control end of the third switch unit is connected to the external control module, a first end of the third switch unit is connected to the second common node, a second end of the third switch unit is connected to the second amplifying unit, and an output end of the second amplifying unit is connected to the external control module;

[0022] The second amplifying unit is used to convert the second total current into a second total voltage; the third switching unit is used to be turned on in a third functional mode to output the second total voltage to the external control module.

[0023] Optionally, when the ratio of the second total voltage to the first total voltage is greater than a first threshold, the recognized image is determined to be a target image.

[0024] Optionally, in the third functional mode, the data signal line is used to provide a 0V voltage.

[0025] The present disclosure also provides a heterogeneously integrated sensing, storage, and computing integrated chip, comprising a CMOS control chip and a detection array chip, wherein the CMOS control chip comprises a scanning signal line and a data signal line in any sensing, storage, and computing integrated circuit as described above, and a first switch unit and a resistive storage unit in a plurality of photoelectric detection modules arranged in an array; the detection array chip comprises a plurality of photoelectric detection units arranged in an array in any sensing, storage, and computing integrated circuit as described above;

[0026] The CMOS control chip further includes a plurality of first pads arranged in an array, the first pads being electrically connected to corresponding first switch units;

[0027] The detection array chip further includes a plurality of second pads arranged in an array, the second pads being electrically connected to corresponding photoelectric detection units;

[0028] The plurality of first pads of the CMOS control chip are bonded to the plurality of second pads of the detection array chip.

[0029] The present disclosure also provides a method for manufacturing a sensing-storage-computing integrated chip, which is applied to manufacturing the sensing-storage-computing integrated chip as described above, wherein the first switch unit includes a transistor; the manufacturing method includes:

[0030] The source, drain and gate of the transistor are fabricated on one side of the substrate of the CMOS control chip;

[0031] A resistive switching memory cell is fabricated on a side of the transistor where the source is away from the substrate;

[0032] The detection array chip is bonded to a side of the transistor source away from the substrate.

[0033] Optionally, a resistive switching memory cell is fabricated on a side of the transistor source away from the substrate, including:

[0034] A bottom electrode, a resistive dielectric layer and a top electrode are sequentially formed on a side of the source of the transistor away from the substrate.

[0035] Optionally, bonding the detection array chip to a side of the transistor source away from the substrate includes:

[0036] Making a first pad on a side of the source of the transistor away from the substrate;

[0037] Making a second pad electrically connected to the photoelectric detection unit on the detection array chip;

[0038] The first pad of the CMOS control chip is bonded to the second pad of the detection array chip.

[0039] The present disclosure provides a heterogeneously integrated sensing, storage and computing integrated circuit, chip and its manufacturing method. The sensing, storage and computing integrated circuit includes a plurality of scanning signal lines, a plurality of data signal lines and a plurality of photoelectric detection modules arranged in an array. Each photoelectric detection module includes a first switch unit, a resistive storage unit and a photoelectric detection unit. The scanning signal line is used to provide a conduction control signal to the photoelectric detection module to control the on and off of the first switching unit. The data signal line is used to provide a resistance state conversion signal to the photoelectric detection module to adjust the resistance state of the resistive storage unit. The photoelectric detection module has a first functional mode, a second functional mode and a third functional mode. In the first functional mode, all the first switching units are turned on in sequence, and the photoelectric detection unit corresponding to the turned-on first switching unit will generate a photocurrent that matches the detected optical signal intensity, and the first common node will output the generated photocurrent to the external control module. In the second functional mode, the first switch unit of the corresponding optical detection module is turned on, and the weighted resistance state is written into the corresponding resistive storage unit. In the third functional mode, all the first switch units are turned on, so that the resistive storage unit converts the photocurrent of the image into a resistive current based on the corresponding weighted resistance state, and all the resistive currents are accumulated at the second common node to obtain a second total current, which is output to the external control module. In the first functional mode, the second functional mode and the third functional mode, all the first switch units can be turned on to make the photocurrents generated by each photodetection unit converge to the first common node, so that all the photocurrents are accumulated at the first common node to obtain a first total current, which is output to the external control module. The external control module generates an image recognition result according to the first total current and the second total current under a preset algorithm to determine whether the captured image is a target image. Therefore, the sensing, storage and computing integrated circuit provided by the present disclosure can realize the functions of image acquisition, weight storage and calculation, thereby realizing the integration of sensing, storage and computing. In addition, the second end of the first switch unit is bonded to the first end of the photodetection unit, so that the photodetection units made of various materials can be heterogeneously integrated into the sensing, storage and computing integrated circuit provided by the present disclosure, thereby realizing that the sensing, storage and computing integrated circuit can be compatible with photodetection units of multiple materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 A schematic diagram of the structure of a sensing, storage and computing integrated circuit provided in an embodiment of the present disclosure.

[0042] Figure 2 A structural diagram of another sensing, storage and computing integrated circuit provided in an embodiment of the present disclosure.

[0043] Figure 3 A schematic diagram of the structure of a sensing, storage and computing integrated chip provided in an embodiment of the present disclosure.

[0044] Figure 4 A schematic flow chart of a method for manufacturing a sensing-storage-computing integrated chip provided in an embodiment of the present disclosure.

[0045] Figure 5 A cross-sectional schematic diagram of a sensing, storage, and computing integrated chip package provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating the examples of the present application.

[0047] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0048] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0049] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0050] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0051] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure. The first node, the second node and the third node are not actual circuit units.

[0052] It will be apparent to those skilled in the art that various modifications and variations can be made to this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application may be combined with each other unless there is any inconsistency.

[0053] Figure 1 This is a schematic diagram of a sensing, storage and computing integrated circuit provided by an embodiment of the present disclosure. Figure 1 As shown, the sensing, storage and computing integrated circuit includes: a plurality of scanning signal lines 100, a plurality of data signal lines 200 and a plurality of photoelectric detection modules 300 arranged in an array.

[0054] The photodetection module 300 includes a first switch unit 310, a resistive memory unit 320, and a photodetection unit 330. The control end of the first switch unit 310 in the same column is connected to the corresponding scan signal line 100, and the first end of the first switch unit 310 in the same row is connected to the corresponding data signal line 200. The second end of the first switch unit 310 is bonded to the first end of the photodetection unit 330, and the second end of the photodetection unit 330 is electrically connected to the first common node A; the first end of the resistive memory unit 320 is connected to the second end of the first switch unit 310, and the second end of the resistive memory unit 320 is electrically connected to the second common node B; the first common node A and the second common node B are used to electrically connect to the external control module 400.

[0055] Exemplarily, the first switch unit 310 and the photodetection unit 330 are connected by flip-chip bonding, so that the second end of the first switch unit 310 is bonded to the first end of the photodetection unit 330. By using flip-chip bonding to connect the first switch unit 310 and the photodetection unit 330, the first switch unit 310 can be connected to a photodetection unit 330 made of conventional CMOS-compatible silicon materials, and can also be connected to a photodetection unit 330 made of non-CMOS-compatible materials such as mercury cadmium telluride (HgCdTe), indium antimonide (InSb), and aluminum gallium nitride (AlGaN). This enables the photodetection units 330 made of various materials to be heterogeneously integrated into the integrated sensing, storage, and computing circuit provided by the present disclosure, and can also achieve the versatility of the integrated sensing, storage, and computing chip to meet different band requirements and different scenario requirements. In addition, the use of flip-chip bonding can reduce signal delay and improve heat dissipation, thereby facilitating the realization of large-scale integrated sensing, storage, and computing arrays.

[0056] It should be noted that the flip-chip bonding method used in the present disclosure to achieve heterogeneous integration of the photoelectric detection unit into the sensing, storage and computing integrated circuit is only an example. It can also be achieved by using methods such as micro-transfer technology, three-dimensional interconnect integration or wafer-level bonding, and no specific limitation is made here.

[0057] The scan signal line 100 is used to provide a conduction control signal, and the conduction control signal is used to control the on-off state of the first switch unit 310 .

[0058] Exemplarily, the first switch unit 310 may be a transistor, for example, and the conduction control signal may be a high level signal or a low level signal. The on-off state of the first switch unit 310 is controlled by controlling the gate voltage of the first switch unit 310 .

[0059] The data signal line 200 is used to provide a resistance-state conversion signal, and the resistance-state conversion signal is used to adjust the resistance state of the resistive memory cell.

[0060] For example, the resistance state in the resistive memory cell can be changed from a high resistance state to a low resistance state, or from a low resistance state to a high resistance state, by adjusting the voltage of the resistance conversion signal.

[0061] In the first functional mode, the photodetection module 300 is used to turn on the first switch unit 310 so that the photodetection unit 330 generates a photocurrent according to the intensity of the optical signal of the detected image, and the first common node A is used to output the photocurrent.

[0062] Specifically, in the first functional mode, the photodetection module 300 collects image data for the image to be captured. The scanning signal line 100 provides a conduction control signal to sequentially turn on the first switch units 310 of all photodetection modules 300. At this time, the data signal line 200 provides a low-level voltage. When the corresponding first switch unit 310 is turned on, the photodetection unit 330 of the photodetection module 300 corresponding to each pixel of the image to be captured generates a photocurrent that matches the optical signal intensity of the detected pixel. This photocurrent is then output to the external control module via the first common node A. This achieves image capture by collecting the photocurrent corresponding to the optical signal intensity of each pixel.

[0063] In the second functional mode, the photodetection module 300 is used to turn on the first switch unit 310 so that the resistive memory unit 320 is adjusted to a corresponding weighted resistance state based on the written resistance state conversion signal.

[0064] Exemplarily, the resistive memory unit 320 is used to implement analog storage, and can store various types of resistance states, such as a high resistance state, a low resistance state, or an analog resistance value.

[0065] As an example, in the second functional mode, the photodetection module 300 is used to turn on the first switch unit 310 so that the resistive memory unit 320 is adjusted to a corresponding weighted resistance state based on the written resistance state conversion signal. The weighted resistance state can be, for example, an analog resistance value. The present disclosure writes the resistance state conversion signal provided by the data signal line 200 into the resistive memory unit 320 through the turned-on first switch unit, so that the weighted resistance state of the resistive memory unit 320 is adjusted to the corresponding analog resistance value. Thus, the present disclosure implements a weighted resistance state storage function.

[0066] As another example, in the second functional mode, the weighted resistance state of the target image is stored in the resistive storage unit 320 of the corresponding photodetection module 300 , and the weighted resistance state may be, for example, a high resistance state or a low resistance state.

[0067] When storing high-resistance and low-resistance state information in the resistive memory cells 320 of the multiple photodetection modules 300, the scanning signal lines 100 connected to the first switch units 310 of the multiple photodetection modules 300 in the first row first provide a conduction control signal to turn on the first switch units 310 in the first row. The multiple data signal lines 200 corresponding to the multiple photodetection cells 330 in which high-resistance state information needs to be stored first provide a high-resistance voltage to store the high-resistance state information in some of the resistive memory cells 320. Then, the multiple data signal lines 200 corresponding to the multiple photodetection cells 330 in which low-resistance state information needs to be stored provide a low-resistance voltage to store the low-resistance state information in another portion of the resistive memory cells 320, thereby storing the high-resistance and low-resistance state information in the photodetection modules 300 in the first row. The weighted resistance state is then filled in the same way for the photodetection modules 300 in the next row until the weighted resistance state storage is completed for all rows of photodetection modules 300.

[0068] When storing high-resistance and low-resistance information in the resistive memory cells 320 of the multiple photodetection modules 300, the data signal lines 200 corresponding to the multiple photodetection modules 300 in the first column can be supplied with a high-resistance voltage, and the scanning signal lines 100 connected to the rows of photodetection modules 300 corresponding to the high-resistance information to be stored can be supplied with a conduction control signal to turn on some of the first switch units 310, thereby storing the high-resistance information. Subsequently, the data signal lines 200 corresponding to the multiple photodetection modules 300 in the first column can be supplied with a low-resistance voltage, and the scanning signal lines 100 connected to the rows of photodetection modules 300 corresponding to the low-resistance information to be stored can be supplied with a conduction control signal to turn on some of the first switch units 310, thereby storing the low-resistance information. Thus, the high-resistance and low-resistance information are stored in the photodetection modules 300 in the first column. The weighted resistance state can be filled in the same manner for the photodetection modules 300 in the next column until the weighted resistance state storage is completed for all columns of photodetection modules 300. Therefore, the present disclosure realizes the weight resistance state storage function.

[0069] It should be noted that the weighted resistance states of analog resistance value, high resistance state and low resistance state are merely examples, and the weighted resistance states may also be other types of resistance states, which are not specifically limited here.

[0070] In the third functional mode, the photodetection module 300 is used to turn on the first switch unit 310 so that the resistive storage unit 320 converts the photocurrent of the image into a resistive current based on the corresponding weighted resistance state, and the second common node B is used to provide a second total current, which is the sum of all resistive currents.

[0071] Exemplarily, in the third functional mode, all scanning signal lines 100 provide conduction control signals, turning on the first switch units 310 of all photodetection modules 300, and the photodetection units 330 of all photodetection modules 300 generate photocurrents based on the optical signal intensity of the detected image. The resistive switching storage units 320 of all photodetection modules 300 convert the photocurrents generated by the corresponding photodetection units 330 into resistive switching currents based on the weighted resistance states stored in the second functional mode. All generated resistive switching currents are accumulated at the second common node B to obtain a second total current, which is output to the external control module 400, thereby completing the calculation function.

[0072] The first common node is further used to provide a first total current, which is the sum of all photocurrents; the first total current and the second total current are used to generate an image recognition result under a preset algorithm.

[0073] Specifically, since the first common node A is the output node at which the photodetection unit 330 directly outputs the photocurrent to the external control module 400, and the second common node B is the output node at which the resistive current generated by adding weighted resistance state information to the photocurrent output by the photodetection unit 330 is output to the external control module 400, it is possible to simultaneously collect the photocurrent generated by one or more photodetection units 330 and their corresponding resistive currents. Therefore, in the first functional mode, the second functional mode, and the third functional mode, all of the first switching units 310 can be turned on to converge the photocurrents generated by each photodetection unit 330 to the first common node A, so that all of the photocurrents are accumulated at the first common node A to obtain a first total current, which is then output to the external control module.

[0074] An analog-to-digital conversion unit is provided in the external control module 400. The external control module 400 converts the received first total current and the second total current into voltages, and converts the analog signals of the converted voltages into digital signals. The collected image information is compared with the image information of the target image under a preset algorithm to determine the image recognition result.

[0075] In the first functional mode of the present disclosure, all first switch units are turned on in sequence, and the photoelectric detection unit corresponding to the turned-on first switch unit will generate a photocurrent that matches the detected optical signal intensity, and the first common node will output the generated photocurrent to the external control module. In the second functional mode, the first switch unit of the corresponding optical detection module is turned on, and the weighted resistance state is written into the corresponding resistive storage unit. In the third functional mode, all first switch units are turned on, so that the resistive storage unit converts the image photocurrent into a resistive current based on the corresponding weighted resistance state. All resistive currents are accumulated at the second common node to obtain a second total current, which is output to the external control module. In the first functional mode, the second functional mode, and the third functional mode, all first switch units can be turned on to accumulate all photocurrents at the first common node to obtain a first total current, which is output to the external control module. The external control module generates an image recognition result based on the first total current and the second total current under a preset algorithm to determine whether the captured image is the target image. Therefore, the sensing, storage, and computing integrated circuit provided by the present disclosure can realize the functions of image acquisition, weight storage, and calculation, thereby realizing sensing, storage, and computing integration. In addition, the second end of the first switching unit is bonded to the first end of the photoelectric detection unit, so that the photoelectric detection units made of various materials can be heterogeneously integrated into the sensing, storage and computing integrated circuit provided by the present invention, thereby realizing that the sensing, storage and computing integrated circuit can be compatible with photoelectric detection units made of multiple materials.

[0076] In some embodiments, Figure 2 A schematic diagram of the structure of another sensing, storage and computing integrated circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the integrated sensing, storage and computing circuit also includes: a first output module 510 and a second output module 520; the first common node A is connected to the first output module 510, and the second common node B is connected to the second output module 520; the first output module 510 is used to convert the first total current into a first total voltage, and the second output module 520 is used to convert the second total current into a second total voltage.

[0077] Specifically, in the first, second, or third functional modes, all scanning signal lines 100 provide on-control signals to turn on the first switch units 310 of all photodetection modules 300, and all data signal lines 200 provide low-level voltages. The photodetection units 330 of the photodetection modules 300 corresponding to each pixel of the image to be captured generate photocurrents based on the intensity of the detected optical signals. The photocurrents generated by each photodetection unit 330 are ultimately aggregated to a first common node A to achieve accumulation of all photocurrents. The first common node A outputs a first total current obtained by summing the photocurrents to the first output module 510. The first output module 510 converts the first total current into a first total voltage and outputs it to the external control module 400, thereby achieving image capture.

[0078] In the third functional mode, all scanning signal lines 100 provide conduction control signals, turning on the first switch units 310 of all photodetection modules 300, and the photodetection units 330 of all photodetection modules 300 generate photocurrents based on the optical signal intensity of the detected image. The resistive switching storage units 320 of all photodetection modules 300 convert the photocurrents generated by the corresponding photodetection units 330 into resistive switching currents based on the weighted resistance states stored in the second functional mode. All generated resistive switching currents are accumulated at the second common node B to obtain a second total current. The second common node B outputs the second total current to the second output module 520. The second output module 520 then converts the second total current into a second total voltage and outputs it to the external control module 400, thereby completing the calculation function.

[0079] In some embodiments, see Figure 2 The first output module 510 includes a second switching unit 511 and a first amplifying unit 512 .

[0080] The control end of the second switch unit 511 is connected to the external control module 400, the first end of the second switch unit 511 is connected to the first common node A, the second end of the second switch unit 511 is connected to the first amplifying unit 512, and the output end of the first amplifying unit 512 is connected to the external control module 400.

[0081] The first amplifying unit 512 is used to convert the first total current into a first total voltage; the second switching unit 511 is used to be turned on in the first functional mode to output the first total voltage to the external control module 400.

[0082] Specifically, in the first functional mode, the second functional mode or the third functional mode, the external control module 400 controls the second switch unit 511 to be turned on, and the photocurrents generated by each photodetection unit 330 are collected at the first common node A and output to the first amplification unit 512 through the turned-on second switch unit 511. The first amplification unit 512 converts the first total current into a first total voltage while also amplifying it to meet the voltage acquisition requirements of the external control module 400.

[0083] In some embodiments, see Figure 2 The second output module 520 includes a third switch unit 521 and a second amplifying unit 522 .

[0084] The control end of the third switch unit 521 is connected to the external control module 400, the first end of the third switch unit 521 is connected to the second common node B, the second end of the third switch unit 521 is connected to the second amplifying unit 522, and the output end of the second amplifying unit 522 is connected to the external control module 400.

[0085] The second amplifying unit 522 is used to convert the second total current into a second total voltage; the third switching unit 521 is used to be turned on in the third functional mode to output the second total voltage to the external control module 400.

[0086] Specifically, in the third functional mode, the external control module 400 controls the third switch unit 521 to be turned on, and the resistive currents generated by the corresponding resistive storage units 320 are collected at the second common node B and output to the second amplifying unit 522 through the turned-on third switch unit 521. The second amplifying unit 522 converts the second total current into a second total voltage while also amplifying it to meet the voltage acquisition requirements of the external control module 400.

[0087] In some embodiments, when the ratio of the second total voltage to the first total voltage is greater than a first threshold, the recognized image is determined to be a target image.

[0088] Specifically, the external control module is provided with an analog-to-digital conversion unit that converts the collected analog signals of the second total voltage and the first total voltage into digital signals. The external control module normalizes the second total voltage according to a preset algorithm, calculates the ratio of the second total voltage to the first total voltage, and compares the calculated ratio with a first threshold. If the ratio of the second total voltage to the first total voltage is greater than the first threshold, the recognized image is determined to be the target image. If the ratio of the second total voltage to the first total voltage is less than or equal to the first threshold, the recognized image is determined not to be the target image, thereby completing the recognition of the collected image. Furthermore, applying normalization to the second total voltage can improve the accuracy of image detection.

[0089] In some embodiments, in the third functional mode, the data signal line is configured to provide a voltage of 0V.

[0090] Specifically, in the third functional mode, after the scanning signal line provides a conduction control signal to turn on the first switch units of all photodetection modules, the data signal line provides a 0V voltage to each first switch unit, thereby avoiding interference with the calculation results of the third functional mode due to the voltage provided by the data signal line.

[0091] Figure 3 This is a schematic diagram of the structure of a sensing, storage and computing integrated chip provided by an embodiment of the present disclosure, such as Figure 3 The sensing, storage and computing integrated chip includes a CMOS control chip 610 and a detection array chip 620. The CMOS control chip 610 includes the scanning signal lines, data signal lines, and the first switch unit and resistive storage unit in the multiple photoelectric detection modules arranged in an array in the sensing, storage and computing integrated circuit corresponding to any of the above embodiments; the detection array chip includes the multiple photoelectric detection units arranged in an array in the sensing, storage and computing integrated circuit corresponding to any of the above embodiments.

[0092] The CMOS control chip 610 further includes a plurality of first pads 611 arranged in an array. The first pads 611 are electrically connected to corresponding first switch units.

[0093] The detection array chip 620 further includes a plurality of second pads 621 arranged in an array. The second pads 621 are electrically connected to corresponding photoelectric detection units.

[0094] The plurality of first pads 611 of the CMOS control chip 610 are bonded to the plurality of second pads 621 of the detection array chip 620 .

[0095] For example, the figure only shows a plurality of first pads 611 arranged in an array and a plurality of second pads 621 arranged in an array. The plurality of first pads 611 arranged in an array correspond one-to-one to the number and position of the plurality of photoelectric detection modules arranged in an array, and the plurality of second pads 621 arranged in an array also correspond one-to-one to the number and position of the plurality of photoelectric detection modules arranged in an array. Therefore, the plurality of first pads 611 arranged in an array correspond one-to-one to the number and position of the plurality of second pads 621 arranged in an array. After the plurality of first pads 611 and the plurality of second pads 621 are bonded and connected, the photoelectric detection unit is connected to the first switch unit, thereby forming a sensing, storage and computing integrated circuit. Moreover, the first pad 611 and the second pad 621 are bonded and connected, so that the photoelectric detection unit and the first switch unit are flip-chip bonded, so that the photoelectric detection units made of various materials can be heterogeneously integrated into the sensing, storage and computing integrated chip provided by the present disclosure, thereby realizing that the sensing, storage and computing integrated chip can be compatible with photoelectric detection units of multiple materials.

[0096] It should be noted that the flip-chip bonding method used in the present disclosure to achieve heterogeneous integration of the photoelectric detection unit into the sensing, storage and computing integrated circuit is only an example. It can also be achieved by using methods such as micro-transfer technology, three-dimensional interconnect integration or wafer-level bonding, and no specific limitation is made here.

[0097] Figure 4 This is a flow chart of a method for manufacturing a sensing-storage-computing integrated chip provided in an embodiment of the present disclosure. The method for manufacturing a sensing-storage-computing integrated chip is applied to manufacture the sensing-storage-computing integrated chip corresponding to the above embodiment, and the first switching unit includes a transistor.

[0098] like Figure 4 As shown, the manufacturing method includes: S710-S730.

[0099] S710 , fabricating a source, a drain, and a gate of a transistor on one side of a substrate of a CMOS control chip.

[0100] Specifically, Figure 5 A cross-sectional diagram of a sensing, storage, and computing integrated chip package provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, a source 811, a drain 812 and a gate 813 of a transistor are fabricated on one side of a substrate 810 of a CMOS control chip, and an insulating layer 814 is further fabricated between the gate 813 and the substrate 810, thereby completing the fabrication of the first switch unit.

[0101] S720 , fabricating a resistive memory cell on a side of the transistor source away from the substrate.

[0102] For details, see Figure 5 , a resistive switching memory unit is fabricated on a side of the source 811 of the transistor away from the substrate 810 , thereby completing the connection between the resistive switching memory unit and the source of the first switch unit.

[0103] S730 , bonding the detection array chip to the side of the source of the transistor away from the substrate.

[0104] For example, see Figure 5The transistor and the detection array chip are connected by flip-chip bonding, so that the source 811 of the transistor is bonded to the corresponding photodetection unit of the detection array chip. The flip-chip bonding method is used to connect the source 811 of the transistor to the photodetection unit, so that the source 811 of the transistor can be connected to the photodetection unit made of conventional CMOS-compatible silicon materials, and can also be connected to photodetection units made of non-CMOS compatible materials such as mercury cadmium telluride (HgCdTe), indium antimonide (InSb), and aluminum gallium nitride (AlGaN). This can achieve the versatility of the integrated sensing, storage, and computing chip under different band requirements and different scenario requirements. In addition, the flip-chip bonding method can reduce signal delay and improve heat dissipation, which is conducive to the realization of large-scale integrated sensing, storage, and computing arrays. In addition, the present disclosure realizes that photodetection units made of various materials can be heterogeneously integrated into the integrated sensing, storage, and computing chip provided by the present disclosure, and realizes that the integrated sensing, storage, and computing chip can be compatible with photodetection units of multiple materials.

[0105] In some embodiments, a resistive switching memory cell is fabricated on a side of a transistor source away from a substrate, including:

[0106] A bottom electrode, a resistive dielectric layer and a top electrode are sequentially formed on a side of the source of the transistor away from the substrate.

[0107] For example, see Figure 5 , a bottom electrode 815, a resistive dielectric layer 816, and a top electrode 817 are sequentially fabricated on the side of the transistor source 811 away from the substrate 810. The bottom electrode 815 generally requires high chemical stability and low reactivity, and is therefore made of an inert material to ensure that the interface with the resistive dielectric layer 816 remains stable during operation while providing good conductivity. The top electrode 817 is made of an active metal material, and the resistive dielectric layer 816 is generally made of at least one of a metal oxide, a chalcogenide, a perovskite material, an organic material, and a nitride. Among them, the metal oxide may be hafnium oxide, tantalum pentoxide, titanium dioxide, bismuth ferrite, and the like.

[0108] In some embodiments, bonding the detection array chip on a side of the transistor source away from the substrate includes: forming a first pad on a side of the transistor source away from the substrate.

[0109] A second pad electrically connected to the photoelectric detection unit is manufactured on the detection array chip.

[0110] The first pad of the CMOS control chip is bonded to the second pad of the detection array chip.

[0111] For example, the transistor and the detection array chip are connected by flip-chip bonding. Figure 5First, a first pad 611 is made on the side of the source 811 of the transistor away from the substrate 810, and a second pad 621 electrically connected to the photodetection unit is made on the detection array chip. The first pad 611 of the CMOS control chip is bonded to the second pad 621 of the detection array chip, thereby enabling the photodetection unit and the first switch unit to be flip-chip bonded, so that the photodetection units made of various materials can be heterogeneously integrated into the sensing, storage and computing integrated chip provided by the present invention, thereby realizing that the sensing, storage and computing integrated chip can be compatible with photodetection units of multiple materials.

[0112] It should be noted that the flip-chip bonding method used in the present disclosure to achieve heterogeneous integration of the photoelectric detection unit into the sensing, storage and computing integrated circuit is only an example. It can also be achieved by using methods such as micro-transfer technology, three-dimensional interconnect integration or wafer-level bonding, and no specific limitation is made here.

[0113] The above are merely specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not limited to these embodiments, but is to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A heterogeneously integrated sensing, storage and computing circuit, characterized in that: include: a plurality of scanning signal lines, wherein the scanning signal lines are used to provide a conduction control signal; a plurality of data signal lines, wherein the data signal lines are used to provide resistance conversion signals; A plurality of photoelectric detection modules arranged in an array, each of the photoelectric detection modules comprising a first switch unit, a resistive storage unit, and a photoelectric detection unit; The control terminals of the first switch units in the same column are connected to the corresponding scan signal lines, and the first terminals of the first switch units in the same row are connected to the corresponding data signal lines; the conduction control signal is used to control the on / off state of the first switch units; The resistance state conversion signal is used to adjust the resistance state of the resistive memory unit; The second end of the first switch unit is bonded to the first end of the photodetection unit, and the second end of the photodetection unit is electrically connected to the first common node; the first end of the resistive memory unit is connected to the second end of the first switch unit, and the second end of the resistive memory unit is electrically connected to the second common node; the first common node and the second common node are used to be electrically connected to an external control module; In the first functional mode, the photoelectric detection module is used to turn on the first switch unit, so that the photoelectric detection unit generates a photocurrent according to the optical signal intensity of the detected image, and the first common node is used to output the photocurrent; In the second functional mode, the photoelectric detection module is used to turn on the first switch unit so that the resistive memory unit is adjusted to a corresponding weighted resistance state based on the written resistance state conversion signal; In the third functional mode, the photodetection module is used to turn on the first switch unit, so that the resistive storage unit converts the image photocurrent into a resistive current based on the corresponding weighted resistance state; In which, the first common node is also used to provide a first total current, which is the sum of all photocurrents; the second common node is used to provide a second total current, which is the sum of all resistive currents; the first total current and the second total current are used to generate image recognition results under a preset algorithm.

2. The sensing, storage and computing integrated circuit according to claim 1, characterized in that: Also includes: A first output module and a second output module; the first common node is connected to the first output module, and the second common node is connected to the second output module; The first output module is used to convert the first total current into a first total voltage, and the second output module is used to convert the second total current into a second total voltage.

3. The sensing, storage and computing integrated circuit according to claim 2, characterized in that: The first output module includes a second switch unit and a first amplification unit; The control end of the second switch unit is connected to the external control module, the first end of the second switch unit is connected to the first common node, the second end of the second switch unit is connected to the first amplifying unit, and the output end of the first amplifying unit is connected to the external control module; The first amplifying unit is used to convert the first total current into the first total voltage; the second switching unit is used to be turned on in the first functional mode to output the first total voltage to the external control module.

4. The sensing, storage and computing integrated circuit according to claim 2, characterized in that: The second output module includes a third switch unit and a second amplifying unit; The control end of the third switch unit is connected to the external control module, the first end of the third switch unit is connected to the second common node, the second end of the third switch unit is connected to the second amplifying unit, and the output end of the second amplifying unit is connected to the external control module; The second amplifying unit is used to convert the second total current into the second total voltage; the third switching unit is used to be turned on in a third functional mode to output the second total voltage to the external control module.

5. The sensing, storage and computing integrated circuit according to claim 2, characterized in that: When the ratio of the second total voltage to the first total voltage is greater than a first threshold, the recognized image is determined to be a target image.

6. The sensing, storage and computing integrated circuit according to claim 1, characterized in that: In the third functional mode, the data signal line is used to provide a 0V voltage.

7. A heterogeneously integrated sensing, storage and computing chip, characterized in that: Comprising the sensing-storage-computing integrated circuit according to any one of claims 1 to 6; the sensing-storage-computing integrated chip comprises a CMOS control chip and a detection array chip, the CMOS control chip comprises a scanning signal line, a data signal line, and a first switch unit and a resistive storage unit in a plurality of photoelectric detection modules arranged in an array in the sensing-storage-computing integrated circuit; the detection array chip comprises a plurality of photoelectric detection units arranged in an array in the sensing-storage-computing integrated circuit; The CMOS control chip further includes a plurality of first pads arranged in an array, wherein the first pads are electrically connected to corresponding first switch units; The detection array chip further includes a plurality of second pads arranged in an array, wherein the second pads are electrically connected to corresponding photoelectric detection units; The plurality of first pads of the CMOS control chip are bonded to the plurality of second pads of the detection array chip.

8. A method for manufacturing a sensing-storage-computing integrated chip, characterized in that: Applied to manufacturing the sensing, storage and computing integrated chip according to claim 7, the first switch unit includes a transistor; the manufacturing method includes: Fabricating the source, drain and gate of the transistor on one side of the substrate of the CMOS control chip; Fabricating the resistive memory unit on a side of the source of the transistor away from the substrate; The detection array chip is bonded to a side of the source of the transistor away from the substrate.

9. The method for manufacturing a sensing-storage-computing integrated chip according to claim 8, characterized in that: The resistive memory unit is fabricated on a side of the source of the transistor away from the substrate, comprising: A bottom electrode, a resistive dielectric layer and a top electrode are sequentially formed on a side of the source of the transistor away from the substrate.

10. The method for manufacturing a sensing-storage-computing integrated chip according to claim 8, characterized in that: The step of bonding the detection array chip at a side of the source of the transistor away from the substrate comprises: fabricating the first pad on a side of the source of the transistor away from the substrate; Making the second pad electrically connected to the photoelectric detection unit on the detection array chip; The first pad of the CMOS control chip is bonded to the second pad of the detection array chip.

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