Formation method of semiconductor structure
By forming through holes and metal layers on the substrate surface in semiconductor manufacturing, and performing modification and planarizing grinding, the problem of high cost of chemical mechanical grinding process is solved, and the effect of reducing process costs and improving semiconductor structural performance is achieved.
Patent Information
- Application Number
- CN202510370175.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-06-13
AI Technical Summary
Chemical mechanical grinding process is costly in semiconductor manufacturing. As the number of processes increases, the machine loss and life decrease, and the process cost continues to increase.
By forming a dielectric layer on the substrate surface, etching forms through holes, forming a metal seed layer on the bottom and side walls of the through holes and the surface of the dielectric layer, modifying the metal layer, growing the initial metal layer and polishing to form a flush metal layer.
The deposition thickness of the metal layer on the surface of the dielectric layer is reduced, the mask time and cost are shortened, the planarization effect is improved, the performance of the semiconductor structure is improved, and the process cost is reduced.
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Figure CN120149265A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art
[0002] Chemical Mechanical Polishing (CMP) technology is a key step in semiconductor manufacturing to achieve high flatness on the surface of a wafer. It combines chemical and physical methods to smooth the substrate surface. Under a certain pressure and in the presence of a polishing liquid, the wafer and the polishing pad move relative to each other. By means of the organic combination between the mechanical grinding action of nano-abrasives and the chemical corrosion action of oxidants, catalysts, etc., substances are gradually peeled off from the wafer surface, thereby achieving a high flatness effect. This technology has the following advantages for device manufacturing: improving the overall flatness of the wafer plane, improving metal step coverage and its related reliability, and making it possible to increase the number of layers with a smaller chip size.
[0003] With the development of semiconductor manufacturing technology, the integration degree of wafers is continuously increasing, and the number of metal interconnect layers is constantly increasing. Taking copper as an example, the requirements for copper chemical deposition and copper chemical mechanical polishing processes are increasing. The chemical mechanical polishing process is a very costly process in wafer manufacturing. As the number of process times increases, the machine loss and life are reduced, and the process cost is also constantly increasing.
[0004] Therefore, reducing the cost of the chemical mechanical polishing process is a technical problem that urgently needs to be solved at present. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which reduces the deposition thickness of the metal layer on the surface of the dielectric layer, thus directly reducing the masking time and masking cost during the planarization process, and improving the planarization effect and the performance of the semiconductor structure.
[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a dielectric layer on the surface of the substrate; etching the dielectric layer to form a through hole in the dielectric layer, exposing a part of the surface of the substrate; forming a metal seed layer on the bottom surface and the side wall surface of the through hole and the surface of the dielectric layer; performing a modification treatment on the metal seed layer on the surface of the dielectric layer; growing an initial metal layer on the surface of the metal seed layer, the initial metal layer filling the through hole and extending to the surface of the dielectric layer, and the growth rate of the initial metal layer on the surface of the metal seed layer being inhibited; performing a planarization polish on the initial metal layer to form a metal layer in the through hole, and the top surface of the metal layer being flush with the surface of the dielectric layer.
[0007] Optionally, the growth rate of the initial metal layer on the metal seed layer on the surface of the dielectric layer is less than the growth rate of the initial metal layer on the metal seed layer on the bottom surface and the sidewall surface of the through hole.
[0008] Optionally, the method for modifying the metal seed layer on the surface of the dielectric layer includes: performing surface treatment on the metal seed layer on the surface of the dielectric layer with an inhibitor, and the inhibitor is adsorbed on the surface of the metal seed layer on the surface of the dielectric layer.
[0009] Optionally, the components of the inhibitor include: one or a combination of polyethylene glycol, polyvinylpyrrolidone, and imidazole derivatives. The concentration range of the inhibitor is 100–300 mg / L, the time range of the surface treatment is 5 min - 20 min, and the temperature range of the surface treatment is 20°C - 40°C.
[0010] Optionally, the aspect ratio range of the through hole is 2 - 5.
[0011] Optionally, the ratio range of the thickness of the metal seed layer to the minimum diameter of the through hole is 1:10 to 1:6.
[0012] Optionally, after forming the metal seed layer and before performing the modification treatment on the metal seed layer on the surface of the dielectric layer, it further includes: forming an initial filling layer on the surface of the metal seed layer; removing the initial filling layer on the surface of the metal seed layer on the surface of the dielectric layer to form a filling layer, and the filling layer fills the through hole.
[0013] Optionally, after performing the modification treatment on the metal seed layer on the surface of the dielectric layer and before growing the initial metal layer on the surface of the metal seed layer, it further includes removing the filling layer.
[0014] Optionally, the metal seed layer and the metal layer are made of the same metal material; the dielectric layer includes a barrier layer formed on the surface of the substrate, a low-k dielectric layer formed on the surface of the barrier layer, and an organosilicide layer formed on the low-k dielectric layer.
[0015] Optionally, the substrate includes a substrate and a device layer formed on the substrate, and the metal layer forms an electrical connection with the device layer.
[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0017] In the method for forming a semiconductor structure of the present invention, a dielectric layer is formed on the surface of a substrate, the dielectric layer is etched, and a through hole exposing a partial surface of the substrate is formed in the dielectric layer; a metal seed layer is formed on the bottom surface and the sidewall surface of the through hole and on the surface of the dielectric layer, the metal seed layer on the surface of the dielectric layer is modified, an initial metal layer is grown on the surface of the metal seed layer, the initial metal layer fills the through hole and extends onto the surface of the dielectric layer, the growth rate of the initial metal layer on the surface of the metal seed layer is inhibited, the initial metal layer is planarized and polished, a metal layer is formed in the through hole, and the top surface of the metal layer is flush with the surface of the dielectric layer; by inhibiting the growth rate of the initial metal layer on the surface of the metal seed layer, the thickness of the initial metal layer on the surface of the dielectric layer is reduced, so that the planarization polishing process can reduce the polishing time, greatly reduce the process cost, and improve the planarization effect, improve the performance of the semiconductor structure, and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 is a schematic structural diagram of a semiconductor structure in an embodiment;
[0019] Figures 2 to 10 is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION
[0020] As in the background art, the performance of the existing semiconductor structure is poor, and the following is a specific description.
[0021] First, please refer to Figure 1 , a semiconductor structure includes: a substrate (not shown in the figure); a dielectric layer 100 is formed on the surface of the substrate; the dielectric layer 100 is etched, and a through hole 101 exposing a partial surface of the substrate is formed in the dielectric layer 100; a metal seed layer 102 is formed on the surface of the through hole 101 and on the surface of the dielectric layer 100; an initial metal layer 103 is formed on the surface of the metal seed layer 102.
[0022] The inventors found that subsequently, the initial metal layer 103 is planarized until the surface of the dielectric layer 100 is exposed, and a metal layer is formed in the through hole. The growth rate of the initial metal layer 103 on the surface of the metal seed layer 102 is the same. While the initial metal layer 103 is formed in the through hole 101, the initial metal layer 103 will also be formed on the surface of the metal seed layer on the surface of the dielectric layer 100. As time goes by, after the through hole 101 is filled with the initial metal layer, the formed thickness (d) of the initial metal layer 103 on the surface of the dielectric layer 100 is relatively large. This will increase the difficulty in the process of planarizing the initial metal layer 103 on the surface of the dielectric layer 100, resulting in a longer grinding time and higher costs.
[0023] Through research, the inventors found that by modifying the metal seed layer on the surface of the dielectric layer, the growth rate of the initial metal layer on the modified metal seed layer is inhibited. That is to say, the formed thickness of the initial metal layer on the modified metal seed layer is thin. In the process of planarizing the initial metal layer until the surface of the dielectric layer is exposed, the grinding time and costs are significantly reduced, and the planarization effect is improved, enhancing the performance of the semiconductor structure, with a wide range of applications.
[0024] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the accompanying drawings.
[0025] Figures 2 to 10 It is a schematic diagram of the structures of the steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
[0026] First, please refer to Figure 2 , and provide a substrate 200.
[0027] A dielectric layer 201 is formed on the substrate 200. Specifically, a barrier layer 201-1 is formed on the surface of the substrate 200, a low-k dielectric layer 201-2 is formed on the surface of the barrier layer 201-1, and an organosilicide layer 201-3 is formed on the surface of the low-k dielectric layer 201-2.
[0028] The substrate 200 includes a substrate (not shown in the figure) and a device layer (not shown in the figure) formed on the substrate. The device layer can be a transistor or a plug, etc.
[0029] In this embodiment, the barrier layer 201-1 functions to block the diffusion of metal ions to prevent damage to the substrate 200.
[0030] In this embodiment, the silicide layer 201-3 ensures the surface flatness of the low-k dielectric layer 201-2.
[0031] Please refer to Figure 3 , etch the dielectric layer 201 to form a via hole 202 in the dielectric layer 201, exposing a part of the surface of the substrate 200.
[0032] In this embodiment, the aspect ratio of the via hole 202 ranges from 2 to 5. A suitable aspect ratio can ensure good filling and growth of the metal layer in the via hole 202, avoiding problems such as incomplete filling or difficult growth caused by the via hole 202 being too deep or too narrow, thereby improving the electrical performance and reliability of the semiconductor structure, and also helping to optimize the parameter settings of the manufacturing process.
[0033] In this embodiment, specifically, the damascene process is used to etch the silicide layer 201-3, the low-k dielectric layer 201-2, and the barrier layer 201-1 in sequence to form a via hole 202 in the dielectric layer 201, exposing a part of the surface of the substrate 200.
[0034] In this embodiment, the surface of the substrate 200 exposed by the via hole 202 is the area of the device layer that needs to be electrically connected.
[0035] In this embodiment, the via hole 202 is in the shape of "wider at the top and narrower at the bottom".
[0036] In some other embodiments, the via hole 202 can also be a hole with the same width at the top and bottom.
[0037] In this embodiment, the process for forming the via hole 202 is a dry etching process; in other embodiments, a wet etching process or a process combining a wet etching process and a dry etching process can also be used.
[0038] The reason for using the dry etching process to etch the dielectric layer 201 to form the via hole 202 is that the etching rate of the dry etching in the longitudinal direction is greater than that in the transverse direction, so that a via hole 202 with good surface quality can be formed in the longitudinal direction without damaging other devices in the transverse direction.
[0039] In this embodiment, the specific parameters of the dry etching process include: the gases used include CF 4 gas, CH 3 F gas and O 2 , the flow rate of the CF 4 gas is 5 sccm to 100 sccm, the flow rate of the CH 3 F gas is 8 sccm to 50 sccm, and the O 2The flow rate is from 10 sccm to 100 sccm, the chamber pressure is from 10 mtorr to 2000 mtorr, the RF power is from 50 W to 300 W, the bias voltage is from 30 V to 100 V, and the time is from 4 seconds to 50 seconds.
[0040] Please refer to Figure 4 , a metal seed layer 203 is formed on the bottom surface and the side wall surface of the through hole 202 and the surface of the dielectric layer 201.
[0041] In this embodiment, the process of forming the metal seed layer 203 is an atomic layer deposition process.
[0042] In some embodiments, the process of forming the metal seed layer 203 can also be a chemical vapor deposition process or the like.
[0043] In this embodiment, the material of the metal seed layer 203 is copper.
[0044] In some embodiments, the material of the metal seed layer 203 can also be other metals, such as cobalt (Co), tungsten (W), etc.
[0045] In this embodiment, the ratio range of the thickness of the metal seed layer 203 to the minimum diameter of the through hole 202 is from 1:10 to 1:6. The control of this parameter is crucial for the growth of the metal layer and the performance of the semiconductor structure. A suitable ratio can ensure that the metal seed layer 203 forms a good foundation on the bottom and side wall surfaces of the through hole 202, providing uniform support for the subsequent growth of the metal layer. At the same time, it avoids problems such as uneven growth or structural instability caused by the metal seed layer 203 being too thick or too thin, further improving the quality and consistency of the semiconductor structure, and contributing to the realization of high-precision and high-performance semiconductor manufacturing.
[0046] Before performing the modification treatment on the metal seed layer 203 on the surface of the dielectric layer 201, the process also includes please refer to Figures 5 to 6 .
[0047] Please refer to Figure 5 , an initial filling layer 204 is formed on the surface of the metal seed layer 203.
[0048] In this embodiment, the initial filling layer 204 is formed by a spin coating process.
[0049] In this embodiment, the material of the initial filling layer 204 is a bottom anti-reflection coating (BARC) material, such as an organic-inorganic hybrid material (such as SiOC, SiCN) and a silicon-containing silicone. It not only forms good adhesion with the through hole 202 to prevent peeling in subsequent processes; on the other hand, the material properties are stable, without physical or chemical changes, avoiding the introduction of impurities.
[0050] Please refer to Figure 6 , remove the initial filling layer 204 on the surface of the metal seed layer 203 on the surface of the dielectric layer 201 to form a filling layer 205, and the filling layer 205 fills the through hole 202.
[0051] In this embodiment, an etching process is used to remove the initial filling layer 204 on the surface of the metal seed layer 203 on the surface of the dielectric layer 201.
[0052] In this embodiment, a dry etching process is used to remove the initial filling layer 204 on the surface of the metal seed layer on the surface of the dielectric layer 201, including etching gases such as CF 4 , CHF 3 , O 2 , etc. are converted into plasma, and the high-energy ions and free radicals in the plasma are used to etch the BARC layer.
[0053] In some embodiments, a wet etching process or a nitrogen plasma etching process can also be used to remove the initial filling layer 204 on the surface of the metal seed layer on the surface of the dielectric layer 201.
[0054] Please refer to Figure 7 , perform a modification treatment on the metal seed layer 203 on the surface of the dielectric layer 201.
[0055] Figure 7 The small circles are used to distinguish the surface of the dielectric layer 201 after treatment.
[0056] In this embodiment, the method for performing a modification treatment on the metal seed layer 203 on the surface of the dielectric layer 201 includes: using an inhibitor to perform a surface treatment on the metal seed layer 203 on the surface of the dielectric layer 201, and the inhibitor is adsorbed on the surface of the metal seed layer 203 on the surface of the dielectric layer 201; it can effectively adjust the surface properties of the metal seed layer 203, thereby achieving control of the growth rate of the initial metal layer. Through the adsorption effect of the inhibitor, the activity of the metal seed layer 203 on the surface of the dielectric layer 201 can be precisely inhibited, making the growth of the metal layer in the through hole 202 more uniform and controllable, further optimizing the formation process of the semiconductor structure, and improving the controllability and repeatability of the process.
[0057] In this embodiment, the components of the inhibitor include: one or a combination of polyethylene glycol, polyvinylpyrrolidone, and imidazole derivatives. The concentration range of the inhibitor is 100–300 mg / L, the time range of the surface treatment is 5 min - 20 min, and the temperature range of the surface treatment is 20°C - 40°C.
[0058] Please refer to Figure 8, further including removing the filling layer 205.
[0059] In this embodiment, a cleaning process is adopted to remove the filling layer 205. For example, a water-based cleaning method combined with ultrasonic technology is used to remove the filling layer 205 (BARC layer) on the surface of the metal seed layer 203 through chemical action and physical vibration, which can completely remove the filling layer 205 (BARC layer) and is environmentally friendly.
[0060] Please refer to Figure 9 , an initial metal layer 206 is grown on the surface of the metal seed layer 203. The initial metal layer 206 fills the through hole 202 and extends to the surface of the dielectric layer 201, and the growth rate of the initial metal layer 206 on the surface of the metal seed layer 203 is inhibited.
[0061] In this embodiment, the growth rate of the initial metal layer 206 on the metal seed layer 203 on the surface of the dielectric layer 201 is less than the growth rate of the initial metal layer 206 on the metal seed layer 203 on the bottom surface and side wall surface of the through hole 202, which can more precisely control the growth direction and morphology of the metal layer. This difference in growth rate can ensure that the metal layer preferentially fills the through hole 202, avoiding excessive growth on the surface of the dielectric layer 201, thereby reducing the accumulation of the metal layer on the surface of the dielectric layer 201, further improving the flatness and stability of the semiconductor structure, and reducing the difficulty and cost of subsequent planarization grinding.
[0062] In this embodiment, the material of the metal layer is copper.
[0063] In other embodiments, the material of the metal layer can also be cobalt or tungsten.
[0064] In this embodiment, a chemical electroplating process is used to form a metal layer on the metal seed layer 203. The metal layer covers part of the side wall of the metal seed layer 203. Since the chemical electroplating process is essentially to connect the wafer to the cathode and place it in an acidic solution containing metal ions to be deposited, and at the same time place cobalt connected to the anode in the solution, so that the current flows from the copper electrode of the anode to the wafer of the cathode, and the ionized ions nucleate on the metal seed layer 203 and finally form the metal layer.
[0065] Please refer to Figure 10 , planarization grinding is performed on the initial metal layer 206 to form a metal layer 207 in the through hole 202, and the top surface of the metal layer 207 is flush with the surface of the dielectric layer 201.
[0066] In this embodiment, the surface of the metal layer 207 is flush with the surface of the low-k dielectric layer 201-2.
[0067] In this embodiment, during the process of planarization grinding of the initial metal layer 206, the silicide layer 201-3 is simultaneously ground away, exposing the surface of the low-k dielectric layer 201-2.
[0068] In this embodiment, a chemical mechanical polishing process is used to perform planarization grinding on the initial metal layer 206.
[0069] In this embodiment, by suppressing the growth rate of the initial metal layer 206 on the surface of the metal seed layer 203, the thickness of the initial metal layer 206 on the surface of the dielectric layer 201 is reduced. In this way, the planarization grinding process can reduce the grinding time, greatly reduce the process cost, and improve the planarization effect, enhancing the performance of the semiconductor structure, and having a wide range of applications.
[0070] In this embodiment, the metal layer forms an electrical connection with the device layer.
[0071] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dielectric layer on the surface of the substrate; Etching the dielectric layer to form a through hole in the dielectric layer that exposes a portion of the surface of the substrate; forming a metal seed layer on the bottom surface and sidewall surface of the through hole and the surface of the dielectric layer; Performing modification treatment on the metal seed layer on the surface of the dielectric layer; growing an initial metal layer on the surface of the metal seed layer, wherein the initial metal layer fills the through hole and extends to the surface of the dielectric layer, and the growth rate of the initial metal layer on the surface of the metal seed layer is suppressed; The initial metal layer is planarized and ground to form a metal layer in the through hole, wherein the top surface of the metal layer is flush with the surface of the dielectric layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: A growth rate of the initial metal layer on the metal seed layer on the surface of the dielectric layer is lower than a growth rate of the initial metal layer on the metal seed layer on the bottom surface and the sidewall surface of the through hole.
3. The method for forming a semiconductor structure according to claim 1, wherein: The method for modifying the metal seed layer on the surface of the dielectric layer includes: The metal seed layer on the surface of the dielectric layer is surface treated by using an inhibitor, and the inhibitor is adsorbed on the surface of the metal seed layer on the surface of the dielectric layer.
4. The method for forming a semiconductor structure according to claim 3, wherein: The components of the inhibitor include: one or a combination of polyethylene glycol, polyvinyl pyrrolidone and imidazole derivatives, the concentration range of the inhibitor is 100-300 mg / L, the time range of the surface treatment is 5min-20min, and the temperature range of the surface treatment is 20℃-40℃.
5. The method for forming a semiconductor structure according to claim 1, wherein: The aspect ratio of the through hole is in the range of 2-5.
6. The method for forming a semiconductor structure according to claim 1, wherein: The ratio of the thickness of the metal seed layer to the minimum diameter of the through hole is in a range of 1:10 to 1:
6.
7. The method for forming a semiconductor structure according to claim 1, wherein: After forming the metal seed layer and before modifying the metal seed layer on the surface of the dielectric layer, the method further includes: forming an initial filling layer on the surface of the metal seed layer; The initial filling layer on the surface of the metal seed layer on the surface of the dielectric layer is removed to form a filling layer, and the filling layer completely fills the through hole.
8. The method for forming a semiconductor structure according to claim 7, wherein: After the metal seed layer on the surface of the dielectric layer is modified and before the initial metal layer is grown on the surface of the metal seed layer, the method further includes removing the filling layer.
9. The method for forming a semiconductor structure according to claim 1, wherein: The metal seed layer and the metal layer are made of the same metal material; the dielectric layer comprises a barrier layer formed on the surface of the substrate, a low-k coefficient dielectric layer formed on the surface of the barrier layer, and an organic silicon compound layer formed on the low-k coefficient dielectric layer.
10. The method for forming a semiconductor structure according to claim 1, wherein: The base comprises a substrate and a device layer formed on the substrate, and the metal layer is electrically connected to the device layer.