A high-power semiconductor package and its preparation method

Abstract

The present invention discloses a high-power semiconductor package and a preparation method thereof, which relates to the field of semiconductor packaging technology. The high-power semiconductor package includes: a packaging substrate provided with a first wiring layer, a ceramic base provided with a second wiring layer, and a plurality of chips electrically connected to the second wiring layer; the ceramic base is embedded in the packaging substrate, and the ceramic base is electrically connected to the packaging substrate based on the third wiring layer; the packaging substrate is provided with a notch structure, and a first electrical channel is provided at the frame position of the notch structure, and a second electrical channel is provided in the internal area of ​​the notch structure. The packaging substrate is provided with a first electrical channel of a first height and a second electrical channel of a second height. The top of at least one chip placed on the ceramic base is connected to the first electrical channel through a metal connecting component. By using the packaging substrate inlaid with a wiring ceramic base layer, the current carrying capacity inside the package body is improved, the operating temperature of the device is reduced, and the working life of the device is extended.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a high-power semiconductor package and a preparation method thereof. Background Art

[0002] High-power semiconductor packages are electronic devices capable of handling high voltages and high currents, enabling functions such as converting electrical energy, controlling circuits, and changing voltage and frequency within electronic devices, whether direct current or alternating current. Existing high-power packages typically utilize die bonding on a metal frame or ceramic substrate, combined with wire bonding to achieve electrical connections between the chip and the substrate's electrodes.

[0003] Current wirebond connections, constrained by process requirements, result in taller and larger overall dimensions for high-power semiconductor packages. Wirebond transmission also creates significant parasitic inductance, which degrades the high-frequency performance of power devices and increases power losses. Furthermore, ceramic substrates with complex interconnect structures are typically expensive and difficult to manufacture. Summary of the Invention

[0004] The present invention aims to overcome the shortcomings of the prior art by providing a high-power semiconductor package and a method for manufacturing the same. By nesting a package substrate with a notched structure and a ceramic base, wire bonding is eliminated, achieving a miniaturized package. The chip is die-bonded to the base, improving heat dissipation, and electrical connectivity is achieved through the coordination of the base's wiring layers.

[0005] The present invention provides a high-power semiconductor package, comprising: a package substrate provided with a first wiring layer, a ceramic base provided with a second wiring layer, and a plurality of chips electrically connected to the second wiring layer;

[0006] The ceramic base is embedded in the packaging substrate, and the ceramic base is electrically connected to the packaging substrate based on the third wiring layer;

[0007] The first wiring layer is provided with a first electrical channel of a first height and a second electrical channel of a second height, the packaging substrate is provided with a notch structure, and the first electrical channel is provided at a border position of the notch structure, and the second electrical channel is provided in an inner area of ​​the notch structure;

[0008] The top electrode of the chip is connected to the bottom of the semiconductor package through a metal component and the first electrical channel to form a first electrical pin; at least one bottom electrode of the chip is connected to the bottom of the semiconductor package based on the second wiring layer of the ceramic base and the second electrical channel to form a second electrical pin.

[0009] Furthermore, a matching through groove is provided in the notch structure, and the ceramic base is embedded in the matching through groove;

[0010] The third wiring layer is located in the inner area of ​​the notch structure and is connected to the second electrical channel.

[0011] Furthermore, the second wiring layer is provided with a plurality of pad structures, and a plurality of chips are correspondingly attached to the plurality of pads;

[0012] The plurality of chips include a first chip and a second chip, wherein a first electrical type electrode is provided on the top of the first chip, and a second electrical type electrode and a third electrical type electrode are provided on the bottom of the first chip;

[0013] A fourth electrical type electrode, a fifth electrical type electrode and a sixth electrical type electrode are provided at the bottom of the second chip;

[0014] Bottom electrodes of the first chip and the second chip are fixed on the ceramic base based on a conductive medium.

[0015] Furthermore, the plurality of pad structures include a first pad for connecting to a second electrical electrode at the bottom of the first chip and a second pad for connecting to a bottom electrode of the second chip;

[0016] The first pad and the second pad are electrically connected to a second electrical path of the packaging substrate based on the third wiring layer.

[0017] Furthermore, a connection pad is provided on the top surface of the notch structure at a position corresponding to the first electrical channel;

[0018] The top electrode of the first chip is electrically connected to the connection pad based on an electrical connection component, and / or the top electrode of the second chip is electrically connected to the connection pad based on an electrical connection component.

[0019] Furthermore, the electrical connection component is a weldable metal sheet, or the electrical connection component is a metal sheet having a weldable metal layer.

[0020] Furthermore, the first pad and the second pad form an interconnection pad based on the third wiring layer, and the second electrical type electrode of the first chip and the fourth electrical type electrode of the second chip are electrically connected based on the interconnection pad.

[0021] Furthermore, the second wiring layer is provided with a first sub-pad connected to the fifth electrical type electrode of the second chip, and a second sub-pad connected to the sixth electrical type electrode of the second chip;

[0022] Passive components are mounted between the first sub-pad and the second sub-pad.

[0023] Furthermore, the bottom of the package substrate is provided with a first electrical pin and a second electrical pin; the bottom of the ceramic base is provided with a fifth electrical pin and a sixth electrical pin;

[0024] The first electrical pin is electrically connected to the first electrical channel, and the second electrical pin is electrically connected to the second electrical channel.

[0025] A fifth electrical channel and a sixth electrical channel are provided in the ceramic base. The fifth electrical channel is electrically connected to the fifth electrical pin, and the sixth electrical channel is electrically connected to the sixth electrical pin.

[0026] The present invention also provides a method for preparing a high-power semiconductor package, the method being used to prepare the high-power semiconductor package, the method comprising:

[0027] preparing a packaging substrate with a first wiring layer;

[0028] preparing a ceramic base with a second wiring layer;

[0029] Embedding and fixing the ceramic base in the packaging substrate;

[0030] preparing a third wiring layer on the ceramic base and the packaging substrate;

[0031] Fix the chip and passive components to the corresponding pad positions on the ceramic base through a conductive medium;

[0032] Soldering a first electrical connection component on the top surface of the first chip;

[0033] Performing plastic encapsulation on the substrate to obtain a package body;

[0034] The package body is divided into several semiconductor packages by a cutting device.

[0035] The present invention provides a high-power semiconductor package and a preparation method thereof, in which a high-heat dissipation ceramic base is directly embedded and arranged on a packaging substrate, and a wiring layer is provided on the packaging substrate and the ceramic base, so that the chip is electrically connected to the ceramic base and the packaging substrate based on mounting, meeting the integration and miniaturization packaging requirements of high-power semiconductor packaging, while reducing the parasitic resistance inside the package, and can effectively reduce the working heat of the package; by directly mounting the chip on the ceramic base based on the wiring layer, direct heat dissipation of the chip can be achieved, thereby improving the heat dissipation effect of the high-power semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 1 is a top view of the structure of a high-power semiconductor package according to an embodiment of the present invention;

[0037] Figure 2 is a cross-sectional view of the structure of a high-power semiconductor package according to an embodiment of the present invention;

[0038] Figure 3 is a bottom view of the structure of a high-power semiconductor package according to an embodiment of the present invention;

[0039] Figure 4 is a flow chart of a method for preparing a high-power semiconductor package according to an embodiment of the present invention;

[0040] Figure 5 Schematic diagram of the frame structure of the package substrate in an embodiment of the present invention;

[0041] Figure 6 2. It is a schematic diagram of the structure of a ceramic base in an embodiment of the present invention;

[0042] Figure 7 is a schematic diagram of the assembled packaging substrate and ceramic base in an embodiment of the present invention;

[0043] Figure 8 2 is a schematic diagram of the assembled structure of the package substrate and the ceramic base in an embodiment of the present invention;

[0044] Figure 9 This is a cross-sectional view of the assembled structure of the package substrate and the ceramic base in an embodiment of the present invention;

[0045] Figure 10 This is a schematic diagram of the connection structure of the chip and device mounted on the ceramic base in an embodiment of the present invention:

[0046] Figure 11 1 is a schematic diagram of a panel assembly with a top electrical connection component mounted thereon according to an embodiment of the present invention;

[0047] Figure 12 is a cross-sectional view of a state where a top electrical connection component is mounted in an embodiment of the present invention;

[0048] Figure 13 This is a schematic diagram of another state in which a top electrical connection component is mounted in an embodiment of the present invention;

[0049] Figure 14 This is a cross-sectional view of another structure in a state where a top electrical connection component is mounted in accordance with an embodiment of the present invention;

[0050] Figure 15 2 is a schematic diagram of the panel structure of the semiconductor package after plastic sealing in an embodiment of the present invention;

[0051] Figure 16 It is a cross-sectional view of the panel structure of the semiconductor package after plastic sealing in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0053] Example 1:

[0054] Figure 1 A schematic structural diagram of a high-power semiconductor package according to an embodiment of the present invention is shown; Figure 2 A cross-sectional view of the structure of a high-power semiconductor package according to an embodiment of the present invention is shown; Figure 3 A bottom view of the structure of a high-power semiconductor package in an embodiment of the present invention is shown; the high-power semiconductor package includes: a packaging substrate 2 provided with a first wiring layer 3, a ceramic base 1 provided with a second wiring layer 4, and a plurality of chips electrically connected to the second wiring layer 4, the first wiring layer 3 is arranged as a wiring structure of a vertical structure, and the bottom surface of the packaging substrate 2 is provided with electrical pins for connecting to an external working circuit. Based on the first wiring layer 3, the electrical connection between the top surface electrical structure of the packaging substrate 2 and the bottom electrical pins can be met.

[0055] The ceramic base 1 forms several chip bonding positions based on the second wiring layer 4, so that the chips of the high-power semiconductor package can be directly bonded on the ceramic base 1, and the ceramic base 1 adopts high heat dissipation material, which can timely conduct and dissipate the heat generated by the chip operation, thereby improving the heat dissipation efficiency of the semiconductor package.

[0056] Specifically, the ceramic base 1 is embedded in the packaging substrate 2, and the ceramic base 1 is electrically connected to the packaging substrate 2 based on the third wiring layer 5, so that the packaging substrate 2 can be wrapped around the periphery of the ceramic base 1, thereby improving the heat exchange efficiency between the first wiring layer 3 and the ceramic base 1 and achieving good heat dissipation effect.

[0057] Furthermore, the packaging substrate 2 can be a printed circuit board (PCB), which can meet the circuit layout design requirements, and the ceramic base 1 can be a copper bonding (DBC: Direct Bonding Copper) ceramic plate with good thermal conductivity to meet the heat dissipation requirements of the high-power semiconductor package.

[0058] Furthermore, by electrically connecting the ceramic base 1 and the internal circuit layer of the packaging substrate 2, the connection method of wire bonding can be reduced, so that the internal circuit arrangement of the high-power packaging device is compact, and miniaturized packaging and integrated packaging structure can be achieved.

[0059] Please refer to Figure 2 The first wiring layer 3 is provided with a first electrical channel 31 of a first height and a second electrical channel 32 of a second height, the first height is greater than the second height, the packaging substrate 2 is provided with a notch structure formed based on a groove, the frame position of the notch structure is provided with the first electrical channel 31, the first height is equal to the thickness of the frame position of the notch structure, so that the first electrical channel 31 can pass through the frame position of the notch structure of the packaging substrate 2, the internal area of ​​the notch structure is provided with the second electrical channel 32, the second height is equal to the thickness of the internal area position of the notch structure, so that the second electrical channel 32 can pass through the internal area of ​​the notch structure of the packaging substrate 2, through the staggered distribution of the first electrical channel 31 and the second electrical channel 32, the electrical connection position of the first wiring layer 3 can meet the electrical connection requirements of the top electrode and the bottom electrode of the chip, thereby improving the convenience of electrical connection between the packaging substrate 2 and the chip.

[0060] Furthermore, the notch structure is formed based on the height difference between the first height and the second height, so that the chip can be accommodated in the notch structure, thereby realizing compact packaging of the high-power semiconductor package and reducing the overall size of the high-power semiconductor package.

[0061] The top electrode of the chip is connected to the first electrical pin 21 at the bottom of the package based on the first electrical channel 31, and the bottom electrode of the chip is connected to the second electrical pin 22 at the bottom of the package based on the second electrical channel 32. The high-power semiconductor package forms a mounting portion with the external working circuit based on the first electrical pin 21 and the second electrical pin 22, thereby meeting the electrical connection requirements between the high-power semiconductor package and the external working circuit, and the bottom surface of the ceramic base 1 can be directly mounted on the external working circuit along with the bottom surface of the semiconductor package. In conjunction with the heat dissipation structure of the external working circuit, efficient heat dissipation can be achieved, thereby improving the heat dissipation efficiency of the high-power semiconductor package.

[0062] Furthermore, the first electrical channel 31 and the second electrical channel 32 pass through the top and bottom surfaces of the packaging substrate 2 in a vertical direction, and the first electrical channel 31 and the second electrical channel 32 are perpendicular to the bottom surface of the packaging substrate 2. The first wiring layer 3 is arranged in a vertical structure based on the first electrical channel 31 and the second electrical channel 32, thereby optimizing the circuit arrangement structure inside the packaging substrate 2, meeting the electrical connection requirements of the chip, and realizing the miniaturization and compact packaging of the high-power semiconductor package.

[0063] Specifically, a matching through-groove is provided in the notch structure, and the ceramic base 1 is embedded in the matching through-groove. By opening a matching through-groove in the middle of the notch structure of the packaging substrate 2, the ceramic base 1 can be embedded in the packaging substrate 2, and the top surface of the ceramic base 1 can be exposed on the top surface of the packaging substrate 2, and the bottom surface of the ceramic base 1 can be exposed on the bottom surface of the packaging substrate 2. The chip is solid-die on the second wiring layer 4 on the top surface of the ceramic base 1 and can be directly mounted and contacted with the ceramic base 1, so that the heat generated by the chip can be effectively transferred to the ceramic base 1, and efficient heat dissipation can be performed based on the bottom surface of the ceramic base 1.

[0064] Furthermore, the chip is die-bonded on the top surface of the ceramic base 1, that is, the chip is located in the notch structure, and the height difference between the first height and the second height is equal to the thickness of the chip, so that the top surface of the chip is flush with the top surface of the notch structure frame of the packaging substrate 2, so that electrical connection is made between the chip and the top surface of the packaging substrate 2 through the electrical connecting component 8.

[0065] The third wiring layer 5 is located in the internal area of ​​the notch structure and is connected to the second electrical channel 32. The third wiring layer 5 spans between the ceramic base 1 and the packaging substrate 2. One end of the third wiring layer 5 is connected to the second wiring layer 4 of the ceramic base 1, and the other end of the third wiring layer 5 is connected to the first wiring layer 3 of the packaging substrate 2, that is, the first wiring layer 3 and the second wiring layer 4 form a conductive connection based on the third wiring layer 5.

[0066] Furthermore, the second wiring layer 4 and the third wiring layer 5 are planar circuit structures, and the second wiring layer 4 and the third wiring layer 5 are located in a second height plane. The second wiring layer 4 is arranged on the top surface of the ceramic base 1, and the third wiring layer 5 is arranged after the ceramic base 1 and the packaging substrate 2 are spliced ​​and connected, so that the third wiring layer 5 can be connected to the second wiring layer 4, and at the same time, the third wiring layer 5 can be connected to the first wiring layer 3 in the notch structure, thereby realizing electrical connection between the first wiring layer 3 and the second wiring layer 4.

[0067] Furthermore, the second wiring layer 4 is provided with a connection position that matches the third wiring layer 5. Based on the third wiring layer 5 covering the connection position of the second wiring layer 4, a die-bonding pad for placing the chip is formed, so that the chip can be directly mounted or die-bonded on the ceramic base 1.

[0068] Specifically, the second wiring layer 4 is provided with a plurality of pad structures, and a plurality of chips are correspondingly attached to the plurality of pads. The plurality of chips include a first chip 6 and a second chip 7. A first electrical electrode is provided on the top of the first chip 6, and a second electrical electrode and a third electrical electrode are provided on the bottom of the first chip 6.

[0069] A fourth electrical type electrode, a fifth electrical type electrode and a sixth electrical type electrode are provided at the bottom of the second chip 7, wherein the first electrical type electrode and the fourth electrical type electrode have the same electrical type, the second electrical type electrode and the fifth electrical type electrode have the same electrical type, and the third electrical type electrode and the sixth electrical type electrode have the same electrical type.

[0070] The bottom electrodes of the first chip 6 and the second chip 7 are fixed to the ceramic base using a conductive medium. The first chip 6 and the second chip 7 are directly die-bonded to the ceramic base 1 using a conductive medium, and the ceramic base 1 forms a heat sink for the first chip 6 and the second chip 7. The heat sink directly dissipates heat from the first chip 6 and the second chip 7, thereby improving the heat dissipation effect of the package.

[0071] Specifically, the plurality of pad structures include a first pad for connecting to the second electrical electrode at the bottom of the first chip 6 and a second pad for connecting to the bottom electrode of the second chip 7;

[0072] The first pad and the second pad are electrically connected to the second electrical path 32 of the package substrate via the second wiring layer 4. The second wiring layer 4 includes a first sub-wiring 41 and a second sub-wiring 42. The first sub-wiring 41 is provided at the location of the first pad, and the second sub-wiring 42 is provided at the location of the second pad.

[0073] Furthermore, the first sub-wiring 41 is provided with a first line segment, and the second sub-wiring 42 is provided with several second line segments, and the first line segment of the first sub-wiring 41 and the several second line segments are staggered, so that an interconnection structure can be formed between the first sub-wiring 41 and the second sub-wiring 42, that is, the first chip 6 and the second chip 7 are solid-chip on the second wiring layer 4, and the first chip 6 and the second chip 7 can form an interconnection structure based on the second wiring layer 4.

[0074] Specifically, a connection pad is provided on the top surface of the notch structure at a position corresponding to the first electrical channel 31. The top electrode of the first chip 6 is electrically connected to the connection pad via an electrical connection component 8, and / or the top electrode of the second chip 7 is electrically connected to the connection pad via the electrical connection component 8. The electrical connection component 8 is provided to achieve electrical connection between the chip and the package substrate 2, enabling the electrical connection component 8 to meet the electrical connection requirements between the chip and the package substrate 2. This avoids multiple connection points formed by multi-wire welding, reduces parasitic induction at the connection points, and thus effectively reduces the parasitic resistance of the electrical loop between the chip and the package substrate 2.

[0075] Furthermore, the electrical connection component 8 is a metal sheet, or the electrical connection component 8 is a plated metal plate. Through the structure of the electrical connection component 8, the packaging substrate 2 and the chip are connected in a flat and compact manner, reducing the effective area of ​​the current loop, thereby reducing the inductance.

[0076] Furthermore, the electrical connection component 8 can be a leaky ring. The electrical connection component 8 based on the leaky ring can meet the stability of the structural connection between the electrical connection component 8 and the packaging substrate 2, and the leaky area of ​​the electrical connection component 8 can form a heat dissipation channel, thereby improving the heat dissipation efficiency of the package.

[0077] Specifically, the first pad and the second pad form an interconnect pad based on the third wiring layer 5, and the second electrical electrode of the first chip 6 and the fourth electrical electrode of the second chip 7 are electrically connected based on the interconnect pad, that is, the second electrical electrode of the first chip 6 and the fourth electrical electrode of the second chip 7 are interconnected based on the third wiring layer 5. The bottom of the packaging substrate 2 is provided with a first electrical pin 21 and a second electrical pin 22, and the bottom of the ceramic base 1 is provided with a fifth electrical pin 13 and a sixth electrical pin 14; the first electrical pin 2 1 is electrically connected to the first electrical channel 31, the second electrical pin 22 is electrically connected to the second electrical channel 32, a fifth electrical channel 11 and a sixth electrical channel 12 are provided in the ceramic base 1, the fifth electrical channel 11 is electrically connected to the fifth electrical pin 13, and the sixth electrical channel 12 is electrically connected to the sixth electrical pin 14, so that the semiconductor package can be electrically connected to an external circuit based on the first electrical pin 21 and the second electrical pin 22, thereby improving the convenience of electrical connection of the semiconductor package.

[0078] Furthermore, the fifth electrical electrode of the second chip 7 can be electrically connected to the external working circuit based on the fifth electrical channel 11 and the fifth electrical pin 13, and the sixth electrical electrode of the second chip 7 can be electrically connected to the external working circuit based on the sixth electrical channel 12 and the sixth electrical pin 14, which can effectively shorten the length of the electrical connection line in the semiconductor package, simplify the line arrangement of the semiconductor package, and realize compact packaging of the semiconductor package.

[0079] Specifically, the second sub-wiring 42 is provided with a first sub-pad 421 and a second sub-pad 422, the fifth electrical electrode of the second chip 7 is correspondingly mounted on the first sub-pad 421, and the sixth electrical electrode of the second chip 7 is correspondingly mounted on the second sub-pad 422, the first sub-pad 421 and the second sub-pad 422 are connected to the bottom of the semiconductor package based on the fifth electrical channel 11 and the sixth electrical channel 12 to form the fifth electrical pin 13 and the sixth electrical pin 14, and the semiconductor package is electrically connected to the external working circuit based on the first electrical pin 21, the second electrical pin 22, the fifth electrical pin 13 and the sixth electrical pin 14.

[0080] A capacitor 9 is mounted between the first sub-pad 421 and the second sub-pad 422, so that the capacitor 9 is connected between the fifth electrical electrode and the sixth electrical electrode of the second chip 7. The electrical circuit where the second chip 7 is located is filtered based on the capacitor 9, which can reduce the parasitic effects of the circuit where the second chip 7 is located, and at the same time reduce the risk of high-frequency noise generated by the package during fast switching.

[0081] Furthermore, in this embodiment, gallium nitride (GaN) and silicon carbide (SiC) are co-sealed, and a capacitor 9 is mounted between the first sub-pad 421 and the second sub-pad 422. Power buffering and matching of the gallium nitride chip and the silicon carbide chip are performed based on the capacitor 9. Due to the characteristic differences between the gallium nitride and silicon carbide chips (such as threshold voltage and switching speed), dynamic imbalance may easily occur during co-sealing. Therefore, the current between the gallium nitride chip and the silicon carbide chip is buffered based on the capacitor 9.

[0082] Specifically, the first chip 6 and the second chip 7 are directly mounted on the ceramic base 1, and the second electrical electrode of the first chip 6 and the fourth electrical electrode of the second chip 7 are electrically interconnected via the first sub-wiring 41 and the second sub-wiring 42. The first electrical electrode of the first chip 6 is directly connected to the external circuit via the electrical connection component 8 and the first electrical channel 31 of the package substrate 2, thereby optimizing the current transmission path, reducing parasitic inductance, and improving electrical performance and heat dissipation efficiency.

[0083] The third wiring layer 5 spans the second height layer of the ceramic base 1 and the packaging substrate 2, that is, the third wiring layer 5 is arranged in the notch structure of the packaging substrate 2, and the electrical interconnection between the third electrical electrode of the first chip 6 and the fifth electrical electrode of the second chip 7 is realized through the third wiring layer 5, and further through the connection design of the third wiring layer and the second electrical channel 32 of the packaging substrate 2, the fifth electrical electrode of the second chip 7 is reliably connected to the external circuit.

[0084] The fifth electrical electrode and the sixth electrical electrode of the second chip 7 are directly connected to the external circuit through the fifth electrical channel 11 and the sixth electrical channel 12 of the ceramic base 1, and a capacitor 9 is welded between the first sub-pad 421 and the second sub-pad 422 formed by the second sub-wiring 42 to improve power supply stability, suppress high-frequency interference, alleviate voltage spikes, optimize circuit dynamic response performance, and ensure the reliability and stability of the package in high-power, high-frequency applications.

[0085] Furthermore, the second electrical type electrode of the first chip 6 and the fourth electrical type electrode of the second chip 7 are electrically connected based on the interlacing of the first line segment and the second line segment;

[0086] The third electrical type electrode of the first chip 6 and the fifth electrical type electrode of the second chip 7 are electrically connected based on the third wiring layer 5;

[0087] The sixth electrical electrode of the second chip 7 is connected to the external circuit based on the sixth electrical channel, and the fifth electrical electrode of the second chip 7 is connected to the external circuit based on the fifth electrical channel, so that the circuit connection of the second chip 7 forms a Kelvin bridge circuit connection, which can realize the fast switching control of the high-power semiconductor package. After the first chip 6 and the second chip 7 are connected based on the first circuit arrangement layer 3, the second circuit arrangement layer 4 and the third circuit arrangement layer 5, and connected to the external working circuit, the electrical connection structure requirements of the high-power semiconductor package are met.

[0088] An embodiment of the present invention provides a high-power semiconductor package, in which a high-heat dissipation ceramic base 1 is directly embedded on a packaging substrate 2, and by providing a wiring layer on the packaging substrate 2 and the ceramic base 1, the chip is electrically connected to the ceramic base 1 and the packaging substrate 2 based on mounting, meeting the requirements of package integration and miniaturization, while reducing the parasitic resistance inside the package, and effectively reducing the working heat of the package; by directly mounting the chip on the ceramic base 1 based on the wiring layer, direct heat dissipation of the chip can be achieved, thereby improving the heat dissipation effect of the package.

[0089] Example 2:

[0090] Figure 4A flow chart of a method for preparing a high-power semiconductor package according to an embodiment of the present invention is shown. The method for preparing a high-power semiconductor package includes:

[0091] S11: preparing a package substrate 2 with a first wiring layer 3.

[0092] Figure 5 A schematic diagram of the opening frame structure of the packaging substrate in an embodiment of the present invention is shown. The raw material plate is photolithographically processed, a pattern mask is prepared on the raw material plate, several areas to be processed are divided on the raw material plate based on the pattern mask, and several notch structures are etched on the raw material plate based on a laser etching process.

[0093] Furthermore, a laser etching operation is performed at the middle position of the notch structure by using a laser etching device, and the raw material plate of the corresponding area is etched away at the middle position of the notch structure according to the outline of the ceramic base 1, so that a matching through groove is formed in the notch structure.

[0094] Specifically, after the etching process of the notch structure of the packaging substrate 2 is completed, according to the product specifications of the semiconductor package, a laser drilling device is used to perform a drilling operation at the corresponding position of the packaging substrate 2, and a plurality of through-hole structures are prepared on the packaging substrate 2 based on the laser drilling equipment. Conductive channels are formed in the plurality of through-hole structures by means of copper plug holes or coating a conductive layer, so that the packaging substrate 2 can meet the electrical arrangement of the chip.

[0095] Furthermore, the resistance of the conductive path inside the package substrate 2 can be reduced by using the copper plug hole, thereby improving the stability and reliability of the conductive path between the package substrate 2 and the chip.

[0096] Furthermore, by electroplating nickel gold or coating silver paste in the through hole, the electrical conductivity of the through hole is achieved, which can meet the electrical channel connection requirements of the vertical structure inside the packaging substrate 2 and reduce the preparation cost of the packaging substrate 2.

[0097] Furthermore, based on a plurality of electrical channel structures distributed in the notch structure of the packaging substrate 2 and in conjunction with electrical pins arranged on the bottom surface of the packaging substrate 2 , a first wiring layer 3 of the packaging substrate 2 is formed.

[0098] Furthermore, the first wiring layer 3 can form a vertical structure of electrical channel arrangement based on the conductive channels designed at different heights on the notch structure, which can fully improve the spatial structure utilization of the packaging substrate 2 and improve the structural compactness of the packaging substrate 2.

[0099] Furthermore, a plurality of hollow areas are provided at the frame position of the notch structure of the packaging substrate 2, so that when the packaging substrate 2 is in the panel structure state, the notch structures are interconnected, so as to facilitate the subsequent use of the plastic encapsulation resin process for plastic encapsulation.

[0100] S12: preparing the ceramic base 1 with the second wiring layer 4.

[0101] Figure 6 A schematic diagram of the ceramic base structure in an embodiment of the present invention is shown. A copper bonding (DBC: Direct Bonding Copper) ceramic plate of appropriate size is selected, and a copper metal layer is plated on the ceramic plate. A second wiring layer 4 is formed on the top surface of the ceramic base 1 based on patterned etching, and several chip bonding pads are formed on the second wiring layer 4 to meet the chip bonding requirements.

[0102] Furthermore, a first sub-wiring 41 and a second sub-wiring 42 are provided on the second wiring layer 4 . The first sub-wiring 41 satisfies the die-bonding requirement of the first chip 6 , and the second sub-wiring 42 satisfies the die-bonding requirement of the second chip 7 .

[0103] S13: The ceramic base 1 is embedded and fixed in the packaging substrate 2 .

[0104] Specifically, Figure 7 A schematic diagram showing the assembly of the package substrate and the ceramic base according to an embodiment of the present invention is shown; Figure 8 A schematic diagram of the panel structure after the package substrate and the ceramic base are assembled in an embodiment of the present invention is shown; Figure 9 A cross-sectional view of the assembled structure of the packaging substrate and the ceramic base in an embodiment of the present invention is shown; a plurality of ceramic bases 1 are embedded in the matching through grooves of a plurality of packaging substrates 2 in a one-to-one correspondence, and the ceramic base 1 and the packaging substrate 2 can be connected based on a conductive adhesive to ensure the bonding and fixation between the ceramic base 1 and the packaging substrate 2, and to meet the heat transfer between the ceramic base 1 and the packaging substrate 2, so that the working heat of the semiconductor package can be dissipated through the ceramic base 1, thereby effectively improving the heat dissipation effect of the semiconductor package.

[0105] Furthermore, the ceramic base 1 can be fixed in the packaging substrate 2 based on welding. Solder is placed in the matching groove of the packaging substrate 2, and the ceramic base 1 is correspondingly embedded in the matching groove. The ceramic base 1 is welded and fixed in the matching groove of the packaging substrate 2 by reflow soldering or hot pressing.

[0106] Furthermore, solder is placed in the matching groove of the packaging substrate 2, and the ceramic base 1 is correspondingly embedded in the matching groove. The packaging substrate 2 is placed in a reflow furnace for heating, so that the solder is heated and melted at a preset temperature, thereby satisfying the welding fixation between the ceramic base 1 and the packaging substrate 2.

[0107] S14 : preparing a third wiring layer 5 on the ceramic base 1 and the packaging substrate 2 .

[0108] Specifically, Figure 10 A schematic diagram of the connection structure of chips and devices mounted on a ceramic base in an embodiment of the present invention is shown: the third wiring layer 5 is formed on the ceramic base 1 and the packaging substrate 2 by electroplating, and the third wiring layer 5 spans between the ceramic base 1 and the packaging substrate 2, so that the third wiring layer 5 can meet the electrical connection requirements between the first wiring layer 3 and the second wiring layer 4.

[0109] Furthermore, the third wiring layer 5 can be prepared by rolling copper foil. Rolled copper foil is a product made by repeatedly rolling and annealing high-precision copper strips using the principle of plastic processing, and has good ductility and bending resistance.

[0110] Furthermore, the third wiring layer 5 can be prepared by active metal brazing, which is to add active elements to the brazing material to form a reaction layer on the ceramic surface through chemical reaction, thereby improving the wettability of the brazing material on the ceramic surface, thereby enabling direct brazing connection between the ceramic and the metal, which can improve the stability of the structural setting of the third wiring layer 5 and ensure that the third wiring layer 5 has a good electrical connection effect.

[0111] Furthermore, the third wiring layer 5 can also be prepared by metal sputtering, and a pattern mask is covered on the surface of the ceramic base 1 and the packaging substrate 2, so that the layout position of the third wiring layer 5 can be reserved on the surface of the ceramic base 1 and the packaging substrate 2. Metal particles are bombarded on the layout position reserved by the pattern mask under the action of high voltage, so that the metal particles can adhere to the placement position, thereby forming the third wiring layer 5.

[0112] Specifically, in this embodiment, the ceramic base 1 is embedded in the matching through groove of the packaging substrate 2 so that the top surface of the ceramic base 1 is flush with the second height layer plane of the notch structure of the packaging substrate 2, and an etching path accommodating the third wiring layer 5 is etched on the ceramic base 1 and the packaging substrate 2 by laser etching equipment, and a metal pad is arranged on the etching path based on metal pad bonding, thereby forming the third wiring layer 5.

[0113] Based on the third wiring layer 5 , the die-bonding pad where the first sub-wiring 41 is located and the die-bonding pad where the second sub-wiring 42 is located form an interconnected pad structure to meet the die-bonding requirements of the first chip 6 and the second chip 7 .

[0114] S15: Fix the chip and passive components to the corresponding pad positions on the ceramic base through the conductive medium.

[0115] Specifically, a first pad for placing the first chip 6 and a second pad for placing the second chip 7 are provided on the top surface of the ceramic base 1. The first chip 6 is bonded and fixed to the first pad by a metal conductive adhesive or a polymer adhesive, and the second chip 7 is bonded to the second pad by a metal conductive adhesive or a polymer adhesive, ensuring that the first chip 6 and the second chip 7 have good connection mechanical and electrical properties with the ceramic base 1.

[0116] Furthermore, the polymer adhesive may be epoxy resin or silicone, which has good bonding strength, good electrical conductivity and thermal stability, and meets the die-bonding requirements of the first chip 6 and the second chip 7 .

[0117] Specifically, before mounting the first chip 6 and the second chip 7, a first sub-pad 421 corresponding to the fifth electrical electrode of the second chip 7 and a second sub-pad 422 corresponding to the sixth electrical electrode of the second chip 7 are arranged on the second sub-wiring 42, and a capacitor 9 is mounted between the first sub-pad 421 and the second sub-pad 422, so that the capacitor 9 can be connected to the electrical circuit where the first chip 6 and the second chip 7 are located, thereby achieving the effect of buffering the current.

[0118] S16: Soldering a first electrical connection component on the top surface of the first chip.

[0119] The first chip 6 is die-bonded on the top pad structure of the ceramic base 1 so that the top pad of the first chip 6 is flush with the top surface of the frame position of the notch structure of the packaging substrate 2. By mounting an electrical connection component 8 between the first chip 6 and the top surface of the packaging substrate 2, the top pad of the first chip 6 can be electrically connected to the packaging substrate 2 based on the electrical connection component 8, and the first electrical connectivity requirement of the high-power semiconductor packaging structure is realized, thereby meeting the electrical connection requirement of the semiconductor package.

[0120] Furthermore, the electrical connection component 8 can be configured as a metal foil structure, which can meet the electrical connection between the first chip 6 and the packaging substrate 2; the metal foil can be set as an annular metal plate structure, which can reduce the heat generated by the electrical connection component 8 during operation, thereby reducing the operating heat of the semiconductor package.

[0121] Specifically, Figure 11 A schematic diagram of a panel assembly with top electrical connection components mounted thereon is shown in an embodiment of the present invention; Figure 12 A cross-sectional view of the state in which a top electrical connection component is mounted in an embodiment of the present invention is shown; on the interlocking assembly panel structure of the packaging substrate 2 and the ceramic base 1, the electrical connection component 8 can be mounted at several corresponding positions of the panel structure. By mounting several electrical connection components 8 on the panel structure in a one-to-one correspondence, the convenience of plastic sealing and segmentation of the panel structure can be improved, the plastic sealing reliability of the semiconductor package can be improved, and the amount of metal material used when the electrical connection component 8 is mounted can be reduced, thereby reducing the preparation cost of the semiconductor package.

[0122] Specifically, Figure 13 It shows another schematic diagram of a state where a top electrical connection component is mounted in an embodiment of the present invention; Figure 14 A cross-sectional view of the structure of another state in which a top electrical connection component is mounted in an embodiment of the present invention is shown. The electrical connection component 8 can be mounted by a metal frame structure, that is, by patterning and etching a metal plate, the metal plate can form a metal frame structure, and the metal frame structure can adapt to the assembly structure formed by the package substrate 2 and the ceramic base 1. By mounting the metal frame in the assembly structure, the mounting and connection requirements of several electrical connection components 8 and several corresponding positions in the assembly structure can be realized at the same time, thereby improving the convenience and efficiency of the semiconductor package preparation.

[0123] Furthermore, a plurality of electrical connection components 8 are formed into a frame based on the metal frame structure, and are divided during subsequent plastic encapsulation cutting, which can simplify the process steps of preparing the semiconductor package and improve the preparation efficiency of the high-power semiconductor package.

[0124] S17: performing plastic encapsulation on the substrate to obtain a package body.

[0125] Specifically, Figure 15 It shows a schematic diagram of the panel structure of the semiconductor package after plastic sealing in an embodiment of the present invention; Figure 16A cross-sectional view of the panel structure after plastic sealing of the semiconductor package in an embodiment of the present invention is shown. The packaging substrate 2 and several chips on the ceramic base 1 are plastic sealed by a plastic sealing resin, and a plastic sealing layer 10 is formed on top of the ceramic base 1 and the packaging substrate 2, so that the first chip 6 and the second chip 7 can be accommodated on the plastic sealing layer 10. The plastic sealing layer 10 is formed on the top of the panel structure based on the plastic sealing resin, thereby obtaining a package body in a panel structure state.

[0126] Furthermore, the molding resin is filled on the top of the panel structure so that the molding resin can flow through the hollow area of ​​the notch structure frame position of the packaging substrate 2, thereby covering the top of the panel structure and improving the stability of the molding resin molding the top of the panel structure.

[0127] S18: Dividing the package body into several semiconductor packages by cutting equipment.

[0128] Specifically, a cutting line is set on the package body, and the panel package structure is divided along the cutting line by laser cutting equipment to obtain a plurality of semiconductor power devices, and it is ensured that each semiconductor package is provided with a package substrate 2 and a ceramic base 1, and the semiconductor package is mechanically supported and protected by a plastic encapsulation colloid.

[0129] Before cutting the panelized packaging structure, the colloid of the panelized packaging structure can be polished by a polishing device so that the electrical pins at the bottom of the packaging substrate 2 can be exposed to meet the electrical connection requirements between the power device and the external circuit.

[0130] An embodiment of the present invention provides a method for preparing a high-power semiconductor package, in which a high-heat dissipation ceramic base 1 is directly embedded and set on a packaging substrate 2, and by providing a wiring layer on the packaging substrate 2 and the ceramic base 1, the chip is electrically connected to the ceramic base 1 and the packaging substrate 2 based on mounting, meeting the requirements of package integration and miniaturization, while reducing the parasitic resistance inside the package, and effectively reducing the working heat of the package; by directly mounting the chip on the ceramic base 1 based on the wiring layer, direct heat dissipation of the chip can be achieved, thereby improving the heat dissipation effect of the package.

[0131] In addition, the above is a detailed introduction to a high-power semiconductor package and a preparation method thereof provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A high-power semiconductor package, characterized in that: The high-power semiconductor package includes: a package substrate provided with a first wiring layer, a ceramic base provided with a second wiring layer, and a plurality of chips electrically connected to the second wiring layer; The ceramic base is embedded in the packaging substrate, and the ceramic base is electrically connected to the packaging substrate based on the third wiring layer; The first wiring layer is provided with a first electrical channel of a first height and a second electrical channel of a second height, the packaging substrate is provided with a notch structure, and the first electrical channel is provided at a border position of the notch structure, and the second electrical channel is provided in an inner area of ​​the notch structure; The top electrode of the chip is connected to the bottom of the semiconductor package through an electrical connection component and the first electrical path to form a first electrical pin; at least one bottom electrode of the chip is connected to the bottom of the semiconductor package based on the second wiring layer of the ceramic base and the second electrical path to form a second electrical pin; The second wiring layer on the ceramic base is provided with a plurality of pad structures, and a plurality of chips are correspondingly attached to the plurality of pads; The plurality of chips include a first chip and a second chip, wherein a first electrical type electrode is provided on the top of the first chip, and a second electrical type electrode and a third electrical type electrode are provided on the bottom of the first chip; A fourth electrical type electrode, a fifth electrical type electrode and a sixth electrical type electrode are provided at the bottom of the second chip; The bottom electrodes of the first chip and the second chip are fixed on the ceramic base based on a conductive medium; The plurality of pad structures include a first pad for connecting to a second electrical electrode at the bottom of the first chip and a second pad for connecting to a second electrical electrode at the bottom of the second chip; The first pad and the second pad are electrically connected to a second electrical path of the packaging substrate based on the third wiring layer; The first pad and the second pad form an interconnect pad based on the third wiring layer, and the second electrical type electrode of the first chip and the fourth electrical type electrode of the second chip are electrically connected based on the interconnect pad; A matching through groove is provided in the notch structure, and the ceramic base is embedded in the matching through groove; The third wiring layer is located in the inner area of ​​the notch structure and is connected to the second electrical channel.

2. The high-power semiconductor package according to claim 1, wherein: A connection pad is provided on the top surface of the notch structure at a position corresponding to the first electrical channel; The top electrode of the first chip is electrically connected to the connection pad based on an electrical connection component, and / or the top electrode of the second chip is electrically connected to the connection pad based on an electrical connection component.

3. The high-power semiconductor package according to claim 2, wherein: The electrical connection component is a weldable metal sheet, or the electrical connection component is a metal sheet with a weldable metal layer.

4. The high-power semiconductor package according to claim 1, wherein: The second wiring layer is provided with a first sub-pad connected to the fifth electrical type electrode of the second chip, and a second sub-pad connected to the sixth electrical type electrode of the second chip; Passive components are mounted between the first sub-pad and the second sub-pad.

5. The high-power semiconductor package according to claim 1, wherein: The bottom of the package substrate is provided with a first electrical pin and a second electrical pin; the bottom of the ceramic base is provided with a fifth electrical pin and a sixth electrical pin; The first electrical pin is electrically connected to the first electrical channel, and the second electrical pin is electrically connected to the second electrical channel. A fifth electrical channel and a sixth electrical channel are provided in the ceramic base. The fifth electrical channel is electrically connected to the fifth electrical pin, and the sixth electrical channel is electrically connected to the sixth electrical pin.

6. A method for preparing a high-power semiconductor package, characterized in that: The preparation method is used to prepare the high-power semiconductor package according to any one of claims 1 to 5, and the preparation method comprises: preparing a packaging substrate with a first wiring layer; preparing a ceramic base with a second wiring layer; Embedding and fixing the ceramic base in the packaging substrate; preparing a third wiring layer on the ceramic base and the packaging substrate; Fix the chip and passive components to the corresponding pad positions on the ceramic base through a conductive medium; Soldering a first electrical connection component on the top surface of the first chip; Performing plastic encapsulation on the substrate to obtain a package body; The package body is divided into several semiconductor packages by a cutting device.

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