Phase frequency detector structure and phase-locked loop

Abstract

The invention discloses a phase frequency detector structure and a phase-locked loop. The phase frequency detector structure comprises an edge detection module, a static random access memory module, a reset signal generation module and a direction signal generation module, the edge detection module is used for processing the reference signal and the feedback signal and outputting an edge pulse signal; the static access memory is used for storing the power supply signal when receiving the edge pulse signal and obtaining a UP signal and a DOWN signal; the reset signal generation module is used for generating a reset signal according to the UP signal and the DOWN signal to reset the static random access memory module; the direction signal generation module is used for outputting a direction signal according to the UP signal and the DOWN signal. According to the phase-locked loop, the edge pulse signals are stored in real time through the static random storage module, no dead zone exists, the blind zone range is extremely small, the phase difference of the input signals can be correctly reflected, and therefore the locking precision of the phase-locked loop can be improved, and power consumption is small.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a phase frequency detector structure and a phase locked loop based on a static random access memory. Background Art

[0002] At present, the phase frequency detector (PFD) is a key circuit widely used in fields such as frequency synthesis, phase locked loop (PLL), and clock synchronization. The main function of the PFD is to detect the phase difference and frequency difference of the input signal, and then provide a control signal for the phase locked loop (PLL). By comparing signals in the time domain, the PFD can achieve very high-precision frequency and phase synchronization. In practical applications, with the rapid development of integrated circuit technology, especially in the context of increasing demand for low power consumption in embedded systems, communication devices, portable devices, etc., low-power PFD has become a research hotspot. The design of low-power PFD not only helps to reduce the total power consumption of the system, but also can extend the usage time of portable devices (such as smart phones, wearable devices) and improve the overall energy efficiency of the devices.

[0003] The basic function of the PFD is to compare the phase and frequency differences of two input signals and generate a control signal proportional to the phase difference. A typical three-state PFD (TSPD) consists of two rising-edge-triggered D flip-flops with reset terminals and a logic AND gate. Although the TSPD structure considers reducing the dead zone, there is still a relatively large dead zone, and the existence of the dead zone time makes the PFD unable to correctly reflect the phase difference of the input signal, affecting the locking accuracy of the phase locked loop.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0005] In view of the above deficiencies of the existing technology, the purpose of the present invention is to provide a phase frequency detector structure and a phase locked loop based on a static random access memory, so as to solve the problem that the locking accuracy of the phase locked loop is relatively low because the PFD of the existing TSPD structure cannot correctly reflect the phase difference of the input signal due to the existence of the dead zone time.

[0006] The technical solution of the present invention is as follows:

[0007] In a first aspect, the present invention provides a phase frequency detector structure, which includes: a first edge detection module, a second edge detection module, a first static random access memory module, a second static random access memory module, a reset signal generation module, and a direction signal generation module;

[0008] The first edge detection module is connected to the first static random access memory module and is used for outputting a first edge pulse signal after delaying the reference signal.

[0009] The first static random access memory module is connected to a power supply signal, and is configured to store the power supply signal and obtain a first rectangular pulse signal when receiving the first edge pulse signal; the first rectangular pulse signal is an UP signal;

[0010] The second edge detection module is connected to the second static random access memory module, and is configured to output a second edge pulse signal after delaying a feedback signal;

[0011] The second static random access memory is connected to a power supply signal, and is configured to store the power supply signal and obtain a second rectangular pulse signal when receiving the second edge pulse signal; the second rectangular pulse signal is a DOWN signal;

[0012] The reset signal generation module is respectively connected to the first edge detection module, the second edge detection module, the first static random access memory module, and the second static random access memory module, and is configured to generate a reset signal according to the UP signal and the DOWN signal to reset the first static random access memory module and the second random access memory module;

[0013] The direction signal generation module is respectively connected to the first static random access memory module and the second static random access memory module, and is configured to output a direction signal according to the UP signal and the DOWN signal.

[0014] In a further setting of the present invention, the first edge detection module includes: a first NOT gate, a second NOT gate, a third NOT gate, and a first AND gate;

[0015] The first NOT gate, the second NOT gate, and the third NOT gate are connected in sequence;

[0016] The input end of the first NOT gate and the first input end of the first AND gate are connected to the reference signal;

[0017] The output end of the third NOT gate is connected to the second input end of the first AND gate; the output end of the first AND gate is connected to the first static random access memory module;

[0018] The reference signal is delayed by the first NOT gate, the second NOT gate, and the third NOT gate to obtain a first delayed signal and is input to the first AND gate;

[0019] The first AND gate performs an AND operation on the first delayed signal and the reference signal and outputs the first edge pulse signal to the first static random access memory module.

[0020] In a further setting of the present invention, the first static random access memory module includes: a first static random access memory, a first MOS transistor, and a second MOS transistor;

[0021] The gate of the first MOS transistor is connected to the output terminal of the first AND gate. The drain of the first MOS transistor is connected to a power supply voltage, and the source of the first MOS transistor is connected to the first static random access memory;

[0022] The gate of the second MOS transistor is connected to the reset signal. The drain of the second MOS transistor is connected to a power supply voltage, and the source of the second MOS transistor is connected to the first static random access memory;

[0023] The first MOS transistor is controlled to conduct by the first edge pulse signal, and a power supply signal is stored in the first static random access memory as an UP signal;

[0024] The second MOS transistor is controlled by the reset signal, and a power supply signal is input to the first static random access memory module to perform a reset process on the first static random access memory module.

[0025] In a further arrangement of the present invention, the second edge detection module includes: a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, and a second AND gate;

[0026] The fourth NOT gate, the fifth NOT gate, and the sixth NOT gate are connected in sequence;

[0027] The input terminal of the fourth NOT gate and the first input terminal of the second AND gate are connected to the feedback signal;

[0028] The output terminal of the sixth NOT gate is connected to the second input terminal of the second AND gate; the output terminal of the second AND gate is connected to the second static random access memory module;

[0029] The feedback signal is delayed by the fourth NOT gate, the fifth NOT gate, and the sixth NOT gate to obtain a second delay signal and is input to the second AND gate;

[0030] The second AND gate processes the second delay signal and the feedback signal and outputs a second edge pulse signal to the second static random access memory module.

[0031] In a further arrangement of the present invention, the second static random access memory module includes: a second static random access memory, a third MOS transistor, and a fourth MOS transistor;

[0032] The gate of the third MOS transistor is connected to the output terminal of the second AND gate. The drain of the third MOS transistor is connected to a power supply voltage, and the source of the third MOS transistor is connected to the second static random access memory;

[0033] The gate of the fourth MOS transistor is connected to the reset signal, the drain of the fourth MOS transistor is connected to the power supply voltage, and the source of the fourth MOS transistor is connected to the second static random access memory;

[0034] The third MOS transistor is controlled to conduct by the second edge pulse signal, and the power signal is stored in the second static random access memory as the UP signal;

[0035] The fourth MOS transistor is controlled by the reset signal, and the power signal is input to the second static access memory to perform a reset process on the second static random access memory.

[0036] In a further arrangement of the present invention, the direction signal generation module includes: a seventh NOT gate, an eighth NOT gate, a first NOR gate, a second NOR gate, a third NOR gate, and a fourth NOR gate;

[0037] The input terminal of the seventh NOT gate is connected to the DOWN signal, and the output terminal of the seventh NOT gate is connected to the second input terminal of the first NOR gate;

[0038] The first input terminal of the first NOR gate is connected to the UP signal, and the output terminal of the first NOR gate is connected to the first input terminal of the third NOR gate;

[0039] The input terminal of the eighth NOT gate is connected to the UP signal, and the output terminal of the eighth NOT gate is connected to the second input terminal of the second NOR gate;

[0040] The first input terminal of the second NOR gate is connected to the DOWN signal, and the output terminal of the second NOR gate is connected to the second input terminal of the fourth NOR gate;

[0041] The second input terminal of the third NOR gate is connected to the output terminal of the fourth NOR gate;

[0042] The first input terminal of the fourth NOR gate is connected to the output terminal of the third NOR gate.

[0043] In a further arrangement of the present invention, the reset signal generation module includes: a third AND gate and a fifth NOR gate;

[0044] The first input terminal of the third AND gate is connected to the UP signal, the second input terminal of the third AND gate is connected to the DOWN signal, and the output terminal of the third AND gate is connected to the second input terminal of the fifth NOR gate;

[0045] The first input terminal of the fifth NOR gate is connected to an external reset signal, and the output terminal of the fifth NOR gate is connected to the first static random access memory module and the second static random access memory module.

[0046] Further arrangement of the present invention: when the first edge pulse signal is active low, the first MOS transistor and the second MOS transistor are PMOS transistors; when the first edge pulse is active high, the first MOS transistor and the second MOS transistor are NMOS transistors;

[0047] The first static random access memory includes: a ninth NOT gate and a tenth NOT gate; the input terminal of the ninth NOT gate is connected to the source electrode of the first MOS transistor, the output terminal of the ninth NOT gate is connected to the input terminal of the tenth NOT gate; the input terminal of the tenth NOT gate is connected to the source electrode of the second MOS transistor, and the output terminal of the tenth NOT gate is connected to the input terminal of the ninth NOT gate.

[0048] Further arrangement of the present invention: when the second edge pulse signal is active low, the third MOS transistor and the fourth MOS transistor are PMOS transistors; when the second edge pulse is active high, the third MOS transistor and the fourth MOS transistor are NMOS transistors;

[0049] The second static random access memory includes: an eleventh NOT gate and a twelfth NOT gate; the input terminal of the eleventh NOT gate is connected to the source electrode of the third MOS transistor, the output terminal of the eleventh NOT gate is connected to the input terminal of the twelfth NOT gate; the input terminal of the twelfth NOT gate is connected to the input terminal of the fourth MOS transistor, and the output terminal of the twelfth NOT gate is connected to the input terminal of the eleventh NOT gate.

[0050] In a second aspect, the present invention further provides a phase-locked loop, which includes an oscillator and the frequency discriminator and phase discriminator as described above, and the frequency discriminator and phase discriminator are connected to the oscillator.

[0051] A frequency discriminator and phase detector structure and a phase-locked loop provided by the present invention, the frequency discriminator and phase detector structure comprising: a first edge detection module, a second edge detection module, a first static random access memory module, a second static random access memory module, a reset signal generation module, and a direction signal generation module; the first edge detection module is used for delaying a reference signal and outputting a first edge pulse signal; the first static random access memory module is used for storing a power supply signal when receiving the first edge pulse signal and obtaining a first rectangular pulse signal; the first rectangular pulse signal is an UP signal; the second edge detection module is used for delaying a feedback signal and outputting a second edge pulse signal; the second static access memory is used for storing the power supply signal when receiving the second edge pulse signal and obtaining a second rectangular pulse signal; the second rectangular pulse signal is a DOWN signal; the reset signal generation module is used for generating a reset signal according to the UP signal and the DOWN signal to reset the first static random access memory module and the second random access memory module; the direction signal generation module is used for outputting a direction signal according to the UP signal and the DOWN signal. By using the static random access memory module to store the edge pulse signal in real time, the present invention can achieve no dead zone and a very small blind area range, can correctly reflect the phase difference of the input signal, and thus can improve the locking accuracy of the phase-locked loop. In addition, the static random access memory module is a very simple negative feedback, can quickly complete the data latch, and thus has relatively lower power consumption than the traditional TSPD. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on the structures shown in these drawings without creative efforts.

[0053] Figure 1 is a schematic diagram of a traditional three-state PFD (TSPD).

[0054] Figure 2 is a principle block diagram of the frequency discriminator and phase detector structure in the present invention.

[0055] Figure 3 is a waveform diagram of each signal of the frequency discriminator and phase detector structure in the present invention.

[0056] Figure 4 is an actual simulation diagram of the frequency discriminator and phase detector structure in the present invention.

[0057] Figure 5 is a waveform diagram of each signal of the first edge detection module in the present invention.

[0058] Figure 6 It is a simulation diagram of the frequency discriminator and phase detector structure in an embodiment of the present invention under other divided-frequency clocks.

[0059] Figure 7 It is a circuit schematic diagram of the first edge detection module and the first static random access memory module in an embodiment of the present invention.

[0060] Figure 8 It is a circuit schematic diagram of the second edge detection module and the second static random access memory module in an embodiment of the present invention.

[0061] Figure 9 It is a circuit schematic diagram of the direction signal generation module in an embodiment of the present invention.

[0062] Figure 10 It is a circuit schematic diagram of the reset signal generation module in an embodiment of the present invention.

[0063] Reference numerals in the drawings: 100, the first edge detection module; 200, the second edge detection module; 300, the first static random access memory module; 400, the second static random access memory module; 500, the reset signal generation module; 600, the direction signal generation module. Detailed implementation manners

[0064] The present invention provides a frequency discriminator and phase detector structure and a phase-locked loop. To make the objectives, technical solutions and effects of the present invention clearer and more definite, the following further describes the present invention in detail with reference to the accompanying drawings and by way of examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0065] In the embodiments and the scope of the patent application, unless otherwise specifically defined in the text for articles, the articles "a", "an", "the" and "said" may also include the plural form. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, such descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features.

[0066] It should be further understood that the term "comprising" used in the specification of the present invention means the presence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is "connected" or "coupled" to another element, it can be directly connected or coupled to other elements, or there may also be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any unit and all combinations of one or more of the associated listed items.

[0067] Those skilled in the art of the present technology can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of those of ordinary skill in the art to which the present invention pertains. It should also be understood that terms such as those defined in a general dictionary should be understood to have a meaning consistent with the meaning in the context of the prior art, and will not be interpreted with an idealized or overly formal meaning unless specifically defined as here.

[0068] In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0069] Common PFD implementation methods include SSPD, BBPD, TSPD, etc. In a phase-locked loop (PLL), SSPD (Sub-Sampling Phase Detector) is a sub-sampling phase detector that realizes phase comparison by injecting a lower-frequency reference signal into a high-frequency signal. The design and implementation of SSPD may be more complex than that of a traditional PFD, requiring precise analog sample-and-hold circuits and transconductance units, or snapshot circuits and time-to-digital converters; at the same time, the charge pump of the SSPD phase detector is greatly affected by PVT (process, voltage, temperature), and the phase detection range is only from -90° to 90°, and the operating speed is slow.

[0070] BBPD (Bang-Bang Phase Detector) has been widely used in the fields of high-speed communication and data recovery due to its simplicity and high efficiency, but there are also some limitations and challenges. Due to the existence of random noise generated by various circuit components (usually including thermal noise and flicker noise), BBPD may be affected in many practical applications. Especially when the BBPD input is mainly random noise, its average output has a linear relationship with the average input value (within a certain range). In addition, compared with other PFD structures, the BBPD structure has higher power consumption.

[0071] As Figure 1 shown, a typical TSPD (Tri-State Phase Detector) consists of two rising-edge-triggered D flip-flops with reset terminals and a logical AND gate. The data terminal D of the D flip-flop is always connected to a high level. This frequency and phase detector is triggered by the rising edges of the ref_clk and div_clk clocks, generating high-level UP and DN rectangular pulse signals. The UP signal and the DN signal are provided to the reset signal rst of the D flip-flop through the AND gate. When both the UP signal and the DN signal are high level, the reset signal makes it return to a low level.

[0072] Although the TSPD structure considers reducing the dead zone, there is still a relatively large dead zone. The existence of the dead zone time makes the PFD unable to correctly reflect the phase difference of the input signal, affecting the locking accuracy of the phase-locked loop. To address the above technical problems, the present invention provides a frequency and phase detector structure and a phase-locked loop. By using a static random access memory module to store the edge pulse signal in real time, it is possible to achieve no dead zone and a very small blind zone range, correctly reflect the phase difference of the input signal, thereby improving the locking accuracy of the phase-locked loop, and being able to control the PFD to still work stably when the input signal frequency is high, thereby reducing power consumption and ensuring the stability of the system. In addition, the static random access memory module is a very simple negative feedback, which can quickly complete the data latch, so the power consumption is relatively smaller than that of the traditional TSPD.

[0073] Please also refer to Figures 2 to 10 , the present invention provides a preferred embodiment of a frequency and phase detector structure.

[0074] In some embodiments, as Figure 2As shown in the figure, the present invention provides a frequency discriminator and phase detector structure, which includes: a first edge detection module 100, a second edge detection module 200, a first static random access memory module 300, a second static random access memory module 400, a reset signal generation module 500, and a direction signal generation module 600. The first edge detection module 100 is connected to the first static random access memory module 300 and is used to output a first edge pulse signal ref_rise after delaying the reference signal ref_clk; the first static random access memory module 300 is connected to the power supply signal VDD and is used to store the power supply signal VDD when receiving the first edge pulse signal ref_rise and obtain a first rectangular pulse signal; the first rectangular pulse signal is the UP signal UP; the second edge detection module 200 is connected to the second static random access memory module 400 and is used to output a second edge pulse signal div_rise after delaying the feedback signal div_clk; the second static access memory is connected to the power supply signal VDD and is used to store the power supply signal when receiving the second edge pulse signal div_rise and obtain a second rectangular pulse signal; the second rectangular pulse signal is the DOWN signal DOWN; the reset signal generation module 500 is respectively connected to the first edge detection module 100, the second edge detection module 200, the first static random access memory module 300, and the second static random access memory module 400, and is used to generate a reset signal according to the UP signal and the DOWN signal to reset the first static random access memory module 300 and the second random access memory module; the direction signal generation module 600 is respectively connected to the first static random access memory module 300 and the second static random access memory module 400, and is used to output a direction signal dir according to the UP signal and the DOWN signal.

[0075] Specifically, the first edge detection module 100 can process the input reference signal ref_clk and output a first edge pulse signal ref_rise to control the first static random access memory module 300 to be connected to the power supply signal VDD, and the second edge detection module 200 can process the input feedback signal div_clk and output a second edge pulse signal div_rise to control the second static random access memory module 400 to be connected to the power supply signal VDD. The first static random access memory module 300 stores the power supply signal VDD and obtains an UP signal UP, and the second static random access memory module 400 stores the power supply signal VDD and obtains a DOWN signal DOWN.

[0076] The reset signal generation module 500 can output a reset signal rst_n to the first static random access memory module 300 and the second random access memory module after receiving the UP signal and the DOWN signal, so as to implement the reset process of the first static random access memory module 300 and the second static random access memory module 400. The direction signal generation module 600 can output a direction signal dir after receiving the UP signal UP and the DOWN signal DOWN, that is, obtain a lag or lead flag signal.

[0077] In the above technical solution, the present invention can avoid the loss of pulse signals by storing the edge pulse signals in real time through the static random access memory module, so that there is no dead zone and the blind zone range is extremely small, and the phase difference of the input signal can be correctly reflected. Therefore, the locking accuracy of the phase-locked loop can be improved, and it can be ensured that the PFD can still work stably when the input signal frequency is high, thereby reducing power consumption and ensuring the stability of the system. In addition, the static random access memory module is a very simple negative feedback structure, which can quickly complete the data latch, so the power consumption is relatively smaller than that of the traditional TSPD, which can extend the usage time of portable devices (such as smart phones, wearable devices, etc.), improve the overall energy consumption of the devices, and is also applicable to clock recovery circuits, clock synchronization circuits, and clock synthesizers, etc.

[0078] The overall waveform of the present invention is as Figure 3 shown, and the actual spectre simulation waveform is as Figure 4 shown, where the waveform diagrams of each signal of the first edge detection module are as Figure 5 shown. When the reference frequency is 5 MHz, the power consumption of the present invention is only 52.974 uW, while the power consumption measured by spectre simulation of the traditional three-state PFD (TSPD) under the same conditions is 97.416 uW. In addition, the overall PFD circuit layout is also relatively small, and the total area can be reduced to 2396.7 um 2 . As Figure 6 shown, the required phase difference can still be measured when div_clk and ref_clk are not of the same frequency.

[0079] In some embodiments, such as Figure 2 and Figure 7As shown, the first edge detection module 100 includes: a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, and a first AND gate AND1. The first NOT gate NOT1, the second NOT gate NOT2, and the third NOT gate NOT3 are connected in sequence; the input terminal of the first NOT gate NOT1 and the first input terminal of the first AND gate AND1 are connected to the reference signal ref_clk; the output terminal of the third NOT gate NOT3 is connected to the second input terminal of the first AND gate AND1; the output terminal of the first AND gate AND1 is connected to the first static random access memory module 300; the reference signal ref_clk is delayed by the first NOT gate NOT1, the second NOT gate NOT2, and the third NOT gate NOT3 to obtain a first delayed signal ref_dlyb and input it to the first AND gate AND1; the first AND gate AND1 performs an AND operation on the first delayed signal and the reference signal ref_clk and then outputs the first edge pulse signal ref_rise to the first static random access memory module 300.

[0080] Further, the first static random access memory module 300 includes: a first static random access memory SARM1, a first MOS transistor M1, and a second MOS transistor M2. The gate of the first MOS transistor M2 is connected to the output terminal of the first AND gate AND1, the drain of the first MOS transistor M1 is connected to the power supply voltage VDD, the source of the first MOS transistor M1 is connected to the first static random access memory SARM1; the gate of the second MOS transistor M2 is connected to the reset signal rst_n, the drain of the second MOS transistor M2 is connected to the power supply voltage VDD, the source of the second MOS transistor M2 is connected to the first static random access memory SARM1; the first MOS transistor M1 is controlled by the first edge pulse signal ref_rise to conduct, and stores the power supply signal VDD into the first static random access memory as the UP signal; the second MOS transistor M2 is controlled by the reset signal rst_n to input the power supply signal VDD to the first static random access memory module 300 to perform a reset process on the first static random access memory module 300.

[0081] Specifically, the first NOT gate NOT1, the second NOT gate NOT2, and the third NOT gate NOT3 delay the reference signal ref_clk to obtain a first delayed signal ref_dlyb. Then the first AND gate AND1 performs an AND operation on the original signal (reference signal) and the first delayed signal ref_dlyb to obtain the required pulse signal, and this pulse signal is a pulse signal generated following the falling edge.

[0082] When the first edge pulse signal ref_rise is active low, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors; when the first edge pulse signal ref_rise is active high, the first MOS transistor M1 and the second MOS transistor M2 are NMOS transistors. In this embodiment, taking the first MOS transistor M1 and the second MOS transistor M2 as PMOS transistors as an example, the original signal and the first delay signal ref_dlyb are ANDed to obtain an active low pulse signal. It can be seen from Figure 5 that there is and only three NOT gate delay units with a low level between the falling edges of the original signal and the first delay signal ref_dlyb. When the first edge detection module 100 generates an active low pulse signal, the first MOS transistor M1 conducts, and the power supply voltage VDD is stored into the first static random access memory through the UP signal terminal of the first static random access memory SARM1 to obtain the UP signal. The second MOS transistor is connected to the other end of the first static random access memory SARM1. When the reset signal rst_n is low, the power supply voltage VDD is input to the other end of the first static random access memory SARM1, and a low level is stored into the UP signal terminal of the first static random access memory SARM1 to reset the first static random access memory SARM1.

[0083] In some embodiments, such as Figure 2 and Figure 8 shown, the second edge detection module 200 includes: a fourth NOT gate NOT4, a fifth NOT gate NOT5, a sixth NOT gate NOT6 and a second AND gate AND2. The fourth NOT gate NOT4, the fifth NOT gate NOT5 and the sixth NOT gate NOT6 are connected in sequence; the input terminal of the fourth NOT gate NOT4 and the first input terminal of the second AND gate AND2 are connected to the feedback signal div_clk; the output terminal of the sixth NOT gate NOT6 is connected to the second input terminal of the second AND gate ADN2; the output terminal of the second AND gate ADN2 is connected to the second static random access storage module 400; the feedback signal div_clk is delayed by the fourth NOT gate NOT4, the fifth NOT gate NOT5 and the sixth NOT gate NOT6 to obtain a second delay signal and input it to the second AND gate AND2; the second AND gate ADN2 processes the second delay signal div_dlyb and the feedback signal div_clk and outputs a second edge pulse signal div_rise to the second static random access storage module 400.

[0084] Further, the second static random storage module 400 includes: a second static random access memory SARM2, a third MOS transistor M3, and a fourth MOS transistor M4. The gate of the third MOS transistor M3 is connected to the output terminal of the second AND gate AND2. The drain of the third MOS transistor M3 is connected to the power supply voltage VDD. The source of the third MOS transistor M3 is connected to the second static random access memory SARM2. The gate of the fourth MOS transistor M4 is connected to the reset signal rst_n. The drain of the fourth MOS transistor M4 is connected to the power supply voltage VDD. The source of the fourth MOS transistor M4 is connected to the second static random access memory SARM2. The third MOS transistor M3 is turned on under the control of the second edge pulse signal div_rise, and the power supply signal VDD is stored in the second static random access memory SARM2 as the UP signal. The fourth MOS transistor M4 is controlled by the reset signal rst_n, and the power supply signal VDD is input to the second static access memory SARM2 to perform a reset process on the second static random access memory SARM2.

[0085] Specifically, the fourth NOT gate NOT4, the fifth NOT gate NOT5, and the sixth NOT gate NOT6 perform a certain delay on the feedback signal div_clk to obtain a second delay signal div_dlyb. Then, the second AND gate AND2 performs an AND operation on the original signal (feedback signal) and the second delay signal div_dlyb to obtain the required pulse signal.

[0086] When the second edge pulse signal div_rise is active low, the third MOS transistor M3 and the fourth MOS transistor M4 are PMOS transistors. When the second edge pulse signal div_rise is active high, the third MOS transistor M3 and the fourth MOS transistor M4 are NMOS transistors. In this embodiment, taking the third MOS transistor M3 and the fourth MOS transistor M4 as PMOS transistors as an example, a pulse signal that is active low is obtained after performing an AND operation on the original signal and the second delay signal div_dlyb. When the second edge detection module 200 generates a pulse signal that is active low, the third MOS transistor M3 is turned on, and the power supply voltage VDD is stored in the second static random access memory SRAM2 through the DOWN signal terminal of the second static random access memory SRAM2 to obtain the DOWN signal. The fourth MOS transistor M4 is connected to the other end of the second static random access memory SRAM2. When the reset signal rst_n is low, the power supply voltage VDD is input to the other end of the second static random access memory SRAM2, and a low level is stored in the DOWN signal terminal of the second static random access memory SRAM2 to implement the reset of the second static random access memory SRAM2.

[0087] In some embodiments, such as Figure 2 and Figure 9 shown, the direction signal generation module 600 includes: a seventh NOT gate NOT7, an eighth NOT gate NOT8, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, and a fourth NOR gate NOR4. The input terminal of the seventh NOT gate NOT7 is connected to the DOWN signal, and the output terminal of the seventh NOT gate NOT7 is connected to the second input terminal of the first NOR gate NOR1; the first input terminal of the first NOR gate NOR1 is connected to the UP signal, and the output terminal of the first NOR gate NOR1 is connected to the first input terminal of the third NOR gate NOR3; the input terminal of the eighth NOT gate is connected to the UP signal, and the output terminal of the eighth NOT gate NOT8 is connected to the second input terminal of the second NOR gate NOR2;

[0088] the first input terminal of the second NOR gate NOR2 is connected to the DOWN signal, and the output terminal of the second NOR gate NOR is connected to the second input terminal of the fourth NOR gate NOR4; the second input terminal of the third NOR gate NOR3 is connected to the output terminal of the fourth NOR gate NOR4; the first input terminal of the fourth NOR gate NOR4 is connected to the output terminal of the third NOR gate NOR3.

[0089] Specifically, the seventh NOT gate NOT7, the first NOR gate NOR1, the eighth NOT gate NOT8, and the second NOR gate NOR2 constitute two decoding circuits, which can convert the input UP signal and DOWN signal. When (UP, DOWN) = (1, 1), it is decoded as (0, 0), and the decoding output of the rest of the inputs remains unchanged. The third NOR gate NOR3 and the fourth NOR gate NOR4 constitute a latch, which is active high, and the direction signal dir is output through the output terminal of the third NOR gate NOR3. The direction signal generation module 600 is an auxiliary circuit and can be used in a phase-locked loop or other subsequent circuits.

[0090] In some embodiments, such as Figure 7 and Figure 8As shown, the first static random access memory SARM1 includes: a ninth NOT gate NOT9 and a tenth NOT gate NOT10; the input terminal of the ninth NOT gate NOT9 is connected to the source electrode of the first MOS transistor M1, and the output terminal of the ninth NOT gate NOT9 is connected to the input terminal of the tenth NOT gate NOT10; the input terminal of the tenth NOT gate NOT10 is connected to the source electrode of the second MOS transistor M2, and the output terminal of the tenth NOT gate NOT10 is connected to the input terminal of the ninth NOT gate NOT9. The second static random access memory SARM2 includes: an eleventh NOT gate NOT11 and a twelfth NOT gate NOT12; the input terminal of the eleventh NOT gate NOT11 is connected to the source electrode of the third MOS transistor M3, and the output terminal of the eleventh NOT gate NOT11 is connected to the input terminal of the twelfth NOT gate NOT12; the input terminal of the twelfth NOT gate NOT12 is connected to the input terminal of the fourth MOS transistor, and the output terminal of the twelfth NOT gate NOT12 is connected to the input terminal of the eleventh NOT gate NOT11.

[0091] The structures of the first static random access memory SARM1 and the second static random access memory SARM2 are relatively simple, with relatively few transistors used, and there are not as many state switches as in traditional TSPD. Therefore, the static random access memory is a very simple negative feedback, which can quickly complete data latching, accelerate charge and discharge, reduce the conduction time from VDD to GND, and thus reduce power consumption.

[0092] In some embodiments, such as Figure 2 and Figure 10 As shown, the reset signal generation module 500 includes: a third AND gate AND3 and a fifth NOR gate NOR5; the first input terminal of the third AND gate AND3 receives the UP signal, the second input terminal of the third AND gate AND3 receives the DOWN signal, and the output terminal of the third AND gate AND3 is connected to the second input terminal of the fifth NOR gate NOR5; the first input terminal of the fifth NOR gate receives the external reset signal rst, and the output terminal of the fifth NOR gate NOR5 is connected to the first static random access memory module 300 and the second static random access memory module 400.

[0093] Specifically, the reset signal generation module 500 is composed of a two-input AND gate and a two-input NOR gate. The third AND gate AND3 can perform an AND operation on the UP signal and the DOWN signal to determine whether the UP signal and the DOWN signal are both high-level at the same time, and then perform a NOR operation on the result of the third AND gate AND3 and the external reset signal rst to obtain a reset signal with active-low level, which can drive the second MOS transistor M2 or the fourth MOS transistor M4 to turn on, so as to realize the reset of the first static random access memory SARM1 and the second static random access memory SARM2. It should be noted that when the second MOS transistor M2 and the fourth MOS transistor M4 are NMOS transistors, the reset signal generation module 500 can generate a reset signal rst_n with active-high level to drive the second MOS transistor M2 and the fourth MOS transistor M4 to turn on.

[0094] In some embodiments, the present invention further provides a phase-locked loop, which includes an oscillator and the frequency discriminator and phase detector as described above, and the frequency discriminator and phase detector is connected to the oscillator. Specifically, as described in an embodiment of a frequency discriminator and phase detector, it will not be elaborated here. It should be noted that when the frequency discriminator and phase detector is applied to a phase-locked loop, the smic180nm analog CMOS process library can be used, which can meet the PFD requirements of most phase-locked loops, realize accurate and fast phase difference signal output, and further meet the requirements such as fast locking and low power consumption of the phase-locked loop.

[0095] In summary, the frequency discriminator and phase detector structure and phase-locked loop provided by the present invention have the following

[0096] Beneficial effects:

[0097] The edge pulse signal is stored in real time through the static random access memory module, so that there is no dead zone and the blind zone range is extremely small, and the phase difference of the input signal can be correctly reflected, thereby improving the locking accuracy of the phase-locked loop, and enabling the PFD to still work stably when the frequency of the input signal is relatively high, thereby reducing power consumption and ensuring the stability of the system;

[0098] The static random access memory module is a very simple negative feedback, which can quickly complete the data latch, so the power consumption is relatively smaller than that of the traditional TSPD;

[0099] The clock edge detection module is built with simple NOT gates and AND gates, which can further reduce power consumption;

[0100] And overall, the structure is simple and the feedback circuit is clear.

[0101] It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or modifications can be made according to the above description, and all such improvements and modifications shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A frequency detector and phase detector structure, characterized in that: include: A first edge detection module, a second edge detection module, a first static random access memory module, a second static random access memory module, a reset signal generating module and a direction signal generating module; The first edge detection module is connected to the first static random access memory module, and is used to output a first edge pulse signal after delaying the reference signal; The first static random access memory module is connected to the power signal, and is used to store the power signal and obtain a first rectangular pulse signal when receiving the first edge pulse signal; the first rectangular pulse signal is an UP signal; The second edge detection module is connected to the second static random access memory module, and is used to output a second edge pulse signal after delaying the feedback signal; The second static access memory is connected to the power signal, and is used to store the power signal and obtain a second rectangular pulse signal when receiving the second edge pulse signal; the second rectangular pulse signal is a DOWN signal; The reset signal generating module is connected to the first edge detection module, the second edge detection module, the first static random access memory module and the second static random access memory module respectively, and is used to generate a reset signal according to the UP signal and the DOWN signal to reset the first static random access memory module and the second random access memory module; The direction signal generating module is connected to the first static random access memory module and the second static random access memory module respectively, and is used for outputting a direction signal according to the UP signal and the DOWN signal.

2. The phase frequency detector structure according to claim 1, characterized in that: The first edge detection module includes: a first NOT gate, a second NOT gate, a third NOT gate and a first AND gate; The first NOT gate, the second NOT gate and the third NOT gate are connected in sequence; The input end of the first NOT gate and the first input end of the first AND gate are connected to the reference signal; The output end of the third NOT gate is connected to the second input end of the first AND gate; the output end of the first AND gate is connected to the first static random access memory module; The reference signal is delayed by the first NOT gate, the second NOT gate and the third NOT gate to obtain a first delayed signal and input it into the first AND gate; The first AND gate performs AND processing on the first delayed signal and the reference signal and then outputs the first edge pulse signal to the first static random access memory module.

3. The phase frequency detector structure according to claim 2, characterized in that: The first static random access memory module includes: a first static random access memory, a first MOS transistor and a second MOS transistor; The gate of the first MOS transistor is connected to the output end of the first AND gate, the drain of the first MOS transistor is connected to the power supply voltage, and the source of the first MOS transistor is connected to the first static random access memory; The gate of the second MOS transistor is connected to the reset signal, the drain of the second MOS transistor is connected to the power supply voltage, and the source of the second MOS transistor is connected to the first static random access memory; The first MOS tube is turned on under the control of the first edge pulse signal, and stores the power signal into the first static random access memory as an UP signal; The second MOS tube is controlled by the reset signal, and inputs the power signal to the first static random access memory module to perform a reset process on the first static random access memory module.

4. The phase frequency detector structure according to claim 1, characterized in that: The second edge detection module includes: a fourth NOT gate, a fifth NOT gate, a sixth NOT gate and a second AND gate; The fourth NOT gate, the fifth NOT gate and the sixth NOT gate are connected in sequence; The input end of the fourth NOT gate and the first input end of the second AND gate are connected to the feedback signal; The output end of the sixth NOT gate is connected to the second input end of the second AND gate; the output end of the second AND gate is connected to the second static random access memory module; The feedback signal is delayed by the fourth NOT gate, the fifth NOT gate and the sixth NOT gate to obtain a second delayed signal and input it into the second AND gate; The second AND gate processes the second delayed signal and the feedback signal and then outputs a second edge pulse signal to the second static random access memory module.

5. The phase frequency detector structure according to claim 6, characterized in that: The second static random access memory module includes: a second static random access memory, a third MOS transistor and a fourth MOS transistor; The gate of the third MOS tube is connected to the output end of the second AND gate, the drain of the third MOS tube is connected to the power supply voltage, and the source of the third MOS tube is connected to the second static random access memory; The gate of the fourth MOS tube is connected to the reset signal, the drain of the fourth MOS tube is connected to the power supply voltage, and the source of the fourth MOS tube is connected to the second static random access memory; The third MOS tube is turned on under the control of the second edge pulse signal, and stores the power signal into the second static random access memory as an UP signal; The fourth MOS transistor is controlled by the reset signal and inputs the power signal to the second static access memory to perform a reset process on the second static random access memory.

6. The phase frequency detector structure according to claim 1, characterized in that: The direction signal generating module comprises: a seventh NOT gate, an eighth NOT gate, a first NOR gate, a second NOR gate, a third NOR gate and a fourth NOR gate; The input end of the seventh NOT gate is connected to the DOWN signal, and the output end of the seventh NOT gate is connected to the second input end of the first NOR gate; The first input terminal of the first NOR gate is connected to the UP signal, and the output terminal of the first NOR gate is connected to the first input terminal of the third NOR gate; The input end of the eighth NOT gate is connected to the UP signal, and the output end of the eighth NOT gate is connected to the second input end of the second NOR gate; The first input terminal of the second NOR gate is connected to the DOWN signal, and the output terminal of the second OR gate is connected to the second input terminal of the fourth NOR gate; The second input terminal of the third NOR gate is connected to the output terminal of the fourth NOR gate; The first input terminal of the fourth NOR gate is connected to the output terminal of the third NOR gate.

7. The phase frequency detector structure according to claim 1, characterized in that: The reset signal generating module comprises: a third AND gate and a fifth NOR gate; The first input end of the third AND gate is connected to the UP signal, the second input end of the third AND gate is connected to the DOWN signal, and the output end of the third AND gate is connected to the second input end of the fifth NOR gate; The first input end of the fifth NOR gate is connected to an external reset signal, and the output end of the fifth NOR gate is connected to the first static random access memory module and the second static random access memory module.

8. The phase frequency detector structure according to claim 3, characterized in that: When the first edge pulse signal is at a low level and effective, the first MOS transistor and the second MOS transistor are PMOS transistors; when the first edge pulse signal is at a high level and effective, the first MOS transistor and the second MOS transistor are NMOS transistors; The first static random access memory includes: a ninth NOT gate and a tenth NOT gate; the input end of the ninth NOT gate is connected to the source of the first MOS tube, and the output end of the ninth NOT gate is connected to the input end of the tenth NOT gate; the input end of the tenth NOT gate is connected to the source of the second MOS tube, and the output end of the tenth NOT gate is connected to the input end of the ninth NOT gate.

9. The phase frequency detector structure according to claim 5, characterized in that: When the second edge pulse signal is at a low level and effective, the third MOS tube and the fourth MOS tube are PMOS tubes; when the second edge pulse signal is at a high level and effective, the third MOS tube and the fourth MOS tube are NMOS tubes; The second static random access memory includes: an eleventh NOT gate and a twelfth NOT gate; the input end of the eleventh NOT gate is connected to the source of the third MOS tube, and the output end of the eleventh NOT gate is connected to the input end of the twelfth NOT gate; The input end of the twelfth NOT gate is connected to the input end of the fourth MOS tube, and the output end of the twelfth NOT gate is connected to the input end of the eleventh NOT gate.

10. A phase-locked loop, characterized in that: It comprises an oscillator and a frequency detector and a phase detector as claimed in any one of claims 1 to 9, wherein the frequency detector and the phase detector are connected to the oscillator.

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