Linear frequency modulation signal circuit based on DDS

Abstract

The invention discloses a linear frequency modulation signal circuit based on a DDS (Direct Digital Synthesizer), and aims to solve the problems that a traditional frequency agility circuit adopts a single-path DDS circuit to output signals, and the frequency agility rate is limited by the performance of the DDS and is generally in a microsecond level. The switch is adopted to control output and switching of the two DDS circuits, when one DDS circuit is outputting a frequency agility signal, the other DDS circuit completes number setting operation, therefore, when the output signal needs to be switched, the working DDS circuit can be immediately closed, the other DDS circuit which completes number setting is switched on, the frequency agility rate is determined by the switching frequency of the switch, and the frequency agility rate of the DDS circuit is determined by the switching frequency of the switch. And the frequency agility rate is increased to 20ns.

Description

Technical Field

[0001] The present invention belongs to the technical field of microwave radio frequency signal processing, and particularly relates to a linear frequency modulation signal circuit based on DDS. Background Art

[0002] In modern electronic systems, frequency synthesis technology is crucial. The PLL technology ensures stable output frequency through closed-loop control, but is limited by the frequency switching speed; while the DDS technology has a fast frequency conversion speed and high frequency resolution, and can achieve fast frequency switching in the digital domain, but is limited by the output frequency upper limit and spurious indexes. Combining PLL and DDS technologies can realize a frequency synthesizer with both fast frequency switching and high spectral purity. A high-frequency reference signal is generated by DDS and then frequency synthesized and phase locked through PLL to obtain the required output frequency. This method has a wide range of application scenarios in the fields of communication, measurement and control, radar, and medical treatment.

[0003] Fast and accurate frequency switching is the key to frequency agility. By combining PLL and DDS, a frequency switching time in the microsecond level can be achieved, maintaining low spurs and low phase noise, meeting the requirements of modern radar and frequency modulation communication systems. At the same time, through precise frequency control and adjustment, the generation of linear frequency modulation signals can also be realized, which plays an important role in radar detection, target tracking, and communication systems.

[0004] Existing linear frequency modulation signal systems, such as a system for generating broadband linear frequency modulation signals with the publication number CN108983157A, include: an initial module for generating a first frequency modulation signal; a phase-locked loop module communicatively connected to the initial module for converting the first frequency modulation signal into a second frequency modulation signal; and a modulation module communicatively connected to the phase-locked loop module for converting the second frequency modulation signal into a third frequency modulation signal. The linear frequency modulation signal of this patent only uses PLL without adopting DDS, resulting in limited frequency resolution and accuracy, slow frequency switching speed, slow linear frequency modulation speed, and inaccurate phase and amplitude control, which limits its performance in applications requiring high-precision and high-performance frequency synthesis. Summary of the Invention

[0005] The purpose of the present invention is to provide a linear frequency modulation signal circuit based on DDS. By combining DDS and PLL, the high frequency resolution and fast conversion speed of DDS, as well as the high-frequency output and good phase noise performance of PLL, can be fully utilized; through the dual-channel DDS circuit switch switching mechanism, the linear frequency modulation and frequency agility time are effectively shortened, fast frequency switching is realized, and a relatively high output frequency and stable phase noise are maintained.

[0006] To solve the above problems, the technical solution of the present invention is as follows: A linear frequency modulation signal circuit based on DDS, comprising: a communication circuit, an FPGA control circuit, a clock circuit, a PLL circuit and a DDS circuit; The communication circuit is connected to an external circuit and the FPGA control circuit, receives a linear frequency modulation signal parameter instruction input externally, and transmits it to the FPGA control circuit; The clock circuit receives a reference clock input externally, generates and outputs a clock signal for the FPGA control circuit; The FPGA control circuit converts the received signal into corresponding timing logic to control the PLL circuit and the DDS circuit; The PLL circuit generates a reference frequency signal for the DDS circuit according to the signal transmitted by the FPGA control circuit; The DDS circuit generates and outputs a frequency agile signal or a linear frequency modulation signal according to the signals transmitted by the FPGA control circuit and the PLL circuit; Wherein, the DDS circuit includes a first DDS circuit, a second DDS circuit and a switch circuit. The input ends of the first DDS circuit and the second DDS circuit are electrically connected to the PLL circuit, and the output ends of the first DDS circuit and the second DDS circuit are electrically connected to the switch circuit; the timing control pins of the first DDS circuit and the second DDS circuit are electrically connected to the FPGA control circuit; the FPGA control circuit configures the frequency control word and the frequency step register of the DDS circuit through a serial port, so that the DDS circuit outputs a frequency agile signal or a linear frequency modulation signal.

[0007] According to an embodiment of the present invention, the input end of the PLL circuit is connected to an external reference clock, the RF output N end of the PLL circuit is electrically connected to the input end of the DDS circuit, and the serial port input end of the PLL circuit is electrically connected to the FPGA control circuit; After the linear frequency modulation signal circuit of the DDS circuit is powered on, the FPGA control circuit configures the registers of the DDS circuit through a serial port, performs timing control on the DDS circuit, and writes a frequency control word to the PLL circuit to lock and output the frequency required by the user.

[0008] According to an embodiment of the present invention, after the output frequency of the PLL circuit is continuously locked for a preset time, the FPGA control circuit initializes the registers of the DDS circuit, receives the signal sent by the communication circuit, realizes the control of the DDS circuit, and enables the DDS circuit to output a linear frequency modulation signal.

[0009] According to an embodiment of the present invention, when the communication circuit sends a signal to indicate that the first DDS circuit outputs a chirp signal, the FPGA control circuit controls the switch circuit to turn on the first DDS circuit, so that the first DDS circuit outputs a frequency-agile signal or a chirp signal; meanwhile, the FPGA control circuit sends a frequency control word of a preset chirp signal to the second DDS circuit for setting data. When the communication circuit sends a signal to indicate switching to the second DDS circuit to output a chirp signal, the FPGA control circuit controls the switch circuit to turn on the second DDS circuit and turn off the first DDS circuit; based on the frequency control word, the second DDS circuit outputs a chirp signal or a frequency-agile signal after being switched by the switch circuit.

[0010] According to an embodiment of the present invention, the switch circuit is a microwave switch, and the frequency-agile time of the DDS circuit is controlled by the switch frequency. By adjusting the frequency of the switch circuit, the frequency-agile time of the DDS circuit is increased to the nanosecond level.

[0011] According to an embodiment of the present invention, the chirp signal circuit based on DDS further includes a power supply circuit. The power supply circuit distributes the voltage by adjusting the resistance value of an external input +5V voltage, outputs a 3.3V analog voltage to the PLL circuit and the clock circuit, outputs a 3.3V digital voltage to the FPGA control circuit and the communication circuit, and outputs a 2.5V analog voltage to the DDS circuit.

[0012] According to an embodiment of the present invention, the communication circuit, the FPGA control circuit, the clock circuit, the PLL circuit, the DDS circuit and the power supply circuit are integrated on an HTCC ceramic substrate through SIP packaging technology. BGA chips are implanted on the back of the HTCC ceramic substrate, and corresponding signals are transmitted by the BGA chips.

[0013] According to an embodiment of the present invention, the differential input pins and output pins of the communication circuit are electrically connected to the BGA chip. The communication circuit converts the differential signals RX+ and RX- into a single-ended TTL logic level RX, or converts the single-ended signal TX into differential signals TX+ and TX- for output.

[0014] Due to the above technical solutions, the present invention has the following advantages and positive effects compared with the prior art: 1) In the linear frequency modulation signal circuit based on DDS in an embodiment of the present invention, for the traditional frequency agile circuit that uses a single-channel DDS circuit to output signals, the frequency agile rate is limited by the performance of the DDS itself, generally at the microsecond level. The present invention uses a switch to control the output and switching of two DDS circuits. When one DDS circuit is outputting a frequency agile signal, the other DDS circuit has completed the data setting operation. Therefore, when it is necessary to switch the output signal, the working DDS circuit can be immediately turned off, and at the same time, the other DDS circuit that has completed the data setting can be turned on. The frequency agile rate is determined by the switch switching frequency, and the frequency agile rate is increased to 20 ns.

[0015] 2) For the traditional hierarchical design idea, the architecture divided into a radio frequency layer, a local oscillator layer, and a control layer according to functions results in a large overall size of the system. In order to achieve system integration, the present invention adopts a more compact and efficient architecture design scheme. By reasonably designing the layout of each module and the radio frequency transmission line, the PLL circuit, DDS circuit, control circuit FPGA, clock circuit, and LDO circuit are integrated through the SIP packaging process. A ceramic substrate made by the high-temperature co-fired ceramic process is used as the substrate, and multiple integrated circuit chips and passive devices are integrated in a single package to form a system-level product with perfect functions, having the advantages of high integration and miniaturization. This integrated packaging method simplifies the assembly steps, reduces the number of connectors and cavities, thereby reducing costs and assembly complexity, improving production efficiency, ensuring the consistency of the system radio frequency performance, and enhancing the stability and reliability of the system.

[0016] 3) For the traditional components that use radio frequency connectors and low-frequency connectors for power supply and signal transmission, resulting in an increase in the size of the components, the present invention implants balls on the back of the HTCC substrate, and the power signal, input reference signal, and radio frequency output signal are transmitted through BGA balls, realizing high-density circuit wiring, further reducing the size of the linear frequency modulation signal circuit. Compared with the traditional cables and connectors, the BGA ball has lower transmission loss. In this design, the BGA balls are arranged in an array, and the BGA balls for grounding signals are distributed around the BGA balls for transmitting radio frequency signals to form a microwave shield, making the microwave shielding and electromagnetic compatibility of the circuit better. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a block diagram of the linear frequency modulation signal circuit based on DDS in an embodiment of the present invention; Figure 2 is a power supply circuit diagram in an embodiment of the present invention; Figure 3 is an integration schematic diagram of the linear frequency modulation signal circuit based on DDS in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The following further elaborates in detail on a linear frequency modulation signal circuit based on DDS proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer based on the following description and the claims.

[0019] Please refer to Figure 1 , this embodiment provides a linear frequency modulation signal circuit based on DDS, including a communication circuit, an FPGA control circuit, a clock circuit, a PLL circuit, and a DDS circuit; wherein, the communication circuit connects the external circuit and the FPGA control circuit, receives the linear frequency modulation signal parameter instruction input externally, and transmits it to the FPGA control circuit. The clock circuit receives the external input reference clock, generates and outputs a clock signal for the FPGA control circuit. The FPGA control circuit converts the received signal into corresponding timing logic to control the PLL circuit and the DDS circuit. The PLL circuit generates a reference frequency signal for the DDS circuit according to the signal transmitted by the FPGA control circuit. The DDS circuit generates and outputs a frequency agile signal or a linear frequency modulation signal according to the signals transmitted by the FPGA control circuit and the PLL circuit.

[0020] Among them, the DDS circuit includes a first DDS circuit, a second DDS circuit, and a switch circuit. The input ends of the first DDS circuit and the second DDS circuit are electrically connected to the PLL circuit, and the output ends of the first DDS circuit and the second DDS circuit are electrically connected to the switch circuit; the timing control pins of the first DDS circuit and the second DDS circuit are electrically connected to the FPGA control circuit. The FPGA control circuit configures the frequency control word and the frequency step register of the DDS circuit through a serial port, so that the DDS circuit outputs a frequency agile signal or a linear frequency modulation signal.

[0021] Specifically, this linear frequency modulation signal circuit based on DDS uses an external reference clock of 100 MHz. The quality of the clock source has a direct impact on the AC characteristics of the chip, especially in a system involving high-precision signal processing. The phase noise and excitation characteristics of a specific frequency clock source need to meet specific requirements, and the parameters and excitation can be directly coupled to the quality of the output signal.

[0022] The input end of the clock circuit is connected to the 100 MHz external reference clock, and the output end is connected to the FPGA control circuit. The external reference clock is a sine signal. The clock circuit converts the sine signal into a CMOS signal through a level and inputs it into the FPGA as the system clock of the FPGA. The phase-locked loop integrated inside the clock chip locks the output clock to the input reference clock, and its output clock and the input clock have the same frequency and phase, featuring low output jitter and low skew between output ports. The 3.3V voltage of the clock circuit is provided by the LDO circuit.

[0023] The PLL circuit includes a phase-locked loop chip and peripheral resistors and capacitors. Among them, the phase-locked loop chip integrates a fractional and integer frequency divider frequency source chip for the VCO, and forms a complete frequency synthesizer with low noise, low power consumption, and high stability through the peripheral resistors and capacitors. The input end of the PLL circuit is connected to an external reference clock of 100 MHz. The N terminal of its RF output RFOUT is connected to the RF input end of the DDS circuit, and the P terminal of the RF output is output through the RF port. The SPI serial port of the PLL circuit is connected to the control circuit FPGA. After the linear frequency modulation signal circuit of the DDS is powered on for 2 ms, the FPGA configures the register through the SPI serial port to perform timing control on it, locks and outputs the frequency required by the user, and realizes frequency multiplication or division of the reference clock signal.

[0024] Optionally, the above phase-locked loop chip can output signal frequencies from 50 MHz to 4 GHz. The output frequency of the PLL frequency source is calculated by the formula. See the following formula, f VCO is the output frequency; N int is the preset integer part division ratio of the output frequency; N frac is the division ratio of the fractional part of the output frequency; f REF is the reference input frequency; R is the preset division ratio of the reference divider.

[0025] The DDS circuit in this embodiment integrates a 14-bit high-speed DAC, programmable DAC current output, supports DAC mixing, and integrates harmonic cancellation, which can improve the spurious suppression ability. The DDS circuit includes two DDS circuits, namely A and B, and a switching circuit. The input end of the DDS circuit is connected to the PLL circuit, and the PLL provides the reference input clock. The output signal of the DDS circuit is connected to the switching circuit, and the timing control pins of the DDS circuit are connected to the FPGA control circuit. The FPGA control circuit configures the frequency control word and frequency step word registers of the DDS chip through the SPI serial port, so that the DDS circuit outputs a frequency agile signal or a linear frequency modulation signal. The switching circuit is connected to the output of the DDS circuit to control the output and switching of the two DDS circuits. The DDS circuit requires 2.5 V and 1.1 V levels. The LDO circuit provides 2.5 V voltage, and the external input is 1.1 V voltage.

[0026] During the frequency locking process of the PLL circuit, the asynchronous reset pin of the DDS circuit is low, and the DDS circuit remains in the low-level reset state. When the PLL circuit is frequency locked for 50 ms, the FPGA control circuit sets the asynchronous reset pin high, initializes the frequency control word and frequency step word registers of the two DDS chips through the SPI serial port, and receives the selection signal from the RS422 serial communication circuit. Its working principle is as follows: When the RS422 serial communication circuit selects the A-channel DDS to output a chirp signal, the FPGA control circuit controls the switch circuit to turn on the A-channel DDS circuit, and this DDS circuit outputs a frequency-agile signal or a chirp signal; meanwhile, the FPGA control circuit sends the frequency control word of the preset chirp signal to the B-channel DDS circuit for setting data operation, so as to quickly switch to the B-channel output when needed. When the RS422 serial communication circuit selects to switch to the B-channel DDS to output a signal, the FPGA controls the switch circuit to turn off the A-channel DDS circuit and turn on the B-channel DDS circuit. Using the pre-set frequency control word, the B-channel DDS circuit outputs a frequency chirp signal.

[0027] The frequency-agile time of the DDS circuit is in the microsecond level, and in this application, two DDS circuits are switched by a microwave switch. The frequency-agile time of the DDS circuit is determined by the switch frequency, and the frequency-agile time can be increased to 20 ns.

[0028] The output frequency of the DDS circuit is obtained by the following formula, f o represents the waveform frequency, f s represents the system clock frequency, FTW is the frequency control word, and the required frequency and the corresponding sine and cosine waveforms are output by changing the frequency word.

[0029] The chirp signal circuit based on DDS in this embodiment further includes a power supply circuit, and this power supply circuit is a low-dropout linear voltage regulator circuit LDO, which provides a stable voltage for the PLL circuit, the DDS circuit, the FPGA control circuit and the clock circuit. Please refer to Figure 2 , this power supply circuit includes an LDO chip and peripheral resistors and capacitors. Among them, the power input pin and the CE pin of the LDO chip input a +5V voltage through BGA ball planting and are grounded through a capacitor. The VOUT and FB pins of the LDO chip distribute a 3.3V analog power supply to the PLL circuit and the clock circuit through the resistance value of the voltage-dividing resistor, a 3.3V digital power supply is input to the FPGA control circuit, and a 2.5V analog power supply is input to the DDS circuit. The resistance value of the LDO circuit is obtained by the following formula.

[0030] In this embodiment, the communication circuit adopts an RS422 serial communication circuit. The differential input pins and output pins of this communication circuit are connected to the external input and output of the BGA balls, and the RS422 serial communication circuit is connected to the FPGA control circuit. The RS422 serial communication circuit converts the differential signals RX+ and RX- into a single-ended TTL logic level RX, and converts the single-ended signal TX into differential signals TX+ and TX- for output, enabling data to be sent and received at different baud rates on the serial communication interface. For the FPGA control circuit, the received serial data is converted into parallel data through the RX interface, and functions with different requirements are implemented according to the codes sent by the host computer. The parallel data is converted into serial data through the TX interface and sent out bit by bit through the data line. The RS422 serial communication circuit is connected to the host computer to control the switching of the FPGA frequency code, signal bandwidth, and chirp signal waveform, and select the signal output of the A or B channel DDS circuit.

[0031] For the above chirp signal circuit based on DDS, the PLL circuit, DDS circuit, communication circuit, clock circuit, FPGA control circuit, and power supply circuit are integrated on the HTCC ceramic substrate through the SIP packaging process. BGA chips are ball-mounted on the back of the HTCC ceramic substrate, and the radio frequency signals, input signals, and voltage signals of the circuit board are transmitted through the BGA.

[0032] For the integrated design of the chirp signal circuit based on DDS, refer to Figure 3 the schematic diagram of the circuit module distribution. After reasonable layout, there are the FPGA control circuit module 01, DDS circuit modules 02 and 03, PLL circuit module 04, switch circuit module 05, clock circuit module 06, RS422 serial communication circuit module 07, 5V to 3.3V digital voltage LDO module 08, 5V to 2.5V voltage LDO module 09, 5V to 3.3V analog voltage LDO module 10. According to the above layout, the size of the chirp signal circuit based on DDS is reduced to 18mm × 18mm × 1.6mm, realizing miniaturization and making up for the troubles caused by insufficient space.

[0033] In summary, for the chirp signal circuit based on DDS in this embodiment, the PLL circuit, DDS circuit, control circuit FPGA, clock circuit, switch circuit, and LDO circuit are integrated on the HTCC ceramic substrate through the SIP packaging process, which can achieve fast and accurate frequency switching and stable and reliable signal output. The combination of DDS and PLL can make full use of the high frequency resolution and fast conversion speed of DDS, as well as the high frequency output and good phase noise performance of PLL. Through the dual-channel DDS circuit switch switching mechanism, the chirp and frequency agility time are effectively shortened, fast frequency switching is achieved, and a high output frequency and stable phase noise are maintained. The present invention has the advantages of miniaturization, simple structure, reasonable design, and good stability, and significantly improves the chirp speed.

[0034] The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, provided that these changes fall within the scope of the claims of the present invention and its equivalent technologies, they still fall within the protection scope of the present invention.

Claims

1. A linear frequency modulation signal circuit based on DDS, characterized in that: include: Communication circuit, FPGA control circuit, clock circuit, PLL circuit and DDS circuit; The communication circuit connects the external circuit and the FPGA control circuit, receives the linear frequency modulation signal parameter instruction input from the outside, and transmits it to the FPGA control circuit; The clock circuit receives an external reference clock, generates and outputs a clock signal for the FPGA control circuit; The FPGA control circuit converts the received signal into corresponding timing logic to control the PLL circuit and the DDS circuit; The PLL circuit generates a reference frequency signal for the DDS circuit according to the signal transmitted by the FPGA control circuit; The DDS circuit generates and outputs an agile frequency signal or a linear frequency modulation signal according to the signal transmitted by the FPGA control circuit and the PLL circuit; Wherein, the DDS circuit includes a first DDS circuit, a second DDS circuit and a switching circuit, the input ends of the first DDS circuit and the second DDS circuit are electrically connected to the PLL circuit, and the output ends of the first DDS circuit and the second DDS circuit are electrically connected to the switching circuit; the timing control pins of the first DDS circuit and the second DDS circuit are electrically connected to the FPGA control circuit; the FPGA control circuit configures the frequency control word and the frequency step register of the DDS circuit through the serial port so that the DDS circuit outputs an agile frequency signal or a linear frequency modulation signal.

2. The linear frequency modulation signal circuit based on DDS as claimed in claim 1, characterized in that: The input end of the PLL circuit is connected to an external reference clock, the RF output N end of the PLL circuit is electrically connected to the input end of the DDS circuit, and the serial port input end of the PLL circuit is electrically connected to the FPGA control circuit; When the linear frequency modulation signal circuit of the DDS circuit is powered on, the FPGA control circuit configures the register of the DDS circuit through the serial port, performs timing control on the DDS circuit, and writes the frequency control word to the PLL circuit to lock and output the frequency required by the user.

3. The linear frequency modulation signal circuit based on DDS as claimed in claim 2, characterized in that: After the output frequency of the PLL circuit is continuously locked for a preset time, the FPGA control circuit initializes the register of the DDS circuit, receives the signal sent by the communication circuit, and controls the DDS circuit so that the DDS circuit outputs a linear frequency modulation signal.

4. The linear frequency modulation signal circuit based on DDS as claimed in claim 1, characterized in that: When the communication circuit sends a signal to instruct the first DDS circuit to output a linear frequency modulation signal, the FPGA control circuit controls the switch circuit to turn on the first DDS circuit, so that the first DDS circuit outputs an agile frequency signal or a linear frequency modulation signal; at the same time, the FPGA control circuit sends a preset frequency control word of the linear frequency modulation signal to the second DDS circuit for a setting operation; When the communication circuit sends a signal indicating switching the second DDS circuit to output a linear frequency modulation signal, the FPGA control circuit controls the switch circuit to turn on the second DDS circuit and turn off the first DDS circuit; based on the frequency control word, the second DDS circuit outputs a linear frequency modulation signal or a fast frequency conversion signal after being switched by the switch circuit.

5. The linear frequency modulation signal circuit based on DDS as claimed in claim 1, characterized in that: The switching circuit is a microwave switch, and the agile frequency change time of the DDS circuit is controlled by the switching frequency. By adjusting the frequency of the switching circuit, the agile frequency change time of the DDS circuit is increased to nanosecond level.

6. The linear frequency modulation signal circuit based on DDS as claimed in claim 1, characterized in that: It also includes a power supply circuit, which distributes the external input +5V voltage by adjusting the resistance value, outputs a 3.3V analog voltage to the PLL circuit and the clock circuit, outputs a 3.3V digital voltage to the FPGA control circuit and the communication circuit, and outputs a 2.5V analog voltage to the DDS circuit.

7. The linear frequency modulation signal circuit based on DDS as claimed in claim 6, characterized in that: The communication circuit, FPGA control circuit, clock circuit, PLL circuit, DDS circuit and power supply circuit are integrated on the HTCC ceramic substrate through the SIP packaging process. The back of the HTCC ceramic substrate is planted with a BGA chip, and the corresponding signal is transmitted by the BGA chip.

8. The linear frequency modulation signal circuit based on DDS as claimed in claim 7, characterized in that: The differential input pins and output pins of the communication circuit are electrically connected to the BGA chip, and the communication circuit converts the differential signals RX+ and RX- into single-ended TTL logic levels RX, or converts the single-ended signal TX into differential signals TX+ and TX- for output.

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