Current quantity analog-digital converter and image sensor

Abstract

The application discloses a current quantification analog-digital converter and an image sensor. The current quantification analog-digital converter comprises a first-stage digital logic control module, a second-stage digital logic control module, a first-stage digital-analog converter, a second-stage digital-analog converter, an output register and a current input stage and a current polarity judgment module connected in sequence; the two digital logic control modules are connected with the current polarity judgment module; the first-stage digital logic control module is connected with the first-stage digital-analog converter, and the second-stage digital logic control module is connected with the second-stage digital-analog converter; the two digital logic control modules are connected with the output register; and the first-stage digital-analog converter and the second-stage digital-analog converter are connected with a current comparator. The current quantification analog-digital converter realizes a two-stage current quantification structure, has a small area and high energy efficiency, can directly quantize a current signal, and has high conversion speed and conversion precision for current quantification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a current-mode analog-to-digital converter and an image sensor. BACKGROUND

[0002] With the continuous development of image sensor technology, the requirements for analog-to-digital converters are also increasing. However, there are still some problems to be solved in the prior art. On the one hand, with the continuous reduction of pixel size, the width of the column-level analog-to-digital converter is limited, making it difficult to further reduce the area. The voltage-mode image sensor in the related art occupies a large area in the column-level design, which becomes extremely challenging in the case of small pixel pitch. On the other hand, the energy efficiency of the analog-to-digital converter is crucial in image sensor design, and advanced image sensor architectures require faster AD conversion speed with minimal power consumption. The voltage-type analog-to-digital converter used in the related art has large area, low energy efficiency, and low quantization conversion speed and conversion accuracy.

[0003] The above statements are only used to provide background technical information related to the present application, and do not necessarily constitute the prior art. SUMMARY

[0004] The purpose of the present application is to provide a current-mode analog-to-digital converter and an image sensor. In order to have a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not a general review, nor is it intended to determine key / important components or delineate the scope of protection of these embodiments. Its only purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0005] According to one aspect of an embodiment of the present application, a current-mode analog-to-digital converter is provided, comprising a first-stage digital logic control module, a second-stage digital logic control module, a first-stage digital-to-analog converter, a second-stage digital-to-analog converter, an output register, and a current input stage and a current polarity judgment module connected in sequence.

[0006] The input end of the first-stage digital logic control module and the input end of the second-stage digital logic control module are both connected to the output end of the current polarity judgment module;

[0007] The first output end of the first-stage digital logic control module is connected to the first-stage digital-to-analog converter, and the first output end of the second-stage digital logic control module is connected to the second-stage digital-to-analog converter;

[0008] The second output end of the first-stage digital logic control module and the second output end of the second-stage digital logic control module are both connected to the output register;

[0009] The first-stage digital-to-analog converter and the second-stage digital-to-analog converter are connected to the current comparator.

[0010] In some embodiments of the present application, the current polarity judging module comprises a current comparator, which comprises a source follower, a voltage negative feedback circuit and an inverter connected in sequence.

[0011] In some embodiments of the present application, the source follower comprises a first NMOS transistor, a first PMOS transistor, a first switch and a second switch, the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor; the first pole of the first NMOS transistor is connected to the first end of the first switch, the second end of the first switch is connected to the first end of the second switch, the second end of the second switch is connected to the first pole of the first PMOS transistor, the second pole of the first NMOS transistor, the second pole of the first PMOS transistor, the second end of the first switch and the gate of the first NMOS transistor are connected to the voltage negative feedback circuit; the second end of the first switch is connected to the input end of the current comparator.

[0012] In some embodiments of the present application, the voltage negative feedback circuit comprises a second PMOS transistor and a second NMOS transistor; the gate of the second NMOS transistor is connected to the gate of the second PMOS transistor and the second end of the first switch respectively; the first pole of the second PMOS transistor is connected to the first pole of the first NMOS transistor; the second pole of the second PMOS transistor is connected to the first pole of the second NMOS transistor and the gate of the first NMOS transistor respectively; the second pole of the second NMOS transistor is connected to the second pole of the first PMOS transistor.

[0013] In some embodiments of the present application, the inverter comprises a third PMOS transistor and a third NMOS transistor; the gate of the third NMOS transistor is connected to the gate of the third PMOS transistor and the second pole of the second PMOS transistor respectively; the first pole of the third PMOS transistor is connected to the first pole of the second PMOS transistor; the second pole of the third PMOS transistor is connected to the first pole of the third NMOS transistor; the second pole of the third NMOS transistor is connected to the second pole of the second NMOS transistor, and the second pole of the third PMOS transistor is connected to the output end of the current comparator.

[0014] In some embodiments of the present application, any one of the first-stage digital-to-analog converter and the second-stage digital-to-analog converter comprises a global structure and a local structure connected to each other, the global structure is used to generate a global current signal; the local structure is a column-level structure, which is used to compare and judge the current signal of the global structure to obtain a column-level quantization result.

[0015] In some embodiments of the present application, the first stage digital-to-current converter comprises a current-mode current digital-to-analog converter or a current-mode successive approximation register digital-to-analog converter.

[0016] In some embodiments of the present application, the second stage digital-to-current converter comprises a current-mode current digital-to-analog converter or a current-mode successive approximation register digital-to-analog converter or a current-mode ramp integral digital-to-analog converter.

[0017] In some embodiments of the present application, the current input stage comprises a simple current mirror, a common-source common-gate current mirror, a low-voltage common-source common-gate current mirror or a Wilson current mirror.

[0018] According to another aspect of the embodiments of the present application, there is provided an image sensor comprising the current quantization analog-to-digital converter of any of the embodiments of the present application.

[0019] One of the aspects of the embodiments of the present application provides technical solutions which can include the following beneficial effects:

[0020] The current quantization analog-to-digital converter provided by the embodiments of the present application comprises a first stage digital logic control module, a second stage digital logic control module, a first stage digital-to-analog converter, a second stage digital-to-analog converter, an output register and a current input stage and a current polarity judgment module connected in sequence, the input end of the first stage digital logic control module and the input end of the second stage digital logic control module are both connected to the output end of the current polarity judgment module, the first output end of the first stage digital logic control module is connected to the first stage digital-to-analog converter, the first output end of the second stage digital logic control module is connected to the second stage digital-to-analog converter, the second output end of the first stage digital logic control module and the second output end of the second stage digital logic control module are both connected to the output register, and the first stage digital-to-analog converter and the second stage digital-to-analog converter are both connected to the current comparator, thereby realizing a two-stage current quantization structure, reducing the area, improving the energy efficiency, directly quantizing the current signal, and improving the conversion speed and conversion precision of the current quantization and the sampling rate.

[0021] The above description is only a summary of the technical solutions of the embodiments of the present application, in order to more clearly understand the technical means of the embodiments of the present application, the embodiments of the present application can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments described in the present application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0023] FIG. 1(a) shows a structural schematic diagram of an SS ADC in the related art.

[0024] FIG. 1(b) shows a curve diagram of working process parameters of the SS ADC in the related art.

[0025] FIG. 1(c) shows a structural schematic diagram of a SAR ADC in the related art.

[0026] FIG. 1(d) shows a curve diagram of working process parameters of the SAR ADC in the related art.

[0027] Figure 2 A structural block diagram of a current-mode analog-to-digital converter is shown in one embodiment of the present application.

[0028] Figure 3 A circuit diagram of a current comparator is shown in one embodiment of the present application.

[0029] FIG. 4(a) shows a circuit diagram of a simple current mirror in one embodiment of the present application.

[0030] FIG. 4(b) shows a circuit diagram of a cascode current mirror in one embodiment of the present application.

[0031] FIG. 4(c) shows a circuit diagram of a low-voltage cascode current mirror in one embodiment of the present application.

[0032] Figure 5 A structural block diagram of a current-mode analog-to-digital converter is shown in another embodiment of the present application.

[0033] Figure 6 A structural schematic diagram of a SAR DAC is shown in one embodiment of the present application.

[0034] Figure 7 A structural schematic diagram of a ladder DAC is shown in one embodiment of the present application.

[0035] Figure 8 A structural schematic diagram of an SS DAC is shown in one embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the present application clearer, further description will be given to the present application in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0037] As will be understood by one of skill in the art, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined herein. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0038] With the continuous advancement of image sensor technology, the application of analog-to-digital converters in image sensors becomes increasingly important. Image sensors first capture optical signals and convert them into electrical signals, and then convert the electrical signals into digital signals through ADCs for subsequent processing. In this process, the performance of the ADC directly affects the image quality and overall energy efficiency of the system. With the increase in resolution and dynamic range, the performance requirements for ADCs are also increasing, which requires ADCs to have higher sampling rates, lower power consumption, and smaller areas to meet the needs of miniaturization and high performance.

[0039] Most image sensors in the related art use voltage-mode single slope ADC (SSADC) or voltage-mode successive approximation register ADC (SAR ADC), each of which has its own characteristics. Referring to FIG. 1(a), the structure of SS ADC includes sample / hold circuits (S / H circuits), a ramp generation circuit, a comparator, and a counter. Referring to FIG. 1(b), the ramp generation circuit generates a ramp signal, which is compared with an input signal in the comparator, while the counter starts counting. When the output of the comparator flips, the counter stops counting, and the digital value of the counter at this time is the quantized value. The structure of SS ADC is simple and easy to implement, but its conversion time is proportional to the quantization accuracy, and the speed is relatively slow, so it is suitable for low-frequency signal applications and is usually used in image sensors with low performance requirements. Referring to FIG. 1(c), SAR ADC is composed of sample / hold circuits, a digital-to-analog converter (DAC), a comparator, and a SAR logic control circuit. Referring to FIG. 1(d), SAR ADC gradually approaches the value of the input signal through a bit-by-bit search algorithm until it completely matches. The bit-by-bit search algorithm compares from the most significant bit to the least significant bit, gradually approaching the value of the input signal with the smallest step. Compared with SS ADC, SAR ADC has higher conversion speed and lower power consumption, and is suitable for high-frequency signal and low-power image sensor applications. However, the SAR ADC based on a capacitive digital-to-analog converter (CDAC) in the related art occupies a large silicon area in terms of capacitance and high-gain operational amplifier area. As the pixel area gradually shrinks, this implementation becomes increasingly difficult.

[0040] In addition, the emergence of some new current-mode pixels in the related art poses new challenges to ADCs in image sensors. In addition, some new current-mode pixels that output a current as a signal also pose new requirements for analog-to-digital converters (ADCs). These challenges limit the application range of voltage-mode ADCs. The use of voltage-mode ADCs in the related art requires an additional current-to-voltage conversion module, consumes additional power and area, and greatly increases the design difficulty of column-level ADCs.

[0041] Compared with a voltage type ADC in the related art, an embodiment of the present application provides a current quantization analog-digital converter, which comprises a first-stage digital logic control module, a second-stage digital logic control module, a first-stage digital-analog converter, a second-stage digital-analog converter, an output register, and a current input stage and a current polarity judgment module connected in sequence, the input end of the first-stage digital logic control module and the input end of the second-stage digital logic control module are both connected to the output end of the current polarity judgment module, the first output end of the first-stage digital logic control module is connected to the first-stage digital-analog converter, the first output end of the second-stage digital logic control module is connected to the second-stage digital-analog converter, the second output end of the first-stage digital logic control module and the second output end of the second-stage digital logic control module are both connected to the output register, and the first-stage digital-analog converter and the second-stage digital-analog converter are both connected to a current comparator, thereby realizing a two-stage current quantization structure, reducing the area, improving the energy efficiency, directly quantizing the current signal, and improving the conversion speed and conversion precision of the current quantization and the sampling rate.

[0042] An embodiment of the present application provides a current quantization analog-digital converter and an image sensor.

[0043] Reference Figure 2 An embodiment of the present application provides a current quantization analog-digital converter, which can comprise a first-stage digital logic control module, a second-stage digital logic control module, a first-stage digital-analog converter, a second-stage digital-analog converter, an output register, and a current input stage and a current polarity judgment module connected in sequence.

[0044] The input end of the first-stage digital logic control module and the input end of the second-stage digital logic control module are both connected to the output end of the current polarity judgment module.

[0045] The first output end of the first-stage digital logic control module is connected to the first-stage digital-analog converter, and the first output end of the second-stage digital logic control module is connected to the second-stage digital-analog converter.

[0046] The second output end of the first-stage digital logic control module and the second output end of the second-stage digital logic control module are both connected to the output register.

[0047] The first-stage digital-analog converter and the second-stage digital-analog converter are both connected to a current comparator.

[0048] Exemplarily, the current polarity judgment module comprises a current comparator, as shown in Figure 3 The current comparator comprises a source follower 1, a voltage negative feedback circuit 2, and an inverter 3 connected in sequence.

[0049] Exemplarily, as shown in Figure 3 The source follower 1 comprises a first NMOS tube N1, a first PMOS tube P1, a first switch SCOMP1 Second switch S COMP2 The gate of the first NMOS transistor N1 is connected to the gate of the first PMOS transistor P1; the first terminal of the first NMOS transistor N1 is connected to the first switch S. COMP1 The first end, the first switch S COMP1 The second end is connected to the second switch S COMP2 The first terminal, the second switch S COMP2 The second terminal is connected to the first terminal of the first PMOS transistor P1, the second terminal of the first NMOS transistor N1, the second terminal of the first PMOS transistor P1, and the first switch S. COMP1 The second terminal and the gate of the first NMOS transistor N1 are both connected to a voltage negative feedback circuit; the first switch S COMP1 The second terminal is connected to the input terminal of the current comparator.

[0050] For example, refer to Figure 3 As shown, the voltage negative feedback circuit 2 includes a second PMOS transistor P2 and a second NMOS transistor N2; the gate of the second NMOS transistor N2 is connected to the gate of the second PMOS transistor P2 and the first switch S, respectively. COMP1 The second terminal is connected; the first terminal of the second PMOS transistor P2 is connected to the first terminal of the first NMOS transistor N1; the second terminal of the second PMOS transistor P2 is connected to the first terminal of the second NMOS transistor N2 and the gate of the first NMOS transistor P1 respectively; the second terminal of the second NMOS transistor N2 is connected to the second terminal of the first PMOS transistor P1.

[0051] For example, refer to Figure 3 As shown, inverter 3 includes a third PMOS transistor P3 and a third NMOS transistor N3; the gate of the third NMOS transistor N3 is connected to the gate of the third PMOS transistor P3 and the second terminal of the second PMOS transistor P2, respectively; the first terminal of the third PMOS transistor P3 is connected to the first terminal of the second PMOS transistor P2; the second terminal of the third PMOS transistor P3 is connected to the first terminal of the third NMOS transistor N3; the second terminal of the third NMOS transistor N3 is connected to the second terminal of the second NMOS transistor N2; and the second terminal of the third PMOS transistor P3 is connected to the output terminal of the current comparator.

[0052] For example, either the first-stage digital-to-analog converter or the second-stage digital-to-analog converter includes an interconnected global structure and a local structure. The global structure is used to generate a global current signal, and the local structure is a column-level structure used to compare and judge the current signal of the global structure to obtain a column-level quantization result.

[0053] For example, the first-stage digital-to-analog converter includes a current-mode ladder digital-to-analog converter or a current-mode successive approximation register digital-to-analog converter.

[0054] Exemplarily, the second-stage digital-to-analog converter comprises a current-mode staircase digital-to-analog converter or a current-mode successive approximation register digital-to-analog converter or a current-mode ramp-integrator digital-to-analog converter.

[0055] Exemplarily, the current input stage comprises a simple current mirror, a common-source common-gate current mirror, a low-voltage common-source common-gate current mirror or a Wilson current mirror. Fig. 4(a) shows the structure of a simple current mirror, Fig. 4(b) shows the structure of a common-source common-gate current mirror, and Fig. 4(c) shows the structure of a low-voltage common-source common-gate current mirror.

[0056] The current quantification analog-to-digital converter of the embodiment of the present application realizes a two-stage current quantification structure, has a small area and high energy efficiency, can directly quantify a current signal, has high conversion speed and conversion precision of current quantification, and has a high sampling rate.

[0057] Reference Figure 5 As shown in the drawings, another embodiment of the present application proposes a current quantification analog-to-digital converter, which is a two-stage current-mode analog-to-digital converter (ADC) architecture applied to an image sensor, and aims to have high conversion energy efficiency and faster conversion speed while keeping a small column-level area. The two-stage structure comprises a coarse quantification stage and a fine quantification stage, and by reasonably adjusting the quantification precision of the two stages, the two-stage structure can be flexibly applied to image sensors with different requirements to realize efficient signal conversion. In the AD conversion process, the input current is first coarsely quantified by the first stage, and then the quantification result is refined by the second stage, so as to achieve high-precision quantification. Figure 5 The first-stage IDAC is a first-stage digital-to-analog converter, the second-stage IDAC is a second-stage digital-to-analog converter, the first-stage control module is a first-stage digital logic control module, and the second-stage control module is a second-stage digital logic control module. The current I DAC1 output by the first-stage digital-to-analog converter is added to the current I DAC2 output by the second-stage digital-to-analog converter to obtain a current I DAC . The current I IN input into the current input stage is subtracted from the current I SAMPLE output by the current input stage to obtain a current I SAMPLE . The current I DAC is input into the current input comparator.

[0058] In the first stage of coarse quantization, the current DAC module generates a corresponding reference current, and the input current is judged by the current comparator to obtain the high-bit quantization result DH, and the reference current is maintained as the basis for subsequent fine quantization. Next, the second stage of fine quantization module quantizes the input current more finely to obtain the low-bit quantization result DL, and finally DH and DL are combined to obtain the complete quantization result of the two-stage ADC. This two-stage ADC architecture not only solves the problem of limited ADC area in small pixel pitch image sensors in the structural design, but also meets the application requirements of high speed and low power consumption.

[0059] Two-stage ADC structure:

[0060] The two-stage current-mode ADC structure of the embodiments of the present application realizes high-precision analog-to-digital conversion of the input signal through the combination of the coarse quantization stage and the fine quantization stage. First, the first stage of coarse quantization is used to determine the approximate interval of the input current and generate a preliminary digital quantization result, referred to as the high-bit quantization result (DH). The reference current generated in this coarse quantization stage is maintained for the subsequent fine quantization process. Next, the second stage of fine quantization accurately quantizes the remaining signal to obtain the low-bit quantization result (DL). By combining DH and DL, the two-stage ADC realizes a high-precision quantization process.

[0061] In the entire AD conversion process, the input signal is first quantized by the first stage, and the coarse quantization result is used to set the reference current for fine quantization, ensuring that the second stage can further quantize the subtle changes in the signal. The combination of the two-stage structure not only enables the ADC to have high quantization accuracy, but also effectively balances the area and power consumption. At the same time, the ADC structure is divided into a global structure and a local structure. In the ADC structure used in image sensor applications, the global structure generates a global current signal, and the local structure is a column-level structure, with one column configured for each column to receive the current from the global structure and make a comparison and judgment in the local area to obtain the column-level quantization result. In the embodiments of the present application, the area of the local structure is compressed to a very small size to adapt to applications with small array pitch.

[0062] Current comparator design:

[0063] In the ADC architecture of the present embodiment, the current comparator is one of the key modules for realizing accurate signal conversion. The main function of the comparator is to judge the polarity of the input current and generate a comparison signal CMP to help determine the AD conversion result. Figure 3 The structure diagram of the current comparator in the embodiments of the present application is shown, which adopts a structure composed of a source follower and voltage negative feedback to realize efficient polarity judgment. At the same time, in order to effectively control the power consumption, a power consumption control switch SCOMP is added in the comparator design, which allows the comparator to cut off the feedback branch in the non-working state, thereby reducing the overall power consumption.

[0064] Non-working state: when the current comparator is in the non-working state, the SCOMP switch is open, cutting off the feedback branch, ensuring no power consumption in standby mode.

[0065] Working state: when the current comparator is working, the SCOMP is closed, connecting the feedback branch, making the comparator work normally and completing the judgment of the current polarity. This design can realize flexible switching between low power consumption and normal work of the comparator, ensuring the energy efficiency performance in different working modes.

[0066] Three sub-ADC structures:

[0067] In order to realize efficient analog-to-digital conversion, the embodiment adopts three current-mode sub-ADC (sub-ADC) architectures, which are current-mode successive approximation register (SAR) ADC, current-mode ladder ADC, and current-mode slope integration (SS) ADC. These sub-ADCs are composed of current DAC modules, current comparators (as shown in Figure 3 Among them, the architectures of Ladder ADC and SAR ADC are suitable for the first-stage coarse quantization structure, and the second-stage fine quantization can apply all three architectures. The basic unit constituting these architectures is various current mirrors, and the appropriate current mirror structure is selected according to the specific application requirements. Next, the structure of the DAC in the three current-mode sub-ADCs proposed in the application embodiment will be introduced in detail. Current mirrors are used as the basic unit in each DAC, which has a simple structure and can work at low power voltage.

[0068] Current-mode SAR DAC structure:

[0069] As shown in Figure 6 , the current-mode SAR DAC structure adopts a hierarchical current mirror design, which divides the current mirror structure into two parts. One part is placed in the global part to receive the reference current source and generate reference current bias voltages VBIASCS and VBIASCG; the other part of the current mirror is located in the column-level structure, which amplifies the reference current by adjusting the transistor size and controls the access to the branch IDAC of the total current through the switch.

[0070] In order to shorten the settling time of the circuit, a dummy load branch is added in the current branch IDUM, and the control signals SDi and SDBi are complementary, generated by a two-phase non-overlapping circuit, to ensure that the total current flowing through the current DAC always remains stable. SPWR and SPWRB are a set of complementary reference current input control signals, SPWR is closed to start the DAC when the ADC is working, and SPWR is open to reduce power consumption when the ADC is in standby state. N-bit DAC requires 2N-1 sets of half-current mirror structure, and N clock cycles are required for the AD conversion process.

[0071] Current-mode Ladder DAC structure

[0072] As shown in Figure 7 , the current-mode Ladder DAC structure replicates the reference current ILSB into multiple groups of currents from 0 to N-1 times by current mirrors in the global part. These currents flow into the respective current mirror structures to generate corresponding gate voltages VCSi. In the column-level structure, different multiples of currents are selected by an analog multiplexer and connected to the current mirror.

[0073] In the AD conversion process, the multiplexer is controlled to connect the currents from 0 to N-1 times to the gate in turn, to establish the current IDAC_LADDER step by step, and to compare it with the input current, so as to finally determine the interval in which the input current is located, and to latch the result. The entire AD conversion process also controls the power consumption through the SPWR switch. The N-bit DAC needs an N-to-1 multiplexer and a half-current mirror structure, and the AD conversion process needs 2N-1 clock cycles.

[0074] Current-mode SSDAC structure

[0075] As shown in Figure 8 , the current-mode SSDAC structure replicates the reference current ILSB into 2N branches by current mirrors in the global part, and each branch is controlled by a switch SDi. In order to stabilize the circuit bias state, a dummy load branch is also used. All branches are connected to a half-current mirror to generate the gate voltage VCS, and the column-level half-current mirror structure is used to generate the current IDAC_SS.

[0076] In the AD conversion process, the 2N branches are connected in turn to form a rising ramp current IDAC_SS, which is compared with the input current. When the comparator output flips, the code value recorded by the counter is the final AD conversion result. The SPWRB is used to control the power consumption, and only a small amount of leakage power is consumed when the ADC is in the standby state.

[0077] The current input stage is used to receive the input current from the pixel and to achieve impedance matching with the DAC module, and its basic structure is various current mirror structures shown in FIG. 4(a), FIG. 4(b) and FIG. 4(c). When working, the input current is subtracted from the reference current generated by the DAC module to obtain the differential current IDIFF, which is sent to the current comparator for polarity judgment, and then the comparison output signal CMP is generated. In the AD conversion process, the input current and the reference current generated by the DAC module are compared constantly. When the CMP signal flips, it means that the input current is equal to the reference current, at which time the digital code value is recorded as the final AD conversion result. The current input stage uses the current mirror as the basic unit, which has a simple structure and can work at a low power supply voltage.

[0078] In some examples, one sub-ADC structure is composed of a DAC, a current comparator and a digital control part. The digital control part is composed of dedicated digital circuits such as finite state machine (FSM), counter, etc. Its main functions include generating control signals such as start, stop, reset, etc. and providing appropriate digital input values for the DAC to complete the AD conversion process. In each control circuit, the finite state machine is an indispensable component responsible for managing the overall working state of the ADC, such as reset state, comparison state and completion state, etc. While the control signal of the DAC is different according to different types of ADC.

[0079] Specifically, for Ladder ADC and SS ADC, the control signal of the DAC is generated by the counter. The counter generates a gradually rising current ramp signal in the DAC by controlling the digital code to increment each time. The current signal is compared with the input signal constantly in each period, and when the output result CMP of the comparator flips, the current digital code value is recorded as the quantization result of the ADC and sent to the output register. For SAR ADC, the control signal of the DAC is generated by the dedicated SAR logic. After each comparison is completed, the digital code decides whether to flip the corresponding bit according to the result of CMP, thereby controlling the DAC to generate a signal that gradually approximates the input current. After completing the search of the last bit, the current code value is recorded and sent to the output register as the final comparison result. In summary, all digital parts in the ADC are collectively referred to as the digital control part, which is responsible for managing and coordinating the operation of the ADC modules to ensure the accuracy and efficiency of the AD conversion process.

[0080] The current-mode analog-to-digital converter provided by the embodiments of the present application is a current-mode analog-to-digital converter with small area and high energy efficiency, which is suitable for image sensors with small pixel pitch. By optimizing the structure and working mode of the analog-to-digital converter, the embodiments of the present application can realize high-performance analog-to-digital conversion in a limited column-level width and improve the energy efficiency of the system, which not only solves the design difficulty under small pixel pitch, but also meets the demand of high-speed and low-power application.

[0081] The embodiments of the present application also propose a method of quantizing current based on a two-stage structure, which can ensure the conversion speed and conversion accuracy of the current simultaneously; the embodiments of the present application propose a method of dividing the ADC structure in the image sensor into global structure and local structure, and the idea and method of minimizing the area and power consumption of the local structure; the embodiments of the present application propose a new power management type current comparator structure; the sub-ADC structure of the embodiments of the present application includes but is not limited to SS ADC structure, Ladder ADC structure and SAR ADC structure, which meets the demand of small area and low power consumption of two-stage current-mode ADC.

[0082] Compared with the voltage mode quantization, the current mode quantization structure adopts a current mirror structure, so the power supply voltage can be lower and the power consumption can be smaller; while ensuring the accuracy, the column-level circuit structure is greatly reduced in area compared with the existing structure, and more ADC channels can be integrated in the limited image sensor chip; compared with the small-area single-slope analog-to-digital converter, the structure proposed in the embodiment of the application has fewer conversion periods and faster conversion speed; and it is suitable for current output pixels and does not need to do current-voltage conversion.

[0083] The above description of the various embodiments tends to emphasize the differences between the various embodiments, and the same or similar parts can be referred to each other, and will not be described herein for the sake of brevity.

[0084] Another embodiment of the application provides an image sensor comprising the current analog-to-digital converter of any embodiment of the application.

[0085] The above description of the various embodiments tends to emphasize the differences between the various embodiments, and the same or similar parts can be referred to each other, and will not be described herein for the sake of brevity.

[0086] It should be noted that: the above embodiments only express the implementation of the application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the application. It should be noted that, for those skilled in the art, without departing from the concept of the application, a number of modifications and improvements can be made, which are all within the scope of protection of the application. Therefore, the protection scope of the application should be subject to the appended claims.

Claims

1. A current-quantized analog-to-digital converter, characterized in that, It includes a first-level digital logic control module, a second-level digital logic control module, a first-level digital-to-analog converter, a second-level digital-to-analog converter, an output register, and a current input stage and a current polarity determination module connected in sequence; the current polarity determination module includes a current comparator; The input terminals of the first-level digital logic control module and the second-level digital logic control module are both connected to the output terminal of the current polarity determination module; The first output terminal of the first-stage digital logic control module is connected to the first-stage digital-to-analog converter, and the first output terminal of the second-stage digital logic control module is connected to the second-stage digital-to-analog converter. Both the second output terminal of the first-level digital logic control module and the second output terminal of the second-level digital logic control module are connected to the output register; Both the first-stage digital-to-analog converter and the second-stage digital-to-analog converter are connected to the current comparator; The current output by the first-stage digital-to-analog converter is added to the current output by the second-stage digital-to-analog converter to obtain the current I. DAC The current input stage receives the input current, and the current output by the current input stage is the same as the current I. DAC The current obtained by subtraction is input into the current comparator. The first-stage digital-to-analog converter generates a corresponding reference current, and the high-order quantization result DH is obtained by the current comparator. The second-stage digital-to-analog converter further quantizes the reference current to obtain the low-order quantization result DL. The output register combines the DH and DL to output the complete quantization result.

2. The current quantization analog-to-digital converter according to claim 1, characterized in that, The current comparator includes a source follower, a first inverter, and a second inverter. The input of the current comparator is output through the first inverter and the second inverter connected in series. The input of the source follower is connected to the output of the first inverter, and the output of the source follower is connected to the output of the current comparator.

3. The current quantization analog-to-digital converter according to claim 2, characterized in that, The source follower includes a first NMOS transistor, a first PMOS transistor, a first switch, and a second switch. The gate of the first NMOS transistor is connected to the gate of the first PMOS transistor. The source of the first NMOS transistor is connected to a first terminal of the first switch, the second terminal of the first switch is connected to a first terminal of the second switch, the second terminal of the second switch is connected to the source of the first PMOS transistor, and the second terminal of the first switch is connected to the input terminal of the current comparator. The drain of the first NMOS transistor is connected to VDDA, and the drain of the first PMOS transistor is connected to VSSA. The first inverter includes a second PMOS transistor and a second NMOS transistor; the gate of the second NMOS transistor is connected to the gate of the second PMOS transistor and the second terminal of the first switch, respectively; the source of the second PMOS transistor is connected to the source of the first NMOS transistor; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the first NMOS transistor, respectively; the source of the second NMOS transistor is connected to the drain of the first PMOS transistor; the source of the second PMOS transistor is connected to VDDA; the source of the second NMOS transistor is connected to VSSA.

4. The current-quantized analog-to-digital converter according to claim 3, characterized in that, The second inverter includes a third PMOS transistor and a third NMOS transistor; the gate of the third NMOS transistor is connected to the gate of the third PMOS transistor and the drain of the second PMOS transistor, respectively; the source of the third PMOS transistor is connected to the source of the second PMOS transistor; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor; the source of the third NMOS transistor is connected to the source of the second NMOS transistor; the drain of the third PMOS transistor is connected to the output terminal of the current comparator; the source of the third PMOS transistor is connected to VDDA; the source of the third NMOS transistor is connected to VSSA.

5. The current-quantized analog-to-digital converter according to claim 1, characterized in that, The first-stage digital-to-analog converter includes a current-mode ladder digital-to-analog converter or a current-mode successive approximation register digital-to-analog converter.

6. The current-quantized analog-to-digital converter according to claim 1, characterized in that, The second-stage digital-to-analog converter includes a current-mode ladder digital-to-analog converter, a current-mode successive approximation register digital-to-analog converter, or a current-mode ramp-integral digital-to-analog converter.

7. The current-quantized analog-to-digital converter according to claim 1, characterized in that, The current input stage includes a simple current mirror, a cascode current mirror, a low-voltage cascode current mirror, or a Wilson current mirror.

8. An image sensor, characterized in that, Includes the current quantization analog-to-digital converter according to any one of claims 1-7.

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