Frequency hopping signal timing synchronization device in phased beam agility mode

Abstract

The invention discloses a frequency hopping signal timing synchronization device in a phased beam agility mode. The frequency hopping signal timing synchronization device comprises a clock synchronization unit, a digital resampling unit, a capturing unit, a matched filtering unit, a hopping pulse generation unit and a timing synchronization unit. A satellite-ground time error is obtained by capturing an initial synchronization sequence of each frame, then clock synchronization is carried out through a clock synchronization unit, one-time matched filtering processing is carried out on each hop of synchronized data, and then a timing synchronization unit caches multi-hop data and calculates a timing error. And finally, performing interpolation processing on the data according to the timing error and outputting the timed data. According to the technology, frequency hopping signal timing synchronization in an agile mode can be realized. The technology is suitable for a fast frequency hopping and beam agility satellite communication system.

Description

Technical Field

[0001] The present invention relates to a timing synchronization device for frequency-hopping signals in the phased-array beam agility mode in the field of communications, and is particularly applicable to a fast frequency-hopping and beam-agility satellite communication system. In the frequency-hopping system, the phased-array beam agility may cause the receiver to be unable to receive signals for a long time, resulting in an excessive deviation between the transceiver clocks and difficulty in data timing synchronization. The present invention can quickly perform signal timing synchronization in the beam-agility environment. Background Art

[0002] With the extensive application of phased-array antennas in recent years, it is difficult to synchronize the timing of frequency-hopping systems in the phased-array beam agility mode. During the phased-array beam agility period, the terminal cannot receive signals when the phased-array antenna scans other beam positions, which causes an increase in the satellite-ground time difference, resulting in an excessive satellite-ground frequency-hopping moment and affecting the terminal signal reception and the calculation of in-hop timing errors. In the Gardner loop timing recovery technology in the phased-array agility mode, there is a problem that the timing error cannot be received for a long time, resulting in loop unlocking. This technology is not applicable when the phased-array agility period is long; the square timing technology can solve the in-hop timing recovery problem, but due to accurately synchronizing the satellite-ground with errors, it will cause an excessive deviation in the satellite-ground frequency-hopping moment, resulting in inconsistent satellite-ground frequencies, and thus the terminal cannot complete the de-hopping process. Summary of the Invention

[0003] The purpose of the present invention is to solve the timing synchronization problem of frequency-hopping signals under phased-array beam agility mentioned in the background art. By capturing the synchronization sequence at the start of each frame to obtain the satellite-ground time error, and then synchronizing the satellite-ground clocks through the clock synchronization unit. After synchronization, the data is subjected to a matched filtering process for each hop. Then, the timing synchronization unit caches multiple-hop data and calculates the timing error. Finally, the data is interpolated according to the timing error and the timed data is output.

[0004] The technical solution adopted by the present invention is as follows:

[0005] A timing synchronization device for frequency-hopping signals in the phased-array beam agility mode, comprising a clock synchronization unit 1, a digital resampling unit 2, a capture unit 3, a matched filtering unit 4, a hop pulse generation unit 5, and a timing synchronization unit 6;

[0006] The clock synchronization unit 1 is used to generate a clock with a frequency 4 times that of the symbol clock according to the input reference clock and the hop pulse error input by the capture unit 3, and output the clock to the digital resampling unit 2;

[0007] The digital resampling unit 2 is used to resample the input signal into a signal with a frequency 4 times that of the symbol clock, and output the resampled signal to the capture unit 3 and the matched filtering unit 4;

[0008] The capture unit 3 is used to capture the synchronization sequence of each frame in the signal, compare the error between the position of the synchronization sequence and the hop pulse input by the hop pulse generation unit 5, and output the hop pulse error to the clock synchronization unit 1 and the hop pulse generation unit 5;

[0009] The matched filtering unit 4 is used to perform matched filtering on the signal input by the digital resampling unit 2 in units of hops according to the hop pulse input by the hop pulse generation unit 5, and output the matched filtered signal to the timing synchronization unit 6;

[0010] The hop pulse generation unit 5 is used to generate a hop pulse, adjust the position of the hop pulse according to the hop pulse error input by the capture unit 3, and then output the adjusted hop pulse to the matched filtering unit 4 and the timing synchronization unit 6;

[0011] The timing synchronization unit 6 is used to determine the starting position of each hop signal according to the hop pulse position, perform timing synchronization processing on the matched filtered signal, and output the timed data.

[0012] Further, the clock synchronization unit 1 includes a clock error calculation module 7, a frequency control word calculation module 8, and a digital frequency synthesis module 9;

[0013] The clock error calculation module 7 is used to perform multiple accumulations according to the hop pulse error input by the capture unit 3, calculate the clock error, and output the clock error to the frequency control word calculation module 8;

[0014] The frequency control word calculation module 8 is used to calculate the frequency control word in real time according to the input clock error, and output the frequency control word to the digital frequency synthesis module 9;

[0015] The digital frequency synthesis module 9 is used to generate a clock with a frequency four times that of the symbol clock according to the input frequency control word and the reference clock, and output it to the digital resampling unit 2.

[0016] Further, the timing synchronization unit 6 includes a data cache module 10, a control module 11, a timing error calculation module 12, and a digital interpolation module 13;

[0017] The data cache module 10 is used to cache the matched filtered signal in units of hops, read the data in the memory in units of hops according to the control signal output by the control module 11, and output the read data to the timing error calculation module 12 and the digital interpolation module 13;

[0018] The control module 11 is used to determine the starting position of each hop signal according to the input hop pulse, generate a control signal, and output the control signal to the data cache module 10;

[0019] The timing error calculation module 12 is used to calculate the data timing error by using the square timing method according to the input data, and output the data timing error to the digital interpolation module 13;

[0020] The digital interpolation module 13 is used to perform interpolation processing on the input data according to the data timing error, and output the timed data.

[0021] The present invention has the following advantages compared with the background art:

[0022] 1. The present invention completes frequency hopping synchronization and signal timing recovery under the condition of a relatively long phased array agile period, and can improve the time synchronization accuracy.

[0023] 2. The present invention adopts multi-hop joint timing recovery, which can reduce the timing recovery working threshold. Description of the Drawings

[0024] Figure 1 is the principle block diagram of the present invention.

[0025] Figure 2 is the principle block diagram of the clock synchronization unit 1 of the present invention.

[0026] Figure 3 is the principle block diagram of the timing synchronization unit 6 of the present invention. Detailed Embodiments

[0027] The following further describes the present invention in detail with reference to the drawings and specific embodiments.

[0028] Figure 1 is the principle block diagram of the present invention, including a clock synchronization unit 1, a digital resampling unit 2, a capture unit 3, a matched filtering unit 4, a hop pulse generation unit 5, and a timing synchronization unit 6.

[0029] The clock synchronization unit 1 is used to generate a clock with a frequency four times that of the symbol clock based on the input reference clock and the skip pulse error input by the capture unit 3, and output this clock to the digital resampling unit 2; the digital resampling unit 2 is used to resample the input signal into a signal with a frequency four times that of the symbol clock, and output the resampled signal to the capture unit 3 and the matched filtering unit 4; the capture unit 3 is used to capture the synchronization sequence in each frame of the signal, compare the error between the position of the synchronization sequence and the skip pulse input by the skip pulse generation unit 5, and output the skip pulse error to the clock synchronization unit 1 and the skip pulse generation unit 5; the matched filtering unit 4 is used to perform matched filtering on the signal input by the digital resampling unit 2 in units of skips according to the skip pulse input by the skip pulse generation unit 5, and output the matched filtered signal to the timing synchronization unit 6; the skip pulse generation unit 5 is used to generate skip pulses, adjust the position of the skip pulses according to the skip pulse error input by the capture unit 3, and then output the adjusted skip pulses to the matched filtering unit 4 and the timing synchronization unit 6; the timing synchronization unit 6 is used to determine the starting position of each skip signal according to the position of the skip pulses, perform timing synchronization processing on the matched filtered signal, and output the timed data.

[0030] Figure 2 It is the principle block diagram of the clock synchronization unit 1 of the present invention. Among them, the clock synchronization unit 1 includes a clock error calculation module 7, a frequency control word calculation module 8, and a digital frequency synthesis module 9.

[0031] The clock error calculation module 7 is used to perform multiple accumulations based on the skip pulse error input by the capture unit 3, calculate the clock error, and output the clock error to the frequency control word calculation module 8; the frequency control word calculation module 8 is used to calculate the frequency control word in real time according to the input clock error, and output the frequency control word to the digital frequency synthesis module 9; the digital frequency synthesis module 9 is used to generate a clock with a frequency four times that of the symbol clock according to the input frequency control word and the reference clock, and output it to the digital resampling unit 2.

[0032] Figure 3 It is the principle block diagram of the timing synchronization unit 6 of the present invention. Among them, the timing synchronization unit 6 includes a data buffer module 10, a control module 11, a timing error calculation module 12, and a digital interpolation module 13.

[0033] The data cache module 10 is used to cache the signals after matched filtering in units of hops, read the data in the memory in units of hops according to the control signals output by the control module 11, and output the read data to the timing error calculation module 12 and the digital interpolation module 13; the control module 11 is used to determine the starting position of each-hop signal according to the input hop pulses, generate control signals, and output the control signals to the data cache module 10; the timing error calculation module 12 is used to calculate the data timing error by using the square timing method according to the input data, and output the data timing error to the digital interpolation module 13; the digital interpolation module 13 is used to perform interpolation processing on the input data according to the data timing error, and output the timed data.

Claims

1. A frequency hopping signal timing synchronization device in a phased beam agile mode, characterized in that: It comprises a clock synchronization unit (1), a digital resampling unit (2), a capture unit (3), a matched filter unit (4), a pulse skipping generation unit (5) and a timing synchronization unit (6); The clock synchronization unit (1) is used to generate a clock with a frequency four times that of the symbol clock according to the input reference clock and the pulse skipping error input by the capture unit (3), and output the clock to the digital resampling unit (2); The digital resampling unit (2) is used to resample the input signal into a signal with a frequency four times that of the symbol clock, and output the resampled signal to the capture unit (3) and the matched filter unit (4); The capture unit (3) is used to capture the synchronization sequence of each frame in the signal, compare the error between the synchronization sequence position and the skip pulse input by the skip pulse generation unit (5), and output the skip pulse error to the clock synchronization unit (1) and the skip pulse generation unit (5); The matched filtering unit (4) is used to perform matched filtering on the signal input from the digital resampling unit (2) in units of jumps according to the jump pulses input from the jump pulse generating unit (5), and output the matched filtered signal to the timing synchronization unit (6); The pulse skipping generation unit (5) is used to generate a pulse skipping, and adjust the pulse skipping position according to the pulse skipping error input by the capture unit (3), and then output the adjusted pulse skipping to the matching filter unit (4) and the timing synchronization unit (6); The timing synchronization unit (6) is used to determine the starting position of each jump signal according to the jump pulse position, perform timing synchronization processing on the signal after matching filtering, and output the timed data.

2. The frequency hopping signal timing synchronization device in phased beam agile mode according to claim 1, characterized in that: The clock synchronization unit (1) comprises a clock error calculation module (7), a frequency control word calculation module (8) and a digital frequency synthesis module (9); The clock error calculation module (7) is used to perform multiple accumulation according to the pulse skipping error input by the capture unit (3), calculate the clock error, and output the clock error to the frequency control word calculation module (8); The frequency control word calculation module (8) is used to calculate the frequency control word in real time according to the input clock error, and output the frequency control word to the digital frequency synthesis module (9); The digital frequency synthesis module (9) is used to generate a clock with a frequency four times that of the symbol clock according to the input frequency control word and the reference clock, and output it to the digital resampling unit (2).

3. The frequency hopping signal timing synchronization device in phased beam agile mode according to claim 1, characterized in that: The timing synchronization unit (6) comprises a data buffer module (10), a control module (11), a timing error calculation module (12) and a digital interpolation module (13); The data buffer module (10) is used to buffer the matched filtered signal in units of hops, read the data in the memory in units of hops according to the control signal output by the control module (11), and output the read data to the timing error calculation module (12) and the digital interpolation module (13); The control module (11) is used to determine the starting position of each jump signal according to the input jump pulse, generate a control signal, and output the control signal to the data cache module (10); The timing error calculation module (12) is used to calculate the data timing error using a square timing method according to the input data, and output the data timing error to the digital interpolation module (13); The digital interpolation module (13) is used to perform interpolation processing on input data according to the data timing error and output the timed data.

Images