Cache-free optical fiber video unvarnished transmission method, system and equipment based on FPGA (Field Programmable Gate Array) and medium

Abstract

The invention is suitable for the technical field of video transmission, and provides a cache-free optical fiber video transparent transmission method based on an FPGA, and the method comprises the steps: building a video optical fiber link on an optical fiber network, and enabling the video optical fiber link to be used for transmitting a video stream from a collection end to a receiving end; a high-precision scheduler is integrated, so that a plurality of video streams are subjected to multi-channel parallel processing on the video optical fiber link; generating a video tag for each video frame of the video stream, and embedding the video tag into the corresponding video frame; and based on a security module of the FPGA chip, generating an equipment feature code, and binding the video optical fiber link with the FPGA chip through the equipment feature code. According to the invention, the real-time performance, the bandwidth utilization rate and the security of video transmission can be improved, and more powerful support is provided for various video applications.

Description

Technical Field

[0001] This application belongs to the technical field of video transmission, and particularly relates to a bufferless fiber-optic video transparent transmission method, system, device, and medium based on FPGA. Background Art

[0002] With the rapid development of information technology, video transmission is increasingly widely used in various fields, such as video conferencing, remote monitoring, high-definition video transmission, etc. However, traditional video transmission systems often have problems such as large transmission delays, low bandwidth utilization, and insufficient security, which severely limit the application scope and performance of video transmission systems.

[0003] To solve these problems, in the prior art, video transmission technologies based on FPGA have been proposed. Specifically, the inside of an FPGA contains a large number of logic blocks and programmable interconnects, which can support high-speed parallel data processing. In addition, an FPGA has powerful digital signal processing capabilities and can implement efficient encoding, decoding, modulation, demodulation, and other operations to improve the reliability and speed of data transmission. However, existing FPGA-based video transmission technologies still have some deficiencies, such as a lack of an efficient multi-video source management mechanism, imperfect security protection measures, and limited metadata management capabilities. Summary of the Invention

[0004] Embodiments of this application provide a bufferless fiber-optic video transparent transmission method, system, device, and medium based on FPGA, which can solve one of the above-mentioned prior art problems.

[0005] In a first aspect, embodiments of this application provide a bufferless fiber-optic video transparent transmission method based on FPGA, including:

[0006] Establish a video fiber-optic link on the fiber-optic network, where the video fiber-optic link is used to transmit a video stream from a collection end to a receiving end;

[0007] Integrate a high-precision scheduler to enable multiple video streams to perform multi-channel parallel processing on the video fiber-optic link;

[0008] Generate a video tag for each video frame of the video stream and embed the video tag into the corresponding video frame;

[0009] Based on the security module of the FPGA chip, generate a device feature code, and bind the video fiber-optic link to the FPGA chip through the device feature code.

[0010] Further, the step of establishing a video fiber-optic link on the fiber-optic network, where the video fiber-optic link is used to transmit a video stream from a collection end to a receiving end, includes:

[0011] Configure a video stream data processing module on the FPGA chip at the acquisition end. The video stream data processing module is used to obtain a video stream, perform clock synchronization and frame alignment processing on the video stream, and generate video stream data;

[0012] Establish a video optical fiber link on the optical fiber network to transmit the video stream data to the receiving end;

[0013] Configure a video stream data parsing module and a real-time processing module on the FPGA chip at the receiving end. The video stream data parsing module is used to parse the video stream data, and the real-time processing module is used to monitor the integrity problem during the data transmission process. If an integrity anomaly is detected, a correction mechanism is started.

[0014] Further, the integrated high-precision scheduler includes:

[0015] Calculate the transmission priority of each video stream according to the complexity characteristics and real-time bandwidth requirements of the video stream;

[0016] Based on the transmission priority, use the weighted fair queueing algorithm to allocate transmission time slots for each video stream and generate a time slot allocation table;

[0017] Obtain the network state change trend and dynamically adjust the time slot allocation strategy of the time slot allocation table.

[0018] Further, the calculating the transmission priority of each video stream according to the complexity characteristics and real-time bandwidth requirements of the video stream includes:

[0019] Obtain the texture information and motion intensity of each video frame in the video stream, and generate a complexity score for each video frame;

[0020] Generate the complexity characteristics of the video stream based on the complexity score;

[0021] Based on the complexity characteristics, combined with a preset coding parameter mapping table, determine the coding parameter combination of the video stream, and dynamically adjust the real-time bandwidth requirements of the video stream. The coding parameter combination includes quantization step size and frame rate;

[0022] Based on the complexity characteristics and the real-time bandwidth requirements, use a weighted algorithm to calculate the transmission priority of the video stream.

[0023] Further, generating a video label for each video frame of the video stream and embedding the video label into the corresponding video frame includes:

[0024] Generate a source information label based on the source information of the video stream. The source information label includes a source address and a device number;

[0025] Extract the timestamps of the corresponding video frames according to the time attributes of the video frames;

[0026] Generate priority labels based on the timestamps and complexity scores of each video frame;

[0027] Compress the source information labels, timestamps, and priority labels using a compression encoding algorithm to generate video labels;

[0028] Embed the video labels into the invisible regions of each video frame and encapsulate the video frames into data packets;

[0029] Arrange the frames according to the timestamps in the data packets and determine the processing order of each video frame in the unified video stream through the priority labels.

[0030] Further, the security module based on the FPGA chip generates a device feature code and binds the video optical fiber link to the FPGA chip through the device feature code, including:

[0031] Obtain a preset set of configuration parameters from the FPGA chip, and extract the hardware identification information and link configuration parameters from the set of configuration parameters;

[0032] Use a feature extraction algorithm to encrypt the hardware identification information and the link configuration parameters respectively to generate a device feature code, and the device feature code includes a hardware feature value and a random sequence;

[0033] Generate link parameters according to the authorized device information and transmission characteristics of the video optical fiber link, and the link parameters include an authorized feature value and a transmission feature value;

[0034] Use a dynamic binding algorithm to calculate the correlation degree between the device feature code and the link parameters;

[0035] For the correlation degree exceeding a preset correlation degree threshold, perform a binding operation, and the binding operation includes encrypting the device feature code and updating the link parameters.

[0036] Further, the use of the dynamic binding algorithm to calculate the correlation degree between the device feature code and the link parameters includes:

[0037] Compare the hardware feature value with the authorized feature value to generate a first correlation value;

[0038] Input the random sequence into a preset machine learning model, and generate a second correlation value through the machine learning model;

[0039] Calculate a comprehensive correlation value based on the first correlation value and the second correlation value.

[0040] Second aspect, an embodiment of the present application provides a bufferless fiber optic video transparent transmission system based on FPGA, including:

[0041] A first processing unit, configured to establish a video fiber optic link on the fiber optic network, where the video fiber optic link is used to transmit a video stream from a collection end to a receiving end;

[0042] A second processing unit, configured to integrate a high-precision scheduler to enable multiple video streams to perform multi-channel parallel processing on the video fiber optic link;

[0043] A third processing unit, configured to generate a video label for each video frame of the video stream and embed the video label into the corresponding video frame;

[0044] A fourth processing unit, configured to generate a device feature code based on a security module of the FPGA chip, and bind the video fiber optic link to the FPGA chip through the device feature code.

[0045] Third aspect, an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the above-mentioned bufferless fiber optic video transparent transmission method based on FPGA is implemented.

[0046] Fourth aspect, an embodiment of the present application provides a computer-readable storage medium, including that the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned bufferless fiber optic video transparent transmission method based on FPGA is implemented.

[0047] The beneficial effects of the embodiments of the present application compared with the prior art are:

[0048] The present application discloses a bufferless fiber-optic video transparent transmission method based on FPGA. By establishing a video fiber-optic link on the fiber-optic network, the transmission speed and stability of the video stream can be greatly improved, ensuring real-time and lossless transmission of the video stream. The integrated high-precision scheduler enables multiple video streams to be processed in parallel on the same video fiber-optic link without laying a separate fiber-optic link for each video stream, which not only improves the transmission efficiency but also reduces the system cost. At the same time, the high-precision scheduler can ensure the synchronization and coordination of each video stream, avoiding data conflicts and losses, and thus realizing the management of multiple video sources. In addition, video tags are generated for each video frame and embedded into the corresponding video frame, enhancing the manageability and traceability of video data. Tagging also helps to improve the security and privacy protection level of video data. Additionally, a security module based on the FPGA chip generates a device feature code, and binds the video fiber-optic link to the FPGA chip through this device feature code, significantly enhancing the security of video transmission and effectively preventing illegal access and data leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0050] Figure 1 is a schematic flowchart of a bufferless fiber-optic video transparent transmission method based on FPGA provided by an embodiment of the present invention;

[0051] Figure 2 is a schematic structural diagram of a bufferless fiber-optic video transparent transmission system provided by an embodiment of the present invention;

[0052] Figure 3 is a schematic structural diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, the detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0054] It should be understood that, as used in the specification of this application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0055] It should also be understood that the term "and / or" as used in the specification of this application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0056] As used in the specification of this application and the appended claims, the term "if" may be interpreted, depending on the context, as "when", "once", "in response to determining", or "in response to detecting". Similarly, the phrases "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".

[0057] In addition, in the description of the specification of this application and the appended claims, the terms "first", "second", "third", etc. are only used for differentiating descriptions and should not be construed as indicating or implying relative importance.

[0058] The reference to "one embodiment" or "some embodiments" etc. described in the specification of this application means that a specific feature, structure or characteristic described in connection with that embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in some other embodiments", "in still other embodiments" etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0059] Please refer to Figure 1 As shown, the present invention is a method for cache - less optical - fiber video transparent transmission based on FPGA, comprising the following steps:

[0060] S100. Establish a video optical - fiber link on the optical - fiber network, and the video optical - fiber link is used to transmit a video stream from a collection end to a receiving end;

[0061] In this embodiment, by establishing a video optical - fiber link on the optical - fiber network, the transmission speed and stability of the video stream can be greatly improved, and real - time and lossless transmission of the video stream can be ensured.

[0062] In some of these embodiments, the above step S100 includes:

[0063] Configure a video stream data processing module on the FPGA chip at the acquisition end. The video stream data processing module is used to acquire a video stream, perform clock synchronization and frame alignment processing on the video stream, and generate video stream data.

[0064] Establish a video optical fiber link on the optical fiber network and transmit the video stream data to the receiving end.

[0065] Configure a video stream data parsing module and a real-time processing module on the FPGA chip at the receiving end. The video stream data parsing module is used to parse the video stream data, and the real-time processing module is used to monitor the integrity problem during the data transmission process. If an integrity anomaly is detected, a correction mechanism is started.

[0066] In this embodiment, a video stream data processing module is configured on the FPGA chip at the acquisition end using a hardware description language to obtain the original video stream data. It can be understood that the video stream data processing module can perform clock synchronization processing and frame alignment processing on the video stream. Specifically, a clock synchronization circuit is designed in the FPGA to generate a synchronous clock pulse according to the clock signal at the acquisition end to ensure the time consistency of the video stream data. Then, a frame alignment mechanism is used to perform frame boundary detection on the video stream data. If a frame start flag is detected, frame alignment processing is started to generate frame-aligned video stream data.

[0067] In this embodiment, a dedicated video optical fiber link is established on the optical fiber network to directly transmit the frame-aligned video stream data to the receiving end, avoiding the introduction of data caching. In addition, a bandwidth management module is also provided on the optical fiber network to dynamically adjust the transmission rate of the video stream data to ensure that the video coherence is not affected by network fluctuations.

[0068] In this embodiment, a video stream data parsing module is correspondingly configured in the FPGA at the receiving end to parse the received video stream data according to the clock synchronization signal and frame alignment information. At the same time, a display signal generation logic is implemented using a hardware description language to convert the parsed video stream data into a signal format recognizable by the display device. In addition, a real-time processing module is also configured in the FPGA at the receiving end to monitor frame loss or duplication problems during the data transmission process. If an anomaly is detected, a frame correction mechanism is started to regenerate the correct video stream data. Specifically, the integrity detection result of the video frame is obtained from the receiving end, and an error correction algorithm is used to judge the frame loss or damage situation, generate a retransmission request, and send it to the acquisition end.

[0069] In some embodiments, the receiving - end FPGA is connected to the optical - fiber interface through a high - speed serial interface, acquires video - stream data, and then performs decoding and de - encapsulation processing to restore the original image data. The FPGA utilizes its high - speed parallel processing ability to achieve real - time multiplexing, encoding, and decoding of video signals, and further realizes buffer - less transparent transmission of video signals, thereby reducing transmission latency and improving real - time performance. At the same time, the receiving end adopts the CDR technology. Specifically, the CDR technology is a technology used to recover the clock signal from the received data in high - speed serial communication. It can correctly extract the pixel - point clock and image data even in the case of signal jitter. That is, according to the received synchronous timing information, the CDR technology is used to extract the pixel - point clock and restore the image synchronization signal, so that the receiving end can correctly decode and display the image according to the timing requirements of the sending end.

[0070] S200. Integrate a high - precision scheduler to enable multi - channel parallel processing of multiple video streams on the video optical - fiber link;

[0071] In this embodiment, by integrating a high - precision scheduler, multiple video streams can perform multi - channel parallel processing on the same video optical - fiber link without laying a separate optical - fiber link for each video stream. This not only improves the transmission efficiency but also reduces the system cost. At the same time, the high - precision scheduler can ensure the synchronization and coordination of each video stream, avoid data conflicts and losses, and further realize the management of multiple video sources.

[0072] In this embodiment, the FPGA obtains the transmission requests of multiple video sources, extracts the priority information and bandwidth requirements of each video source, and according to the preset priority rules and bandwidth requirements, uses a high - precision scheduler to calculate the time - slot allocation scheme for each video source. For critical video streams, continuous time slots are preferentially allocated to ensure the transmission quality and real - time performance of critical video streams. For non - critical video streams, a dynamic adjustment strategy is adopted to optimize the time - slot allocation in real time according to changes in the network conditions.

[0073] In this embodiment, the time - slot allocation scheme is transmitted through the optical - fiber link, and the data of multiple video sources are multiplexed in time according to the time - slot allocation scheme and multi - channel parallel processing is implemented inside the FPGA to simultaneously process the transmission tasks of multiple video sources, improving the system sharing efficiency. Specifically, when multiple video sources need to transmit data simultaneously, the high - precision scheduler dynamically allocates time slots according to the transmission priority. At this time, a time slot is simultaneously occupied by multiple video - transmission channels, thus realizing multi - channel parallel transmission. At the same time, there are multiple parallel processing units inside the FPGA, which are used to process the data of multiple video - transmission channels simultaneously, further improving the processing ability and efficiency of the system.

[0074] In some embodiments, the utilization rate of the optical fiber link is monitored in real time. If the detected utilization rate is lower than the preset threshold, the time slot allocation scheme is recalculated, and at the same time, the time slot allocation scheme is periodically updated through the scheduler to ensure the maximum utilization of the optical fiber link and the priority transmission of critical video streams.

[0075] For critical video streams, according to the complexity characteristics and real-time bandwidth requirements of the video streams, the transmission priorities of each video stream are calculated, and the critical video streams are determined based on the transmission priorities.

[0076] In some of these embodiments, the integrated high-precision scheduler includes:

[0077] According to the complexity characteristics and real-time bandwidth requirements of the video streams, calculate the transmission priorities of each video stream;

[0078] Based on the transmission priorities, use the weighted fair queue algorithm to allocate transmission time slots for each video stream and generate a time slot allocation table;

[0079] Obtain the changing trend of the network state and dynamically adjust the time slot allocation strategy of the time slot allocation table.

[0080] In this embodiment, the integrated high-precision scheduler includes a priority management module, a bandwidth allocation module, a network state monitoring module, a time slot allocation module, and a feedback adjustment module. Specifically, the priority management module implements the priority calculation logic through a hardware description language. Among them, the transmission priorities of each video stream are calculated based on the complexity characteristics and real-time bandwidth requirements of the video streams, and finally the priorities of each video stream are output. For the bandwidth allocation module, the weighted fair queue algorithm is used to dynamically allocate bandwidth for each video stream and output the bandwidth allocation results of each video stream. The time slot allocation module generates a time slot allocation table according to the bandwidth allocation results. For the network state monitoring module, it can collect and analyze network state data and generate a network state score. Among them, the network state data includes network bandwidth, delay, and packet loss rate. The feedback control module is used to implement the dynamic adjustment logic, update the time slot allocation table according to the network state score, and then dynamically adjust the time slot allocation strategy.

[0081] In this embodiment, the weighted fair queueing algorithm is adopted to dynamically allocate bandwidth according to the transmission priority of video streams. The weighted fair queueing algorithm ensures that video streams with high transmission priority obtain more bandwidth, thus meeting their higher transmission requirements. According to the calculation results of the weighted fair queueing algorithm, the bandwidth allocation results of each video stream are output, specifically including key information such as the bandwidth size occupied by each video stream and the allocation time. At this time, the time slot allocation module receives the bandwidth allocation results from the bandwidth allocation module, and based on the bandwidth allocation results, conducts time slot planning to generate a time slot allocation strategy, specifically including determining the number of time slots required for each video stream, the start time and end time of the time slots. It can be understood that the time slot planning needs to ensure that there are no conflicts among various video streams during the transmission process and can make full use of network resources. Finally, based on the results of the time slot planning, a time slot allocation table is generated. The above time slot allocation table records the time slot information occupied by each video stream, including time slot number, start time, end time, occupied bandwidth, etc. Each video stream is transmitted on the video optical fiber link based on the time slot allocation table, thereby ensuring the efficient transmission of video streams in the network.

[0082] In this embodiment, data acquisition technology is adopted to obtain network bandwidth, latency, and packet loss rate data. According to preset scoring rules and weights, the above-collected network status data are scored, and a network status score is comprehensively generated. The scoring rules can be flexibly adjusted according to actual needs. In a possible embodiment, the preset scoring criteria are as follows: The bandwidth utilization rate is scored according to the ratio of the actual usage of bandwidth to the total bandwidth. The higher the utilization rate, the higher the score. The latency time is scored according to the length of the network latency. The shorter the latency, the higher the score. Different latency thresholds can be set, corresponding to different scoring intervals. The packet loss rate is scored according to the level of the network packet loss rate. The lower the packet loss rate, the higher the score. Similarly, different packet loss rate thresholds can be set, corresponding to different scoring intervals.

[0083] In this embodiment, different scoring network status score intervals and corresponding time slot allocation strategies are preset in the feedback adjustment module. When the network status score changes, according to the interval where the current score is located, the corresponding time slot allocation strategy is selected for adjustment, and then the time slot allocation table is updated, specifically including adjusting the size, quantity of time slots, and the time slot ratio allocated to different video streams, etc.

[0084] In some of these embodiments, calculating the transmission priority of each video stream according to the complexity characteristics and real-time bandwidth requirements of the video stream includes:

[0085] Obtaining the texture information and motion intensity of each video frame in the video stream, and generating a complexity score for each video frame;

[0086] Based on the complexity score, generating the complexity characteristics of the video stream;

[0087] Based on the complexity feature, in combination with a preset coding parameter mapping table, determine the coding parameter combination of the video stream, and dynamically adjust the real-time bandwidth requirement of the video stream. The coding parameter combination includes quantization step size and frame rate;

[0088] Based on the complexity feature and the real-time bandwidth requirement, use a weighted algorithm to calculate the transmission priority of the video stream.

[0089] In this embodiment, image processing algorithms such as edge detection and gray-level co-occurrence matrix are used to extract the texture information of each frame in the video stream, and then the motion intensity of the video frame is calculated. Combining the texture information and the motion intensity, a complexity score for each frame is generated, and then the complexity scores of all video frames in the video stream are statistically analyzed to obtain the average complexity score of the video stream, which is the complexity feature.

[0090] Specifically, the edge detection method is used to calculate the vertical edge intensity of each video frame. The specific formula is as follows:

[0091]

[0092] where E represents the vertical edge intensity, n represents the size of the image, and I(i, j) represents the gray value of the image at the coordinate (i, j).

[0093] Based on the gray-level co-occurrence matrix, calculate the texture feature of each video frame. The specific formula is as follows:

[0094]

[0095] where C represents the contrast feature of the gray-level co-occurrence matrix, L represents the number of gray levels, and P(i, j) represents the probability value at the position (i, j) in the gray-level co-occurrence matrix.

[0096] In this embodiment, the calculation formula for the motion intensity of each video frame is as follows:

[0097]

[0098] where M represents the motion intensity, W and H respectively represent the width and height of the image, u t and v t represent the horizontal and vertical motion vectors at the position (x, y).

[0099] For each video frame, the calculation formula for the complexity score is as follows:

[0100] S = αE + βC + γM

[0101] Among them, S represents the complexity score, and α, β, and γ respectively represent the weight coefficients of the vertical edge strength, texture feature, and motion intensity.

[0102] In this embodiment, a coding parameter mapping table is established in advance, which maps the complexity features to the coding parameter combinations. The selection of the coding parameters should consider the balance among video quality, coding efficiency, and bandwidth requirements. Specifically, according to the complexity features of the video stream, the corresponding coding parameter combination is searched in the coding parameter mapping table, and based on the found coding parameter combination, the real-time bandwidth requirement of the video stream is dynamically adjusted. For example, for a video stream with higher complexity, a larger quantization step size and a lower frame rate are corresponding, so as to reduce the bandwidth requirement; for a video stream with lower complexity, a smaller quantization step size and a higher frame rate are corresponding, so as to maintain the video quality and ensure that the key video stream can obtain more bandwidth resources.

[0103] In this embodiment, for the real-time bandwidth requirement, it is calculated based on the coding parameter combination of the video stream, and the specific calculation formula is as follows:

[0104]

[0105] Among them, B represents the real-time bandwidth requirement of the video stream, W represents the width of the video frame, H represents the height of the video frame, F represents the frame rate, α represents the compression ratio, Q represents the quantization step size, and C represents the base bitrate constant.

[0106] In this embodiment, according to the weighted algorithm, based on the complexity features and the real-time bandwidth requirement, the transmission priority of the video stream is calculated. The higher the transmission priority, the higher the priority that the video stream should enjoy in network transmission; on the contrary, the lower the transmission priority, the lower the priority of the video stream in network transmission should be correspondingly reduced.

[0107] S300. Generate a video label for each video frame of the video stream, and embed the video label into the corresponding video frame;

[0108] In this embodiment, generating a video label for each video frame and embedding it into the corresponding video frame enhances the manageability and traceability of the video data, and the labeling also helps to improve the security and privacy protection level of the video data.

[0109] In some of the embodiments, the above step S300 includes:

[0110] Generate a source information label based on the source information of the video stream, and the source information label includes the source address and the device number;

[0111] Extract the timestamp of the corresponding video frame according to the time attribute of the video frame;

[0112] Generate a priority label based on the timestamp and complexity score of each video frame;

[0113] Use a compression coding algorithm to compress the source information label, timestamp, and priority label to generate a video label;

[0114] Embed the video label into the invisible area of each video frame and encapsulate the video frame into a data packet;

[0115] Arrange the frames in sequence according to the timestamp in the data packet, and determine the processing order of each video frame in the video stream uniformly through the priority label.

[0116] Specifically, the source information in the video stream usually contains the specific identification of the transmission source device, such as the IP coordinates of the camera and the corresponding device number. Encapsulating it into a source information label helps to quickly locate the video source and facilitates subsequent management and processing. The extraction of the video frame timestamp can be based on the system time at the time of encoding, and the recording form is "year-month-day hour:minute:second millisecond". For example, the timestamp of a certain video frame can be recorded as "20240622103025123", accurate to the millisecond level, ensuring the timing accuracy of the video frame. The generation of the priority label needs to comprehensively consider the time attribute and complexity score of each video frame, and thus weighted summation is used to calculate the priority to generate the priority label.

[0117] In this embodiment, the compression coding of the video label uses algorithms such as Huffman coding, Lempel-Ziv-Welch algorithm or more advanced compression algorithms to compress the source information label, timestamp, and priority label. The compressed data is encapsulated into a compact video label format, such as a binary format, for quick parsing and embedding. Taking Huffman coding compression as an example, an optimal prefix code is constructed based on the frequency of character occurrences. The specific process is as follows: count the frequency of each character or character combination in the source information label, timestamp, and priority label, take each character and its frequency as a node, and construct a priority queue (the node with the lowest frequency is at the front of the queue). Take out the two nodes with the lowest frequencies from the priority queue, merge them and generate a new parent node, whose frequency is the sum of the frequencies of the two child nodes. Reinsert the new parent node into the priority queue, and repeat this process until there is only one node left in the queue, which is the root node of the Huffman tree. Starting from the root node of the Huffman tree, traverse the left subtree and assign "0", traverse the right subtree and assign "1". Each leaf node is the original character, and the path from the root to this node is its Huffman coding. Use the generated coding table to replace each character in the source information label, timestamp, and priority label with its corresponding Huffman coding, and output the encoded data in binary format, which is the compressed video label.

[0118] In this embodiment, the video tag is embedded in the non-visible area of the video frame. It is possible to choose to reserve space at the head of the video frame for embedding. For example, 32 bytes of space are reserved at the head of the frame, and the compressed tag information is written in to ensure that the display quality of the video picture is not affected. At the same time, the video tag is encapsulated into a data packet together with the video frame for convenient network transmission.

[0119] In this embodiment, the timestamps in the data packets are used to sort all the received video frames to ensure that they are processed in the original capture order. Then, the priority tags are used to determine which video frames should be processed first when resources are limited. For example, in real-time video analysis, the video frames with high priority can be processed first to ensure that key events are processed in a timely manner.

[0120] In this embodiment, from the source information to the time attribute, then to the priority assessment, and finally to the tag compression and embedding, the precise management and efficient processing of the video frames are realized. Through the tag-based management, the precise positioning and flexible scheduling of the video frames are realized, meeting the differentiated requirements of different application scenarios for video transmission. Especially in the case of limited network bandwidth, the priority mechanism can ensure the timely transmission of important video frames and improve the user experience.

[0121] S400. A security module based on an FPGA chip generates a device feature code, and binds the video optical fiber link to the FPGA chip through the device feature code.

[0122] In this embodiment, the security module based on the FPGA chip generates a device feature code, and binds the video optical fiber link to the FPGA chip through this device feature code, significantly enhancing the security of video transmission and effectively preventing illegal access and data leakage.

[0123] In some of these embodiments, the above step S400 includes:

[0124] Obtain a preset set of configuration parameters from the FPGA chip, and extract the hardware identification information and link configuration parameters from the set of configuration parameters;

[0125] Use a feature extraction algorithm to encrypt the hardware identification information and the link configuration parameters respectively to generate a device feature code, and the device feature code includes a hardware feature value and a random sequence;

[0126] Generate link parameters according to the authorized device information and transmission characteristics of the video optical fiber link, and the link parameters include an authorized feature value and a transmission feature value;

[0127] Use a dynamic binding algorithm to calculate the correlation degree between the device feature code and the link parameters;

[0128] For the correlation degree exceeding the preset correlation degree threshold, a binding operation is performed, and the binding operation includes encrypting the device feature code and updating the link parameters.

[0129] In this embodiment, a configuration parameter set is configured in the security module of the FPGA chip. The configuration parameter set includes a basic identification parameter and a link configuration parameter. The basic identification parameter is a basic parameter such as hardware identification information, chip serial number, and clock frequency. The link configuration parameter is a preset link parameter of an accessible video optical fiber link, usually including configuration parameters related to the transmission characteristics of the video optical fiber link such as bandwidth, delay, and bit error rate. When binding the video optical fiber link and the FPGA chip, while ensuring that the relevant FPGA chip is an authorized chip of the video optical fiber link, it is also necessary to match the transmission characteristics of the video optical fiber link to ensure the security of the transmission process.

[0130] Specifically, a hardware feature value is generated through the encryption processing of the hardware identification information, and a random sequence is generated through the encryption processing of the link configuration parameters. For the hardware feature value, the AES algorithm is used to encrypt the hardware identification information; for the random sequence, the link configuration parameters are mapped to a random sequence through a hash function. Specifically, each parameter value in the link configuration parameters is converted into a standardized numerical value so that it is between 0 and 1, the standardized numerical value is converted into a string, and these strings are concatenated into a long input string. To maintain the order and distinctiveness of the parameters, a delimiter such as a comma, space, or special character is added between each numerical string, and a suitable hash function is selected to map the above input string to an output string with a fixed length, that is, a random sequence. Specifically, the hash function can be MD5, SHA-1, or SHA-256.

[0131] In this embodiment, a list of all authorized devices in the video optical fiber link is obtained, including the acquisition end, the receiving end, etc., the hardware identification information of the corresponding FPGA chip on the authorized device is obtained, an authorized feature value is generated, and by analyzing the transmission characteristics of the video optical fiber link, feature values such as bandwidth, delay, and bit error rate are extracted to generate a transmission feature value, and then the authorized feature value and the transmission feature value are integrated together to form a complete link parameter.

[0132] In this embodiment, in the dynamic binding operation, if the correlation degree exceeds the preset correlation degree threshold, a binding operation is performed. The binding operation includes two links: device feature code encryption and link parameter update. The device feature code is protected through an encryption algorithm to generate an encrypted feature code, and the encrypted feature code is written into the configuration file of the video optical fiber link. The encrypted feature code is stored in an asymmetric encryption manner, and at the same time, the transmission parameters of the video optical fiber link are updated to the link configuration parameters of the FPGA chip to complete the binding process of the device feature code and the video optical fiber link.

[0133] In some of these embodiments, adopting a dynamic binding algorithm to calculate the correlation degree between the device signature and the link parameters includes:

[0134] Comparing the hardware feature value with the authorized feature value to generate a first correlation value;

[0135] Inputting the random sequence into a preset machine learning model to generate a second correlation value through the machine learning model;

[0136] Calculating a comprehensive correlation value based on the first correlation value and the second correlation value.

[0137] In this embodiment, decrypting the hardware feature value to obtain the hardware identification information of the FPGA chip. It can be understood that among the authorized feature values, there are authorization information such as the hardware identification information, authorization status, and authorization period of the authorized device. Specifically, according to the timestamp at the time of binding, it is judged whether the hardware feature value is within the authorization period. If it is within the valid period, the hardware feature value is compared with the authorized feature value; otherwise, it is determined as an illegal request, and at this time, the first correlation value is assigned 0. When comparing the hardware feature value with the authorized feature value, the decrypted hardware identification information is compared with the pre-stored hardware identification information of the authorized device. If they match, the device is determined to be an authorized device, and at this time, the first correlation value is assigned 1. It can be understood that when the hardware feature value matches the authorized feature value, the first correlation value is assigned 1; if the hardware feature value does not match the authorized feature value or the binding time of the two is not within the authorization time, the first correlation value is assigned 0.

[0138] In this embodiment, the preset machine learning model is used to extract features from the random sequence to obtain the key information in the sequence. The key information extracted is matched with the link parameters to generate and store the second correlation value, and then the weighted summation method is used to calculate the comprehensive correlation value between the first correlation value and the second correlation value.

[0139] Please refer to Figure 2 As shown, the present invention also provides a cacheless fiber optic video transparent transmission system based on FPGA. The system includes:

[0140] A first processing unit 201 for establishing a video fiber optic link on the fiber optic network, where the video fiber optic link is used to transmit the video stream from the acquisition end to the receiving end;

[0141] A second processing unit 202 for integrating a high-precision scheduler to enable multiple video streams to perform multi-channel parallel processing on the video fiber optic link;

[0142] A third processing unit 203 for generating a video label for each video frame of the video stream and embedding the video label into the corresponding video frame;

[0143] The fourth processing unit 204 is configured to generate a device feature code based on the security module of the FPGA chip, and bind the video optical fiber link to the FPGA chip through the device feature code.

[0144] It can be understood that the content in the embodiment of the FPGA-based cacheless fiber optic video transparent transmission method as Figure 1 shown is applicable to the embodiment of the FPGA-based cacheless fiber optic video transparent transmission system. The functions specifically implemented in the embodiment of the FPGA-based cacheless fiber optic video transparent transmission system are the same as those in the embodiment of the FPGA-based cacheless fiber optic video transparent transmission method as Figure 1 shown, and the beneficial effects achieved are also the same as those in the embodiment of the FPGA-based cacheless fiber optic video transparent transmission method as Figure 1 shown.

[0145] It should be noted that for the information interaction, execution process, etc. between the above systems, since they are based on the same concept as the method embodiment of the present invention, for their specific functions and the technical effects brought, please refer to the method embodiment part for details, and will not be elaborated here.

[0146] Those skilled in the art can clearly understand that for the convenience and conciseness of description, only the above-mentioned division of each functional unit and module is used as an example. In practical applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the system is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated here.

[0147] Please refer to Figure 3 shown. The embodiment of the present invention also provides a computer device 3, including: a memory 302, a processor 301, and a computer program 303 stored on the memory 302. When the computer program 303 is executed on the processor 301, it implements the FPGA-based cacheless fiber optic video transparent transmission method described in any one of the above methods.

[0148] The computer device 3 can be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server. The computer device 3 may include, but is not limited to, a processor 301 and a memory 302. Those skilled in the art can understand that Figure 3 The above are only examples of the computer device 3, which do not constitute a limitation on the computer device 3. It may include more or fewer components than those shown in the figure, or combine certain components, or have different components. For example, it may also include input / output devices, network access devices, etc.

[0149] The so-called processor 301 may be a central processing unit (CPU), and the processor 301 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0150] In some embodiments, the memory 302 may be an internal storage unit of the computer device 3, such as the hard disk or memory of the computer device 3. In other embodiments, the memory 302 may also be an external storage device of the computer device 3, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device 3. Further, the memory 302 may also include both the internal storage unit and the external storage device of the computer device 3. The memory 302 is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of the computer program, etc. The memory 302 may also be used to temporarily store data that has been output or will be output.

[0151] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it implements the FPGA-based cacheless fiber video transparent transmission method as described in any one of the above methods.

[0152] In this embodiment, if the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the method of the above embodiment in this application, a computer program can be used to instruct the relevant hardware to complete. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-mentioned method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the photographing device / computer device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk, or an optical disc, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunication signal.

[0153] The above-described embodiments are only used to illustrate the technical solutions of this application, rather than to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for non-buffered optical fiber video transparent transmission based on FPGA, characterized in that: include: Establishing a video optical fiber link on the optical fiber network, wherein the video optical fiber link is used to transmit the video stream from the acquisition end to the receiving end; An integrated high-precision scheduler enables multi-channel parallel processing of multiple video streams on the video optical fiber link; Generating a video tag for each of the video frames of the video stream, and embedding the video tag into the corresponding video frame; The security module based on the FPGA chip generates a device feature code, and the video optical fiber link is bound to the FPGA chip through the device feature code.

2. The method according to claim 1, characterized in that The video optical fiber link is established on the optical fiber network, and the video optical fiber link is used to transmit the video stream from the acquisition end to the receiving end, including: A video stream data processing module is configured on the FPGA chip of the acquisition end, wherein the video stream data processing module is used to obtain the video stream, perform clock synchronization and frame alignment processing on the video stream, and generate video stream data; Establishing a video optical fiber link on the optical fiber network to transmit the video stream data to a receiving end; A video stream data parsing module and a real-time processing module are configured on the FPGA chip at the receiving end. The video stream data parsing module is used to parse the video stream data, and the real-time processing module is used to monitor integrity issues during data transmission. If integrity abnormalities are detected, a correction mechanism is initiated.

3. The method according to claim 1, characterized in that The integrated high-precision scheduler comprises: Calculate the transmission priority of each video stream based on the complexity characteristics of the video stream and the real-time bandwidth requirements; Based on the transmission priority, a weighted fair queue algorithm is used to allocate transmission time slots for each video stream and generate a time slot allocation table; Obtain the network status change trend and dynamically adjust the time slot allocation strategy of the time slot allocation table.

4. The method according to claim 3, characterized in that The step of calculating the transmission priority of each video stream according to the complexity characteristics of the video stream and the real-time bandwidth requirement includes: Acquire texture information and motion intensity of each video frame in the video stream, and generate a complexity score for each video frame; Based on the complexity score, generating a complexity feature of the video stream; Based on the complexity feature and in combination with a preset encoding parameter mapping table, a coding parameter combination of the video stream is determined, and a real-time bandwidth requirement of the video stream is dynamically adjusted, wherein the coding parameter combination includes a quantization step size and a frame rate; Based on the complexity characteristics and the real-time bandwidth requirements, a weighted algorithm is used to calculate the transmission priority of the video stream.

5. The method according to claim 4, characterized in that Generating a video tag for each of the video frames of the video stream and embedding the video tag into the corresponding video frame includes: Based on the source information of the video stream, generating a source information tag, the source information tag including a source address and a device number; Extracting a timestamp of a corresponding video frame according to a time attribute of the video frame; Generate priority labels based on the timestamp and complexity score of each video frame; Using a compression coding algorithm to compress the source information tag, timestamp and priority tag to generate a video tag; Embedding the video tag into a non-visible area of ​​each video frame, and encapsulating the video frame into a data packet; The frames are arranged in sequence according to the timestamp in the data packet, and the processing order of each video frame in the video stream is unified by determining the priority tag.

6. The method according to claim 1, characterized in that The FPGA chip-based security module generates a device feature code, and binds the video optical fiber link to the FPGA chip through the device feature code, including: Obtaining a preset configuration parameter set from the FPGA chip, and extracting hardware identification information and link configuration parameters from the configuration parameter set; Using a feature extraction algorithm to encrypt the hardware identification information and the link configuration parameters respectively to generate a device feature code, wherein the device feature code includes a hardware feature value and a random sequence; Generate link parameters according to the authorized device information and transmission characteristics of the video optical fiber link, wherein the link parameters include an authorization characteristic value and a transmission characteristic value; Using a dynamic binding algorithm, calculating the correlation between the device feature code and the link parameter; If the association degree exceeds a preset association degree threshold, a binding operation is performed, and the binding operation includes encrypting the device feature code and updating link parameters.

7. The method according to claim 6, characterized in that The adopting of a dynamic binding algorithm to calculate the correlation between the device feature code and the link parameter includes: Comparing the hardware characteristic value with the authorization characteristic value to generate a first correlation value; Inputting the random sequence into a preset machine learning model, and generating a second correlation value through the machine learning model; Based on the first correlation value and the second correlation value, a comprehensive correlation value is calculated.

8. An FPGA-based non-buffered optical fiber video transparent transmission system, characterized in that: include: A first processing unit, used to establish a video optical fiber link on the optical fiber network, wherein the video optical fiber link is used to transmit the video stream from the acquisition end to the receiving end; A second processing unit, used to integrate a high-precision scheduler to enable multi-channel parallel processing of multiple video streams on the video optical fiber link; A third processing unit, configured to generate a video tag for each of the video frames of the video stream, and embed the video tag into the corresponding video frame; The fourth processing unit is used to generate a device feature code based on the security module of the FPGA chip, and bind the video optical fiber link to the FPGA chip through the device feature code.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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