A high-gain active pixel circuit and image sensor

Abstract

This application discloses a high-gain active pixel circuit and an image sensor, relating to the field of electronic circuit technology, used to reduce the exposure time required for a pixel circuit to complete the exposure of one frame of an image. The high-gain active pixel circuit includes: a photosensitive circuit, a feedback circuit, and an amplifier circuit; wherein, a first terminal of the photosensitive circuit is coupled to a ground terminal and configured to generate an exposure current based on the intensity of received light; a first terminal of the feedback circuit is coupled to a second terminal of the photosensitive circuit and configured to input the exposure current to clamp the voltage at the second terminal of the photosensitive circuit; the output terminal of the amplifier circuit is coupled to the second terminal of the feedback circuit, and the input terminal of the amplifier circuit is coupled to the second terminal of the photosensitive circuit, configured to clamp the voltage at the second terminal of the photosensitive circuit to a preset voltage through the feedback circuit.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a high-gain active pixel circuit and an image sensor. Background Technology

[0002] An image sensor consists of multiple pixel circuits. Each pixel circuit converts incident light signals into electrical signals through photoelectric conversion to generate image information.

[0003] However, the pixel circuits in related technologies require a long time to complete photoelectric conversion, making it difficult to achieve high-speed image acquisition and limiting the improvement of the frame rate of image sensors. Summary of the Invention

[0004] This application provides a high-gain active pixel circuit and an image sensor, which reduces the exposure time required for the pixel circuit to complete the exposure of one frame of image and improves the frame rate of the image sensor.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, a high-gain active pixel circuit is provided, comprising: a photosensitive circuit, a feedback circuit, and an amplifier circuit; wherein, a first terminal of the photosensitive circuit is coupled to a ground terminal, and the photosensitive circuit is configured to generate an exposure current based on the intensity of received light; a first terminal of the feedback circuit is coupled to a second terminal of the photosensitive circuit, and the feedback circuit is configured to input the exposure current and clamp the voltage at the second terminal of the photosensitive circuit; the output terminal of the amplifier circuit is coupled to the second terminal of the feedback circuit, and the input terminal of the amplifier circuit is coupled to the second terminal of the photosensitive circuit, and the amplifier circuit is configured to clamp the voltage at the second terminal of the photosensitive circuit to a preset voltage through the feedback circuit. The feedback circuit includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first terminal of the first capacitor serves as the first terminal of the feedback circuit. The first terminal of the second capacitor is coupled to the second terminal of the first capacitor, and the second terminal of the second capacitor serves as the second terminal of the feedback circuit. The first terminal of the third capacitor is coupled to the second terminal of the first capacitor, and the second terminal of the third capacitor is coupled to a ground terminal. The first terminal of the fourth capacitor is coupled to the second terminal of the first capacitor, and the second terminal of the fourth capacitor is used to couple to a voltage regulation circuit and is configured to receive an applied voltage so that the second terminal of the fourth capacitor is at a corresponding potential.

[0007] In this embodiment, on one hand, the pixel circuit precisely clamps the voltage at the second terminal of the photosensitive circuit to a preset voltage value through the feedback mechanism of the amplification circuit, forcing the photosensitive circuit to discharge rapidly through the feedback circuit, thereby controlling the exposure time. This shortens the exposure cycle of a single frame image, effectively reducing the overall exposure time of the image sensor and improving frame rate performance. On the other hand, the feedback circuit employs a multi-capacitor coupling structure (first capacitor, second capacitor, third capacitor, and fourth capacitor). The fourth capacitor receives the external voltage applied by the voltage regulation circuit, dynamically adjusting the potential of the feedback node (the second terminal of the first capacitor), thus achieving precise control of the discharge characteristics of the photosensitive circuit. Simultaneously, the voltage regulation circuit achieves a large control range through the injection mechanism of the fourth capacitor, significantly improving the dynamic range of the pixels.

[0008] In one possible implementation, the capacitance values ​​of the first, second, and fourth capacitors are all of the first capacitance value, and the capacitance value of the third capacitor is of the second capacitance value, which is greater than the first capacitance value.

[0009] In this embodiment, the feedback circuit uses a differentiated capacitor configuration. The first and second capacitors, with small capacitance values, ensure a fast signal response and improve the bandwidth and adjustment accuracy of the feedback circuit. The third capacitor, with a large capacitance value, provides a low-impedance grounding path, significantly absorbs node noise, and improves signal integrity. The small capacitance value of the fourth capacitor allows the voltage regulation circuit to inject the control signal with higher efficiency. Combined with the voltage stabilization effect of the third capacitor, it enables exposure adjustment with a wide dynamic range.

[0010] In one possible implementation, the high-gain active pixel circuit further includes: a first branch and a first switch; the first branch is coupled between the second terminal of the photosensitive circuit and the output terminal of the amplifier circuit; the first switch is disposed on the first branch and is configured to be in a closed state between a first time point and a second time point, thereby resetting the amplifier circuit and the photosensitive circuit through the first branch, wherein the first time point is the start time of operation of the high-gain active pixel circuit and the second time point is the end time of reset of the amplifier circuit and the photosensitive circuit.

[0011] In this embodiment, the pixel circuit adds a first branch and a first switch. The first switch closes between the first and second time points, and the first branch quickly resets the amplification circuit and the photosensitive circuit, effectively clearing the residual charge in the photosensitive circuit and the amplification circuit, ensuring the consistency of the circuit state before each exposure, and improving signal accuracy.

[0012] In one possible implementation, the high-gain active pixel circuit further includes: a reset sampling circuit, a second branch, and a second switch; the first terminal of the reset sampling circuit is coupled to the output terminal of the amplifier circuit, and the second terminal of the reset sampling circuit is coupled to the ground terminal; the reset sampling circuit is configured to store voltage information input to the amplifier circuit; the second branch is coupled between the first terminal of the reset sampling circuit and the output terminal of the amplifier circuit; the second switch is disposed on the second branch, and the second switch is configured to be in a closed state between a first time point and a second time point, and the amplifier circuit resets the reset sampling circuit through the second branch; the second switch is also configured to be opened when the change in the output voltage of the amplifier circuit is within a first preset range from the third time point when it is in the closed state; the third time point is the moment when the second switch switches from the closed state to the open state.

[0013] In this embodiment, the pixel circuit achieves more precise reset control and signal sampling through the coordinated design of the reset sampling circuit, the second branch, and the second switch. The second switch is closed between the first and second time points, causing the amplifier circuit to reset the reset sampling circuit and store the reference voltage information. Furthermore, by judging the change in the amplifier circuit's output voltage (opening the switch when it reaches a first preset range at the third time point), sufficient reset is ensured while over-discharge is avoided, significantly reducing reset noise and offset voltage.

[0014] In one possible implementation, the reset sampling circuit includes: a reset sampling capacitor, wherein the first end of the reset sampling capacitor serves as the first end of the reset sampling circuit, and the second end of the reset sampling capacitor serves as the second end of the reset sampling circuit.

[0015] In this embodiment, the pixel circuit uses a reset sampling capacitor as the core component of the reset sampling circuit. By connecting its first terminal to the output of the amplifier circuit and its second terminal to ground, it achieves a highly efficient and reliable reset voltage storage function. The reset sampling capacitor can accurately store the reference voltage information of the amplifier circuit during the reset phase and maintain this reference potential stable during the signal readout phase, thereby effectively eliminating the influence of reset noise and circuit offset voltage.

[0016] In one possible implementation, illumination is generated by the light source at a fourth time point and continues until the illumination stops at a fifth time point; the fourth time point is the start time of the light source's operation, and the fifth time point is the end time of the light source's operation; wherein, the fourth time point occurs after the third time point.

[0017] In this embodiment, the pixel circuit precisely controls the illumination timing (from the fourth time point to the fifth time point) to ensure that illumination only begins after the reset sampling is completed (after the third time point), allowing the photosensitive circuit to be exposed under stable initial conditions. This timing design effectively isolates the reset process from the light signal acquisition stage, avoiding reset noise interference with the exposure process, while ensuring the accuracy of signal sampling during exposure.

[0018] In one possible implementation, the high-gain active pixel circuit further includes: an exposure sampling circuit, a third branch, and a third switch; a first terminal of the exposure sampling circuit is coupled to the output terminal of the amplifier circuit, and a second terminal of the exposure sampling circuit is coupled to a ground terminal; the exposure sampling circuit is configured to store voltage information input to the amplifier circuit; the third branch is coupled between the first terminal of the exposure sampling circuit and the output terminal of the amplifier circuit; the third switch is disposed on the third branch, and the third switch is configured to be in a closed state between a first time point and a second time point, and the amplifier circuit resets the exposure sampling circuit through the third branch; the third switch is also configured to be disconnected when the change in the output voltage of the amplifier circuit is within a second preset range from the sixth time point when it is in the closed state; the sixth time point is the moment when the third switch switches from the closed state to the open state; wherein, the sixth time point occurs after the fifth time point, and the voltage in the second preset range is greater than the voltage in the first preset range.

[0019] In this embodiment, the pixel circuit achieves high-precision acquisition and processing of light signals by introducing an exposure sampling circuit, a third branch, and a third switch. The third switch is closed between the first and second time points to reset the exposure sampling circuit via the amplifier circuit. Subsequently, at the sixth time point (after illumination ends), the third switch is opened based on the output voltage change, ensuring complete recording of signal changes generated by illumination. By separating the voltage ranges of reset sampling and exposure sampling (the second preset range > the first preset range), reset noise and real light signals are effectively distinguished, significantly improving the signal-to-noise ratio. Simultaneously, the illumination timing is strictly matched (sampling continues until the sixth time point after illumination ends), completely capturing voltage changes during exposure and avoiding signal loss.

[0020] In one possible implementation, the exposure sampling circuit includes: an exposure sampling capacitor, the first end of which serves as the first end of the exposure sampling circuit, and the second end of which serves as the second end of the exposure sampling circuit.

[0021] In this embodiment, the pixel circuit uses an exposure sampling capacitor as the core component of the exposure sampling circuit. Through its structure—with its first terminal connected to the output of the amplifier circuit and its second terminal grounded—high-precision optical signal acquisition is achieved. The exposure sampling capacitor can accurately record the voltage changes generated by the optical signal during the exposure phase and maintain signal integrity during the readout phase. Its collaborative work with the reset sampling capacitor enables dual sampling for both reset and exposure. Furthermore, by strictly controlling the sampling period of the exposure sampling capacitor to occur after illumination (the sixth time point), all photogenerated charges are ensured to be completely captured.

[0022] In one possible implementation, starting from the fourth time point, the voltage at the second terminal of the fourth capacitor rises from the first voltage to the second voltage, until starting from the seventh time point, the voltage at the second terminal of the fourth capacitor drops from the second voltage back to the first voltage; the seventh time point is the moment when the voltage at the second terminal of the fourth capacitor begins to drop from the second voltage; wherein, the seventh time point occurs after the sixth time point.

[0023] In this embodiment, the pixel circuit achieves dynamic optimization control of the photosensitive circuit by precisely controlling the voltage modulation timing of the fourth capacitor (from the fourth time point to the seventh time point). During the exposure phase (starting from the fourth time point), the voltage of the fourth capacitor is increased from the first voltage to the second voltage, enhancing the charge collection efficiency of the photosensitive circuit. After the signal readout phase ends (at the seventh time point, i.e., after the sixth time point), the voltage is restored to the first voltage to prepare for the next exposure. This timing-matched voltage modulation has several advantages. First, the high voltage (second voltage) during exposure can expand the full-well capacity of the photosensitive node, improving the pixel dynamic range. Second, the voltage rise and fall are strictly synchronized with the exposure / readout timing to avoid signal interference. Third, capacitive coupling enables DC-free potential adjustment, maintaining low power consumption while improving performance.

[0024] In one possible implementation, after the seventh time point, exposure information is obtained based on the voltage information stored in the exposure sampling circuit and the voltage information stored in the reset sampling circuit.

[0025] In this embodiment, the pixel circuit achieves high-precision photoelectric signal extraction by comparing the voltage information stored in the exposure sampling capacitor and the reset sampling capacitor after the seventh time point.

[0026] In one possible implementation, the photosensitive circuit includes a photodiode, with the anode of the photodiode serving as the first terminal of the photosensitive circuit and the cathode of the photodiode serving as the second terminal of the photosensitive circuit.

[0027] In this embodiment, the pixel circuit uses a photodiode as the core component of the photosensitive circuit. Through a simple structure where its anode is grounded and its cathode is connected to the feedback circuit, efficient photoelectric conversion is achieved. The cathode, serving as the signal output terminal, naturally adapts to the subsequent feedback control loop, facilitating voltage clamping and rapid reset.

[0028] In one possible implementation, the amplifier circuit includes: a first P-type metal-oxide-semiconductor transistor and a first N-type metal-oxide-semiconductor transistor; wherein the source of the first P-type metal-oxide-semiconductor transistor is coupled to a power supply terminal; the drain of the first N-type metal-oxide-semiconductor transistor serves as the output terminal of the amplifier circuit and is coupled to the drain of the first P-type metal-oxide-semiconductor transistor; the source of the first N-type metal-oxide-semiconductor transistor is coupled to a ground terminal; and the gate of the first N-type metal-oxide-semiconductor transistor serves as the input terminal of the amplifier circuit.

[0029] In this embodiment, the pixel circuit employs a common-source amplifier circuit composed of a first P-type metal-oxide-semiconductor transistor (MOSFET) and a first N-type MOSFET. This simple two-transistor design, using the first P-type MOSFET as the active load and the first N-type MOSFET as the input stage, achieves high-performance signal amplification. Furthermore, the high impedance of the gate input of the first N-type MOSFET ensures no interference with the photocurrent, while the push-pull output structure provides fast signal transmission capability. Simultaneously, the compact design requiring only two transistors saves layout area and supports high-density pixel array integration.

[0030] In one possible implementation, the amplifier circuit includes: a second P-type metal-oxide-semiconductor transistor (MOSFET), a third P-type MOSFET, a second N-type MOSFET, and a third N-type MOSFET; wherein the source of the second P-type MOSFET is coupled to a power supply terminal; the source of the third P-type MOSFET is coupled to the drain of the second P-type MOSFET; the drain of the second N-type MOSFET serves as the output terminal of the amplifier circuit and is coupled to the drain of the third P-type MOSFET; the drain of the third N-type MOSFET is coupled to the source of the second N-type MOSFET; the source of the third N-type MOSFET is coupled to a ground terminal; and the gate of the third N-type MOSFET serves as the input terminal of the amplifier circuit.

[0031] In this embodiment, the pixel circuit employs a common-source, common-gate amplifier circuit composed of two pairs of P-type and N-type metal-oxide-semiconductor (MOS) transistors. High-performance signal amplification is achieved through the coordinated operation of these four transistor stages. The second and third P-type MOS transistors form an active load stage, which, in conjunction with the common-source, common-gate amplifier stage formed by the second and third N-type MOS transistors, expands the bandwidth while maintaining ultra-high gain through the isolation effect of the common-gate structure. Furthermore, the current buffering effect of the common-gate stage reduces input noise, significantly improving the signal-to-noise ratio in low-light environments. Simultaneously, the high impedance of the gate input of the third N-type MOS transistor ensures no interference with the optical signal, while the multi-stage negative feedback structure keeps temperature drift within a small range.

[0032] In a second aspect, an image sensor is provided, the image sensor including: a light source;

[0033] The pixel array includes multiple high-gain active pixel circuits, as in the first aspect. Attached Figure Description

[0034] Figure 1 A schematic diagram of a pixel circuit provided for embodiments of this application. Figure 1 ;

[0035] Figure 2 A schematic diagram of a pixel circuit provided for embodiments of this application. Figure 2 ;

[0036] Figure 3 A schematic diagram of the operating timing of a pixel circuit provided for an embodiment of this application;

[0037] Figure 4 A schematic diagram of a high-gain active pixel circuit provided for embodiments of this application. Figure 1 ;

[0038] Figure 5 A schematic diagram of a high-gain active pixel circuit provided for embodiments of this application. Figure 2 ;

[0039] Figure 6 A schematic diagram of a high-gain active pixel circuit provided for embodiments of this application. Figure 3 ;

[0040] Figure 7 This is a timing diagram illustrating the operation of a high-gain active pixel circuit, provided as an embodiment of this application.

[0041] Figure label:

[0042] In the diagram, PD1 is the first photodiode, 101 is the first parasitic capacitance, 201 is the photosensitive circuit, 202 is the amplifier circuit, 203 is the amplifier feedback capacitor, 204 is the amplifier reset switch, 205 is the reset sampling switch, 206 is the exposure sampling switch, 207 is the reset sampling circuit, 2071 is the reset sampling capacitor, 208 is the exposure sampling circuit, and 2081 is the reset sampling capacitor. Exposure sampling capacitor, 209. Output circuit, PD2. Second photodiode, 2011. Second parasitic capacitance, 401. Feedback circuit, 402. First switch, 403. Second switch, 404. Third switch, C1. First capacitor, C2. Second capacitor, C3. Third capacitor, C4. Fourth capacitor, MP1. First P-type metal-oxide-semiconductor transistor, MN1. First N-type metal-oxide-semiconductor transistor, MP2. Second P-type metal-oxide-semiconductor transistor, MP3. Third P-type metal-oxide-semiconductor transistor, MN2. Second N-type metal-oxide-semiconductor transistor, MN3. Third N-type metal-oxide-semiconductor transistor, MP4. Fourth P-type metal-oxide-semiconductor transistor. Metal-oxide-semiconductor transistor (MOS transistor), MP5. Fifth P-type MOS transistor, MN4. Fourth N-type MOS transistor, MN5. Fifth N-type MOS transistor, MN6. Sixth N-type MOS transistor, MN7. Seventh N-type MOS transistor, MN8. Eighth N-type MOS transistor, MN9. Ninth N-type MOS transistor, MN10. Tenth N-type MOS transistor, 501. First terminal, 502. Second terminal, C5. Fifth capacitor, C6. Sixth capacitor, C7. Seventh capacitor, C8. Eighth capacitor, C9. Ninth capacitor, C10. Tenth capacitor. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0044] In the description of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" and "multiple" refer to two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0045] Image sensors are widely used in fields such as photography, video surveillance, medical imaging, and industrial inspection. An image sensor consists of multiple pixel circuits, including but not limited to 3T pixel circuits and 4T pixel circuits.

[0046] like Figure 1 As shown, in the 3T pixel circuit, the anode of the first photodiode (PD) PD1 is coupled to the ground terminal, the cathode of the first photodiode PD1 is coupled to the first terminal of the first parasitic capacitor 101, and the second terminal of the first parasitic capacitor 101 is coupled to the ground terminal. The base of the first photodiode PD1 is also coupled to the drain of the eighth N-type metal-oxide-semiconductor transistor MN8, and the base of the first photodiode PD1 is also coupled to the gate of the ninth N-type metal-oxide-semiconductor transistor MN9. Furthermore, the first terminal of the first parasitic capacitor 101 is also coupled to the drain of the eighth N-type metal-oxide-semiconductor transistor MN8, and the first terminal of the first parasitic capacitor 101 is also coupled to the gate of the ninth N-type metal-oxide-semiconductor transistor MN9. The gate of the eighth N-type metal-oxide-semiconductor transistor MN8 is used to receive a reset signal, and the source of the eighth N-type metal-oxide-semiconductor transistor MN8 is coupled to the power supply terminal. The source of the ninth N-type metal-oxide-semiconductor transistor MN9 is coupled to the power supply terminal, and the drain of the ninth N-type metal-oxide-semiconductor transistor MN9 is coupled to the source of the tenth N-type metal-oxide-semiconductor transistor MN10. The gate of the tenth N-type metal-oxide-semiconductor transistor MN10 is used to receive the row selection signal, and the drain of the tenth N-type metal-oxide-semiconductor transistor MN10 is the output terminal.

[0047] In a 3T pixel circuit, the pixel photosensitive current output by the first photodiode PD1 needs to discharge the first parasitic capacitance 101 of the pixel photosensitive area to obtain the exposure signal. However, the capacitance of the first parasitic capacitance 101 is affected by the size of the pixel photosensitive area. When the capacitance of the first parasitic capacitance 101 is large (e.g., 50fF+), the 3T pixel circuit requires a longer exposure time. Therefore, the current pixel circuit requires a long time to complete the exposure of one frame of image, resulting in a lower frame rate of the image sensor.

[0048] To address the issue of excessively long exposure times in 3T pixel circuits, this disclosure provides an implementation method, such as... Figure 2 As shown, the pixel circuit includes: a photosensitive circuit 201, an amplifier circuit 202, an amplifier feedback capacitor 203, an amplifier reset switch 204, a reset sampling switch 205, an exposure sampling switch 206, a reset sampling circuit 207, an exposure sampling circuit 208, and an output circuit 209. The reset sampling circuit 207 and the exposure sampling circuit 208 constitute a dual sampling circuit.

[0049] The photosensitive circuit 201 includes a second photosensitive diode PD2 and a second parasitic capacitor 2011. The anode of the second photosensitive diode PD2 is coupled to a ground terminal, the cathode of the second photosensitive diode PD2 is coupled to a first terminal of the second parasitic capacitor 2011, and the second terminal of the second parasitic capacitor 2011 is coupled to a ground terminal.

[0050] The amplifier circuit 202 can be a common-source, common-gate amplifier, including: a second P-type metal-oxide-semiconductor transistor MP2, a third P-type metal-oxide-semiconductor transistor MP3, a second N-type metal-oxide-semiconductor transistor MN2, and a third N-type metal-oxide-semiconductor transistor MN3. The source of the second P-type metal-oxide-semiconductor transistor MP2 is coupled to the power supply terminal, and the gate of the second P-type metal-oxide-semiconductor transistor MP2 is used to receive a bias signal. The source of the third P-type metal-oxide-semiconductor transistor MP3 is coupled to the drain of the second P-type metal-oxide-semiconductor transistor MP2, and the gate of the third P-type metal-oxide-semiconductor transistor MP3 is used to receive a bias signal. The drain of the second N-type metal-oxide-semiconductor transistor MN2 is coupled to the drain of the third P-type metal-oxide-semiconductor transistor MP3, and the gate of the second N-type metal-oxide-semiconductor transistor MN2 is used to receive a bias signal. The drain of the third N-type metal-oxide-semiconductor transistor MN3 is coupled to the source of the second N-type metal-oxide-semiconductor transistor MN2. The gate of the third N-type metal-oxide-semiconductor transistor MN3 is coupled to the cathode of the second photodiode PD2 and the first terminal of the second parasitic capacitor 2011. The source of the third N-type metal-oxide-semiconductor transistor MN3 is coupled to the ground terminal.

[0051] The first terminal of the amplifier feedback capacitor 203 is coupled to the cathode of the second photodiode PD2 and the first terminal of the second parasitic capacitor 2011. The second terminal of the amplifier feedback capacitor 203 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2 and the drain of the third P-type metal-oxide-semiconductor transistor MP3.

[0052] The first terminal of the amplifier reset switch 204 is coupled to the cathode of the second photodiode PD2 and the first terminal of the second parasitic capacitor 2011. The second terminal of the amplifier reset switch 204 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2 and the drain of the third P-type metal-oxide-semiconductor transistor MP3.

[0053] The first terminal of the reset sampling switch 205 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2 and the drain of the third P-type metal-oxide-semiconductor transistor MP3.

[0054] The first terminal of the exposure sampling switch 206 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2 and the drain of the third P-type metal-oxide-semiconductor transistor MP3.

[0055] The reset sampling circuit 207 includes a fourth P-type metal-oxide-semiconductor transistor MP4 and a reset sampling capacitor 2071. The source of the fourth P-type metal-oxide-semiconductor transistor MP4 is coupled to the power supply terminal, the drain of the fourth P-type metal-oxide-semiconductor transistor MP4 is coupled to the first terminal of the reset sampling capacitor 2071 and the second terminal of the reset sampling switch 205, and the second terminal of the reset sampling capacitor 2071 is coupled to the ground terminal.

[0056] The exposure sampling circuit 208 includes a fifth P-type metal-oxide-semiconductor transistor MP5 and an exposure sampling capacitor 2081. The source of the fifth P-type metal-oxide-semiconductor transistor MP5 is coupled to the power supply terminal, the drain of the fifth P-type metal-oxide-semiconductor transistor MP5 is coupled to the first terminal of the exposure sampling capacitor 2081 and the second terminal of the exposure sampling switch 206, and the second terminal of the exposure sampling capacitor 2081 is coupled to the ground terminal.

[0057] The gate of the fifth P-type metal-oxide-semiconductor transistor MP5 is coupled to the gate of the fourth P-type metal-oxide-semiconductor transistor MP4.

[0058] The output circuit 209 includes: a fourth N-type metal-oxide-semiconductor transistor MN4, a fifth N-type metal-oxide-semiconductor transistor MN5, a sixth N-type metal-oxide-semiconductor transistor MN6, and a seventh N-type metal-oxide-semiconductor transistor MN7. The drain of the fourth N-type metal-oxide-semiconductor transistor MN4 is coupled to the power supply terminal, and its gate is coupled to the drain of a fourth P-type metal-oxide-semiconductor transistor MP4, the first terminal of the reset sampling capacitor 2071, and the second terminal of the reset sampling switch 205. The source of the fourth N-type metal-oxide-semiconductor transistor MN4 is coupled to the drain of the fifth N-type metal-oxide-semiconductor transistor MN5, whose gate is used to receive the row selection signal, and whose source is coupled to the negative output terminal. The drain of the sixth N-type metal-oxide-semiconductor transistor MN6 is coupled to the power supply terminal, and its gate is coupled to the drain of the fifth P-type metal-oxide-semiconductor transistor MP5, the first terminal of the exposure sampling capacitor 2081, and the second terminal of the exposure sampling switch 206. The source of the sixth N-type metal-oxide-semiconductor transistor MN6 is coupled to the drain of the seventh N-type metal-oxide-semiconductor transistor MN7. The gate of the seventh N-type metal-oxide-semiconductor transistor MN7 is used to receive the row selection signal. The source of the seventh N-type metal-oxide-semiconductor transistor MN7 is coupled to the positive output terminal.

[0059] It should be noted that, Figure 2 The pixel circuit shown introduces an amplifier circuit 202 between the photosensitive circuit 201 and the output circuit 209. The amplifier circuit 202 can clamp the potential of the photosensitive area, adjusting the discharge of the pixel photosensitive current to the parasitic capacitor in the original 3T pixel circuit to discharge to the amplifier feedback capacitor 203. Since the amplifier feedback capacitor 203 is artificially added, it can be designed with a very small capacitance value, thereby significantly reducing the exposure time.

[0060] Combination Figure 2 The pixel circuit shown is as follows: Figure 3 As shown, at the first time t1, the amplifier reset switch 204, reset sampling switch 205, and exposure sampling switch 206 are simultaneously closed, putting the amplifier circuit 202 in a reset state. At the second time t2, the amplifier reset switch 204 is opened, ending the reset state of the amplifier circuit 202. After the output of the amplifier circuit 202 stabilizes, at the third time t3, the reset sampling switch 205 is opened, and the reset voltage of the amplifier circuit 202 and the influence voltage introduced by the amplifier reset switch 204 are stored in the reset sampling capacitor 2071. Subsequently, at the fourth time t4, the light-emitting diode (LED) is lit, and after the LED is exposed for a period of time, it is turned off at the fifth time t5. After the amplifier circuit 202 stabilizes, at the sixth time t6, the exposure sampling switch 206 is opened, and the exposure result (exposure voltage) is stored in the exposure sampling capacitor 2081.

[0061] Thus, when all pixels in the pixel matrix perform the above operations synchronously, the reset voltage and exposure voltage of the pixel will be stored in the corresponding capacitor. Subsequently, the voltages stored in the two capacitors can be read out sequentially or synchronously, and the difference between the two voltages (i.e., the reset voltage and the exposure voltage) can be calculated to obtain the actual pixel exposure value.

[0062] However, for Figure 2 The pixel circuit shown requires a sufficiently small amplifier feedback capacitor 203 to achieve a high enough pixel gain. However, due to the large matrix characteristics of the image sensor, the pixel circuits at different locations are far apart, leading to variations in the amplifier feedback capacitor 203 within different pixel circuits. This variation causes gain mismatch between pixels. The smaller the value of the amplifier feedback capacitor 203, the greater the gain mismatch between pixels. Therefore, Figure 2 The pixel circuit shown is difficult to apply in large-matrix, high-sensitivity image sensors.

[0063] Based on this, this application provides a high-gain active pixel circuit. The high-gain active pixel circuit uses a feedback mechanism of the amplification circuit to precisely clamp the voltage at the second terminal of the photosensitive circuit to a preset voltage value, forcing the photosensitive circuit to discharge rapidly through the feedback circuit, thereby controlling the exposure time. Thus, the exposure cycle of a single frame image can be shortened by setting the feedback circuit, effectively reducing the overall exposure time of the image sensor and improving frame rate performance.

[0064] The high-gain active pixel circuit provided in the embodiments of this application is described below with reference to the accompanying drawings. The high-gain active pixel circuit provided in the embodiments of this application is applicable to pixel arrays within image sensors and can be used to extract image data. In the embodiments of this application, the image sensor can be applied to photographic equipment, video surveillance equipment, medical imaging equipment, industrial inspection equipment, optical mice, etc., and this application does not impose specific limitations on it.

[0065] like Figure 4 The diagram shown is a schematic of a high-gain active pixel circuit provided in an embodiment of this application. The high-gain active pixel circuit includes: a photosensitive circuit 201, an amplifier circuit 202, a feedback circuit 401, a first switch 402, a second switch 403, a third switch 404, a reset sampling circuit 207, an exposure sampling circuit 208, and an output circuit 209. The reset sampling circuit 207 and the exposure sampling circuit 208 constitute a dual sampling circuit.

[0066] The first terminal of the photosensitive circuit 201 is coupled to the ground terminal, and the photosensitive circuit 201 is configured to generate an exposure current according to the intensity of the received light.

[0067] In this embodiment of the application, the photosensitive circuit 201 includes: a second photosensitive diode PD2 and a second parasitic capacitor 2011, wherein the anode of the second photosensitive diode PD2 serves as the first terminal of the photosensitive circuit 201, and the cathode of the second photosensitive diode PD2 serves as the second terminal of the photosensitive circuit 201.

[0068] That is, the anode of the second photodiode PD2 is coupled to the ground terminal, the cathode of the second photodiode PD2 is coupled to the first terminal of the second parasitic capacitor 2011, and the second terminal of the second parasitic capacitor 2011 is coupled to the ground terminal.

[0069] In this embodiment, the pixel circuit uses a photodiode as the core component of the photosensitive circuit. Through a simple structure where its anode is grounded and its cathode is connected to the feedback circuit, efficient photoelectric conversion is achieved. The cathode, serving as the signal output terminal, naturally adapts to the subsequent feedback control loop, facilitating voltage clamping and rapid reset.

[0070] The first terminal of the feedback circuit 401 is coupled to the second terminal of the photosensitive circuit 201. The feedback circuit 401 is configured to: input exposure current and clamp the voltage at the second terminal of the photosensitive circuit 201.

[0071] That is, the first terminal of the feedback circuit 401 is coupled to the cathode of the second photodiode PD2 and the first terminal of the second parasitic capacitor 2011.

[0072] In this embodiment, the feedback circuit 401 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The first terminal of the first capacitor C1 serves as the first terminal of the feedback circuit 401; the first terminal of the second capacitor C2 is coupled to the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2 serves as the second terminal of the feedback circuit 401; the first terminal of the third capacitor C3 is coupled to the second terminal of the first capacitor C1, and the second terminal of the third capacitor C3 is coupled to a ground terminal; the first terminal of the fourth capacitor C4 is coupled to the second terminal of the first capacitor C1, and the second terminal of the fourth capacitor C4 is used to couple to a voltage regulation circuit. The fourth capacitor C4 is configured to receive an applied voltage so that its second terminal is at a corresponding potential.

[0073] That is, the first terminal of the first capacitor C1 is coupled to the cathode of the second photodiode PD2 and the first terminal of the second parasitic capacitor 2011, the first terminal of the third capacitor C3 is coupled to the first terminal of the second capacitor C2, and the first terminal of the fourth capacitor C4 is coupled to the first terminal of the second capacitor C2.

[0074] In this embodiment, the feedback circuit employs a multi-capacitor coupling structure (first capacitor, second capacitor, third capacitor, and fourth capacitor). The fourth capacitor receives the external voltage applied by the voltage regulation circuit, dynamically adjusting the potential of the feedback node (the second terminal of the first capacitor), thereby achieving precise control over the discharge characteristics of the photosensitive circuit. Simultaneously, the voltage regulation circuit, through the injection mechanism of the fourth capacitor, achieves a wide control range, thus significantly improving the dynamic range of the pixels.

[0075] In the embodiments of this application, the capacitance values ​​of the first capacitor C1, the second capacitor C2 and the fourth capacitor C4 are the first capacitance values, and the capacitance value of the third capacitor C3 is the second capacitance value, which is greater than the first capacitance value.

[0076] In this embodiment, the feedback circuit uses a differentiated capacitor configuration. The first and second capacitors, with small capacitance values, ensure a fast signal response and improve the bandwidth and adjustment accuracy of the feedback circuit. The third capacitor, with a large capacitance value, provides a low-impedance grounding path, significantly absorbs node noise, and improves signal integrity. The small capacitance value of the fourth capacitor allows the voltage regulation circuit to inject the control signal with higher efficiency. Combined with the voltage stabilization effect of the third capacitor, it enables exposure adjustment with a wide dynamic range.

[0077] In the embodiments of this application, such as Figure 5 The diagram shown is an equivalent representation of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 from a star connection to a terminal connection. The first terminal 501 is the output terminal of the amplifier circuit 202, and the second terminal 502 is the second terminal of the photosensitive circuit 201.

[0078] The fifth capacitor C5 is the equivalent capacitance between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2. The sixth capacitor C6 is the equivalent capacitance between the second terminal of the first capacitor C1 and the first terminal of the third capacitor C3. The seventh capacitor C7 is the equivalent capacitance between the second terminal of the first capacitor C1 and the first terminal of the fourth capacitor C4. The eighth capacitor C8 is the equivalent capacitance between the first terminal of the second capacitor C2 and the first terminal of the third capacitor C3. The ninth capacitor C9 is the equivalent capacitance between the first terminal of the second capacitor C2 and the first terminal of the fourth capacitor C4. The tenth capacitor C10 is the equivalent capacitance between the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4.

[0079] In the embodiments of this application, the capacitance of the first capacitor C1 is C1, the capacitance of the second capacitor C2 is C2, the capacitance of the third capacitor C3 is C3, and the capacitance of the fourth capacitor C4 is C4. Therefore, the capacitance of the fifth capacitor C5 is C12 = C1 × C2 ÷ (C1 + C2 + C3 + C4), the capacitance of the sixth capacitor C6 is C13 = C1 × C3 ÷ (C1 + C2 + C3 + C4), the capacitance of the seventh capacitor C7 is C14 = C1 × C4 ÷ (C1 + C2 + C3 + C4), the capacitance of the eighth capacitor C8 is C23 = C2 × C3 ÷ (C1 + C2 + C3 + C4), the capacitance of the ninth capacitor C9 is C24 = C2 × C4 ÷ (C1 + C2 + C3 + C4), and the capacitance of the tenth capacitor C10 is C34 = C3 × C4 ÷ (C1 + C2 + C3 + C4).

[0080] In this embodiment, when C1=C2=C4=C, C3=nC (n is a constant, C is the first preset capacitance value), and the voltage regulation circuit coupled to the second terminal of the fourth capacitor C4 is grounded, the tenth capacitor C10 is short-circuited and ineffective. The sixth capacitor C6 and the seventh capacitor C7 are the pixel's capacitance to ground, and the eighth capacitor C8 and the ninth capacitor C9 are the output capacitance to ground of the amplifier circuit 202, none of which affect the current gain of the amplifier circuit 202. At this time, the capacitance value of the fifth capacitor C5 in the circuit is C12=C1×C2÷(C1+C2+C3+C4)=C÷(3+n). If the capacitance value C12 of the fifth capacitor C5 is made to reach the second preset capacitance value Cf (the second preset capacitance value is less than the first preset capacitance value), then the first preset capacitance value C=(3+n)×Cf. Therefore, as long as the capacitance value C3 of the third capacitor is large enough, then n is large enough. The capacitance values ​​C1 of the first capacitor C1, C2 of the second capacitor C2, C3 of the third capacitor C3, and C4 of the fourth capacitor C4 can achieve the effect of a small capacitor with larger capacitance values. The consistency of larger capacitance values ​​among pixels can ensure that the pixel matrix has a low pixel gain mismatch, thereby achieving low noise and high sensitivity of pixels.

[0081] The output terminal of the amplifier circuit 202 is coupled to the second terminal of the feedback circuit 401, and the input terminal of the amplifier circuit 202 is coupled to the second terminal of the photosensitive circuit 201. The amplifier circuit 202 is configured to clamp the voltage at the second terminal of the photosensitive circuit 201 to a preset voltage through the feedback circuit 401.

[0082] In this embodiment, the pixel circuit precisely clamps the voltage at the second terminal of the photosensitive circuit to a preset voltage value through the feedback mechanism of the amplification circuit, forcing the photosensitive circuit to discharge rapidly through the feedback circuit, thereby controlling the exposure time. Thus, the exposure cycle of a single frame image can be shortened by setting the feedback circuit, effectively reducing the overall exposure time of the image sensor and improving frame rate performance.

[0083] In this embodiment, the amplifier circuit 202 is a common-source amplifier, such as... Figure 4 As shown, the amplifier circuit 202 includes a first P-type metal-oxide-semiconductor transistor MP1 and a first N-type metal-oxide-semiconductor transistor MN1.

[0084] In this circuit, the source of the first P-type metal-oxide-semiconductor transistor MP1 is coupled to the power supply terminal; the drain of the first N-type metal-oxide-semiconductor transistor MN1 serves as the output terminal of the amplifier circuit 202 and is coupled to the drain of the first P-type metal-oxide-semiconductor transistor MP1; the source of the first N-type metal-oxide-semiconductor transistor MN1 is coupled to the ground terminal; and the gate of the first N-type metal-oxide-semiconductor transistor MN1 serves as the input terminal of the amplifier circuit 202.

[0085] That is, the drain of the first P-type metal-oxide-semiconductor transistor MP1 is coupled to the second terminal of the second capacitor C2, and the drain of the first N-type metal-oxide-semiconductor transistor MN1 is coupled to the second terminal of the second capacitor C2. The gate of the first N-type metal-oxide-semiconductor transistor MN1 is coupled to the second terminal of the photosensitive circuit 201 (i.e., the cathode of the second photosensitive diode PD2 and the first terminal of the second parasitic capacitor 2011).

[0086] Furthermore, the gate of the first P-type metal-oxide-semiconductor transistor MP1 is used to receive a bias signal.

[0087] In this embodiment, the pixel circuit employs a common-source amplifier circuit composed of a first P-type metal-oxide-semiconductor transistor (MOSFET) and a first N-type MOSFET. This simple two-transistor design, using the first P-type MOSFET as the active load and the first N-type MOSFET as the input stage, achieves high-performance signal amplification. Furthermore, the high impedance of the gate input of the first N-type MOSFET ensures no interference with the photocurrent, while the push-pull output structure provides fast signal transmission capability. Simultaneously, the compact design requiring only two transistors saves layout area and supports high-density pixel array integration.

[0088] In this embodiment, the amplifier circuit 202 is a common-source cascode amplifier, such as... Figure 6 As shown, the amplifier circuit 202 includes: a second P-type metal-oxide-semiconductor transistor MP2, a third P-type metal-oxide-semiconductor transistor MP3, a second N-type metal-oxide-semiconductor transistor MN2, and a third N-type metal-oxide-semiconductor transistor MN3.

[0089] In this circuit, the source of the second P-type metal-oxide-semiconductor transistor MP2 is coupled to the power supply terminal; the source of the third P-type metal-oxide-semiconductor transistor MP3 is coupled to the drain of the second P-type metal-oxide-semiconductor transistor MP2; the drain of the second N-type metal-oxide-semiconductor transistor MN2 serves as the output terminal of the amplifier circuit 202, and the drain of the second N-type metal-oxide-semiconductor transistor MN2 is coupled to the drain of the third P-type metal-oxide-semiconductor transistor MP3; the drain of the third N-type metal-oxide-semiconductor transistor MN3 is coupled to the source of the second N-type metal-oxide-semiconductor transistor MN2; the source of the third N-type metal-oxide-semiconductor transistor MN3 is coupled to the ground terminal; and the gate of the third N-type metal-oxide-semiconductor transistor MN3 serves as the input terminal of the amplifier circuit 202.

[0090] That is, the drain of the third P-type metal-oxide-semiconductor transistor MP3 is coupled to the second terminal of the second capacitor C2, and the drain of the second N-type metal-oxide-semiconductor transistor MN2 is coupled to the second terminal of the second capacitor C2. The gate of the third N-type metal-oxide-semiconductor transistor MN3 is coupled to the second terminal of the photosensitive circuit 201 (i.e., the cathode of the second photosensitive diode PD2 and the first terminal of the second parasitic capacitor 2011).

[0091] Furthermore, the gate of the second P-type metal-oxide-semiconductor transistor MP2 is used to receive the bias signal, and the gate of the second N-type metal-oxide-semiconductor transistor MN2 is used to receive the bias signal.

[0092] In this embodiment, the pixel circuit employs a common-source, common-gate amplifier circuit composed of two pairs of P-type and N-type metal-oxide-semiconductor (MOS) transistors. High-performance signal amplification is achieved through the coordinated operation of these four transistor stages. The second and third P-type MOS transistors form an active load stage, which, in conjunction with the common-source, common-gate amplifier stage formed by the second and third N-type MOS transistors, expands the bandwidth while maintaining ultra-high gain through the isolation effect of the common-gate structure. Furthermore, the current buffering effect of the common-gate stage reduces input noise, significantly improving the signal-to-noise ratio in low-light environments. Simultaneously, the high impedance of the gate input of the third N-type MOS transistor ensures no interference with the optical signal, while the multi-stage negative feedback structure keeps temperature drift within a small range.

[0093] In this embodiment, the high-gain active pixel circuit further includes a first branch, which is coupled between the second terminal of the photosensitive circuit 201 and the output terminal of the amplifier circuit 202.

[0094] In this embodiment, the first switch 402 is disposed on the first branch. The first switch 402 is configured to be in a closed state between the first time point and the second time point, and to reset the amplifier circuit 202 and the photosensitive circuit 201 through the first branch. The first time point is the start time of the operation of the high-gain active pixel circuit, and the second time point is the end time of the reset of the amplifier circuit 202 and the photosensitive circuit 201.

[0095] That is, the first terminal of the first switch 402 is coupled to the cathode of the second photodiode PD2 and the first terminal of the second parasitic capacitor 2011, and the second terminal of the first switch 402 is coupled to the output terminal of the amplifier circuit 202. Specifically, when the amplifier circuit 202 is a common-source amplifier, the second terminal of the first switch 402 is coupled to the drain of the first N-type metal-oxide-semiconductor transistor MN1; when the amplifier circuit 202 is a common-source cascode amplifier, the second terminal of the first switch 402 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2.

[0096] In this embodiment, the pixel circuit adds a first branch and a first switch. The first switch closes between the first and second time points, and the first branch quickly resets the amplification circuit and the photosensitive circuit, effectively clearing the residual charge in the photosensitive circuit and the amplification circuit, ensuring the consistency of the circuit state before each exposure, and improving signal accuracy.

[0097] In this embodiment, the high-gain active pixel circuit further includes a second branch coupled between the first terminal of the reset sampling circuit 207 and the output terminal of the amplifier circuit 202. The first terminal of the reset sampling circuit 207 is coupled to the output terminal of the amplifier circuit 202, and the second terminal of the reset sampling circuit 207 is coupled to a ground terminal; the reset sampling circuit 207 is configured to store voltage information input to the amplifier circuit 202.

[0098] In this embodiment, the second switch 403 is disposed on the second branch. The second switch 403 is configured to be in a closed state between the first time point and the second time point, and the amplifier circuit 202 resets the reset sampling circuit 207 through the second branch. The second switch 403 is also configured to be disconnected when the change in the output voltage of the amplifier circuit 202 is within a first preset range from the third time point when it is in the closed state. The third time point is the moment when the second switch 403 switches from the closed state to the open state.

[0099] The first terminal of the second switch 403 is coupled to the output terminal of the amplifier circuit 202. That is, when the amplifier circuit 202 is a common-source amplifier, the first terminal of the second switch 403 is coupled to the drain of the first N-type metal-oxide-semiconductor transistor MN1; when the amplifier circuit 202 is a common-source cascode amplifier, the first terminal of the second switch 403 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2.

[0100] In this embodiment, the pixel circuit achieves more precise reset control and signal sampling through the coordinated design of the reset sampling circuit, the second branch, and the second switch. The second switch is closed between the first and second time points, causing the amplifier circuit to reset the reset sampling circuit and store the reference voltage information. Furthermore, by judging the change in the amplifier circuit's output voltage (opening the switch when it reaches a first preset range at the third time point), sufficient reset is ensured while over-discharge is avoided, significantly reducing reset noise and offset voltage.

[0101] In this embodiment, the reset sampling circuit 207 includes a fourth P-type metal-oxide-semiconductor transistor MP4 and a reset sampling capacitor 2071. The first terminal of the reset sampling capacitor 2071 serves as the first terminal of the reset sampling circuit 207, and the second terminal of the reset sampling capacitor 2071 serves as the second terminal of the reset sampling circuit 207.

[0102] The source of the fourth P-type metal-oxide-semiconductor transistor MP4 is coupled to the power supply terminal, the drain of the fourth P-type metal-oxide-semiconductor transistor MP4 is coupled to the first terminal of the reset sampling capacitor 2071 and the second terminal of the second switch 403, the first terminal of the reset sampling capacitor 2071 is coupled to the second terminal of the second switch 403, and the second terminal of the reset sampling capacitor 2071 is coupled to the ground terminal.

[0103] In this embodiment, the pixel circuit uses a reset sampling capacitor as the core component of the reset sampling circuit. By connecting its first terminal to the output of the amplifier circuit and its second terminal to ground, it achieves a highly efficient and reliable reset voltage storage function. The reset sampling capacitor can accurately store the reference voltage information of the amplifier circuit during the reset phase and maintain this reference potential stable during the signal readout phase, thereby effectively eliminating the influence of reset noise and circuit offset voltage.

[0104] In this embodiment, illumination is generated by the light source at a fourth time point and continues until the illumination stops at a fifth time point; wherein, the fourth time point occurs after the third time point. The fourth time point is the start time of the light source's operation, and the fifth time point is the end time of the light source's operation.

[0105] In this embodiment, the pixel circuit precisely controls the illumination timing (from the fourth time point to the fifth time point) to ensure that illumination only begins after the reset sampling is completed (after the third time point), allowing the photosensitive circuit to be exposed under stable initial conditions. This timing design effectively isolates the reset process from the light signal acquisition stage, avoiding reset noise interference with the exposure process, while ensuring the accuracy of signal sampling during exposure.

[0106] In this embodiment, the high-gain active pixel circuit further includes a third branch, which is coupled between the first terminal of the exposure sampling circuit 208 and the output terminal of the amplifier circuit 202. The first terminal of the exposure sampling circuit 208 is coupled to the output terminal of the amplifier circuit 202, and the second terminal of the exposure sampling circuit 208 is coupled to a ground terminal; the exposure sampling circuit 208 is configured to store voltage information input to the amplifier circuit 202.

[0107] In this embodiment, a third switch 404 is disposed on a third branch. The third switch 404 is configured to be in a closed state between a first time point and a second time point, during which the amplifier circuit 202 resets the exposure sampling circuit 208 via the third branch. The third switch 404 is also configured to be disconnected when the change in the output voltage of the amplifier circuit 202 reaches a second preset range from the sixth time point while it is in the closed state. The sixth time point occurs after the fifth time point, and the voltage in the second preset range is greater than the voltage in the first preset range. The sixth time point is the moment when the third switch 404 switches from the closed state to the open state.

[0108] The first terminal of the third switch 404 is coupled to the output terminal of the amplifier circuit 202. That is, when the amplifier circuit 202 is a common-source amplifier, the first terminal of the third switch 404 is coupled to the drain of the first N-type metal-oxide-semiconductor transistor MN1; when the amplifier circuit 202 is a common-source cascode amplifier, the first terminal of the third switch 404 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2.

[0109] In this embodiment, the pixel circuit achieves high-precision acquisition and processing of light signals by introducing an exposure sampling circuit, a third branch, and a third switch. The third switch is closed between the first and second time points to reset the exposure sampling circuit via the amplifier circuit. Subsequently, at the sixth time point (after illumination ends), the third switch is opened based on the output voltage change, ensuring complete recording of signal changes generated by illumination. By separating the voltage ranges of reset sampling and exposure sampling (the second preset range > the first preset range), reset noise and real light signals are effectively distinguished, significantly improving the signal-to-noise ratio. Simultaneously, the illumination timing is strictly matched (sampling continues until the sixth time point after illumination ends), completely capturing voltage changes during exposure and avoiding signal loss.

[0110] In this embodiment, the exposure sampling circuit 208 includes a fifth P-type metal-oxide-semiconductor transistor MP5 and an exposure sampling capacitor 2081. The first terminal of the exposure sampling capacitor 2081 serves as the first terminal of the exposure sampling circuit 208, and the second terminal of the exposure sampling capacitor 2081 serves as the second terminal of the exposure sampling circuit 208.

[0111] The source of the fifth P-type metal-oxide-semiconductor transistor MP5 is coupled to the power supply terminal, the drain of the fifth P-type metal-oxide-semiconductor transistor MP5 is coupled to the first terminal of the exposure sampling capacitor 2081 and the second terminal of the third switch 404, the first terminal of the exposure sampling capacitor 2081 is coupled to the second terminal of the third switch 404, and the second terminal of the exposure sampling capacitor 2081 is coupled to the ground terminal.

[0112] In this embodiment, the pixel circuit uses an exposure sampling capacitor as the core component of the exposure sampling circuit. Through its structure—with its first terminal connected to the output of the amplifier circuit and its second terminal grounded—high-precision optical signal acquisition is achieved. The exposure sampling capacitor can accurately record the voltage changes generated by the optical signal during the exposure phase and maintain signal integrity during the readout phase. Its collaborative work with the reset sampling capacitor enables dual sampling for both reset and exposure. Furthermore, by strictly controlling the sampling period of the exposure sampling capacitor to occur after illumination (the sixth time point), all photogenerated charges are ensured to be completely captured.

[0113] In this embodiment, starting from the fourth time point, the voltage at the second terminal of the fourth capacitor C4 rises from the first voltage to the second voltage, until starting from the seventh time point, the voltage at the second terminal of the fourth capacitor C4 drops from the second voltage back to the first voltage; wherein, the seventh time point occurs after the sixth time point. The seventh time point is the moment when the voltage at the second terminal of the fourth capacitor begins to decrease from the second voltage.

[0114] In this embodiment, the pixel circuit achieves dynamic optimization control of the photosensitive circuit by precisely controlling the voltage modulation timing of the fourth capacitor (from the fourth time point to the seventh time point). During the exposure phase (starting from the fourth time point), the voltage of the fourth capacitor is increased from the first voltage to the second voltage, enhancing the charge collection efficiency of the photosensitive circuit. After the signal readout phase ends (at the seventh time point, i.e., after the sixth time point), the voltage is restored to the first voltage to prepare for the next exposure. This timing-matched voltage modulation has several advantages. First, the high voltage (second voltage) during exposure can expand the full-well capacity of the photosensitive node, improving the pixel dynamic range. Second, the voltage rise and fall are strictly synchronized with the exposure / readout timing to avoid signal interference. Third, capacitive coupling enables DC-free potential adjustment, improving performance while maintaining low power consumption.

[0115] In this embodiment of the application, after the seventh time point, exposure information is obtained based on the voltage information stored in the exposure sampling circuit 208 and the voltage information stored in the reset sampling circuit 207.

[0116] In this embodiment, the pixel circuit achieves high-precision photoelectric signal extraction by comparing the voltage information stored in the exposure sampling capacitor and the reset sampling capacitor after the seventh time point.

[0117] In this embodiment, the output circuit 209 includes: a fourth N-type metal-oxide-semiconductor transistor MN4, a fifth N-type metal-oxide-semiconductor transistor MN5, a sixth N-type metal-oxide-semiconductor transistor MN6, and a seventh N-type metal-oxide-semiconductor transistor MN7.

[0118] The drain of the fourth N-type metal-oxide-semiconductor transistor MN4 is coupled to the power supply terminal, and the gate of the fourth N-type metal-oxide-semiconductor transistor MN4 is coupled to the output terminal of the amplifier circuit 202. The source of the fourth N-type metal-oxide-semiconductor transistor MN4 is coupled to the drain of the fifth N-type metal-oxide-semiconductor transistor MN5, the gate of the fifth N-type metal-oxide-semiconductor transistor MN5 is used to receive the row selection signal, and the source of the fifth N-type metal-oxide-semiconductor transistor MN5 is coupled to the negative output terminal.

[0119] When the amplifier circuit 202 is a common-source amplifier, the gate of the fourth N-type metal-oxide-semiconductor transistor MN4 is coupled to the drain of the first N-type metal-oxide-semiconductor transistor MN1; when the amplifier circuit 202 is a common-source cascode amplifier, the gate of the fourth N-type metal-oxide-semiconductor transistor MN4 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2.

[0120] The drain of the sixth N-type metal-oxide-semiconductor transistor MN6 is coupled to the power supply terminal, and the gate of the sixth N-type metal-oxide-semiconductor transistor MN6 is coupled to the output terminal of the amplifier circuit 202. The source of the sixth N-type metal-oxide-semiconductor transistor MN6 is coupled to the drain of the seventh N-type metal-oxide-semiconductor transistor MN7, the gate of the seventh N-type metal-oxide-semiconductor transistor MN7 is used to receive the row selection signal, and the source of the seventh N-type metal-oxide-semiconductor transistor MN7 is coupled to the positive output terminal.

[0121] When the amplifier circuit 202 is a common-source amplifier, the gate of the sixth N-type metal-oxide-semiconductor transistor MN6 is coupled to the drain of the first N-type metal-oxide-semiconductor transistor MN1; when the amplifier circuit 202 is a common-source cascode amplifier, the gate of the sixth N-type metal-oxide-semiconductor transistor MN6 is coupled to the drain of the second N-type metal-oxide-semiconductor transistor MN2.

[0122] The operation of high-gain active pixel circuits is explained in more detail below. Based on Figure 6 ,like Figure 7 The diagram shown is a timing diagram of a high-gain active pixel circuit provided in an embodiment of this application.

[0123] like Figure 7 As shown, when C1=C2=C4=C and C3=nC, the voltage of the voltage regulation circuit coupled to the second terminal of the fourth capacitor C4 is based on... Figure 7 The operating timing shown provides the voltage signal.

[0124] First, at the first time point T1, the first switch 402, the second switch 403, and the third switch 404 are closed, putting the amplifier circuit 202 in a reset state. Then, at the second time point T2, the first switch 402 is opened, ending the reset of the amplifier circuit 202. After the output of the amplifier circuit 202 stabilizes, the second switch 403 is opened at the third time point T3 to save the reset voltage of the amplifier circuit 202 and the influence voltage introduced by the first switch 402 to the reset sampling capacitor 2071.

[0125] At time point T4, following time point T3, the LED is turned on, and simultaneously, the voltage (Vsub) of the voltage regulation circuit coupled to the second terminal of the fourth capacitor C4 is raised from 0 to the common-mode voltage. After the LED has been exposed for a period of time, at time point T5, the LED is turned off to stop exposure. After waiting for the amplifier circuit 202 to stabilize for a period of time, at time point T6, the third switch 404 is disconnected, and the exposure result is saved to the exposure sampling capacitor 2081. Then, at time point T7, the voltage of the voltage regulation circuit coupled to the second terminal of the fourth capacitor C4 is reduced from the common-mode voltage to 0.

[0126] It should be noted that at this point, the tenth capacitor C10 is the ground capacitance of the voltage regulation circuit coupled to the second terminal of the fourth capacitor C4; the sixth capacitor C6 is the ground capacitance of the photosensitive circuit 201; the eighth capacitor C8 is the ground capacitance of the output terminal of the amplifier circuit 202; and the ninth capacitor C9 is the capacitance between the output terminal of the amplifier circuit 202 and the voltage regulation circuit. None of these capacitors will affect the output of the amplifier circuit 202. The fifth capacitor C5 is equivalent to the feedback capacitor of the amplifier circuit 202, and can still be equivalent to a smaller capacitance value with a larger one, ensuring low noise and high sensitivity of the pixels.

[0127] Finally, the voltage change of the voltage regulation circuit at the start of exposure (i.e., the reduction of the common-mode voltage) can be understood as the voltage regulation circuit injecting charge into the photosensitive circuit 201 through the seventh capacitor C7. The amount of charge is Vsub × C ÷ (3 + n). Therefore, after exposure begins, the photosensitive current needs to remove the injected charge before returning to the reset state. Since the capacitance C14 of the seventh capacitor C7 is equal to the capacitance C12 of the fifth capacitor C5, the charge removed by the photosensitive current to restore the reset state can theoretically cause a voltage change Vsub in the output of the amplifier circuit 202. The entire process can be equivalent to: reducing the pixel exposure value by Vsub through the voltage change of the voltage regulation circuit. It can be seen that compared to the voltage regulation circuit's normally grounded operation, this operation can increase the pixel dynamic range by Vsub. The voltage Vsub can be controlled by additional circuitry to achieve a large control range, thereby greatly improving the pixel dynamic range.

[0128] This application also provides an image sensor, including a light source and a pixel array, the pixel array including multiple such... Figure 4 The high-gain active pixel circuit shown, or Figure 6 The high-gain active pixel circuit shown is illustrated. A light source is used to provide illumination to the high-gain active pixel circuit in the pixel array. Since the image sensor in the embodiments of this application includes the aforementioned high-gain active pixel circuit, the technical effects it achieves can also be referred to in the embodiments of the aforementioned high-gain active pixel circuit; therefore, the embodiments of this application will not be repeated here.

[0129] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application.

Claims

1. A high-gain active pixel circuit, characterized in that, include: A photosensitive circuit, wherein a first terminal of the photosensitive circuit is coupled to a ground terminal and is configured to generate an exposure current based on the intensity of the received light. A feedback circuit, wherein a first terminal of the feedback circuit is coupled to a second terminal of the photosensitive circuit, is configured to: input the exposure current and clamp the voltage at the second terminal of the photosensitive circuit; An amplifier circuit, wherein the output terminal of the amplifier circuit is coupled to the second terminal of the feedback circuit and the input terminal of the amplifier circuit is coupled to the second terminal of the photosensitive circuit, is configured to clamp the voltage at the second terminal of the photosensitive circuit to a preset voltage through the feedback circuit. The feedback circuit includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first terminal of the first capacitor serves as the first terminal of the feedback circuit. The first terminal of the second capacitor is coupled to the second terminal of the first capacitor, and the second terminal of the second capacitor serves as the second terminal of the feedback circuit. The first terminal of the third capacitor is coupled to the second terminal of the first capacitor, and the second terminal of the third capacitor is coupled to a ground terminal. The first terminal of the fourth capacitor is coupled to the second terminal of the first capacitor, and the second terminal of the fourth capacitor is used to couple to a voltage regulation circuit and is configured to receive an applied voltage to bring the second terminal of the fourth capacitor to a corresponding potential.

2. The high-gain active pixel circuit according to claim 1, characterized in that, The capacitance values ​​of the first capacitor, the second capacitor, and the fourth capacitor are all first capacitance values, and the capacitance value of the third capacitor is a second capacitance value, wherein the second capacitance value is greater than the first capacitance value.

3. The high-gain active pixel circuit according to claim 1 or 2, characterized in that, The high-gain active pixel circuit also includes: The first branch is coupled between the second terminal of the photosensitive circuit and the output terminal of the amplifier circuit; A first switch, located on the first branch, is configured to be in a closed state between a first time point and a second time point, resetting the amplification circuit and the photosensitive circuit through the first branch. The first time point is the start time of the operation of the high-gain active pixel circuit, and the second time point is the end time of the reset of the amplification circuit and the photosensitive circuit.

4. The high-gain active pixel circuit according to claim 3, characterized in that, The high-gain active pixel circuit also includes: A reset sampling circuit, wherein a first terminal of the reset sampling circuit is coupled to the output terminal of the amplifier circuit, and a second terminal of the reset sampling circuit is coupled to the ground terminal; configured to store voltage information input to the amplifier circuit; The second branch is coupled between the first terminal of the reset sampling circuit and the output terminal of the amplifier circuit; The second switch, located on the second branch, is configured to: be in a closed state between the first time point and the second time point, wherein the amplifier circuit resets the reset sampling circuit through the second branch; and is further configured to: disconnect the second switch when the change in the output voltage of the amplifier circuit is within a first preset range from the third time point when it is in the closed state; wherein the third time point is the moment when the second switch switches from the closed state to the open state.

5. The high-gain active pixel circuit according to claim 4, characterized in that, The reset sampling circuit includes: A reset sampling capacitor is provided, wherein the first end of the reset sampling capacitor serves as the first end of the reset sampling circuit, and the second end of the reset sampling capacitor serves as the second end of the reset sampling circuit.

6. The high-gain active pixel circuit according to claim 4 or 5, characterized in that, The illumination is generated by the light source at the fourth time point and stops at the fifth time point; the fourth time point is the start time of the operation of the light source, and the fifth time point is the end time of the operation of the light source. The fourth time point occurs after the third time point.

7. The high-gain active pixel circuit according to claim 6, characterized in that, The high-gain active pixel circuit also includes: An exposure sampling circuit, wherein a first terminal of the exposure sampling circuit is coupled to the output terminal of the amplifier circuit, and a second terminal of the exposure sampling circuit is coupled to the ground terminal; configured to store voltage information input to the amplifier circuit; The third branch is coupled between the first terminal of the exposure sampling circuit and the output terminal of the amplifier circuit; A third switch, located on the third branch, is configured to: be in a closed state between the first time point and the second time point, during which the amplification circuit resets the exposure sampling circuit through the third branch; and is further configured to: disconnect the third switch when the change in the output voltage of the amplification circuit is within a second preset range from the sixth time point when it is in the closed state; the sixth time point is the moment when the third switch switches from the closed state to the open state. The sixth time point occurs after the fifth time point, and the voltage in the second preset range is greater than the voltage in the first preset range.

8. The high-gain active pixel circuit according to claim 7, characterized in that, The exposure sampling circuit includes: An exposure sampling capacitor is provided, wherein the first end of the exposure sampling capacitor serves as the first end of the exposure sampling circuit, and the second end of the exposure sampling capacitor serves as the second end of the exposure sampling circuit.

9. The high-gain active pixel circuit according to claim 7 or 8, characterized in that, Starting from the fourth time point, the voltage at the second terminal of the fourth capacitor rises from the first voltage to the second voltage, until starting from the seventh time point, the voltage at the second terminal of the fourth capacitor drops from the second voltage back to the first voltage; the seventh time point is the moment when the voltage at the second terminal of the fourth capacitor begins to drop from the second voltage. The seventh time point occurs after the sixth time point.

10. The high-gain active pixel circuit according to claim 9, characterized in that, After the seventh time point, exposure information is obtained based on the voltage information stored in the exposure sampling circuit and the voltage information stored in the reset sampling circuit.

11. The high-gain active pixel circuit according to claim 1, characterized in that, The photosensitive circuit includes a photodiode, wherein the anode of the photodiode serves as the first terminal of the photosensitive circuit, and the cathode of the photodiode serves as the second terminal of the photosensitive circuit.

12. The high-gain active pixel circuit according to claim 1, characterized in that, The amplifier circuit includes: The first P-type metal-oxide-semiconductor transistor has its source coupled to a power supply terminal. The first N-type metal-oxide-semiconductor transistor has its drain as the output terminal of the amplifier circuit and is coupled to the drain of the first P-type metal-oxide-semiconductor transistor; the source of the first N-type metal-oxide-semiconductor transistor is coupled to the ground terminal; and the gate of the first N-type metal-oxide-semiconductor transistor serves as the input terminal of the amplifier circuit.

13. The high-gain active pixel circuit according to claim 1, characterized in that, The amplifier circuit includes: The source of the second P-type metal-oxide-semiconductor transistor is coupled to the power supply terminal. The source of the third P-type metal-oxide-semiconductor transistor is coupled to the drain of the second P-type metal-oxide-semiconductor transistor. The drain of the second N-type metal-oxide-semiconductor transistor serves as the output terminal of the amplifier circuit and is coupled to the drain of the third P-type metal-oxide-semiconductor transistor. The third N-type metal-oxide-semiconductor transistor has its drain coupled to the source of the second N-type metal-oxide-semiconductor transistor; the source of the third N-type metal-oxide-semiconductor transistor is coupled to the ground terminal; and the gate of the third N-type metal-oxide-semiconductor transistor serves as the input terminal of the amplifier circuit.

14. An image sensor, characterized in that, include: light source; A pixel array comprising a plurality of high-gain active pixel circuits as described in any one of claims 1-13.

Images