Multi-layer interconnection circuit board processing method, system, equipment, program product and workpiece

Abstract

The invention relates to a multi-layer interconnection circuit board processing method and system, computer equipment, a computer program product and a workpiece. The method comprises the steps that line structure information of the multi-layer interconnection circuit board is acquired, the line structure information comprises line plate splicing information and multiple pieces of line plate processing information, and at least one piece of line plate processing information comprises target interconnection structure information; laser processing equipment is controlled, a plurality of circuit board blocks are processed on the basis of the circuit board block processing information, at least one circuit board block is provided with a multi-layer interconnection structure, and the multi-layer interconnection structure is obtained through one-time forming on the basis of the target interconnection structure information; and controlling a splicing device, and splicing the circuit board blocks into a multi-layer interconnection circuit board based on the circuit board block splicing information. The method can improve the reliability of the circuit board.

Description

Technical Field

[0001] The present application relates to the technical field of circuit board processing, and particularly to a method, a system, a computer device, a computer program product and a workpiece for processing a multi-layer interconnected circuit board. Background Art

[0002] The multi-layer interconnected structure is a key technology for realizing electrical connection between different circuit layers in a circuit board. Through precise conductive vias and circuit designs, the multi-layer interconnected structure ensures efficient signal transmission between different layers and is a core element in modern high-density circuit board design.

[0003] In traditional technologies, multi-layer circuit boards are mainly processed by layer-by-layer stacking and alignment processing. That is, the inner-layer circuits and outer-layer circuits are processed layer by layer in the direction from the inside to the outside close to the core board. However, this method highly depends on the accuracy and precision during alignment processing. As the number of circuit board layers increases, the probability of alignment deviation is higher. At the same time, as the interconnect density increases, the size of the micro-hole structure continuously decreases. The smaller the size of the micro-hole structure, the higher the alignment accuracy requirement and the easier it is to generate alignment deviation. And any slight alignment deviation may lead to short circuits or open circuits, seriously affecting the reliability of the circuit board. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a method, a system, a computer device, a computer program product and a workpiece for processing a multi-layer interconnected circuit board that can improve the reliability of the circuit board.

[0005] In a first aspect, the present application provides a method for processing a multi-layer interconnected circuit board, the method comprising:

[0006] Obtaining the circuit structure information of the multi-layer interconnected circuit board, wherein the circuit structure information includes circuit board block splicing information and multiple circuit board block processing information, and at least one circuit board block processing information contains target interconnect structure information;

[0007] Controlling a laser processing device to process multiple circuit board blocks based on each circuit board block processing information, wherein at least one circuit board block has a multi-layer interconnected structure, and the multi-layer interconnected structure is obtained by one-time forming based on the target interconnect structure information;

[0008] Controlling a splicing device to splice each circuit board block into a multi-layer interconnected circuit board based on the circuit board block splicing information.

[0009] In one of the embodiments, before obtaining the circuit structure information of the multi-layer interconnected circuit board, it further includes:

[0010] Obtaining the overall circuit structure information of the multi-layer interconnected circuit board, wherein the overall circuit structure information includes the initial interconnect structure information of the multi-layer interconnected structure.

[0011] Based on the initial interconnection structure information, the overall information of the circuit structure is divided into circuit board splicing information and multiple circuit board processing information, wherein at least one piece of circuit board processing information contains target interconnection structure information, and the target interconnection structure information contains all or part of the information of the initial interconnection structure information.

[0012] In one embodiment, the initial interconnection structure information contains the layer number information of the initial interconnection structure; based on the initial interconnection structure information, dividing the overall information of the circuit structure into circuit board splicing information and multiple circuit board processing information includes:

[0013] In the case where it is determined, based on the layer number information of the initial interconnection structure, that the layer number of the initial interconnection structure exceeds a preset layer number threshold, the initial interconnection structure information is divided into multiple target interconnection structure information, wherein the target interconnection structure information contains the information of some layers in the initial interconnection structure;

[0014] Based on each piece of target interconnection structure information, the overall information of the circuit structure is divided into circuit board splicing information and multiple circuit board processing information, so that each piece of target interconnection structure information is respectively divided into different circuit board processing information.

[0015] In one embodiment, the circuit board processing information includes sub-circuit layer information and target interconnection structure information; in the process of controlling a laser processing device to process a circuit board based on the circuit board processing information, the method further includes:

[0016] Controlling a splicing device to fabricate an intermediate board according to the sub-circuit layer information;

[0017] Controlling a laser processing device to process a multi-layer interconnection structure on the intermediate board based on the target interconnection structure information to obtain a circuit board.

[0018] In one embodiment, the sub-circuit layer information includes conductive circuit information; before controlling a splicing device to fabricate an intermediate board according to the sub-circuit layer information, the method further includes:

[0019] Controlling a conductive circuit processing device to process conductive circuits on a plurality of insulating substrates based on the conductive circuit information to obtain a plurality of sub-circuit layers.

[0020] In one embodiment, the multi-layer interconnect circuit board includes a multi-layer interconnect structure; the multi-layer interconnect structure includes a first interconnect structure and a second interconnect structure. The first interconnect structure includes a first opening in a first direction and a second opening in a second direction. The second interconnect structure includes a third opening in the first direction and a fourth opening in the second direction. The first opening and the third opening are located on different layers, and the second opening and the fourth opening are located on different layers; the target interconnect structure information includes the target interconnect structure information of the first interconnect structure and the target interconnect structure information of the second interconnect structure;

[0021] In the process of controlling the splicing device to fabricate the intermediate plate according to the sub-circuit layer information, the method further includes:

[0022] Controlling the splicing device to stack the sub-circuit layers corresponding to the first interconnect structure to form an initial plate;

[0023] Controlling the laser processing device to process the first interconnect structure on the initial plate based on the target interconnect structure information of the first interconnect structure;

[0024] Controlling the splicing device to laminate the initial plate processed with the first interconnect structure with other sub-circuit layers to form an intermediate plate;

[0025] Controlling the laser processing device to process the multi-layer interconnect structure on the intermediate plate based on the target interconnect structure information to obtain a circuit plate, including:

[0026] Controlling the laser processing device to process the second interconnect structure on the intermediate plate based on the target interconnect structure information of the second interconnect structure to obtain a circuit plate.

[0027] In one embodiment, controlling the splicing device to splice the circuit plates into a multi-layer interconnect circuit board based on the circuit plate splicing information, includes:

[0028] Performing a direction transformation on at least one circuit plate based on the circuit plate splicing information;

[0029] Splicing the circuit plates after the direction transformation into a multi-layer interconnect circuit board.

[0030] In one embodiment, controlling the laser processing device to process a plurality of circuit plates based on the processing information of each circuit plate, includes:

[0031] Controlling the laser processing device to emit a high-energy short-pulse laser beam, wherein the laser processing device is configured to control the high-energy short-pulse laser beam to form a multi-layer interconnect structure on the circuit plate at one time based on the target interconnect structure information.

[0032] In one embodiment, the high-energy short-pulse laser beam is a Gaussian laser beam or a flat-top laser beam.

[0033] In one embodiment, when the high-energy short-pulse laser beam is a Gaussian laser beam, the laser processing device further includes a beam shaping component, which is deployed on the optical path of the Gaussian laser beam and is used to shape the Gaussian laser beam into a flat-top laser beam.

[0034] In one embodiment, the wavelength of the short-pulse laser beam is in the green light band to the infrared band.

[0035] In a second aspect, the present application further provides a multi-layer interconnected circuit board processing system, which includes a controller, a laser processing device, and a splicing device, wherein:

[0036] The laser processing device is configured to process circuit board segments;

[0037] The splicing device is configured to splice the circuit board segments into a multi-layer interconnected circuit board;

[0038] The controller is configured to:

[0039] Obtain the circuit structure information of the multi-layer interconnected circuit board, where the circuit structure information includes the processing information of multiple circuit board segments, and at least one circuit board segment processing information contains the target interconnection structure information;

[0040] Control the laser processing device to process multiple circuit board segments based on the processing information of each circuit board segment, where at least one circuit board segment has a multi-layer interconnected structure, and the multi-layer interconnected structure is obtained by one-time forming based on the target interconnection structure information;

[0041] Control the splicing device to splice the circuit board segments into a multi-layer interconnected circuit board based on the circuit board segment splicing information.

[0042] In a third aspect, the present application further provides a computer device, which includes a memory and a processor. When the processor executes the computer program, the following steps are implemented:

[0043] Obtain the circuit structure information of the multi-layer interconnected circuit board, where the circuit structure information includes the circuit board segment splicing information and the processing information of multiple circuit board segments, and at least one circuit board segment processing information contains the target interconnection structure information;

[0044] Control the laser processing device to process multiple circuit board segments based on the processing information of each circuit board segment, where at least one circuit board segment has a multi-layer interconnected structure, and the multi-layer interconnected structure is obtained by one-time forming based on the target interconnection structure information;

[0045] Control the splicing device to splice the circuit board segments into a multi-layer interconnected circuit board based on the circuit board segment splicing information.

[0046] Fourthly, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0047] Obtain the circuit structure information of a multi-layer interconnected circuit board, where the circuit structure information includes circuit board splicing information and multiple circuit board processing information, and at least one circuit board processing information contains target interconnection structure information;

[0048] Control a laser processing device to process multiple circuit boards based on each circuit board processing information, where at least one circuit board has a multi-layer interconnection structure, and the multi-layer interconnection structure is formed in one step based on the target interconnection structure information;

[0049] Control a splicing device to splice each circuit board into a multi-layer interconnected circuit board based on the circuit board splicing information.

[0050] Fifthly, the present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the following steps are implemented:

[0051] Obtain the circuit structure information of a multi-layer interconnected circuit board, where the circuit structure information includes circuit board splicing information and multiple circuit board processing information, and at least one circuit board processing information contains target interconnection structure information;

[0052] Control a laser processing device to process multiple circuit boards based on each circuit board processing information, where at least one circuit board has a multi-layer interconnection structure, and the multi-layer interconnection structure is formed in one step based on the target interconnection structure information;

[0053] Control a splicing device to splice each circuit board into a multi-layer interconnected circuit board based on the circuit board splicing information.

[0054] Sixthly, the present application also provides a workpiece processed by the method as above.

[0055] The above-mentioned multi-layer interconnection circuit board processing method, system, computer equipment, computer program product and workpiece first obtain the circuit structure information of the multi-layer interconnection circuit board, wherein the circuit structure information includes circuit block splicing information and multiple circuit block processing information, and at least one circuit block processing information contains target interconnection structure information, and then control the laser processing equipment to process multiple circuit blocks based on the processing information of each circuit block, wherein at least one circuit block has a multi-layer interconnection structure, and the multi-layer interconnection structure is formed in one time based on the target interconnection structure information, and then control the splicing device to splice each circuit block into a multi-layer interconnection circuit board based on the circuit block splicing information. In this way, since the interconnection structure in each circuit block is formed in one time, the number of alignment operations of the interconnection structure can be effectively reduced, and for interconnection structures with small size and easy to produce alignment deviation, the alignment operation can be reduced by forming in one time, thereby effectively reducing the probability of generating alignment deviation, overcoming the problem of reduced alignment accuracy caused by increasing the number of layers and reducing the size of microholes in the layer-by-layer stacking process, and improving the reliability and processing efficiency of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0057] Figure 1 A schematic diagram of a process for processing a multi-layer interconnection circuit board according to an embodiment;

[0058] Figure 2 A schematic diagram of the structure of a multi-layer interconnection circuit board in one embodiment;

[0059] Figure 3 A schematic diagram of the structure of a circuit board in an embodiment;

[0060] Figure 4 It is a schematic diagram of the structure of a circuit block in another embodiment;

[0061] Figure 5 A schematic diagram of the structure of a multi-layer interconnection circuit board in another embodiment;

[0062] Figure 6 A schematic diagram of a scenario in which a direction of a line plate is changed in one embodiment;

[0063] Figure 7 A distribution diagram of the light spot shape and the drilling effect of a Gaussian laser beam in one embodiment;

[0064] Figure 8 In an embodiment, Figure 7 the spot pattern distribution and drilling effect diagram after shaping the Gaussian laser beam in

[0065] Figure 9 is the structural schematic diagram of a multi-layer interconnect circuit board processing system in an embodiment;

[0066] Figure 10 is the internal structure diagram of a computer device in an embodiment. Specific implementation manners

[0067] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0068] In an exemplary embodiment, as Figure 1 shown, a method for processing a multi-layer interconnect circuit board is provided. In this embodiment, the execution subject of this method is taken as a terminal for example. Among them, the terminal can be a multi-layer interconnect circuit board processing device, or other terminals capable of controlling the multi-layer interconnect circuit board processing device, such as various personal computers, notebook computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices, etc. The multi-layer interconnect circuit board processing device at least includes a laser processing device, and may also include a splicing device, a robot, etc. The splicing device may refer to a device capable of splicing circuit board blocks into a whole, such as a laminator, which can press multiple circuit boards into a whole through high temperature and high pressure. The Internet of Things device can be a smart speaker, a smart TV, a smart air conditioner, a smart vehicle-mounted device, a projection device, etc. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, etc. The head-mounted device can be a virtual reality (VR) device, an augmented reality (AR) device, a smart glasses, etc. It can be understood that the execution subject of this method can also be a server, or a system including a terminal and a server, and is realized through the interaction between the terminal and the server.

[0069] In this embodiment, the method includes the following steps S10-S30. Among them:

[0070] Step S10, obtaining the circuit structure information of the multi-layer interconnect circuit board, where the circuit structure information includes circuit board block splicing information and multiple circuit board block processing information, and at least one circuit board block processing information contains target interconnect structure information.

[0071] Among them, a multi-layer interconnection circuit board may refer to a circuit board in which multiple circuit layers are electrically connected through an interconnection structure. Among them, the interconnection structure may include at least one of conductive vias and conductive traces, etc. The conductive vias may include at least one of conductive through vias, conductive blind vias, and conductive buried vias, etc. Each circuit layer in the multi-layer interconnection circuit board may include an insulating substrate and an interconnection structure. The insulating substrate is composed of an insulating material, and the interconnection structure is composed of a conductive material. Among them, the conductive material may include at least one of conductive metals and conductive compounds, etc. The insulating material may include at least one of resins and glass fibers, etc. By stacking and laminating multiple circuit layers to form an overall structure, high-density and high-performance signal transmission and electrical connection can be achieved.

[0072] In some feasible embodiments, the conductive metal may be copper.

[0073] In some feasible embodiments, the conductive via may be obtained by processing a hole structure filled with a conductive material. Among them, the hole structure may refer to an opening that connects at least two circuit layers. The hole structure may include at least one of through holes, blind holes, and buried holes, etc. For example, as Figure 2 shown, Figure 2 the middle third layer in it may be the core layer of the board. The interconnection structure may include a conductive blind via 201, a conductive through via 202, and a conductive buried via 203. It can be understood that the application does not limit the application of the hole structure. In some embodiments, the hole structure can also be applied to the pins for inserting electronic components or chips to mount the electronic components or chips on the electronic circuit board; in some other embodiments, when the size of the hole structure is large, it can also be used to bury electronic components or chips.

[0074] The number of layers of the interconnection structure can be used to characterize the number of circuit layers where the interconnection structure is located. The interconnection structure includes a single-layer interconnection structure and a multi-layer interconnection structure. Among them, the single-layer interconnection structure may refer to an interconnection structure that is only located in one circuit layer but can connect the circuit layer where it is located and its adjacent circuit layer; the multi-layer interconnection structure may refer to an interconnection structure that is itself located in multiple circuit layers and can connect the multiple circuit layers where it is located and its adjacent circuit layers. For example, as Figure 2 shown, Figure 2 the blind via 201 in the upper left corner in it is only located in the first circuit layer but can connect the first and second circuit layers. Therefore, this blind via 201 belongs to the single-layer interconnection structure, while Figure 2 the other interconnection structures in it are all located in multiple circuit layers and can connect the multiple circuit layers where they are located and their adjacent circuit layers. Therefore, they belong to the multi-layer interconnection structure.

[0075] The target interconnect structure information may refer to the interconnect structure information corresponding to a multi-layer interconnect structure. That is, in the case where a multi-layer interconnect structure is included in the multi-layer interconnect circuit board to be processed, the multi-layer interconnect structure can be divided into one circuit board section, so that the interconnect structure information of the multi-layer interconnect structure is divided into the circuit board section processing information corresponding to the same circuit board section, so as to process the multi-layer interconnect structure by one-time forming without the need for layer-by-layer alignment and stacking.

[0076] In some feasible embodiments, the multi-layer interconnect structure may include a high aspect ratio interconnect structure. The high aspect ratio interconnect structure may refer to a multi-layer interconnect structure with an aspect ratio greater than a preset aspect ratio threshold. The non-high aspect ratio interconnect structure may refer to an interconnect structure with an aspect ratio not greater than the preset aspect ratio threshold. In the case where a high aspect ratio interconnect structure is included in the multi-layer interconnect circuit board to be processed, the high aspect ratio interconnect structure can be divided into multiple non-high aspect ratio interconnect structures, and each non-high aspect ratio interconnect structure is divided into different circuit board sections. After each non-high aspect ratio interconnect structure is formed by one-time forming, they are then spliced to form a high aspect ratio interconnect structure. In this way, compared with the layer-by-layer alignment processing method, the number of stacking alignment processes is less and the processing accuracy is higher. At the same time, dividing the high aspect ratio interconnect structure into multiple non-high aspect ratio interconnect structures can overcome the technical defect that the one-time forming processing of the high aspect ratio interconnect structure is difficult and may instead lead to a reduction in processing quality, thereby obtaining a multi-layer interconnect circuit board with higher accuracy and higher quality.

[0077] It can be understood that the non-high aspect ratio interconnect structures formed by dividing the high aspect ratio interconnect structure may include single-layer interconnect structures and multi-layer interconnect structures. In some feasible embodiments, at least some of the non-high aspect ratio interconnect structures are multi-layer interconnect structures. The non-high aspect ratio interconnect structure being a multi-layer interconnect structure can reduce the alignment processing steps, thereby improving the processing accuracy. However, in the case of a more complex structure, it is allowed that some of the non-high aspect ratio interconnect structures are single-layer interconnect structures to reduce the processing difficulty and improve the flexibility of dividing the high aspect ratio interconnect structure into non-high aspect ratio interconnect structures.

[0078] The circuit structure information may refer to the information required in the manufacturing process of the multi-layer interconnect circuit board, and may include at least one of the geometric structure, area division, electrical connection relationship, material properties, and manufacturing process parameters of the multi-layer interconnect circuit board.

[0079] The circuit board section may refer to a circuit board that contains all the circuit structures of a partial area of the multi-layer interconnect circuit board. At least one circuit board section has an interconnect structure. The interconnect structure in at least one circuit board section is a multi-layer interconnect structure. The division of the circuit board section can be determined according to the actual situation of the circuit structure of the multi-layer interconnect circuit board, and this embodiment does not limit this.

[0080] Among them, the interconnect structure in the circuit board segment can be a conductive via. When dividing the circuit board segment, at least one opening of the conductive via in the circuit board segment should be located on the surface of the circuit board segment, so as to facilitate the laser to drill from the surface of the circuit board segment into the interior of the circuit board segment, thereby realizing the one-time forming of the conductive via.

[0081] In some feasible embodiments, the multi-layer interconnect circuit board can be divided according to the circuit layers, and the total number of layers of the multiple circuit board segments obtained after division is equal to the number of layers of the multi-layer interconnect circuit board. In this way, each circuit board segment can include all the circuit structures of multiple adjacent circuit layers in the multi-layer interconnect circuit board. For example, as Figure 3 shown, a five-layer interconnect circuit board is divided into a two-layer circuit board segment 301 and a three-layer circuit board segment 302.

[0082] In the case of dividing the multi-layer interconnect circuit board according to the circuit layers, at least one opening of each conductive via in the multi-layer interconnect circuit board is located on the surface of the circuit board segment.

[0083] In some other feasible embodiments, the multi-layer interconnect circuit board can be divided according to the circuit layers and divided along a direction parallel to the plane where the circuit layers are located. For example, as Figure 4 shown, Figure 4 the part enclosed by the solid line frame in the figure represents a circuit board segment, and the five-layer interconnect circuit board is divided into six circuit board segments. In this way, for a complex circuit board structure with multiple interconnect structures on the same layer, it can be divided and processed more flexibly.

[0084] In this embodiment, the processing process of the multi-layer interconnect circuit board includes the processing process of the circuit board segment and the splicing process of the circuit board segment, that is, first divide a multi-layer interconnect circuit board into multiple circuit board segments, process each circuit board segment separately, and then splice the processed circuit board segments into a whole to obtain the multi-layer interconnect circuit board. Therefore, the circuit structure information at least includes the circuit board segment processing information of each circuit board segment and the circuit board segment splicing information. Among them, the circuit board segment processing information is used to guide the processing process of the circuit board segment, and can include the detailed process parameters and design requirements required for a single circuit board segment during the manufacturing process. For example, the layout of the conductive circuit, the position and size of the through hole, the thickness of the insulating material, the layer alignment accuracy requirements, etc.; the circuit board segment splicing information is used to guide the circuit board segment splicing process, and can include information such as the alignment method, splicing position, splicing accuracy, and electrical connection relationship required for multiple circuit board segments during the splicing process. For example, the relative position between each circuit board segment, the design of the splicing interface, and the electrical performance requirements of the overall structure after splicing.

[0085] Exemplarily, before processing a multi-layer interconnected circuit board, process design can be carried out based on the actual requirements of the multi-layer interconnected circuit board to be processed, and circuit structure information can be generated. The designed circuit structure information is used to process the multi-layer interconnected circuit board. During the process of processing the multi-layer interconnected circuit board, the circuit structure information of the pre-designed multi-layer interconnected circuit board can be directly obtained.

[0086] Step S20: Control a laser processing device to process a plurality of circuit boards based on the processing information of each circuit board. At least one of the circuit boards has a multi-layer interconnected structure, and the multi-layer interconnected structure is formed in one step based on the target interconnected structure information.

[0087] Exemplarily, after obtaining the processing information of each circuit board, the laser processing device can be controlled to process each circuit board respectively based on the processing information of each circuit board.

[0088] In some feasible embodiments, for a circuit board with a multi-layer interconnected structure, the processing information of the circuit board may include the number of circuit layers information, conductive line processing information, and target interconnected structure information; the processing process of the circuit board may include: determining the number of circuit layers corresponding to the circuit board according to the number of circuit layers information, and taking the corresponding number of insulating substrates to the processing platform by manual or controlling a manipulator, a robot, etc.; then, controlling the laser processing device to process conductive lines on each insulating substrate according to the conductive line processing information to obtain sub-circuit layers; then, controlling the splicing device to stack and press the sub-circuit layers with conductive lines processed thereon to form an intermediate board; then, controlling the laser processing device to process hole structures on the intermediate board based on the target interconnected structure information, and controlling the filling device to fill conductive materials into the hole structures to realize the processing of the multi-layer interconnected structure and obtain the circuit board.

[0089] In some other feasible embodiments, during the process of stacking and laminating the sub-circuit layers processed with conductive circuits to form an intermediate plate, the method may further include: according to the circuit plate processing information, taking the first sub-circuit layer manually or by controlling a manipulator, a robot, etc. in the order from the upper layer to the lower layer or from the lower layer to the upper layer, and determining whether the first sub-circuit layer contains a complete interconnection structure. If the first sub-circuit layer contains a complete interconnection structure, controlling a laser processing device to process the complete interconnection structure on the sub-circuit layer according to the interconnection structure information corresponding to the complete interconnection structure, and then taking the next sub-circuit layer manually or by controlling a manipulator, a robot, etc.; if the first sub-circuit layer does not contain a complete interconnection structure, the next sub-circuit layer can be directly taken manually or by controlling a manipulator, a robot, etc.; furthermore, controlling a splicing device to stack and laminate the next sub-circuit layer and the previously taken sub-circuit layer to obtain an initial plate, and determining whether the initial plate contains a complete interconnection structure. If the initial plate contains a complete interconnection structure, controlling a laser processing device to process the interconnection structure on the initial plate according to the interconnection structure information corresponding to the complete interconnection structure, and then returning to execute the step of taking the next sub-circuit layer manually or by controlling a manipulator, a robot, etc.; if the initial plate does not contain a complete interconnection structure, the step of taking the next sub-circuit layer manually or by controlling a manipulator, a robot, etc. can be directly executed until the last sub-circuit layer is stacked and laminated with the previously taken sub-circuit layer to form an intermediate plate.

[0090] Since during the process of processing the interconnection structure, when using a laser to process the hole structure, it is usually necessary to drill holes from the material surface into the material interior or to the other side, through the method of layer-by-layer determination during the layer-by-layer stacking process, the processing of parallel interconnection structures can be achieved, and each interconnection structure is formed in one time without the need to align the interconnection structures. Therefore, it still has a high processing accuracy. For example, assume a circuit plate as Figure 5 shown. Figure 5The third layer of the circuit board in [it] can be the core layer. This circuit board includes a 5-layer interconnect structure 504, as well as 1 layer of conductive blind vias 501, 2 layers of conductive blind vias 503, and 2 layers of conductive buried vias 502 arranged in parallel with the 5-layer interconnect structure 504. When processing this circuit board, the sub-circuit layers can be fabricated sequentially from the lower layer to the upper layer. The sub-circuit layer of the bottommost layer only includes a part of the 5-layer interconnect structure 504 and does not include the complete interconnect structure. Therefore, no treatment is performed, and the next sub-circuit layer is fabricated. That is, an insulating material layer and a conductive material layer are sequentially laminated on the sub-circuit layer of the bottommost layer, and the circuit structure of the next sub-circuit layer is processed on the conductive material layer. It can be determined that in the initial board formed by stacking the bottommost two sub-circuit layers, only a part of the 5-layer interconnect structure 504, a part of the 2 layers of conductive buried vias 502, and the complete interconnect structure are still not included. Further, the next sub-circuit layer is fabricated on the previously fabricated sub-circuit layer to form an initial board. At this time, it can be found that the initial board formed by stacking the bottommost three sub-circuit layers includes a part of the 5-layer interconnect structure 504 and the complete 2 layers of conductive buried vias 502. Therefore, based on the interconnect structure information corresponding to the complete 2 layers of conductive buried vias 502, the 2 layers of conductive buried vias 502 can be processed on this initial board, and then the next layer of the sub-circuit layer is fabricated. This is continued until the initial board includes the topmost sub-circuit layer to form an intermediate board. At this time, the 5-layer interconnect structure 504 is present on this intermediate board, and the 5-layer interconnect structure 504 can be further processed on this intermediate board to obtain a complete circuit board.

[0091] Step S30: Control the splicing device to splice each circuit board into a multi-layer interconnect circuit board based on the circuit board splicing information.

[0092] Exemplarily, after each circuit board is processed, each circuit board can be placed according to the circuit board splicing information manually or by controlling a manipulator, a robot, etc. Then, control the splicing device to press-fit each circuit board so that the surfaces of each circuit board are connected to each other to form a whole, obtaining a multi-layer interconnect circuit board.

[0093] In the above-mentioned multi-layer interconnection circuit board processing method, firstly, the circuit structure information of the multi-layer interconnection circuit board is obtained, wherein the circuit structure information includes circuit block splicing information and multiple circuit block processing information, and at least one circuit block processing information contains target interconnection structure information, and then the laser processing equipment is controlled to process multiple circuit blocks based on the processing information of each circuit block, wherein at least one circuit block has a multi-layer interconnection structure, and the multi-layer interconnection structure is formed in one time based on the target interconnection structure information, and then the splicing device is controlled to splice each circuit block into a multi-layer interconnection circuit board based on the circuit block splicing information. In this way, since the interconnection structure in each circuit block is formed in one time, the number of alignment operations of the interconnection structure can be effectively reduced, and for interconnection structures with small size and easy to produce alignment deviation, the alignment operation can be reduced by forming in one time, thereby effectively reducing the probability of generating alignment deviation, overcoming the problem of decreased alignment accuracy caused by increasing the number of layers and reducing the size of microholes in the layer-by-layer stacking process, and improving the reliability and processing efficiency of the circuit board.

[0094] In an exemplary embodiment, before obtaining the circuit structure information of the multi-layer interconnection circuit board, steps S01-S02 are also included, wherein:

[0095] Step S01, obtaining overall circuit structure information of a multi-layer interconnection circuit board, wherein the overall circuit structure information includes initial interconnection structure information of the multi-layer interconnection structure.

[0096] It should be noted that in the process of stacking and aligning the sub-circuit layers layer by layer, the single-layer interconnect structure can allow a wider range of alignment deviations. Single-layer interconnect structures are usually in the same plane, the interconnect size is relatively large, and a certain process margin is usually reserved during design. Therefore, even if there is a certain deviation in alignment, it will not have a serious impact on the electrical connection. The multi-layer interconnect structure is a three-dimensional structure, which is not only the key to electrical connection, but also plays a mechanical support role to a certain extent. Therefore, there are many restrictions on its size and position. If the alignment deviation is too large, it may not only cause the conductive hole to fail to properly connect to the pad or wire of the target layer, thereby causing the interruption of the electrical connection between the layers, but also may cause the hole wall to be loosely bonded to the interlayer material, reducing the mechanical strength and reliability of the circuit board.

[0097] The overall circuit structure information may refer to the complete design data of the entire multi-layer interconnection circuit board. The multi-layer interconnection circuit board includes an interconnection structure. The initial interconnection structure information may refer to the complete design data of the complete interconnection structure in the multi-layer interconnection circuit board.

[0098] For example, before processing a multi-layer interconnection circuit board, a process design may be performed based on actual requirements of the multi-layer interconnection circuit board to be processed to generate overall circuit structure information.

[0099] Step S02: Based on the initial interconnection structure information, divide the overall circuit structure information into circuit board splicing information and multiple circuit board processing information. Among them, at least one piece of circuit board processing information contains target interconnection structure information, and the target interconnection structure information contains all or part of the information of the initial interconnection structure information.

[0100] Exemplarily, based on the initial interconnection structure information, the structure of a multi-layer interconnection circuit board can be divided. The multi-layer interconnection circuit board is divided into multiple circuit boards. Correspondingly, the overall circuit structure information is divided into corresponding circuit board processing information and circuit board splicing information according to the circuit boards.

[0101] In some feasible embodiments, the overall circuit structure information can be the design drawing of a multi-layer interconnection circuit board, the circuit board processing information can be the design drawing of a circuit board, the initial interconnection structure information can be the position information of the initial interconnection structure, and the circuit board splicing information can be the position information at the junction between a circuit board and an adjacent circuit board. The design drawing of the multi-layer interconnection circuit board can be divided into sub-circuit drawings of multiple circuit boards according to the position information of the initial interconnection structure and a preset division rule, and at the same time, the position at the junction between each circuit board and an adjacent circuit board can be determined.

[0102] Among them, the preset division rule can be determined in advance according to the actual situation, test results, etc. For example, the preset division rule can include at least one of the following: splitting along a specified direction; not splitting the interconnection structure; at least one opening of the multi-layer interconnection structure is located on the surface of the circuit board; the aspect ratio of the multi-layer interconnection structure in each circuit board does not exceed a preset aspect ratio threshold; etc.

[0103] In the case where the interconnection structures are not split into different circuit boards, the multi-layer interconnection structures in the multi-layer interconnection circuit board will be divided into the same circuit board as a whole. Therefore, the target interconnection structure information contains all the information of the initial interconnection structure information.

[0104] In the case where the interconnection structures are all split into different circuit boards, the multi-layer interconnection structures in the multi-layer interconnection circuit board will be divided into multiple circuit boards. Therefore, each piece of target interconnection structure information only contains part of the information of the initial interconnection structure information.

[0105] In this embodiment, by dividing the circuit boards based on the initial interconnection structure information, it helps to improve the processing accuracy and position accuracy of the conductive vias, better ensure that the conductive vias are correctly connected to the pads or traces of the target layer, avoid interruption of interlayer electrical connections, and improve the mechanical strength and reliability of the circuit board.

[0106] In an exemplary embodiment, the initial interconnect structure information includes the number of layers of the initial interconnect structure; based on the initial interconnect structure information, the overall line structure information is divided into line segment splicing information and multiple line segment processing information, including steps S021 - S022, where:

[0107] Step S021, when it is determined based on the number of layers of the initial interconnect structure that the number of layers of the initial interconnect structure exceeds a preset layer threshold, the initial interconnect structure information is divided into multiple target interconnect structure information, where the target interconnect structure information includes information on some layers in the initial interconnect structure.

[0108] It should be noted that when a laser penetrates a material, its energy will decay as the depth increases. For conductive holes with a high aspect ratio, the attenuation of the laser energy will cause the processing effect at the bottom of the conductive hole to deteriorate, and it may even not be able to penetrate completely. Additionally, in some embodiments, during laser drilling, the material is removed by melting and vaporization through the photothermal ablation mechanism of laser pulses on the material. However, for conductive holes with a high aspect ratio, slag or recast layers are likely to form on the hole walls, resulting in rough hole walls, affecting the subsequent electroplating quality, and the thermal effect will be more serious. During the electroplating process, it is also more difficult for the electroplating solution to flow evenly into the holes, resulting in uneven electroplating layer thickness on the hole walls and at the bottom of the holes. It is possible that the hole mouth is over-plated while the hole bottom is under-plated, thus affecting the electrical conductivity of the circuit board.

[0109] Among them, the preset layer threshold can be determined in advance based on the thickness of each circuit layer of the multi-layer interconnect circuit board, the number of layers and diameter of the multi-layer interconnect structure, and a preset aspect ratio threshold. The preset aspect ratio threshold can be determined based on the actual processing conditions of drilling, and this embodiment does not limit this. For example, assume that a multi-layer interconnect circuit board has a total of 5 layers, each layer with a thickness of 1, and it includes a 5-layer interconnect structure with a diameter of 1 and a preset aspect ratio threshold of 3. Then the aspect ratio of this 5-layer interconnect structure is 5, which exceeds the preset aspect ratio threshold. Therefore, this 5-layer interconnect structure can be divided into a 3-layer interconnect structure and a 2-layer interconnect structure. In this way, compared with the method of processing and aligning layer by layer for 5 layers, only one alignment is required, and the processing accuracy is higher. Compared with the method of forming a 5-layer interconnect structure at one time, the processing quality of the 3-layer interconnect structure and the 2-layer interconnect structure is higher.

[0110] Exemplarily, after obtaining the initial interconnection structure information, the layer number information of the initial interconnection structure can be extracted from the initial interconnection structure information. Based on this layer number information, it is determined whether the layer number of the initial interconnection structure exceeds a preset layer number threshold. If the layer number of the initial interconnection structure exceeds the preset layer number threshold, the initial interconnection structure can be divided into multiple target interconnection structures. Correspondingly, the initial interconnection structure information is divided into multiple target interconnection structure information according to the target interconnection structures. If the layer number of the initial interconnection structure does not exceed the preset layer number threshold, there is no need to divide the initial interconnection structure, and the initial interconnection structure is determined as the target interconnection structure, and the initial interconnection structure information is determined as the target interconnection structure information.

[0111] Step S022: Based on each target interconnection structure information, divide the overall line structure information into line segment splicing information and multiple line segment processing information, so that each target interconnection structure information is divided into different line segment processing information respectively.

[0112] Exemplarily, after determining the target interconnection structure information, based on the target interconnection structure information, the multi-layer interconnection circuit board can be structurally divided, and the multi-layer interconnection circuit board is divided into multiple line segments. Correspondingly, the overall line structure information is divided into corresponding line segment processing information and line segment splicing information according to the line segments.

[0113] In this embodiment, by setting a preset layer number threshold and dividing the conductive vias with a layer number exceeding the preset layer number threshold into different line segments for separate processing, the processing accuracy and processing effect of the high aspect ratio conductive vias can be effectively improved.

[0114] In an exemplary embodiment, the line segment processing information includes sub-line layer information and target interconnection structure information; in the process of controlling the laser processing equipment to process the line segment based on the line segment processing information, the method further includes steps S21 - S22, where:

[0115] Step S21: Control the splicing device to manufacture an intermediate segment according to the sub-line layer information.

[0116] Among them, the segmented line segments can also be multi-layer structures.

[0117] The sub-line layer can refer to the basic component unit of the line segment. Each sub-line layer is an independent circuit layer with specific electrical functions and structural designs. The sub-line layer can be pre-processed based on its corresponding line structure information.

[0118] The intermediate segment can refer to a multi-layer composite board formed by laminating multiple sub-line layers.

[0119] The sub-circuit layer information may refer to the information required for the processing of the sub-circuit layer. It may include at least one of the number of sub-board layers information, conductive line information, identification information of the sub-circuit layer, storage location information of the sub-circuit layer, etc.

[0120] In some feasible embodiments, for each circuit board, according to the identification information or storage location information of its corresponding sub-circuit layer, etc., a human or a controlled robot, robotic arm, etc. can pick up the sub-circuit layer corresponding to the circuit board.

[0121] In some other feasible embodiments, for each circuit board, according to the number of sub-board layers information, conductive line information, etc. corresponding to it, conductive lines can be processed on an insulating substrate to obtain a sub-circuit layer.

[0122] As an example, one layer of insulating material layer and one layer of metal material layer can be pre-pressed according to the sub-circuit layer information of each sub-circuit layer, and conductive lines are processed on the pressed metal material layer to obtain a sub-circuit layer. Furthermore, a human or a controlled robot, robotic arm, etc. can pick up the corresponding sub-circuit layer based on the sub-circuit layer information, and place the picked-up sub-circuit layer in a splicing device, and control the splicing device to press and combine each sub-circuit layer to form an intermediate board.

[0123] As another example, the intermediate board can also be made by a layer-by-layer growth method. Specifically, a human or a controlled robot, robotic arm, etc. can pick up the corresponding insulating material layer and metal material layer based on the sub-circuit layer information, place them in a splicing device, control the splicing device to press and combine the insulating material layer and the metal material layer, control the conductive line processing equipment to process the inner conductive lines on the pressed metal material layer, and then a human or a controlled robot, robotic arm, etc. can pick up the corresponding insulating material layer and metal material layer based on the sub-circuit layer information, place them on the metal material layer with processed conductive lines, control the splicing device to press and combine the alternately stacked insulating material layers and metal material layers, and then control the conductive line processing equipment to process the inner conductive lines on the pressed metal material layer. By pressing and processing the conductive lines multiple times in this way, an intermediate board is obtained.

[0124] Step S22, control the laser processing equipment, and based on the target interconnect structure information, process a multi-layer interconnect structure on the intermediate board to obtain a circuit board.

[0125] Exemplarily, after obtaining the intermediate board, based on the target interconnect structure information corresponding to the intermediate board, control the laser processing equipment to emit a laser beam to the intermediate board, and control the laser beam to move to the processing sites corresponding to the multi-layer interconnect structure, process hole structures on the intermediate board, and then control the filling device to fill the hole structures with conductive materials to achieve the processing of the multi-layer interconnect structure and obtain a circuit board.

[0126] In this embodiment, by means of laser drilling, holes with a larger depth-to-width ratio can be processed, so that a multi-layer interconnect structure with higher precision can be formed in one step, meeting the design requirements of more complex multi-layer boards.

[0127] In an exemplary embodiment, the sub-circuit layer information includes conductive line information; before the control splicing device manufactures the intermediate plate according to the sub-circuit layer information, the method further includes:

[0128] Controlling a conductive line processing device to process conductive lines on a plurality of insulating substrates based on the conductive line information to obtain a plurality of sub-circuit layers.

[0129] Among them, the conductive line processing device may refer to a device for processing conductive lines. For example, an LDI (Laser Direct Imaging) device, a high-power laser drilling device, etc.

[0130] The insulating substrate may refer to a non-conductive material for supporting and isolating the conductive parts in a circuit. The sub-board layer number information may refer to information for describing the number of circuit layers in a circuit board. Usually, the circuit layers are separated by insulating substrates from each other. Therefore, the number of insulating substrates is the same as the number of sub-circuit layers.

[0131] The conductive line information may refer to the information required for processing the conductive lines in a multi-layer interconnect circuit board, and may be used to define at least one of the running direction, width, spacing, connection relationship of the conductive lines in the circuit board, and the interaction mode with other components.

[0132] Exemplarily, for each circuit board, according to the corresponding sub-board layer number information, the number of insulating substrates required for its processing can be determined. Then, through manual operation or by controlling a robot, a robotic arm, etc., the corresponding number of insulating substrates can be picked up, and a conductive material layer can be laminated on each insulating substrate. Further, for each insulating substrate laminated with a conductive material layer, it can be first placed on a processing platform, and then the conductive line processing device is controlled to remove the conductive material in the non-conductive line area on the conductive material layer based on the conductive line information corresponding to the circuit board. The unremoved conductive material can form corresponding conductive lines on the insulating substrate, obtaining a plurality of sub-circuit layers corresponding to the circuit board.

[0133] In this embodiment, since the allowable alignment deviation range of the conductive lines is larger, directly processing the conductive lines on the insulating substrate and then performing layer-by-layer lamination has less impact on the processing accuracy and quality of the circuit board, and the process is simple.

[0134] In an exemplary embodiment, a multi-layer interconnect circuit board includes a multi-layer interconnect structure; the multi-layer interconnect structure includes a first interconnect structure and a second interconnect structure. The first interconnect structure includes a first opening in a first direction and a second opening in a second direction. The second interconnect structure includes a third opening in the first direction and a fourth opening in the second direction. The first opening and the third opening are located on different layers, and the second opening and the fourth opening are located on different layers; the target interconnect structure information includes the target interconnect structure information of the first interconnect structure; the target interconnect structure information includes the target interconnect structure information of the first interconnect structure and the target interconnect structure information of the second interconnect structure; in the process of controlling the splicing device to manufacture an intermediate board according to the sub-circuit layer information, the method further includes steps S221-S223, where:

[0135] Step S221, controlling the splicing device to stack the respective sub-circuit layers corresponding to the first interconnect structure to form an initial board;

[0136] Step S222, controlling the laser processing device to process the first interconnect structure on the initial board based on the target interconnect structure information of the first interconnect structure;

[0137] Step S223, controlling the splicing device to laminate the initial board processed with the first interconnect structure with other sub-circuit layers to form an intermediate board.

[0138] It should be noted that, by laminating the respective circuit boards in the circuit board layer-adding direction, the combination between the respective circuit boards is closer and the combination effect is better. In this way, when dividing the blocks, it is necessary to divide them by layer. For a circuit board with a relatively complex structure, multiple multi-layer interconnect structures may be distributed on the same circuit layer, and the number of layers and the opening positions of these multi-layer interconnect structures may be different. In this case, if the blocks are divided according to the multi-layer interconnect structure with fewer layers, the multi-layer interconnect structure with more layers will be divided into multiple interconnect structures, which will increase the alignment times of the multi-layer interconnect structure, resulting in an increased probability of alignment deviation, thereby affecting the processing accuracy of the multi-layer interconnect circuit board. If the blocks are divided according to the multi-layer interconnect structure with more layers, after laminating the respective sub-circuit layers together, usually only one-time forming of the multi-layer interconnect structure with more layers can be achieved, and it is often difficult for the laser to penetrate the material surface to directly process buried holes inside the circuit board. If the blocks are divided according to the multi-layer interconnect structure with more layers, and when processing the sub-circuit layers, the multi-layer interconnect structures with fewer layers are processed layer by layer, these multi-layer interconnect structures with fewer layers still need to be aligned and stacked, which is prone to alignment errors, thereby affecting the processing quality of the circuit board.

[0139] Wherein, the first direction may refer to the circuit board layer-adding direction or the opposite direction of the layer-adding direction, and the second direction is collinear with the first direction but in the opposite direction.

[0140] Exemplarily, after determining the circuit board to be processed, it is possible to first judge whether a group of multi-layer interconnect structures with openings on both sides located on different layers are included in the circuit board based on the circuit structure information corresponding to the circuit board.

[0141] If only one multi-layer interconnect structure is included in the circuit board, or multiple multi-layer interconnect structures are included, but the openings on at least one side of each multi-layer interconnect structure are located on the same circuit layer, the splicing device can be directly controlled to cooperate with the conductive circuit processing equipment to process the intermediate board in a layer-by-layer growth manner. The layer-by-layer growth manner may include: controlling the splicing device to press a metal material layer on at least one side of the core board layer or any sub-circuit layer, then controlling the conductive circuit processing equipment to perform circuit processing on the metal material layer to form an inner conductive circuit, and then controlling the splicing device to press an insulating material layer and a metal material layer on the metal material layer, and then performing inner layer pattern processing on the metal material layer to form an inner layer circuit. After multiple pressings and conductive circuit processings like this, a multi-layer stacked intermediate board can be obtained.

[0142] If the circuit board includes multiple multi-layer interconnect structures and the openings on both sides of each multi-layer interconnect structure are located on different layers, any one of the multi-layer interconnect structures can be first determined as the first interconnect structure, and the splicing device can be controlled to cooperate with the conductive circuit processing equipment to process the initial board in a layer-by-layer growth manner; then, based on the target interconnect structure information of the first interconnect structure, the laser processing equipment can be controlled to emit a laser beam towards the initial board, and the laser beam can be controlled to move to the processing site corresponding to the first interconnect structure to process a hole structure on the initial board. Furthermore, the filling device can be controlled to fill the hole structure with a conductive material to complete the processing of the first interconnect structure; furthermore, the splicing device can be controlled to use the initial board processed with the first interconnect structure as the board core, and other sub-circuit layers can be processed on the initial board in a layer-by-layer growth manner to form an intermediate board.

[0143] Among them, other sub-circuit layers refer to other sub-circuit layers in each sub-circuit layer corresponding to the circuit board except the sub-circuit layer corresponding to the first interconnect structure.

[0144] In some feasible embodiments, when there are more than two multi-layer interconnect structures included in the circuit board, after any first interconnect structure is processed, a first interconnect structure is re-determined from the multi-layer interconnect structures, and then processed according to the same method as above until the last multi-layer interconnect structure remains unprocessed, and the last multi-layer interconnect structure is determined as the second interconnect structure.

[0145] Controlling the laser processing equipment to process the multi-layer interconnect structure on the intermediate board based on the target interconnect structure information to obtain the circuit board includes:

[0146] Control the laser processing equipment, and based on the target interconnection structure information of the second interconnection structure, process the second interconnection structure on the intermediate plate to obtain a circuit plate.

[0147] Exemplarily, after the first interconnection structure is processed to obtain the intermediate plate, other multi-layer interconnection structures can be determined as the second interconnection structure. Then, based on the target interconnection structure information of the second interconnection structure, control the laser processing equipment to emit a laser beam towards the intermediate plate, and control the laser beam to move to the processing site corresponding to the second interconnection structure, process a hole structure on the intermediate plate. Further, control the filling device to fill the hole structure with a conductive material to achieve the processing of the second interconnection structure and obtain a circuit plate.

[0148] In this embodiment, one-time forming of each multi-layer interconnection structure can be achieved, and for each multi-layer interconnection structure, regardless of whether it is a through hole, blind hole or buried hole in the circuit plate, it can be processed into a through hole with both sides penetrated during processing. In this way, when setting the laser processing parameters, more consideration can be given to the processing quality of the holes, without having to consider the quality problems that may be caused by over-deep processing. On the other hand, since one-time forming of each multi-layer interconnection structure can be achieved, when performing processing design, only the hardware conditions of the processing equipment need to be considered, and based on the hardware conditions, the processing accuracy and processing effect can be maximally improved.

[0149] In an exemplary embodiment, based on the circuit plate splicing information, splice the circuit plates into a multi-layer interconnection circuit board, including steps S31 - S32, where:

[0150] Step S31, based on the circuit plate splicing information, perform a direction transformation on at least one circuit plate.

[0151] Among them, the direction transformation can refer to the process of changing the direction of the circuit plate. The direction transformation can include one or a combination of mirror flipping and rotation, etc. By performing a direction transformation on the circuit plate, reorientation of the circuit plate can be achieved. For example, as Figure 6 shown, Figure 6 the part enclosed by the dotted line box represents a circuit plate, and the part enclosed by the solid line box represents a multi-layer interconnection circuit board. The second layer from top to bottom of this multi-layer interconnection circuit board can be the core layer. It can be found from this that this multi-layer interconnection circuit board is spliced by this circuit plate and the circuit plates after two mirror flips in the horizontal and vertical directions.

[0152] The circuit plate splicing information can include the splicing position information and splicing direction information of each circuit plate during the splicing process.

[0153] Exemplarily, for each circuit board, it is possible to determine whether a direction transformation is required according to the corresponding splicing direction information in the circuit board splicing information. If it is determined based on the splicing direction information that the current direction of the circuit board is consistent with its target direction during the splicing process, then the direction transformation may not be required; if it is determined based on the splicing direction information that the current direction of the circuit board is inconsistent with its target direction during the splicing process, then the splicing device can be controlled to perform a direction transformation on it so that the current direction of the circuit board is transformed to coincide with the target direction.

[0154] Step S32: Splice the circuit boards after the direction transformation into a multi-layer interconnected circuit board.

[0155] Exemplarily, in the case where it is determined that each circuit board is in the target direction, the splicing device can be controlled to splice the circuit boards into a multi-layer interconnected circuit board.

[0156] In this embodiment, for circuit boards with the same circuit structure but only different directions, batch processing can be achieved through simple direction transformation, thereby effectively improving the processing efficiency.

[0157] In an exemplary embodiment, controlling a laser processing device to process a plurality of circuit boards based on the processing information of each of the circuit boards includes:

[0158] Controlling the laser processing device to emit a short-pulse laser beam, wherein the laser processing device is configured to control the short-pulse laser beam to form a multi-layer interconnected structure on the circuit board at one time based on the target interconnected structure information.

[0159] A short-pulse laser beam refers to a laser beam whose pulse width is less than or equal to the nanosecond order of magnitude, including nanosecond pulse width, picosecond pulse width, and femtosecond pulse width. Lasers that emit short-pulse laser beams include ultrafast lasers and nanosecond lasers. Among them, the laser beam emitted by an ultrafast laser is an ultrafast laser with a pulse width less than or equal to the picosecond order of magnitude, and the laser beam emitted by a nanosecond laser is a nanosecond laser with a pulse width of the nanosecond order of magnitude.

[0160] The laser that emits the short-pulse laser beam can also be a carbon dioxide laser. The original laser pulse emitted by the carbon dioxide laser is a long-pulse laser beam with a microsecond order of magnitude, but the long-pulse laser beam can be switched into the short-pulse laser beam required for processing through a pulse modulation device, such as through radio frequency pulse modulation technology.

[0161] In some exemplary embodiments, the lasers that emit short-pulse laser beams include ultrafast lasers and nanosecond lasers.

[0162] The conductive material layer of a circuit board usually uses copper or aluminum, which has a low absorption rate of laser, only 0.5% - 10%. The carbon dioxide laser emitted by a carbon dioxide laser has a long wavelength, usually between 9.3 µm and 10.6 µm, and a long pulse width. Although the long-pulse-width carbon dioxide laser can be switched into a short-pulse laser beam required for processing through a pulse control device, it is impossible to make the peak power of the carbon dioxide laser beam reach the damage threshold of conductive materials such as copper or aluminum. However, the short-pulse laser beams emitted by ultrafast lasers and nanosecond lasers, such as laser beams with picosecond pulse widths or nanosecond pulse widths, have a large peak power and can quickly damage copper. Therefore, when using carbon dioxide laser for processing, the surface of the conductive material layer must be browned or blackened before processing, or a windowing process must be carried out at the processing position of the multi-layer interconnect structure to pre-remove the surface conductive material layer, and then the carbon dioxide laser is used to ablate and remove the insulating material layer to process and form a hole structure. The process flow steps are numerous and the processing efficiency is slow.

[0163] Therefore, to improve the drilling efficiency, the short-pulse laser beam preferably uses an ultrafast laser or a nanosecond laser. Both ultrafast lasers and nanosecond lasers can quickly break through the conductive material layer, without the need to pre-treat the conductive material layer of the circuit board in advance, which can effectively simplify the process flow and improve the overall transfer efficiency of the circuit board production process.

[0164] In an exemplary embodiment, the short-pulse laser beam is an ultrafast laser. The laser processing equipment is provided with a laser for emitting a short-pulse laser beam, and the laser can use an ultrafast laser, including picosecond lasers and femtosecond lasers. The ultrafast laser can output a short-pulse laser beam with a pulse width less than or equal to the picosecond level. Due to the extremely short pulse time, the laser energy is concentrated and released in an extremely short time, so the peak power is extremely high, reaching the GW (Gigawatt) level, making the laser energy concentrated in a very small time and space range, triggering multi-photon absorption and / or avalanche ionization at the processing position of the material, breaking the molecular chain of the material, vaporizing the material, forming smaller particles, and realizing the rapid removal of the material. Moreover, the interaction time between the laser pulse of the ultrafast laser and the material is extremely short, resulting in less thermal impact on the material around the hole structure, and no carbon slag is generated during the processing, and a better hole structure morphology can be obtained, which has significant advantages in the application of processing multi-layer interconnect structures on circuit boards. Therefore, using an ultrafast laser is more conducive to improving the processing efficiency and processing quality of multi-layer interconnect structures.

[0165] It can be understood that during actual drilling, for the purpose of maximizing drilling efficiency and optimizing drilling accuracy, a short-pulse laser beam with an appropriate wavelength can be selected according to the processing depth and aperture size requirements of the hole structure.

[0166] In some feasible embodiments, the wavelengths of the short-pulse laser beams include the infrared band, the green light band, and the ultraviolet band, with wavelengths in the range of 343 - 1064 nm. Among them, 343 nm corresponds to the wavelength of violet light, and it can be emitted by an ultraviolet nanosecond laser or an ultraviolet picosecond laser; 1064 nm corresponds to the infrared wavelength, and it can be emitted by an infrared picosecond laser or an infrared femtosecond laser.

[0167] Further, the wavelengths of the short-pulse laser beams are selected in the range from the green light band to the infrared band, with wavelengths in the range of 515 nm to 1064 nm.

[0168] The focused spot size of the laser beam is proportional to the wavelength of the laser beam. The focused spot size formed by a short-pulse laser beam with too short a wavelength is too small, which will reduce the processing depth and the processing efficiency of hole structures with a large aperture size. In addition, restricted by the production principle of solid-state lasers, the maximum output power of a laser with a shorter wavelength is lower, which is determined by the frequency doubling efficiency during the laser generation process. Therefore, the maximum output power of an ultraviolet laser is less than that of a green light or infrared band laser. In order to make the energy density of the focused spot formed by the laser beam output by the ultraviolet laser large enough to quickly penetrate the material layer in the multi-layer interconnect structure area on the circuit board, the size of the focused spot must be small, and a smaller-sized focused spot will significantly reduce the processing depth and the processing efficiency of hole structures with a large aperture size.

[0169] Selecting short-pulse laser beams in the green light band and the infrared band, with high laser power, enables the focused spot to have the characteristics of both high energy density and a relatively large size, which is beneficial to improving the processing efficiency of the multi-layer interconnect structure.

[0170] In some feasible embodiments, the wavelength of the short-pulse laser beam is selected according to the thermal sensitivity characteristics of the processing material.

[0171] It can be understood that when the wavelength of the short-pulse laser beam is too long, such as a short-pulse laser beam with an infrared wavelength, although it can form a large-sized focused spot, and the laser with an infrared wavelength has a high power, both are beneficial to efficiently processing hole structures with a large processing depth and a large aperture size. However, during the processing of a short-pulse laser beam with an infrared wavelength, a large amount of heat will be generated, carbonizing the material and having an adverse impact on the processing quality of the hole structure.

[0172] Specifically, for materials sensitive to heat, a short-pulse laser beam in the green light band can be selected. For example, when processing ABF (Ajinomoto Build-up Film) materials, a green picosecond laser or a green femtosecond laser can be used; for materials that value processing efficiency but can tolerate a certain amount of heat influence, a short-pulse laser beam in the infrared band can be selected. For example, when processing BT (Bismaleimide Triazine) resin materials, an infrared picosecond laser or an infrared femtosecond laser can be used.

[0173] In some feasible embodiments, the short-pulse laser beam is a Gaussian laser beam or a flat-top laser beam.

[0174] Reference Figure 7 and Figure 8 , Figure 7 are the spot shape distribution diagram and drilling effect diagram of the Gaussian laser beam, Figure 8 is to Figure 7 The Gaussian laser beam in is shaped into a flat-top laser beam, and the spot shape distribution and drilling effect diagram are shown. The spot shape of the Gaussian laser beam is Gaussian-shaped in space, and the spot shape of the flat-top laser beam is an ideal flat-top shape in space. However, the beam shape in practical applications is not an ideal shape. Therefore, the flat-top laser beam pointed out in the present invention also includes a quasi-flat-top laser beam with a non-ideal shape.

[0175] In an exemplary embodiment, when the short-pulse laser beam is a Gaussian laser beam, the laser processing device further includes a beam shaping component, which is deployed on the optical path of the Gaussian laser beam and is used to shape the Gaussian laser beam into a flat-top laser beam.

[0176] The original state of the laser beam emitted by the laser is a Gaussian laser beam. By deploying a beam shaping component on the optical path of the Gaussian laser beam, the Gaussian laser beam can be converted into a flat-top laser beam. As Figure 7 shown, the spot shape of the Gaussian laser beam presents a Gaussian distribution in space, and the laser energy of the beam has the characteristic that the intensity is high in the middle and gradually decreases along the Gaussian contour outward. Considering that the hole structure of the multi-layer interconnect structure usually has processing requirements with a relatively high processing depth and a relatively large aperture size, although the Gaussian laser beam before flat-top laser beam shaping has a higher peak pulse energy, the characteristics of the focused spot size being small at the processing position of the circuit board and the energy distribution being strong in the center and weak at the edge result in the processed holes not only having a small opening, but also forming a V-shaped or quasi-V-shaped structure with a wide top and a narrow bottom due to uneven energy distribution, thereby limiting the maximum depth of the processed holes, having a poor processing morphology, and low processing efficiency.

[0177] As Figure 8As shown, the spot energy distribution of the flat-top laser beam is uniform. Although the peak pulse energy is lower than that of the Gaussian laser beam before shaping, the energy density distribution of the focused spot formed by the shaped flat-top laser is more uniform. During the shaping process, the adjustment of the spot size can be added to form a focused spot with a uniform energy density distribution and a larger size. Considering that the hole structures for processing multi-layer interconnect structures usually have high processing depths and large hole diameters, the laser processing needs to be carried out in a way of drilling around the hole. When using a large-sized focused spot for drilling around the hole, the drilling efficiency can be increased by several times, and the focused spot with a more uniform energy density distribution can significantly increase the drilling depth through multiple repeated processing. By shaping the Gaussian laser beam into a flat-top laser for processing multi-layer interconnect structures, it helps to more efficiently process hole structures with high processing depths and large hole diameters. In addition, compared with the Gaussian laser beam, the flat-top laser beam can more effectively utilize the laser energy, reduce the damage to the materials in the surrounding area, and also contribute to a more uniform morphology inside the hole diameter of the multi-layer interconnect structure.

[0178] When the processing depth of the multi-layer interconnect structure is relatively large, the processing method of the multi-layer interconnect structure can be to drill holes into the interior of the circuit board from both sides in the thickness direction of the circuit board. This can reduce the depth of single-sided drilling, lower the drilling difficulty, and improve the processing efficiency. In some other embodiments, according to the processing requirements and appropriate parameter settings, the hole structure that penetrates all the single-layer sub-circuit layers of the circuit board can also be directly processed by single-sided drilling.

[0179] It can be understood that the processing method of drilling holes into the interior of the circuit board from both sides in the thickness direction of the circuit board can form a through-hole structure on the circuit board. After this through-hole structure is pressed together with other circuit boards, it can be used as a through-hole, blind hole, or buried hole in the multi-layer interconnect circuit board. This embodiment does not limit this.

[0180] In some feasible embodiments, the circuit board can be first placed on the processing platform manually or by controlling a manipulator, robot, etc., so that the first surface faces the laser processing equipment. Then, control the laser processing equipment to drill the first hole section into the interior of the circuit board from the first surface of the circuit board along the third direction. Furthermore, the circuit board can be flipped manually or by controlling a manipulator, robot, etc. so that the second surface faces the laser processing equipment, or the laser head of the laser processing equipment can also be controlled to face the second surface. Then, control the laser processing equipment to drill the second hole section into the interior of the circuit board from the second surface of the circuit board along the fourth direction. The second hole section is connected to the first hole section to form a multi-layer interconnect structure.

[0181] It should be understood that although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0182] Based on the same inventive concept, an embodiment of the present application also provides a multi-layer interconnect circuit board processing system for implementing the above-mentioned multi-layer interconnect circuit board processing method. The implementation solutions provided by this system to solve problems are similar to the implementation solutions described in the above method. Therefore, the specific limitations in one or more embodiments of the multi-layer interconnect circuit board processing system provided below can refer to the limitations on the multi-layer interconnect circuit board processing method in the above text, and will not be repeated here.

[0183] In an exemplary embodiment, as Figure 9 shown, a multi-layer interconnect circuit board processing system is provided. The system includes a controller 906, a laser processing device 902, and a splicing device 904, where:

[0184] The laser processing device 902 is configured to process the circuit board segments 908;

[0185] The splicing device 904 is configured to splice the circuit board segments 908 into a multi-layer interconnect circuit board 910;

[0186] The controller 906 is configured to:

[0187] Obtain the circuit structure information of the multi-layer interconnect circuit board 910, where the circuit structure information includes multiple circuit board segment processing information, and at least one circuit board segment processing information contains target interconnect structure information;

[0188] Control the laser processing device 902 to process multiple circuit board segments 908 based on the circuit board segment processing information, where at least one circuit board segment 908 has a multi-layer interconnect structure, and the multi-layer interconnect structure is formed in one step based on the target interconnect structure information;

[0189] Control the splicing device 904 to splice the circuit board segments 708 into a multi-layer interconnect circuit board 910 based on the circuit board segment splicing information.

[0190] In an exemplary embodiment, the controller may also implement the steps in the above method embodiments.

[0191] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as Figure 10 shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a method for processing a multi-layer interconnected circuit board. The display unit of the computer device is used to form a visually visible picture, which may be a display screen, a projection device, or a virtual reality imaging device. The display screen may be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device may be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0192] Those skilled in the art can understand that Figure 10 the structure shown in

[0193] is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0194] In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps in the above method embodiments.

[0195] In one embodiment, a computer program product is provided, including a computer program which, when executed by a processor, implements the steps in the above method embodiments.

[0196] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0197] Those of ordinary skill in the art can understand that all or part of the processes in the above method embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above method embodiments. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., and are not limited thereto. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., and are not limited thereto.

[0198] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0199] The above embodiments only express several implementation manners of this application, and the description is relatively specific and detailed. However, it should not be construed as a limitation on the patent scope of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several deformations and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application should be subject to the appended claims.

Claims

1. A method for processing a multi-layer interconnection circuit board, characterized in that: The method comprises: Acquire circuit structure information of the multi-layer interconnection circuit board, wherein the circuit structure information includes circuit board splicing information and multiple circuit board processing information, and at least one of the circuit board processing information contains target interconnection structure information; Controlling a laser processing device to process a plurality of circuit plates based on the processing information of each circuit plate, wherein at least one of the circuit plates has a multi-layer interconnection structure, and the multi-layer interconnection structure is formed in one step based on the target interconnection structure information; The control splicing device splices the circuit blocks into a multi-layer interconnected circuit board based on the circuit block splicing information.

2. The method according to claim 1, characterized in that Before obtaining the circuit structure information of the multi-layer interconnection circuit board, the method further includes: Acquire the overall information of the circuit structure of the multi-layer interconnection circuit board, wherein the overall information of the circuit structure includes the initial interconnection structure information of the multi-layer interconnection structure; Based on the initial interconnection structure information, the overall circuit structure information is divided into circuit block splicing information and multiple circuit block processing information, wherein at least one of the circuit block processing information contains target interconnection structure information, and the target interconnection structure information contains all or part of the initial interconnection structure information.

3. The method according to claim 2, characterized in that The initial interconnection structure information includes information about the number of layers of the initial interconnection structure; based on the initial interconnection structure information, the overall circuit structure information is divided into circuit block splicing information and multiple circuit block processing information, including: When it is determined based on the layer number information of the initial interconnect structure that the number of layers of the initial interconnect structure exceeds a preset layer number threshold, the initial interconnect structure information is divided into a plurality of target interconnect structure information, wherein the target interconnect structure information includes information of some layers in the initial interconnect structure; Based on each of the target interconnection structure information, the circuit structure overall information is divided into circuit block splicing information and a plurality of circuit block processing information, so that each of the target interconnection structure information is respectively divided into different circuit block processing information.

4. The method according to claim 1, characterized in that: The circuit plate processing information includes sub-circuit layer information and target interconnection structure information; in the process of controlling the laser processing equipment to process the circuit plate based on the circuit plate processing information, the method further includes: Controlling the splicing device to produce the intermediate plate according to the sub-circuit layer information; The laser processing equipment is controlled to process a multi-layer interconnection structure on the intermediate plate based on the target interconnection structure information to obtain a circuit plate.

5. The method according to claim 4, characterized in that The sub-circuit layer information includes conductive circuit information; before the control splicing device makes the intermediate plate according to the sub-circuit layer information, the method further includes: The conductive circuit processing equipment is controlled to process the conductive circuits on a plurality of insulating substrates based on the conductive circuit information to obtain a plurality of sub-circuit layers.

6. The method according to claim 4, characterized in that The multi-layer interconnection circuit board includes a multi-layer interconnection structure; the multi-layer interconnection structure includes a first interconnection structure and a second interconnection structure, the first interconnection structure includes a first opening in a first direction and a second opening in a second direction, the second interconnection structure includes a third opening in the first direction and a fourth opening in the second direction, the first opening and the third opening are located in different layers, and the second opening and the fourth opening are located in different layers; the target interconnection structure information includes the target interconnection structure information of the first interconnection structure and the target interconnection structure information of the second interconnection structure; In the process of controlling the splicing device to produce the intermediate plate according to the sub-circuit layer information, the method further includes: Controlling the splicing device to stack the sub-circuit layers corresponding to the first interconnection structure to form an initial block; Controlling a laser processing device to process a first interconnect structure on the initial plate based on target interconnect structure information of the first interconnect structure; Controlling the splicing device to press the initial plate processed with the first interconnection structure and other sub-circuit layers to form an intermediate plate; The controlling laser processing device processes a multi-layer interconnection structure on the intermediate plate based on the target interconnection structure information to obtain a circuit plate, including: The laser processing equipment is controlled to process the second interconnect structure on the intermediate plate based on the target interconnect structure information of the second interconnect structure to obtain a circuit plate.

7. The method according to any one of claims 1 to 6, characterized in that: The method of splicing the circuit blocks into a multi-layer interconnected circuit board based on the circuit block splicing information includes: Based on the line block splicing information, changing the direction of at least one of the line blocks; The circuit boards after direction change are spliced ​​into a multi-layer interconnected circuit board.

8. The method according to any one of claims 1 to 6, characterized in that: The controlling laser processing equipment processes a plurality of circuit plates based on the processing information of each circuit plate, including: The laser processing device is controlled to emit a short pulse laser beam, wherein the laser processing device is configured to control the short pulse laser beam to form a multi-layer interconnection structure on the circuit board at one time based on target interconnection structure information.

9. The method according to claim 8, characterized in that The short pulse laser beam is a Gaussian laser beam or a flat-top laser beam.

10. The method according to claim 9, characterized in that In the case where the short pulse laser beam is a Gaussian laser beam, the laser processing equipment further comprises a beam shaping component, which is disposed on the optical path of the Gaussian laser beam and is used to shape the Gaussian laser beam into a flat-top laser beam.

11. The method according to claim 8, characterized in that The wavelength of the short pulse laser beam is from the green light band to the infrared band.

12. A multi-layer interconnection circuit board processing system, characterized in that: The system includes a controller, a laser processing device and a splicing device, wherein: The laser processing equipment is configured to process circuit boards; The splicing device is configured to splice the circuit blocks into a multi-layer interconnected circuit board; The controller is configured to: Acquire circuit structure information of the multi-layer interconnection circuit board, wherein the circuit structure information includes a plurality of circuit board processing information, and at least one of the circuit board processing information includes target interconnection structure information; Controlling the laser processing equipment to process a plurality of circuit plates based on the processing information of each circuit plate, wherein at least one of the circuit plates has a multi-layer interconnection structure, and the multi-layer interconnection structure is formed in one step based on the target interconnection structure information; The splicing device is controlled to splice the circuit blocks into a multi-layer interconnected circuit board based on the circuit block splicing information.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 11 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

15. A workpiece, characterized in that: The workpiece is obtained by machining using the method according to any one of claims 1 to 11.

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