Semiconductor structure and method of manufacturing the same, memory, electronic device

Abstract

The present disclosure relates to a semiconductor structure, a manufacturing method thereof, a memory, and an electronic device. The manufacturing method of the semiconductor structure comprises: providing a substrate, and forming a stack structure on one side of the substrate; the stack structure comprises: a plurality of target material layers stacked along a vertical direction of the substrate, and a support material layer between any two adjacent target material layers; etching the stack structure along the vertical direction of the substrate to form an etching groove extending along a first direction; forming a sacrificial material layer in the etching groove; and performing a plurality of target processes cyclically on the obtained structure after the sacrificial material layer is formed, so that the remaining part of each target material layer corresponds to form a first step, and a plurality of first steps are arranged as a ladder structure along a second direction; the second direction intersects the first direction. The present disclosure is conducive to efficient manufacturing of the ladder structure.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a semiconductor structure and its manufacturing method, a memory, and an electronic device. Background Technology

[0002] With the development of semiconductor technology, in order to further pursue the miniaturization of device structures, the process has been transformed from planar to three-dimensional, that is, the arrangement of memory cells in three-dimensional space, which has become the main development direction of current memory structure research.

[0003] Currently, in 3D memory, when wiring bit lines at different heights, each layer's bit lines need to be wired individually. However, as the number of stacked layers of memory cells increases to hundreds or thousands, the number of individual wiring processes also needs to increase by hundreds or thousands, which significantly increases the complexity of the manufacturing process. Therefore, the manufacturing of staircase structures is particularly important. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure provide a semiconductor structure and its manufacturing method, a memory, and an electronic device to achieve efficient manufacturing of stepped structures.

[0005] To achieve the above objectives, in a first aspect, some embodiments of this disclosure provide a method for manufacturing a semiconductor structure, comprising: providing a substrate and forming a stacked structure on one side of the substrate; the stacked structure comprising: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a support material layer located between any two adjacent target material layers; etching the stacked structure along a direction perpendicular to the substrate to form an etching trench extending along a first direction; forming a sacrificial material layer in the etching trench; repeatedly performing the target process on the structure obtained after forming the sacrificial material layer, such that the retained portion of each target material layer forms a first step, and the plurality of first steps are arranged in a stepped structure along a second direction; the second direction intersects the first direction.

[0006] One of the target processes includes: etching away the sacrificial material layer of the target height along the direction perpendicular to the substrate to expose the sidewall of the target material layer of the target layer; etching the target material layer of the target layer along the direction parallel to the substrate, and simultaneously etching each target material layer exposed on the side of the target layer away from the substrate from top to bottom along the direction parallel to the substrate.

[0007] In some embodiments, the etching rates are different between the target material layer and the sacrificial material layer.

[0008] In some embodiments, the target material layer is etched using a wet etching process; the etching selectivity ratio of the target material layer to the sacrificial material layer is greater than or equal to 10:1.

[0009] In some embodiments, the target material layers are etched by a remote plasma source etching process; and the etching selectivity ratio of the target material layers to the sacrificial material layers is greater than 1:1 and less than or equal to 5:1.

[0010] In some embodiments, the sacrificial material layers are etched by an anisotropic etching process.

[0011] In some embodiments, the target material layers of the target layers are etched along the parallel substrate direction, and each target material layer exposed on the side of the target layer away from the substrate is etched synchronously from top to bottom along the parallel substrate direction, and the method further comprises: etching each target material layer symmetrically on both sides of the etching trench in the second direction to form a stepped structure symmetrically arranged around the etching trench.

[0012] In some embodiments, the method for manufacturing the semiconductor structure further comprises: forming an isolation spacer on one side of the substrate. The stack structure is formed on one side of the isolation spacer, and the etching trench exposes the side wall of the isolation spacer facing the stack structure.

[0013] In some embodiments, the target material layers comprise metal material layers or semiconductor material layers. The method for manufacturing the semiconductor structure further comprises: patterning the target material layers to form a common bit line connected to each first step respectively, and a bit line connected to the common bit line. The common bit line extends along the second direction.

[0014] In some embodiments, the method for manufacturing the semiconductor structure further comprises: forming an isolation structure filling the etching trench and the etching removal region of each target material layer; or etching each adjacent support material layer as a mask to form a second step corresponding to the remaining part of each support material layer; and forming an isolation structure filling the etching trench and the etching removal region of each target material layer and each support material layer.

[0015] In some embodiments, the method for manufacturing the semiconductor structure further comprises: forming a via at least through the isolation structure on the surface of the first step away from the substrate; and forming a bit line lead in the via.

[0016] In a second aspect, the present disclosure provides, according to some embodiments, a semiconductor structure, comprising a substrate, a stack structure, and a sacrificial material layer. The stack structure is located on one side of the substrate; the stack structure comprises a plurality of target material layers stacked along a vertical substrate direction, and a support material layer located between any two adjacent target material layers; the stack structure has an etching trench extending along a first direction; and the sacrificial material layer fills the etching trench. Each target material layer and the sacrificial material layer are configured to form a reserved portion of each target material layer corresponding to a first step after a plurality of target processes are cyclically performed, and a plurality of first steps are arranged as a staircase structure along a second direction; the second direction intersects the first direction. The target process comprises: etching and removing a target height of the sacrificial material layer along the vertical substrate direction to expose a sidewall of the target material layer of the target layer; etching the target material layer of the target layer along a parallel substrate direction, and synchronously etching each target material layer exposed on a side of the target layer away from the substrate along the parallel substrate direction from top to bottom.

[0017] In some embodiments, the semiconductor structure further comprises an isolation spacer wall located on one side of the stack structure along the parallel substrate direction. The sacrificial material layer is located between the isolation spacer wall and the stack structure.

[0018] In some embodiments, the semiconductor structure further comprises an isolation spacer wall located on one side of the stack structure along the parallel substrate direction. The sacrificial material layer is located between the isolation spacer wall and the stack structure.

[0019] In some embodiments, the semiconductor structure further comprises an isolation spacer wall located on one side of the stack structure along the parallel substrate direction. The sacrificial material layer is located between the isolation spacer wall and the stack structure.

[0020] In some embodiments, the semiconductor structure further comprises an isolation spacer wall located on one side of the stack structure along the parallel substrate direction. The sacrificial material layer is located between the isolation spacer wall and the stack structure.

[0021] The embodiments of the present disclosure can have / at least have the following advantages:

[0022] In the embodiments of the present disclosure, after forming the laminated structure on the substrate side and forming the sacrificial material layer in the etched groove of the laminated structure, the obtained structure after forming the sacrificial material layer can be cyclically executed multiple times. Any target process includes: etching and removing the target height of the sacrificial material layer along the vertical substrate direction, exposing the sidewall of the target material layer of the target layer; etching the target material layer of the target layer along the parallel substrate direction, and synchronously etching each target material layer exposed to the target layer away from the substrate side from top to bottom along the parallel substrate direction. Thus, the etching time of different layers of target material layers in the spatial dimension can be utilized to form the first step corresponding to multiple target material layers, so as to obtain the ladder structure. In this way, compared with the related art, the step partition is manufactured by adjusting and etching multiple groups of cycles, and the ladder structure is formed by multiple replication etching processes. The present scheme only needs to perform once mask pattern definition, so as to realize one-step manufacturing of multiple layers of steps, thereby reducing the complexity of the process procedure, and realizing efficient manufacturing of the ladder structure.

[0023] Details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1 A flowchart of a manufacturing method of a semiconductor structure provided in some embodiments;

[0026] Figure 2 A cross-sectional schematic diagram of a semiconductor structure provided in some embodiments;

[0027] Figure 3 A flowchart of a target process provided in some embodiments;

[0028] Figure 4 A cross-sectional schematic diagram of the structure obtained after removing the target height of the sacrificial material layer in some embodiments;

[0029] Figure 5 A cross-sectional schematic diagram of the structure obtained after etching the target material layer of the target layer in some embodiments;

[0030] Figure 6A cross-sectional view of a structure after forming a double-stepped staircase structure in some embodiments;

[0031] Figure 7 A cross-sectional view of a structure after forming an isolation spacer in some embodiments;

[0032] Figure 8 A cross-sectional view of a structure after forming a single-stepped staircase structure in some embodiments;

[0033] Figure 9 A cross-sectional view of a structure after forming an isolation structure in some embodiments;

[0034] Figure 10 A cross-sectional view of a structure after forming an isolation structure in some other embodiments;

[0035] Figure 11 A perspective view of a structure after patterning a target material layer in some embodiments;

[0036] Figure 12 A top view of a semiconductor structure in some embodiments;

[0037] Figure 13 A flowchart of another method of fabricating a semiconductor structure in some embodiments;

[0038] Figure 14 A cross-sectional view of a structure after forming a mask structure in some embodiments;

[0039] Figure 15 A cross-sectional view of a structure after forming a patterned stack structure in some embodiments;

[0040] Figure 16 A cross-sectional view of a structure after forming an insulating structure in some embodiments;

[0041] Figure 17 A cross-sectional view of a structure after etching an insulating structure around sidewalls of an array of cells in some embodiments;

[0042] Figure 18 A cross-sectional view of a structure after forming a support frame in some embodiments;

[0043] Figure 19 A cross-sectional view of a structure after forming a hard mask layer in some embodiments;

[0044] Figure 20A cross-sectional view of a structure after etching the layers of support material exposed in the first etch hole for some embodiments;

[0045] Figure 21 A cross-sectional view of a structure after removing the hard mask layer for some embodiments;

[0046] Figure 22 A cross-sectional view of a structure after forming a high-k dielectric material layer and a second electrode material layer for some embodiments;

[0047] Figure 23 A cross-sectional view of a structure after forming a high-k dielectric layer and a second electrode layer for some embodiments;

[0048] Figure 24 A cross-sectional view of a structure after forming a planarization layer for some embodiments;

[0049] Figure 25 A cross-sectional view of a structure after forming a word line hole for some embodiments;

[0050] Figure 26 A cross-sectional view of a structure after forming a transistor housing slot for some embodiments;

[0051] Figure 27 A cross-sectional view of a structure after forming a transistor and a word line for some embodiments;

[0052] Figure 28 A cross-sectional view of a structure after forming a via for some embodiments;

[0053] Figure 29 A cross-sectional view of a structure after forming a bit line lead for some embodiments.

[0054] BRIEF DESCRIPTION OF DRAWINGS

[0055] 1-substrate, 2-laminated structure, 21-target material layer, 22-support material layer, G-etching groove, 3-sacrificial material layer, 4-staircase structure, 41-first step, 42-second step, 5-isolation spacer, 6-isolation structure, A-array region, B-peripheral region, C-capacitor, 71-first electrode, 72-second electrode, 720-second electrode material layer, 721-second electrode conductive layer, 722-polysilicon layer, 73-high-K dielectric layer, 730-high-K dielectric material layer, T-transistor, 81-gate, 82-gate dielectric layer, 83-semiconductor layer, BL-bit line, CBL-common bit line, WL-word line, 9-mask structure, 91-photoresist pattern layer, 92-first anti-reflection layer, 93-mask material layer, 94-second anti-reflection layer, 10-array unit, 101-conductive branch, 11-insulation structure, 111-nitride layer, 112-oxide layer, 12-support frame, 13-hard mask layer, 14-first protective layer, 15-first etching hole, 16-second protective layer, 17-planarization layer, 18-word line hole, 19-third protective layer, S-transistor accommodating groove, 20-insulation sealing layer, H-via, CT-bit line lead, CT1-seed layer, CT2-metal wire. DETAILED DESCRIPTION

[0056] For the purpose of facilitating the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the accompanying drawings. In the drawings, preferred embodiments of the present disclosure are shown. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure.

[0058] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In addition, it will be understood that when a term is used in the singular, it can be intended to include the plural, unless the context clearly indicates otherwise. It will be understood that the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections but do not to limit the scope, applicability or configuration thereof. The terms "first," "second," "third," etc. are generally only used to distinguish one element or action from another, and do not necessarily indicate an order of importance, priority, or sequence. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0059] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0060] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

[0061] In three-dimensional memory, a staircase structure based on metal-oxide stack structure is widely concerned. The staircase structure can be formed by alternately stacking a plurality of insulating layers and a plurality of conductive layers, so as to lead out the signal line connected to the corresponding layer of memory cells by using any conductive layer, thereby solving the problem that the signal line is difficult to lead out after the three-dimensional stacking of memory cells.

[0062] In the current manufacturing method, the step partition needs to be manufactured by adjusting and etching multiple cycles, and the staircase structure needs to be formed by multiple replication etching processes. However, as the number of stacked layers of memory cells in three-dimensional memory increases, the staircase structure manufacturing method which needs to be repeated multiple times also tends to be more complex, and therefore a more efficient staircase structure manufacturing method needs to be developed.

[0063] Based on this, some embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, which is conducive to reducing the complexity of the process procedure and realizing efficient manufacturing of the stepped structure.

[0064] In the first aspect, referring to Figure 1 Some embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, which includes the following steps S100-S400.

[0065] S100, referring to Figure 2 A substrate 1 is provided, and a laminated structure 2 is formed on one side of the substrate 1. The laminated structure 2 includes: a plurality of target material layers 21 stacked in a direction perpendicular to the substrate 1, and a support material layer 22 located between any two adjacent target material layers 21.

[0066] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductor material, or any combination of the material types thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) or a silicon germanium-on-insulator, etc.

[0067] For example, referring to Figure 2 The laminated structure 2 starts to stack with the support material layer 22.

[0068] It should be noted that the laminated structure 2 can also start to stack with the target material layer 21, and the present disclosure does not limit this.

[0069] In some examples, the target material layer 21 includes a metal material layer or a semiconductor material layer.

[0070] For example, the target material layer 21 can be W, and can also be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, and Co-based alloy, Fe-based alloy, Ni-based alloy, FeNi-based alloy, CoNi-based alloy, FeCo-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, low-carbon steel, stainless steel, or conductive metal nitride (e.g., titanium nitride TiN), conductive metal silicide, conductive metal carbide, conductive doped semiconductor (e.g., doped polysilicon), conductive metal oxide semiconductor (e.g., indium tin oxide), and other conductive materials, and can also be SiNx, doped polysilicon, amorphous silicon, doped polysilicon germanium, AsGa, AlAsGa, InP, and other semiconductors or dielectric materials.

[0071] For example, the support material layer 22 can be SiO2 material, and can also be SiNx, AlOx, HfOx, TiOx, SiOxNy, SiOxCzNy, or other insulating materials.

[0072] In some embodiments, the thicknesses of the plurality of target material layers 21 can be the same or different, the thicknesses of the plurality of support material layers 22 can be the same or different, and the thicknesses of the target material layers 21 and the support material layers 22 can be set according to specific process requirements. In addition, the stack structure 2 can include a plurality of pairs of target material layers 21 and support material layers 22 alternately stacked. For example, the stack structure 2 can include 3 pairs, 6 pairs, 32 pairs, 64 pairs, 128 pairs, or more than 128 pairs of target material layers 21 and support material layers 22. It should be noted that although specific numbers of pairs of target material layers 21 and support material layers 22 are exemplified here, other numbers of pairs of target material layers 21 and support material layers 22 can also be used in other embodiments, which are not limited in the present disclosure.

[0073] S200, please continue to refer to Figure 2 , etching the stack structure 2 in the direction perpendicular to the substrate 1 to form an etching groove G extending in the first direction (e.g., the Z direction).

[0074] In some embodiments, please continue to refer to Figure 2 , the etching groove G can extend through the stack structure 2 and to the substrate 1, or can only extend through some pairs of target material layers 21 and support material layers 22 of the stack structure 2. It should be noted that in the embodiments of the present disclosure, the number of steps in the final formed step structure 4 is less than or equal to the number of pairs of target material layers 21 and support material layers 22 through which the etching groove G extends.

[0075] For example, the etching groove G can be formed by dry etching based on a mask.

[0076] S300, please continue to see Figure 2 , to form a sacrificial material layer 3 in the etched trench G.

[0077] For example, the sacrificial material layer 3 can be a metal nitride layer, such as titanium nitride (TiN) or silicon nitride (SiN).

[0078] For example, the sacrificial material layer 3 is formed by a deposition process, including but not limited to physical vapor deposition, chemical vapor deposition, epitaxial deposition or atomic layer deposition process, etc.

[0079] For example, after forming the sacrificial material layer 3 in the etched trench G, the method of manufacturing the semiconductor structure further comprises: using a grinding process to make the surface of the sacrificial material layer 3 away from the substrate 1 and the surface of the stack structure 2 away from the substrate 1 flush, the grinding process includes but is not limited to chemical mechanical polishing (CMP) process.

[0080] S400, please see Figure 2 and Figure 6 , the target material layer 21 of the target layer is exposed, and the target material layer 21 of the target layer is exposed. Figure 2 The target material layer 21 of the target layer is exposed, and the target material layer 21 of the target layer is exposed. Figure 6 The target material layer 21 of the target layer is exposed, and the target material layer 21 of the target layer is exposed.

[0081] For example, the etching rate between the target material layer 21 and the sacrificial material layer 3 is different.

[0082] For example, the target material layer 21 and the support material layer 22 have a high etching selectivity, which is easy to avoid or reduce the etching damage of the support material layer 22 while etching the target material layer 21.

[0083] In some embodiments, please see Figure 3 , a target process includes steps S410~S420.

[0084] S410, please see Figure 4 , the target height of the sacrificial material layer 3 is etched and removed along the direction perpendicular to the substrate 1, and the sidewall of the target material layer 21 of the target layer is exposed.

[0085] In some examples, the sacrificial material layer 3 is etched by anisotropic etching process.

[0086] For example, the anisotropic etching process can be a dry etching process, such as radio frequency plasma source dry etching process.

[0087] For example, please refer to Figure 4 The target height can be 50 nm, 100 nm, or 200 nm, etc. For example, the target height is 100 nm.

[0088] For example, the target height can be the sum of the height (i.e. the size in the vertical substrate 1 direction) of the target material layer 21 and the support material layer 22.

[0089] In some embodiments, the target material layer 21 and the sacrificial material layer 3 have different etching rates, which facilitates separate etching of the target material layer 21 and the sacrificial material layer 3.

[0090] S420, please refer to Figure 5 The target material layer 21 of the target layer is etched along the parallel substrate 1 direction, and each target material layer 21 exposed to the side of the target layer away from the substrate 1 is etched from top to bottom along the parallel substrate 1 direction at the same time.

[0091] In some examples, the etching width of the target material layer 21 of the target layer can be determined by matching the width of the step to be formed. For example, the etching width can be 300 nm, 500 nm, or 700 nm, etc. For example, the target width includes but is not limited to 500 nm. Thus, by adjusting the etching width of the target material layer 21 of the target layer, the width of the corresponding step in the step structure 4 can be controlled correspondingly.

[0092] It is worth mentioning that in the embodiments of the present disclosure, the width of each step in the step structure 4 can also be controlled by one or more of the following ways: adjusting the etching selectivity ratio of each target material layer 21 relative to the sacrificial material layer 3, adjusting the thickness of the support material layer 22, or adjusting the width of the etching groove G.

[0093] In some examples, the target material layer 21 is etched by a wet etching process; the etching selectivity ratio of the target material layer 21 to the sacrificial material layer 3 is greater than or equal to 10:1.

[0094] For example, the etching selectivity ratio of the target material layer 21 to the sacrificial material layer 3 is 10:1, 15:1, or 20:1.

[0095] In some examples, the target material layer 21 is etched by a remote plasma source etching process; the etching selectivity ratio of the target material layer 21 to the sacrificial material layer 3 is greater than 1:1 and less than or equal to 5:1.

[0096] For example, the etching selectivity ratio of the target material layer 21 to the sacrificial material layer 3 is 1.5:1, 2:1, 3:1, 4:1, or 5:1.

[0097] For example, the target material layer 21 is etched by a remote plasma source etching process. The reaction gas of the plasma source can be a mixed gas of nitrogen trifluoride gas (NF3), helium (He) and chlorine (Cl2). The volume ratio of the nitrogen trifluoride gas to the chlorine gas can be 1:5-2:5, and the volume ratio of the helium to the sum of the volume of the nitrogen trifluoride and the chlorine can be 1:3-1:1.

[0098] In some examples, the target material layer 21 can be etched by a vapor etching process.

[0099] It should be noted that the target material layer 21 is etched by an isotropic etching process. It should be noted that in the isotropic etching process, the etching rate in all directions is the same when etching the same material.

[0100] In some embodiments, referring to Figure 6 , step S420 further includes: S421, symmetrically etching each target material layer 21 on both sides of the etching groove G in the second direction (for example, the X direction) to form a double-step staircase structure 4 symmetrically arranged around the etching groove G.

[0101] In some embodiments, before forming the stack structure 2 on one side of the substrate 1 in step S100, the following step S110 is further included.

[0102] S110, referring to Figure 7 , forming an isolation barrier 5 on one side of the substrate 1.

[0103] Correspondingly, referring to Figure 7 , the stack structure 2 is formed on one side of the isolation barrier 5 in step S100; and the etching groove G exposes the side wall of the isolation barrier 5 facing the stack structure 2 in step S200.

[0104] For example, the isolation barrier 5 can be made of the same material as the support material layer 22.

[0105] For example, the isolation barrier 5 can be SiO2 material, and can also be SiNx, AlOx, HfOx, TiOx, SiOxNy, SiOxCzNy or other insulating materials.

[0106] In some examples, referring to Figure 8 , step S420 further includes: S422, etching each target material layer 21 on the side of the etching groove G in the second direction (for example, the X direction) away from the isolation barrier 5 to form a single-step staircase structure 4 on the side of the etching groove G in the second direction (for example, the X direction) away from the isolation barrier 5.

[0107] In some embodiments, after step S400, the method for manufacturing the semiconductor structure further comprises the following step S500a or S500b.

[0108] S500a, please refer to Figure 9 to form the isolation structure 6 filling the etching groove G and the etching removal region of each target material layer 21.

[0109] S500b, please refer to Figure 10 to etch the adjacent support material layer 22 respectively as a mask of each first step 41, so that the reserved part of each support material layer 22 corresponds to form a second step 42; form the isolation structure 6 filling the etching groove G and the etching removal region of each target material layer 21 and each support material layer 22.

[0110] For example, in step S500b, etching the adjacent support material layer 22 respectively as a mask of each first step 41 can adopt a dry etching process.

[0111] For example, the isolation structure 6 can be made of the same material as the support material layer 22.

[0112] For example, the isolation structure 6 can be SiO2 material, and can also be SiNx, AlOx, HfOx, TiOx, SiOxNy, SiOxCzNy or other insulating materials.

[0113] In some embodiments, please refer to Figure 11 The semiconductor structure includes an array region A and a peripheral region B. The step structure 4 can be arranged in the peripheral region B. The semiconductor structure further includes a plurality of array units 10 distributed in the array region A.

[0114] It should be noted that the distribution position, distribution number and step stacking number of the step structure 4 in the semiconductor structure in the embodiments of the present disclosure can be matched with the demand setting. The embodiments of the present disclosure do not limit this.

[0115] In some embodiments, after step S500a or S500b, the method for manufacturing the semiconductor structure further comprises the following step S600.

[0116] S600, please continue to refer to Figure 11 to pattern the target material layer 21, form a common bit line CBL connected with each first step 41 respectively, and a bit line BL connected with the common bit line CBL. Wherein, the common bit line CBL extends along the second direction (for example, the X direction).

[0117] For example, the common bit line CBL, the bit line BL and the first step 41 can be an integral structure.

[0118] In some embodiments, please refer toFigure 12 The array unit 10 includes a transistor T and a capacitor C. The transistor T includes a gate 81, a gate dielectric layer 82 surrounding a sidewall of the gate 81, and a semiconductor layer 83. The gate 81 is electrically connected with a word line WL. The semiconductor layer 83 can be used as a channel region and source / drain of the transistor T. The semiconductor layer 83 is electrically connected with a bit line BL and a first electrode 71 of the capacitor C respectively at opposite outer walls of the semiconductor layer 83 in the X direction. The word line WL can extend in a direction perpendicular to the substrate 1. The bit line BL can extend in a third direction (e.g., the Y direction). A plurality of array units 10 can be arranged in columns in the third direction (e.g., the Y direction). The third direction intersects the second direction.

[0119] For example, a column of array units 10 share a same bit line BL.

[0120] For example, two adjacent columns of array units 10 are respectively located at two sides of the bit line BL and share a same bit line BL.

[0121] For example, each bit line BL can be electrically connected with a common bit line CBL in a same layer through a corresponding selection transistor (not shown in the figure) in the same layer. Here, the same layer means that the two have substantially the same height from the surface of the substrate 1. Figure 12 For example, each bit line BL can be electrically connected with a common bit line CBL in a same layer through a corresponding selection transistor (not shown in the figure) in the same layer. Here, the same layer means that the two have substantially the same height from the surface of the substrate 1.

[0122] It is to be noted that in some embodiments, each first step 41 in the stepped structure 4 can be an external terminal of the corresponding common bit line CBL and be led out through the lead line CT.

[0123] It is to be noted that some embodiments below illustrate the preparation of each array unit 10 in the array region A of the semiconductor structure.

[0124] In some examples, referring to Figure 13 , the method for preparing the semiconductor structure further includes the following steps S710-S716.

[0125] S701, please understand in combination with Figure 12 and Figure 14 that the mask structure 9 formed above the stack structure 2 includes a photoresist pattern layer 91, a first anti-reflection layer 92, a mask material layer 93, and a second anti-reflection layer 94 stacked from top to bottom.

[0126] For example, the first anti-reflection layer 92 can be a silicon oxynitride (SiON) layer.

[0127] For example, the mask material layer 93 can be a carbide layer.

[0128] For example, the second anti-reflection layer 94 can be a nitride layer, such as silicon nitride (SiN).

[0129] S702, please understand in combination withFigure 12 and Figure 15 It is understood that based on the photoresist pattern layer 91, the underlying structure is etched, and polished to expose the upper surface of the second anti-reflective layer 94 away from the substrate 1, to obtain a patterned stack structure 2, form an array unit 10, and make the target material layer 21 remaining in the array unit 10 contain a bit line BL extending in a first direction, and a plurality of conductive branches 101 spaced apart in the first direction (e.g. Z direction) and extending outside the bit line BL in a second direction (e.g. X direction).

[0130] For example, the stack structure 2 can be etched by a photolithography process.

[0131] S703, please combine Figure 12 and Figure 16 It is understood that the insulating structure 11 covering the stack structure 2 and filling the etched region of the stack structure 2 is formed, and the insulating structure 11, for example, includes a laminated nitride layer 111 and an oxide layer 112.

[0132] For example, the nitride layer 111 can be a silicon nitride (SiN) layer.

[0133] For example, the oxide layer 112 can be a silicon oxide (SiO) layer.

[0134] S704, please combine Figure 12 and Figure 17 It is understood that the insulating structure 11 on the sidewall of the array unit 10 is etched to expose the sidewall of each target material layer 21.

[0135] S705, please combine Figure 12 and Figure 18 It is understood that a support frame 12 is formed in the etched region of the insulating structure 11, and polished to expose the top support material layer 22 of the stack structure 2.

[0136] For example, the support frame 12 can be formed of silicon nitride (SiN).

[0137] S705, please combine Figure 12 and Figure 19 It is understood that a hard mask layer 13 is formed covering the stack structure 2.

[0138] In some examples, please refer to Figure 19 Before forming the hard mask layer 13 in step S705, a first protective layer 14 covering the top support material layer 22 in the stack structure 2 can also be formed, and the hard mask layer 13 is formed away from the surface of the first protective layer 14. substrate 1.

[0139] For example, the first protective layer 14 can be a silicon nitride (SiN) layer.

[0140] S706, please combineFigure 12 and Figure 19 In the (b) figure and the (d) figure of

[0141] For example, the hard mask layer 13 can be a poly layer.

[0142] S707, please combine Figure 12 and Figure 20 understand that the etching exposes each support material layer 22 in the first etching hole 15, so that the exposed end of the corresponding conductive branch 101 is away from the bit line BL, and the exposed end constitutes the first electrode 71 of the capacitor C.

[0143] For example, each support material layer 22 exposed in the first etching hole 15 can be etched by a wet etching process.

[0144] S708, please combine Figure 12 and Figure 21 understand that the hard mask layer 13 is removed.

[0145] In some examples, the capacitor C further includes a high-K dielectric layer 73 and a second electrode 72. The method for manufacturing the semiconductor structure further includes steps S709-S710.

[0146] S709, please combine Figure 12 and Figure 22 understand that the high-K dielectric material layer 730 covering the first electrode 71 is formed, and the second electrode material layer 720 covering the high-K dielectric material layer 730 and filling the removed area of each support material layer 22 and the first etching hole 15 is formed.

[0147] In some examples, the second electrode material layer 720 and the second electrode 72 each include a second electrode conductive layer 721 and a poly layer 722 arranged in a stack, wherein the second electrode conductive layer 721 covers the high-K dielectric layer 73, and the poly layer 722 covers the second electrode conductive layer 721.

[0148] For example, the material of the second electrode conductive layer 721 can be titanium (Ti) or titanium nitride (TiN).

[0149] S710, please combine Figure 12 and Figure 23 understand that the high-K dielectric material layer 730 and the second electrode material layer 720 are patterned to obtain the high-K dielectric layer 73 and the second electrode 72.

[0150] It should be noted that please refer to Figure 23Before patterning the high-K dielectric material layer 730 and the second electrode material layer 720, a second protective layer 16 can be formed to cover the surface of the second electrode 72 facing away from the substrate 1; correspondingly, after patterning the high-K dielectric material layer 730 and the second electrode material layer 720, the surface of the second electrode 72 facing away from the substrate 1 which is not etched is covered with the second protective layer 16.

[0151] S711, please combine Figure 12 and Figure 24 It is understood that the planarization layer 17 is formed in the etched region of the high-K dielectric material layer 730 and the second electrode material layer 720.

[0152] In some examples, the surface of the planarization layer 17 facing away from the substrate 1 is flush with the surface of the second protective layer 16 facing away from the substrate 1.

[0153] For example, the planarization layer 17 can be an oxide layer, such as a silicon oxide (SiO) layer.

[0154] S712, please combine Figure 12 and Figure 25 It is understood that the word line hole 18 is formed between the first electrode 71 and the bit line BL, and penetrates the corresponding conductive branch 101 in the vertical direction of the substrate 1.

[0155] It should be noted that, referring to Figure 25 Before forming the word line hole 18, a third protective layer 19 can be formed to cover the surface of the planarization layer 17 and the second protective layer 16 facing away from the substrate 1; correspondingly, after forming the word line hole 18, the surface of the planarization layer 17 and the second protective layer 16 facing away from the substrate 1 which is not etched is covered with the third protective layer 19.

[0156] S713, please combine Figure 12 and Figure 26 It is understood that the transistor accommodating groove S is formed based on etching the corresponding conductive branch 101 according to the word line hole 18.

[0157] For example, the etching of each conductive branch 101 based on the word line hole 18 can adopt an isotropic etching process, such as wet etching (Wet etch), isotropic dry remote plasma source (RPS) etching or vapor etching.

[0158] S714, please combine Figure 12 and Figure 27 It is understood that the semiconductor layer 83, the gate dielectric layer 82 covering the inner wall of the transistor accommodating groove S, and the word line WL covering the gate dielectric layer 82 and filling the word line hole 18 are formed.

[0159] It should be noted that, referring to Figure 27As shown in (a1) of FIG. 1, the transistor T includes a gate 81, a gate dielectric layer 82 surrounding the sidewall of the gate 81, and a semiconductor layer 83. The gate 81 is electrically connected to the word line WL.

[0160] At S715, referring to Figure 27 , an insulating cap layer 20 is formed on top of the second electrode 72, the word line WL, and the planarization layer 17.

[0161] For example, the insulating cap layer 20 can be an oxide layer, such as a silicon oxide (SiO) layer.

[0162] In some embodiments, the method for manufacturing the semiconductor structure further includes steps S810-S820.

[0163] At S810, referring to Figure 12 and Figure 28 , it is understood that the via hole H is formed through the isolation structure 6 away from the surface of the substrate 1.

[0164] It is noted that, for the purpose of clearly showing the via hole H, Figure 28 the isolation structure 6 is not shown in FIG. 1, but it is understood that, as to the position of the isolation structure 6 in the semiconductor structure and the structure of the isolation structure 6, etc., reference can be made to the related examples in Figure 9 or Figure 10 .

[0165] At S820, referring to Figure 12 and Figure 29 , it is understood that the bit line lead CT is formed in the via hole H.

[0166] In some examples, the bit line lead CT includes a seed layer CT1 and a metal wire CT2, wherein the seed layer CT1 covers the via hole H, and the metal wire CT2 covers the seed layer CT1 and fills the via hole H.

[0167] For example, the material of the seed layer CT1 includes titanium (Ti) or titanium nitride (TiN).

[0168] For example, the metal wire CT2 can be made of the same material as the target material layer 21, such as tungsten (W).

[0169] As to the regulation of the etching selectivity ratio mentioned in some embodiments of the present disclosure, some possible solutions are listed as follows.

[0170] In some embodiments, the etching selectivity ratio can be regulated by using different etchants and / or different infrared heating time.

[0171] In some examples, the etching selectivity ratio of the target material layer 21 and the sacrificial material layer 3 can be controlled by using different etchants.

[0172] For example, the etchant can be a mixture of nitrogen trifluoride (NF3) and oxygen (O2), a mixture of sulfur hexafluoride (SF6), oxygen (O2) and argon (Ar), a mixture of trifluoromethane (CHF3) and oxygen (O2), or a mixture of difluoromethane (CH2F2), oxygen (O2) and argon (Ar).

[0173] In some examples, the etching selectivity ratio of the target material layer 21 and the sacrificial material layer 3 can be controlled by using different infrared heating times.

[0174] In a second aspect, the present disclosure also provides a semiconductor structure according to some embodiments. It should be noted that the semiconductor structure manufactured by the method described above has the technical advantages of the method, and the structure also has the same or corresponding technical features as the above embodiments. For details, please refer to the corresponding description of the corresponding technical features in the above embodiments, which will not be described in detail here.

[0175] In some embodiments, referring to Figure 2 , the semiconductor structure includes a substrate 1, a stack structure 2 and a sacrificial material layer 3. The stack structure 2 is located on one side of the substrate 1 and includes a plurality of target material layers 21 stacked in a direction perpendicular to the substrate 1, and a support material layer 22 located between any two adjacent target material layers 21. The stack structure 2 has an etching trench G extending in a first direction (for example, the Z direction). The sacrificial material layer 3 fills the etching trench G.

[0176] In some examples, each target material layer 21 and the sacrificial material layer 3 are configured to form a reserved portion of each target material layer 21 corresponding to a first step 41 after the target process is performed multiple times in a cycle, and a plurality of first steps 41 are arranged as a staircase structure 4 (as shown in Figure 6 ) in a second direction. The second direction intersects the first direction. The target process includes etching and removing the sacrificial material layer 3 in a target height in a direction perpendicular to the substrate 1 to expose the sidewall of the target material layer 21 of the target layer; etching the target material layer 21 of the target layer in a direction parallel to the substrate 1, and simultaneously etching each target material layer 21 exposed on the side of the target layer away from the substrate 1 in a direction parallel to the substrate 1 from top to bottom.

[0177] In some embodiments, referring to Figure 7 , the semiconductor structure further includes an isolation barrier 5 located on one side of the stack structure 2 in a direction parallel to the substrate 1. The sacrificial material layer 3 is located between the isolation barrier 5 and the stack structure 2.

[0178] It should be noted that the etching trench G exposes the sidewall of the isolation barrier 5 towards the stack structure 2, and the sacrificial material layer 3 fills the etching trench G and is located between the isolation barrier 5 and the stack structure 2.

[0179] In some examples, the etching rates between the target material layer 21 and the sacrificial material layer 3 are different.

[0180] In some examples, the etching rates between the target material layer 21 and the support material layer 22 are different.

[0181] Thirdly, this disclosure also provides a memory according to some embodiments. It should be noted that the memory also possesses the technical advantages of the aforementioned semiconductor structure and its manufacturing method. For the parts that are the same as or corresponding to those in the above embodiments, please refer to the corresponding descriptions in the above embodiments, which will not be described in detail below.

[0182] In some embodiments, the memory includes at least one stepped structure 4. The stepped structure 4 is obtained by etching a semiconductor structure as described in the second aspect of the present disclosure, and the stepped structure 4 includes at least a plurality of first steps 41.

[0183] In some embodiments, please combine Figure 12 and Figure 29 The memory also includes: multiple common bit lines CBL, multiple bit lines BL, and multiple bit line leads CT. The common bit lines CBL are connected to the first step 41, and the bit lines BL are connected to the common bit lines CBL. The connected first step 41, common bit lines CBL, and bit lines BL are portions of the same target material layer 21 located in different regions. The bit line leads CT are located on the surface of the first step 41 away from the substrate 1 and extend along a direction perpendicular to the substrate 1.

[0184] It should be noted that here, please refer to Figure 11 The first step 41, the common bit line CBL, and the bit line BL are different parts of the same target material layer 21 located in different regions. This means that the first step 41, the common bit line CBL, and the bit line BL of the same layer can be obtained by patterning the corresponding target material layer 21.

[0185] Fourthly, this disclosure also provides an electronic device according to some embodiments. This includes the memory described in the third aspect of the embodiments of this disclosure. It should be noted that this electronic device also possesses the technical advantages of the aforementioned semiconductor structure and its manufacturing method, as well as the memory. For parts that are the same as or corresponding to those in the above embodiments, please refer to the corresponding descriptions in the foregoing embodiments; detailed descriptions will not be repeated below.

[0186] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0187] The above embodiments only express several implementation manners of the present disclosure, which are described in a more specific and detailed manner, but cannot be understood as a limitation on the scope of the patent. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, which are all within the protection scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The application relates to a manufacturing method of a memory device, comprising the following steps: providing a substrate, and forming a stack structure on one side of the substrate; the stack structure comprises a plurality of target material layers stacked along a vertical substrate direction, and a support material layer between any two adjacent target material layers; etching the stack structure along the vertical substrate direction to form an etching groove extending along a first direction; forming a sacrificial material layer in the etching groove; performing a plurality of target processes on the obtained structure after forming the sacrificial material layer to make the remaining part of each target material layer correspondingly form a first step, and the plurality of first steps are arranged as a step structure along a second direction intersecting the first direction; wherein one target process comprises the following steps: etching and removing the sacrificial material layer with a target height along the vertical substrate direction to expose the sidewall of the target material layer of a target layer; etching the target material layer of the target layer along a parallel substrate direction, and synchronously etching each target material layer exposed on the side of the target layer away from the substrate from top to bottom along the parallel substrate direction.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein The etching rate of the target material layer is different from that of the sacrificial material layer.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein The target material layer is etched by a wet etching process, and the etching selectivity ratio of the target material layer to the sacrificial material layer is greater than or equal to 10:

1.

4. The method of manufacturing a semiconductor structure according to claim 1, wherein The target material layer is etched by a remote plasma source etching process, and the etching selectivity ratio of the target material layer to the sacrificial material layer is greater than 1:1 and less than or equal to 5:

1.

5. The method of manufacturing a semiconductor structure according to claim 1, wherein The sacrificial material layer is etched by an anisotropic etching process.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein The etching the target material layer of the target layer along a parallel substrate direction, and synchronously etching each target material layer exposed on the side of the target layer away from the substrate from top to bottom along the parallel substrate direction further comprises the following steps: symmetrically etching each target material layer on the two opposite sides of the etching groove in the second direction to form the step structure symmetrically arranged around the etching groove.

7. The method of manufacturing a semiconductor structure according to claim 1, wherein Further comprising the following steps: forming an isolation barrier wall on one side of the substrate; wherein the stack structure is formed on one side of the isolation barrier wall, and the etching groove exposes the sidewall of the isolation barrier wall towards the stack structure.

8. The method of manufacturing a semiconductor structure according to any one of claims 1 to 7, wherein The target material layer comprises a metal material layer or a semiconductor material layer; The manufacturing method further comprises the following steps: patterning the target material layer to form a common bit line connected with each first step respectively, and a bit line connected with the common bit line; wherein the common bit line extends along the second direction.

9. The method of manufacturing a semiconductor structure according to claim 8, wherein Further comprising the following steps: forming an isolation structure filling the etching groove and the etching removal region of each target material layer; or, etching the adjacent support material layer with each first step as a mask to make the remaining part of each support material layer correspondingly form a second step; and forming an isolation structure filling the etching groove and the etching removal region of each target material layer and each support material layer.

10. The method of manufacturing a semiconductor structure according to claim 9, wherein Further comprising the following steps: forming a via penetrating through the isolation structure at least on the surface of the first step away from the substrate; forming a bit line lead in the via.

11. A semiconductor structure, characterized by The application further relates to a memory device, comprising the following steps: a substrate; A stack structure is located on one side of the substrate, and includes a plurality of target material layers stacked along a vertical substrate direction, and a support material layer located between any two adjacent target material layers; the stack structure has an etching trench extending along a first direction; A sacrificial material layer is filled in the etching trench; Each target material layer and the sacrificial material layer are configured to form a reserved portion of each target material layer corresponding to a first step after a target process is performed multiple times in a cycle, and a plurality of first steps are arranged as a staircase structure along a second direction; the second direction intersects the first direction; The target process includes: etching and removing the sacrificial material layer with a target height along the vertical substrate direction to expose a sidewall of the target material layer of a target layer; etching the target material layer of the target layer along the parallel substrate direction, and synchronously etching each target material layer exposed on a side of the target layer away from the substrate from top to bottom along the parallel substrate direction.

12. The semiconductor structure of claim 11, wherein, Further comprising: An isolation barrier wall is located on one side of the stack structure along a direction parallel to the substrate; The sacrificial material layer is located between the isolation barrier wall and the stack structure.

13. A memory, comprising: Comprising: At least one staircase structure; wherein the staircase structure is obtained by etching the semiconductor structure of claim 11 or 12, and the staircase structure at least includes a plurality of first steps.

14. The memory of claim 13, wherein, Further comprising: A plurality of common bit lines, a plurality of bit lines, and a plurality of bit line leads; The common bit line is connected to the first step, the bit line is connected to the common bit line, and the connected first step, common bit line and bit line are respectively parts of the same target material layer located in different regions; the bit line lead is located on the surface of the first step away from the substrate and extends along the vertical substrate direction.

15. An electronic device, comprising: Comprising: The memory of claim 13 or 14.

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