Semiconductor memory device

Abstract

A semiconductor memory device is provided herein. The semiconductor memory device includes: a stack including conductive patterns and interlayer insulating layers alternately stacked; a lower channel portion passing through the stack; a memory layer disposed between the stack and the lower channel portion; an upper channel portion disposed on the lower channel portion; a gate insulating layer surrounding sidewalls of the upper channel portion; a first gate pattern surrounding a sidewall of the gate insulating layer; a separation insulating pattern contacting a first portion of the first gate pattern; and a second gate pattern contacting a second portion of the first gate pattern.

Description

[0001] This application is a divisional application of the invention patent application with the original application number 202111160644.3 (application date: September 30, 2021, invention title: Semiconductor Memory Device and Method of Manufacturing the Same). Technical Field

[0002] Various embodiments of the present disclosure relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more particularly, to a three-dimensional (3D) semiconductor memory device and a method of manufacturing a 3D semiconductor memory device. Background Art

[0003] In order to increase the integration degree of a semiconductor memory device, a three-dimensional (3D) semiconductor memory device has been proposed. The 3D semiconductor memory device may include memory cells arranged three-dimensionally. The memory cells of the 3D semiconductor memory device may be stacked in a longitudinal direction of a channel structure. The channel structure may be connected to a bit line and a source line under the control of a select transistor. Summary of the Invention

[0004] Embodiments of the present disclosure may provide a method of manufacturing a semiconductor memory device. The method of manufacturing a semiconductor memory device may include the steps of: forming a stack; forming a channel hole penetrating the stack; forming a memory layer on sidewalls of the channel hole; forming a lower channel portion in the channel hole; forming an upper channel portion on the lower channel portion; forming a gate insulating layer surrounding sidewalls of the upper channel portion; forming a first gate pattern surrounding sidewalls of the gate insulating layer; forming a separation insulating pattern contacting a first sidewall of the first gate pattern; and forming a second gate pattern contacting a second sidewall of the first gate pattern.

[0005] Embodiments of the present disclosure may provide a method of manufacturing a semiconductor memory device. The method of manufacturing a semiconductor memory device may include the steps of: forming a stack penetrated by a lower channel portion; forming an upper channel portion overlapping the lower channel portion; forming a gate insulating layer surrounding sidewalls of the upper channel portion; forming a first gate pattern surrounding sidewalls of the gate insulating layer and arranged in a plurality of rows; forming a separation insulating pattern between a first row of the first gate pattern and a second row of the first gate pattern; forming a conductive layer filling a space between the first gate patterns; and forming second gate patterns separated from each other by etching the conductive layer to expose the separation insulating pattern.

[0006] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a stack including conductive patterns and interlayer insulating layers stacked alternately; a lower channel portion passing through the stack; a memory layer disposed between the stack and the lower channel portion; an upper channel portion disposed on the lower channel portion; a gate insulating layer surrounding sidewalls of the upper channel portion; a first gate pattern surrounding sidewalls of the gate insulating layer; a separation insulating pattern contacting a first portion of the first gate pattern; and a second gate pattern contacting a second portion of the first gate pattern.

[0007] Embodiments of the present disclosure may provide a semiconductor memory device. The semiconductor memory device may include: a separation insulating pattern including a first surface and a second surface facing opposite directions; a first groove formed in the first surface of the separation insulating pattern; a second groove formed in the second surface of the separation insulating pattern; a first linear gate pattern contacting the first surface of the separation insulating pattern and including a third groove facing the first groove; a second linear gate pattern contacting the second surface of the separation insulating pattern and including a fourth groove facing the second groove; a first tubular gate pattern extending along surfaces of the first groove and the third groove; a second tubular gate pattern extending along surfaces of the second groove and the fourth groove; a channel portion inserted into a central region between the first tubular gate pattern and the second tubular gate pattern; and a gate insulating layer disposed between each of the first tubular gate pattern and the second tubular gate pattern and each of the channel portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2A is a perspective view schematically showing a partial region of a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2B is Figure 2A an enlarged cross-sectional view of region A of

[0011] Figure 3A and Figure 3B show embodiments of a layout of a semiconductor memory device at a height where a drain select line is arranged.

[0012] Figure 4 is a cross-sectional view of the semiconductor memory device taken along line I-I' of Figure 3A

[0013] Figure 5A ​It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 5B It is Figure 5A an exploded perspective view of a partial region of the semiconductor memory device.

[0015] Figure 6 It is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 7 It is a plan view showing a stack, a memory layer, and a lower channel portion.

[0017] Figure 8A , Figure 8B and Figure 8C It is a cross-sectional view showing an embodiment of a method for manufacturing a stack, a memory layer, and a lower channel portion.

[0018] Figure 9 and Figure 10 are a plan view and a cross-sectional view showing an embodiment of a method for manufacturing an upper stack and a first mask pattern, respectively.

[0019] Figure 11A , Figure 11B , Figure 11C and Figure 11D It is a cross-sectional view showing an embodiment of a subsequent process to be performed after forming the first mask pattern.

[0020] Figure 12 It is a cross-sectional view showing an embodiment of a subsequent process to be performed after forming an insulating layer.

[0021] Figure 13 It is along Figure 12 the line III-III' taken plan view.

[0022] Figure 14 and Figure 15 are a plan view and a cross-sectional view showing an embodiment of a method for manufacturing a separation insulating pattern, respectively.

[0023] Figure 16 It is a cross-sectional view showing an embodiment of a method for manufacturing a conductive layer.

[0024] Figure 17A , Figure 17B and Figure 17C It is a magnified cross-sectional view showing an embodiment of a subsequent process for the region C shown in Figure 16 .

[0025] Figure 18 It is along Figure 17C the line IV-IV' taken plan view.

[0026] Figure 19 is a plan view showing a first mask pattern, an upper insulating layer, sidewall insulating layers, and a vertical source contact portion.

[0027] Figure 20A , Figure 20B , Figure 20C , Figure 20D and Figure 20E are cross-sectional views showing embodiments of a method of manufacturing the Figure 19 structure.

[0028] Figure 21A , Figure 21B , Figure 21C , Figure 21D and Figure 21E are cross-sectional views showing embodiments of subsequent processes to be performed after forming the Figure 20E structure.

[0029] Figure 22A and Figure 22B are enlarged cross-sectional views showing embodiments of subsequent processes for the region C shown in Figure 16 .

[0030] Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 23E , Figure 23F , Figure 23G and Figure 23H are cross-sectional views showing embodiments of subsequent processes to be performed after the Figure 11D process.

[0031] Figure 24 is a block diagram showing the configuration of a memory system according to an embodiment of the present disclosure.

[0032] Figure 25 is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The descriptions of the specific structures and functions disclosed herein are for the purpose of describing embodiments according to the concepts of the present disclosure only. Embodiments according to the concepts of the present disclosure may be implemented in various forms, and they should not be construed as limited to the specific embodiments set forth herein.

[0034] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another, and do not imply the number or order of the elements.

[0035] Various embodiments of the present disclosure relate to a semiconductor memory device having improved operational reliability and a method of manufacturing the semiconductor memory device.

[0036] Figure 1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0037] Referring to Figure 1 , the memory cell array may include a plurality of memory cell strings CS1 and CS2 coupled to bit lines BL. The plurality of memory cell strings CS1 and CS2 may be commonly coupled to a source line SL. In one embodiment, the plurality of memory cell strings CS1 and the plurality of memory cell strings CS2 may be commonly coupled to the source line SL.

[0038] A pair of a first memory cell string CS1 and a second memory cell string CS2 may be coupled to each of the bit lines BL.

[0039] Each of the first memory cell string CS1 and the second memory cell string CS2 may include a source select transistor SST, a plurality of memory cells MC, and a drain select transistor DST arranged between the source line SL and the corresponding bit line BL.

[0040] The source select transistor SST may control an electrical connection between the plurality of memory cells MC and the source line SL. A single source select transistor SST may be arranged between the source line SL and the plurality of memory cells MC. Although not shown in the figure, two or more serially connected source select transistors may be arranged between the source line SL and the plurality of memory cells MC. The source select transistor SST may be coupled to a source select line SSL. The operation of the source select transistor SST may be controlled in response to a source gate signal applied to the source select line SSL.

[0041] The plurality of memory cells MC may be arranged in series between the source select transistor SST and the drain select transistor DST. The memory cells MC between the source select transistor SST and the drain select transistor DST may be serially connected to each other. The memory cells MC may be respectively coupled to word lines WL. The operation of the memory cells MC may be controlled in response to a cell gate signal applied to the word lines WL.

[0042] The drain select transistor DST may control an electrical connection between the plurality of memory cells MC and the corresponding bit line BL. The drain select transistor DST may be coupled to a drain select line DSL1 or DSL2. The operation of the drain select transistor DST may be controlled in response to a drain gate signal applied to the drain select line DSL1 or DSL2.

[0043] The first memory cell string CS1 can be coupled to the first drain select line DSL1. The second memory cell string CS2 can be coupled to the second drain select line DSL2. Thus, the first memory cell string CS1 or the second memory cell string CS2 can be selected by selecting one of the bit lines BL and one of the first drain select line DSL1 and the second drain select line DSL2.

[0044] The first memory cell string CS1 and the second memory cell string CS2 can be commonly coupled to each word line WL.

[0045] The first memory cell string CS1 and the second memory cell string CS2 can be commonly coupled to the source select line SSL. Embodiments of the present disclosure are not limited thereto. Although not shown in the figures, in one embodiment, the memory cell array may include a first source select line and a second source select line separated from each other. The first source select line may be coupled to the first memory cell string, and the second source select line may be coupled to the second memory cell string.

[0046] Figure 2A is a perspective view schematically showing a partial region of a semiconductor memory device according to an embodiment of the present disclosure.

[0047] Referring to Figure 2A , the semiconductor memory device may include a stack 10, a channel structure, a memory layer 21, a gate insulating layer 35, a first gate pattern 41, a second gate pattern 45, and a separation insulating pattern 43. The channel structure may include a lower channel portion CH1 and an upper channel portion CH2.

[0048] The stack 10 may include a conductive pattern 13 and an interlayer insulating layer 11. Figure 2A A part of the stack 10 is shown. Figure 2A The conductive pattern 13 shown in Figure 1 can be used as the word line WL described above with reference to

[0049] The lower channel portion CH1 may penetrate the stack 10. The memory layer 21 may be disposed between each of the lower channel portions CH1 and the stack 10. Figure 2A A part of each of the lower channel portions CH1 and a part of the memory layer 21 are shown.

[0050] Each of the lower channel portions CH1 may include a channel layer 23, a core insulating layer 25, and a semiconductor pattern 31. The channel layer 23 may extend along the inner wall 21SW of the memory layer 21. The channel layer 23 may include a semiconductor material such as silicon. The core insulating layer 25 and the semiconductor pattern 31 may fill the central region CH1[CO] of each lower channel portion CH1. The core insulating layer 25 may be surrounded by the channel layer 23. The semiconductor pattern 31 may be disposed between the core insulating layer 25 and the corresponding upper channel portion CH2. The semiconductor pattern 31 may include a semiconductor material such as silicon.

[0051] Each of the upper channel portions CH2 may be respectively disposed on each of the lower channel portions CH1. The channel structure of each memory cell string may include a lower channel portion CH1 and an upper channel portion CH2 that are coupled to each other.

[0052] The upper channel portion CH2 may be stably coupled to the lower channel portion CH1 through the semiconductor pattern 31. Each of the upper channel portions CH2 may include a semiconductor material such as silicon. Each of the upper channel portions CH2 may include a first region 33A and a second region 33B. The first region 33A may be formed of a substantially intrinsic semiconductor material. The second region 33B may be a doped region including conductive impurities. In one embodiment, the second region 33B may include n-type impurities.

[0053] The gate insulating layer 35 may surround the corresponding sidewall 33SW of the upper channel portion CH2. Each of the gate insulating layers 35 may include a semiconductor oxide. In one embodiment, each of the gate insulating layers 35 may include silicon oxide.

[0054] The first gate pattern 41 may surround the corresponding sidewall 35SW of the gate insulating layer 35.

[0055] The second gate pattern 45 may include a first linear gate pattern 45L1 and a second linear gate pattern 45L2 that are isolated from each other by a separation insulating pattern 43. The first linear gate pattern 45L1 and the second linear gate pattern 45L2 may extend in parallel. In one embodiment, each of the first linear gate pattern 45L1 and the second linear gate pattern 45L2 may extend in the Y-axis direction.

[0056] The first gate patterns 41 spaced apart from each other may be coupled to each other through the first linear gate pattern 45L1 or the second linear gate pattern 45L2. Some of the first gate patterns 41 that are coupled to the first linear gate pattern 45L1 among the first gate pattern 41 and the first linear gate pattern 45L1 may be used as referred to above Figure 1The first drain selection line DSL1 described above. The second linear gate pattern 45L2 and other first gate patterns 41 among the first gate patterns 41 that are connected to the second linear gate pattern 45L2 can be used as described above with reference to Figure 1 The second drain selection line DSL2 described above.

[0057] The first gate pattern 41 may include a conductive material different from the conductive material type of the second gate pattern 45. In one embodiment, the first gate pattern 41 may include a conductive barrier layer formed of titanium, titanium nitride, or the like. The second gate pattern 45 may include a metal layer formed of tungsten or the like.

[0058] The first gate pattern 41 may include the same type of conductive material as the second gate pattern 45. In one embodiment, the first gate pattern 41 and the second gate pattern 45 may include refractory metals. Refractory metals may include titanium nitride, tantalum nitride, tungsten nitride, and the like.

[0059] The isolation insulating pattern 43 may include a vertical portion 43P1 and a horizontal portion 43P2. The vertical portion 43P1 of the isolation insulating pattern 43 may be disposed between the first linear gate pattern 45L1 and the second linear gate pattern 45L2. The first linear gate pattern 45L1 and the second linear gate pattern 45L2 may be isolated from each other by the vertical portion 43P1 of the isolation insulating pattern 43. The horizontal portion 43P2 of the isolation insulating pattern 43 may extend from the vertical portion 43P1. The horizontal portion 43P2 of the isolation insulating pattern 43 may extend into the space between each of the first linear gate pattern 45L1 and the second linear gate pattern 45L2 and the stack 10. The horizontal portion 43P2 of the isolation insulating pattern 43 may surround the first gate pattern 41.

[0060] Each of the interlayer insulating layer 11 and the conductive pattern 13 may continuously extend in the X-Y plane such that it overlaps with the first linear gate pattern 45L1, the vertical portion 43P1 of the isolation insulating pattern 43, and the second linear gate pattern 45L2.

[0061] The semiconductor memory device may further include an upper insulating layer 47 and conductive contacts 49.

[0062] The upper insulating layer 47 may cover the isolation insulating pattern 43 and the second gate pattern 45. The conductive contacts 49 may be respectively disposed on the upper channel portion CH2. The conductive contacts 49 may be isolated from each other by the upper insulating layer 47.

[0063] Figure 2B is Figure 2A An enlarged cross-sectional view of region A of

[0064] Refer to Figure 2B, the memory layer 21 may include a tunnel insulating layer TL, a data storage layer DL, and a first barrier insulating layer BI1. The first barrier insulating layer BI1 may surround the channel layer 23. The first barrier insulating layer BI1 may extend into Figure 2A the space between the interlayer insulating layer 11T at the uppermost layer of the stack 10 shown and the isolation insulating pattern 43. The data storage layer DL may be disposed between the first barrier insulating layer BI1 and the channel layer 23. The data storage layer DL may include a material capable of capturing charges. In one example, the data storage layer DL may include silicon nitride. The tunnel insulating layer TL may be disposed between the data storage layer DL and the channel layer 23. The tunnel insulating layer TL may include an insulating material capable of enabling charge tunneling. In one embodiment, the tunnel insulating layer TL may include silicon oxide.

[0065] The semiconductor memory device may further include a second barrier insulating layer BI2. The second barrier insulating layer BI2 may be disposed between the first barrier insulating layer BI1 and the conductive pattern 13. The second barrier insulating layer BI2 may extend into the space between each interlayer insulating layer 11 and the corresponding conductive pattern 13. The first barrier insulating layer BI1 and the second barrier insulating layer BI2 may each include an insulating material that blocks charges. The second barrier insulating layer BI2 may include an insulating material having a dielectric constant higher than that of the first barrier insulating layer BI1. In one embodiment, the first barrier insulating layer BI1 may include silicon oxide, and the second barrier insulating layer BI2 may include a metal oxide.

[0066] The first gate pattern 41 may be spaced apart from the channel layer 23 and the semiconductor pattern 31 of each of the lower channel portions CH1. In one embodiment, the gate insulating layer 35 may extend into the space between the first gate pattern 41 and the channel layer 23 of the lower channel portion CH1 and the space between the first gate pattern 41 and the semiconductor pattern 31 of the lower channel portion CH1. In this way, the first gate pattern 41 may be spaced apart from the channel layer 23 and the semiconductor pattern 31 of each of the lower channel portions CH1 through the gate insulating layer 35.

[0067] The gate insulating layer 35 and each of the upper channel portions CH2 may protrude higher than each of the first gate pattern 41 and the second gate pattern 45 in the direction toward the conductive contact portion 49. The upper channel portion CH2 may protrude higher than the gate insulating layer 35 in the direction toward the conductive contact portion 49.

[0068] The width W2 of each conductive contact portion 49 may be formed to be greater than the width W1 of the upper channel portion CH2. In one embodiment, the conductive contact portion 49 may overlap the upper channel portion CH2 and may extend onto the gate insulating layer 35.

[0069] The conductive contact portion 49 may include a groove 49G. The upper portion of the upper channel portion CH2 may be inserted into the groove 49G. Through the conductive contact portion 49, the upper channel portion CH2 may be coupled to the bit line BL described above with reference to Figure 1 the bit line BL.

[0070] Figure 3A and Figure 3B FIG. shows an embodiment of the layout of a semiconductor memory device at the level where the drain select lines are arranged. Figure 3A FIG. shows Figure 2A the layout of a semiconductor memory device in a region wider than the X-Y plane of Figure 3B is a magnified plan view showing Figure 3A region B shown in FIG. Hereinafter, repeated descriptions of overlapping components will be omitted.

[0071] Referring to Figure 3A , the semiconductor memory device may include drain select lines DSL1, DSL2, and DSL3, which are divided into a first group DSL[A] and a second group DSL[B]. The first group DSL[A] and the second group DSL[B] may be disposed on both sides of the vertical source contact portion 53. In one embodiment, the first group DSL[A] may include a first drain select line DSL1 and a second drain select line DSL2, and the second group DSL[B] may include a third drain select line DSL3.

[0072] The vertical source contact portion 53 may include at least one of doped semiconductor, metal, metal silicide, and metal nitride.

[0073] The first group DSL[A] and the second group DSL[B] may be spaced apart from the vertical source contact portion 53. Sidewall insulating layers 51 may cover the sidewalls of the vertical source contact portion 53.

[0074] Each of the first drain select line DSL1, the second drain select line DSL2, and the third drain select line DSL3 may include first gate patterns 41 spaced apart from each other and second gate patterns 45 connecting the first gate patterns 41 to each other. The second gate pattern 45 of the first drain select line DSL1 may be defined as a first linear gate pattern 45L1, and the second gate pattern 45 of the second drain select line DSL2 may be defined as a second linear gate pattern 45L2.

[0075] The drain select lines of each group may be isolated from each other by isolation insulating patterns 43. In one embodiment, the isolation insulating pattern 43 may be disposed between the first drain select line DSL1 and the second drain select line DSL2. The first linear gate pattern 45L1 may be spaced apart from the second linear gate pattern 45L2 by the isolation insulating pattern 43.

[0076] Each of the first gate patterns 41 may be a tubular gate pattern. The gate insulating layer 35 and the upper channel portion CH2 may be inserted into the central region defined by the tubular gate pattern.

[0077] The first gate patterns 41 may be arranged in multiple rows. The row direction may be defined as the extending direction of the second gate pattern 45. In one embodiment, the row direction may be the Y-axis direction. Each of the second gate patterns 45 may couple the first gate patterns 41 arranged in two or more rows to each other. In one embodiment, each of the first linear gate pattern 45L1 and the second linear gate pattern 45L2 may couple the first gate patterns 41 arranged in four rows to each other.

[0078] The isolation insulating pattern 43 may be disposed between two adjacent rows. The first row and the second row of the first gate patterns 41 may be defined as adjacent rows. The isolation insulating pattern 43 may be disposed between the first row and the second row. The first row of the first gate patterns 41 may be defined as the row included in the first drain select line DSL1, and the second row of the first gate patterns 41 may be defined as the row included in the second drain select line DSL2.

[0079] The first gate pattern 41 may include a first tubular gate pattern 41T1 arranged in the first row, a second tubular gate pattern 41T2 arranged in the second row, a third tubular gate pattern 41T3 arranged in the third row, and a fourth tubular gate pattern 41T4 arranged in the fourth row. The third row of the first gate pattern 41 may be defined as the row included in the first drain select line DSL1, and the fourth row of the first gate pattern 41 may be defined as the row included in the second drain select line DSL2. The first row and the second row may be defined as the rows disposed between the third row and the fourth row.

[0080] Referring Figure 3B , the isolation insulating pattern 43 may include a first surface SU1 and a second surface SU2 facing opposite directions. The isolation insulating pattern 43 may include a first groove G1 formed in the first surface SU1 and a second groove G2 formed in the second surface SU2.

[0081] The first linear gate pattern 45L1 may be in contact with the first surface SU1 of the isolation insulating pattern 43. The first linear gate pattern 45L1 may include a third groove G3 facing the first groove G1 of the isolation insulating pattern 43. The second linear gate pattern 45L2 may be in contact with the second surface SU2 of the isolation insulating pattern 43. The second linear gate pattern 45L2 may include a fourth groove G4 facing the second groove G2 of the isolation insulating pattern 43.

[0082] The first tubular gate pattern 41T1 may extend along the surfaces of the first groove G1 and the third groove G3. The first tubular gate pattern 41T1 may be divided into a first portion T1A and a second portion T1B. The first portion T1A of the first tubular gate pattern 41T1 may be inserted into the first groove G1 of the separation insulating pattern 43 and may contact the separation insulating pattern 43. The second portion T1B of the first tubular gate pattern 41T1 may extend from the first portion T1A and may extend in a direction away from the separation insulating pattern 43. The second portion T1B of the first tubular gate pattern 41T1 may be inserted into the third groove G3 of the first linear gate pattern 45L1 and may contact the first linear gate pattern 45L1.

[0083] The second tubular gate pattern 41T2 may extend along the surfaces of the second groove G2 and the fourth groove G4. The second tubular gate pattern 41T2 may be divided into a first portion T2A and a second portion T2B. The first portion T2A of the second tubular gate pattern 41T2 may be inserted into the second groove G2 of the separation insulating pattern 43 and may contact the separation insulating pattern 43. The second portion T2B of the second tubular gate pattern 41T2 may be inserted into the fourth groove G4 of the second linear gate pattern 45L2 and may contact the second linear gate pattern 45L2.

[0084] The first linear gate pattern 45L1 may connect the first tubular gate pattern 41T1 to the third tubular gate pattern 41T3. The second linear gate pattern 45L2 may connect the second tubular gate pattern 41T2 to the fourth tubular gate pattern 41T4.

[0085] Figure 4 is a cross-sectional view of a semiconductor memory device taken along line I-I'. Hereinafter, repeated descriptions of overlapping components will be omitted. Figure 3A

[0086] Referring Figure 4 , the vertical source contact 53 may extend into the space between the adjacent stacked bodies 10A and 10B. The sidewall insulating layer 51 may extend into the space between each of the stacked bodies 10A and 10B and the vertical source contact 53.

[0087] The semiconductor memory device may further include a source line SL. The stacked bodies 10A and 10B may be disposed on the source line SL.

[0088] Each of the stacked bodies 10A and 10B may further include an interlayer insulating layer 11L and a lower conductive pattern 13L and as described above with reference to Figure 2A ​The interlayer insulating layer 11 and the conductive pattern 13 described above. The lower interlayer insulating layer 11L and the lower conductive pattern 13L may be alternately stacked in the direction in which the interlayer insulating layer 11 and the conductive pattern 13 are alternately stacked.

[0089] The lower interlayer insulating layer 11L may be formed of the same insulating material as the interlayer insulating layer 11. The lower conductive pattern 13L may be formed of the same conductive material as the conductive pattern 13. In the lower conductive pattern 13L, at least one layer adjacent to the source line SL may be used as the source selection line SSL described above with reference to Figure 1 the description.

[0090] The channel layer 23 and the memory layer 21 may extend to the source line SL to pass through the lower interlayer insulating layer 11L and the lower conductive pattern 13L. The lower blocking insulating layer BI2L may be disposed between each lower conductive pattern 13L and the memory layer 21. The lower blocking insulating layer BI2L may extend into the space between each lower conductive pattern 13L and the corresponding lower interlayer insulating layer 11L. The lower blocking insulating layer BI2L may be formed of the same insulating material as the second blocking insulating layer BI2.

[0091] The source line SL may include a channel contact layer 3 in contact with the channel layer 23. The structure for the contact between the channel contact layer 3 and the channel layer 23 may be implemented in various ways. In one embodiment, the channel contact layer 3 may surround a part of the sidewall of the channel layer 23 and may be in contact with the sidewall of the channel layer 23. The channel contact layer 3 may be formed of a semiconductor material including a conductive impurity. In one embodiment, the channel contact layer 3 may include n-type doped silicon.

[0092] The source line SL may further include a first doped semiconductor layer 1 disposed under the channel contact layer 3. The first doped semiconductor layer 1 may be doped with an impurity of at least one of n-type and p-type.

[0093] The channel layer 23 may extend into the interior of the first doped semiconductor layer 1. A dummy memory layer 21D may be further disposed between the channel layer 23 and the first doped semiconductor layer 1. The dummy memory layer 21D may be formed of the same material as the memory layer 21. The dummy memory layer 21D and the memory layer 21 may be separated from each other by the channel contact layer 3. The channel layer 23 may extend into the space between the dummy memory layer 21D and the core insulating layer 25.

[0094] The source line SL may further include a second doped semiconductor layer 5 disposed between each of the stacked bodies 10A and 10B and the channel contact layer 3. The second doped semiconductor layer 5 may include the same conductive impurity as the channel contact layer 3. Each of the memory layer 21, the channel layer 23, the core insulating layer 25, the sidewall insulating layer 51, and the vertical source contact portion 53 may pass through the second doped semiconductor layer 5.

[0095] The vertical source contact portion 53 may be connected to the channel contact layer 3.

[0096] The sidewall insulating layer 51 and the vertical source contact portion 53 may protrude upward higher than the semiconductor pattern 31. In one embodiment, the sidewall insulating layer 51 and the vertical source contact portion 53 may pass through the horizontal portion 43P2 of the separation insulating pattern 43.

[0097] The sidewall insulating layer 51 and the vertical source contact portion 53 may protrude upward higher than each of the first gate pattern 41, the vertical portion 43P1 of the separation insulating pattern 43, and the second gate pattern 45. The upper insulating layer 47 and the sidewall insulating layer 51 may be interposed between the second gate pattern 45 and the vertical source contact portion 53.

[0098] The semiconductor memory device may further include an upper source contact portion 55 disposed on the vertical source contact portion 53. The upper source contact portion 55 may include the same conductive material as the conductive contact portion 49. The upper insulating layer 47 and the sidewall insulating layer 51 may be interposed between the upper source contact portion 55 and the conductive contact portion 49 adjacent to the upper source contact portion 55.

[0099] Although not shown in the figure, the bit line BL described above may be disposed on the conductive contact portion 49 and may extend in a direction intersecting the second gate pattern 45. Figure 1

[0100] Figure 5A Figure 5A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Modifications of the first gate pattern 41' and the second gate pattern 45' are shown. Hereinafter, repeated descriptions of overlapping components will be omitted.

[0101] Figure 5A Referring to

[0102]

[0103] The stack 10 may include a conductive pattern 13 and an interlayer insulating layer 11. Each of the lower channel portions CH1 may include a channel layer 23, a core insulating layer 25, and a semiconductor pattern 31. The separation insulating pattern 43 may include a vertical portion 43P1 and a horizontal portion 43P2.

[0103] The vertical portion 43P1 of the isolation insulating pattern 43 may protrude higher in the Z-axis direction than the second gate pattern 45'. In other words, the top surface of each of the first linear gate pattern 45L1' and the second linear gate pattern 45L2' of the second gate pattern 45' may be set at a height lower than the top surface of the vertical portion 43P1 of the isolation insulating pattern 43.

[0104] Similar to the description with reference to Figure 3A and Figure 3B As described, the first gate pattern 41' may include tubular gate patterns arranged in multiple rows. Some of the tubular gate patterns may be formed asymmetrically. Hereinafter, the tubular gate patterns will be described with reference to Figure 5B description of the tubular gate patterns.

[0105] Figure 5B is Figure 5A exploded perspective view of a partial region of the semiconductor memory device of.

[0106] With reference to Figure 5B , the first gate pattern 41' may include a first tubular gate pattern 41T1', a second tubular gate pattern 41T2', a third tubular gate pattern 41T3' and a fourth tubular gate pattern 41T4'.

[0107] The first tubular gate pattern 41T1' and the second tubular gate pattern 41T2' may be respectively arranged in the first row and the second row adjacent to each other of the first gate pattern 41'. The third tubular gate pattern 41T3' and the fourth tubular gate pattern 41T4' may be respectively arranged in the third row and the fourth row of the first gate pattern 41'. The first row and the second row may be set between the third row and the fourth row.

[0108] The vertical portion 43P1 of the isolation insulating pattern 43 may be set between the first row and the second row.

[0109] The first tubular gate pattern 41T1' may include a first portion T1A' and a second portion T1B', and the second tubular gate pattern 41T2' may also include a first portion T2A' and a second portion T2B'. The first portion T1A' of the first tubular gate pattern 41T1' and the first portion T2A' of the second tubular gate pattern 41T2' may contact the separation insulating pattern 43. The second portion T1B' of the first tubular gate pattern 41T1' and the second portion T2B' of the second tubular gate pattern 41T2' may contact the first linear gate pattern 45L1' and the second linear gate pattern 45L2', respectively. The first portions T1A' and T2A' may protrude higher than the second portions T1B' and T2B' in the Z-axis direction. In this way, each of the first tubular gate pattern 41T1' and the second tubular gate pattern 41T2' may be defined as an asymmetric gate pattern. The first portions T1A' and T2A' may protrude higher than the third tubular gate pattern 41T3' and the fourth tubular gate pattern 41T4' in the Z-axis direction.

[0110] The first linear gate pattern 45L1' and the second linear gate pattern 45L2' may be disposed on the horizontal portion 43P2 of the separation insulating pattern 43. The first groove G1 and the second groove G2 may be formed in two sidewalls of the vertical portion 43P1 of the separation insulating pattern 43, respectively. The third groove G3 and the fourth groove G4 may be formed in the sidewalls of the first linear gate pattern 45L1' and the second linear gate pattern 45L2', respectively. The first groove G1 of the separation insulating pattern 43 may be disposed to face the third groove G3 of the first linear gate pattern 45L1'. The second groove G2 of the separation insulating pattern 43 may be disposed to face the fourth groove G4 of the second linear gate pattern 45L2'.

[0111] The first portion T1A' of the first tubular gate pattern 41T1' and the first portion T2A' of the second tubular gate pattern 41T2' may be inserted into the first groove G1 and the second groove G2, respectively. The second portion T1B' of the first tubular gate pattern 41T1' and the second portion T2B' of the second tubular gate pattern 41T2' may be inserted into the third groove G3 and the fourth groove G4, respectively.

[0112] The first linear gate pattern 45L1' and the second linear gate pattern 45L2' may include a first hole 45H. Some of the third tubular gate pattern 41T3' and the fourth tubular gate pattern 41T4' may be inserted into the first hole 45H.

[0113] The horizontal portion 43P2 of the separation insulating pattern 43 may be penetrated by the second hole 43H. The lower portions of the first to fourth tubular gate patterns 41T1', 41T2', 41T3', and 41T4' may be inserted into the second hole 43H.

[0114] The upper channel portion CH2 and a part of the gate insulating layer 35 may be inserted into the central regions of each of the first to fourth tubular gate patterns 41T1', 41T2', 41T3', and 41T4'.

[0115] Figure 6 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Figure 6 Modifications of the sidewall insulating layer 51' and the vertical source contact 53' are shown. Hereinafter, repeated descriptions of overlapping components will be omitted.

[0116] Referring to Figure 6 , the semiconductor memory device may include a source line SL, stacked bodies 10A and 10B adjacent to each other, a sidewall insulating layer 51', a vertical source contact 53', a memory layer 21, a dummy memory layer 21D, a lower channel portion CH1, a separation insulating pattern 43, an upper channel portion CH2, a gate insulating layer 35, a first gate pattern 41, a second gate pattern 45, an upper insulating layer 47, and a conductive contact 49.

[0117] The source line SL may include a first doped semiconductor layer 1, a channel contact layer 3, and a second doped semiconductor layer 5.

[0118] The stacked bodies 10A and 10B may be disposed on the source line SL.

[0119] The sidewall insulating layer 51' may be formed on the sidewalls of each of the stacked bodies 10A and 10B. The vertical source contact 53' may extend from the channel contact layer 3 in the Z-axis direction.

[0120] The lower channel portion CH1 may include a channel layer 23, a core insulating layer 25, and a semiconductor pattern 31. The sidewall insulating layer 51' and the vertical source contact 53' may protrude higher than the lower channel portion CH1 in the Z-axis direction. In one embodiment, the sidewall insulating layer 51' and the vertical source contact 53' may pass through the horizontal portion 43P2 of the separation insulating pattern 43.

[0121] The top surfaces of each of the sidewall insulating layer 51' and the vertical source contact 53' may be disposed at a height lower than the height of the top surfaces of each of the upper channel portion CH2, the gate insulating layer 35, the first gate pattern 41, and the second gate pattern 45. The upper insulating layer 47 may cover the top surfaces of each of the sidewall insulating layer 51' and the vertical source contact 53'.

[0122] Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described.

[0123] Figure 7It is a plan view showing a stack, a memory layer, and a lower channel portion.

[0124] Referring to Figure 7 , the stack 110 may extend along the X-Y plane. The stack 110 may include isolation regions IR1 and IR2 and array regions AR1 and AR2. The isolation regions IR1 and IR2 and the array regions AR1 and AR2 may extend in parallel. In the X-Y plane, the isolation regions IR1 and IR2 may be arranged to alternate with the array regions AR1 and AR2. In one embodiment, the isolation regions IR1 and IR2 and the array regions AR1 and AR2 may be alternately arranged in the X-axis direction.

[0125] In each of the array regions AR1 and AR2, the stack 110 may be penetrated by channel holes 117. The channel holes 117 may form a plurality of rows and a plurality of columns. The Y-axis direction may be defined as the row direction, and the X-axis direction may be defined as the column direction.

[0126] The memory layer 121 may be disposed on the sidewalls of each channel hole 117.

[0127] The lower channel portion 130 may be provided within the corresponding channel hole 117. Each lower channel portion 130 may include a channel layer 123 and a semiconductor pattern 131.

[0128] The array regions AR1 and AR2 may include a first array region AR1 and a second array region AR2. The lower channel portion 130 may include a first group passing through the stack 110 in the first array region AR1 and a second group passing through the stack 110 in the second array region AR2. The distance L1 between the lower channel portions 130 in each group may be shorter than the distance L2 between the first group of the lower channel portions 130 and the second group of the lower channel portions 130.

[0129] Figure 8A , Figure 8B and Figure 8C It is a cross-sectional view showing an embodiment of a method for manufacturing a stack, a memory layer, and a lower channel portion. Figure 8A , Figure 8B and Figure 8C is a cross-sectional view taken along the Figure 7 line II-II'.

[0130] Referring to Figure 8A , the stack 110 may be formed on the preliminary source structure 100.

[0131] In one embodiment, the preliminary source structure 100 may include a first doped semiconductor layer 101, a first source protection layer 103, a sacrificial source layer 105, a second source protection layer 107, and a preliminary source layer 109 stacked in sequence. The first doped semiconductor layer 101 may include impurities of at least one of n-type and p-type. In one embodiment, the first doped semiconductor layer 101 may include n-type doped silicon. The first source protection layer 103 and the second source protection layer 107 may be formed of a material capable of protecting the first doped semiconductor layer 101 and the preliminary source layer 109 during a subsequent etching process for selectively removing the sacrificial source layer 105. In one embodiment, the first source protection layer 103 and the second source protection layer 107 may include oxides. The sacrificial source layer 105 may include silicon. The preliminary source layer 109 may include undoped silicon or doped silicon.

[0132] The stack 110 may include a first material layer 111 and a second material layer 113 alternately stacked on the preliminary source structure 100. The second material layer 113 may be formed of a material different from that of the first material layer 111. In one embodiment, the first material layer 111 may include an oxide, and the second material layer 113 may include a nitride.

[0133] After forming the stack 110, a channel hole 117 may be formed through the stack 110. The channel hole 117 may extend into the first doped semiconductor layer 101 of the preliminary source structure 100.

[0134] Then, a memory layer 121 may be formed on the surface of each channel hole 117. The memory layer 121 may include Figure 2B the tunnel insulation layer TL, the data storage layer DL, and the first barrier insulation layer BI1 as shown. The memory layer 121 may extend to overlap with the top surface of the stack 110.

[0135] Thereafter, a channel layer 123 may be formed on the memory layer 121. The channel layer 123 may include a semiconductor material such as silicon. The channel layer 123 may extend to overlap with the top surface of the stack 110.

[0136] Next, the central region of each channel hole 117 defined by the channel layer 123 may be filled with a core insulation layer 125.

[0137] Referring to Figure 8B it is possible to etch a part of the core insulation layer 125. In this way, a recessed region 129 may be defined at the top of each channel hole 117.

[0138] Referring to Figure 8C a semiconductor pattern 131 can be used to fill Figure 8BThe recessed region 129 shown. The process for forming the semiconductor pattern 131 may include applying a semiconductor material onto the channel layer 123 to fill Figure 8B the recessed region 129 and performing a planarization process such that the semiconductor material remains only in the channel holes 117.

[0139] A process for planarizing the semiconductor material may be performed such that the memory layer 121 is exposed. In this way, the lower channel portions 130 may be formed in the corresponding channel holes 117. Each lower channel portion 130 may include a channel layer 123, a core insulating layer 125, and a semiconductor pattern 131.

[0140] Figure 9 and Figure 10 are a plan view and a cross-sectional view showing an embodiment of a method of manufacturing an upper stack and a first mask pattern, respectively. Figure 10 is a cross-sectional view taken along Figure 9 the line II-II'.

[0141] Referring to Figure 9 and Figure 10 , an upper stack 140 overlapping the lower channel portions 130 and the stack 110 may be formed. Thereafter, a first mask pattern 147 overlapping each of the lower channel portions 130 may be formed on the upper stack 140.

[0142] The upper stack 140 may include a semiconductor layer 141, a protective layer 143, and a sacrificial layer 145. The semiconductor layer 141 may overlap the stack 110 and the lower channel portions 130. The semiconductor layer 141 may be formed of a substantially intrinsic semiconductor material. The protective layer 143 may be formed on the semiconductor layer 141. The sacrificial layer 145 may be formed on the protective layer 143. The protective layer 143 may include an insulating material having an etching selectivity with respect to the semiconductor layer 141 and the sacrificial layer 145. In one embodiment, the protective layer 143 may include an oxide, and the semiconductor layer 141 and the sacrificial layer 145 may include silicon.

[0143] The first mask pattern 147 may be formed on the sacrificial layer 145. The first mask pattern 147 may include a material having an etching selectivity with respect to the semiconductor layer 141, the protective layer 143, and the sacrificial layer 145. In an embodiment, the first mask pattern 147 may include a nitride.

[0144] Figure 11A , Figure 11B , Figure 11C and Figure 11D are cross-sectional views showing embodiments of subsequent processes to be performed after forming the first mask pattern.

[0145] Referring to Figure 11A, by an etching process using the first mask pattern 147 as an etching barrier, it is possible to etch Figure 10 The semiconductor layer 141, the protective layer 143 and the sacrificial layer 145 are shown. In this way, Figure 10 The semiconductor layer 141 shown may be patterned into an upper channel portion 141C. Figure 10 The sacrificial layer 145 is shown patterned into sacrificial patterns 145S.

[0146] The upper channel portions 141C may be spaced apart from each other. The upper channel portions 141C may be disposed on the lower channel portions 130, respectively. According to an embodiment of the present disclosure, the upper channel portions 141C may be defined as having a shape similar to that of the lower channel portions 130. Figure 10 The thickness of the semiconductor layer 141 is shown to be uniform over the length.

[0147] The sacrificial patterns 145S may be disposed on the upper channel portions 141C, respectively. The protective layer 143 may remain between the upper channel portions 141C and the sacrificial patterns 145S.

[0148] In one embodiment, the width of each of the upper channel portions 141C may be controlled to be smaller than the width of each of the lower channel portions 130. In this case, an edge of a top surface of each of the lower channel portions 130 may be exposed.

[0149] Reference Figure 11B , a gate insulating layer 149 may be formed through an oxidation process. The gate insulating layers 149 may be formed on sidewalls of the upper channel portions 141C, respectively, and may extend onto sidewalls of the sacrificial patterns 145S, respectively.

[0150] During the oxidation process, a portion of the channel layer 123 and a portion of the semiconductor pattern 131 of each lower channel portion 130 may be oxidized. In this manner, each gate insulating layer 149 may include a protrusion 149P extending along an edge of a top surface of each lower channel portion 130 .

[0151] Reference Figure 11C , a first gate pattern 151 surrounding a corresponding sidewall of the gate insulating layer 149 may be formed.

[0152] The process for forming the first gate pattern 151 may include a step of conformally depositing a conductive barrier layer and a step of etching the conductive barrier layer by an etch-back process. The conductive barrier layer may include titanium, titanium nitride, or the like.

[0153] The protrusion 149P of the gate insulating layer 149 allows the first gate pattern 151 to be spaced apart from the channel layer 123 and the semiconductor pattern 131 of the lower channel portion 130 .

[0154] ReferenceFigure 11D , an insulating layer 153 may be formed on the stacked body 110. The insulating layer 153 may cover the first gate pattern 151 and the first mask pattern 147. The insulating layer 153 may be formed to fill a space between the first gate patterns 151.

[0155] Figure 12 is a cross-sectional view illustrating an embodiment of a subsequent process to be performed after forming an insulating layer.

[0156] Reference Figure 12 , can be etched Figure 11D The insulating layer 153A shown in the figure may be etched to reduce the thickness of the insulating layer 153. The insulating layer 153A remaining after the etching process may have a top surface 153TS disposed at a height lower than that of the top surface 141TS of each upper channel portion 141C. The remaining insulating layer 153A may fill the space between the lower portions of the first gate patterns 151 and may overlap the stacked body 110.

[0157] The first gate patterns 151 may be divided into a plurality of groups. In one embodiment, the first gate patterns 151 may include a first group disposed on the stack 110 in the first array region AR1 and a second group disposed on the stack 110 in the second array region AR2.

[0158] Figure 13 is along Figure 12 A plan view taken along line III-III'.

[0159] Reference Figure 13 , a first space WS1 may be defined between the first gate patterns 151 in each group. A second space WS2 may be defined between the first and second groups of the first gate patterns 151. The first space WS1 may be defined to have a width smaller than that of the second space WS2.

[0160] The first gate patterns 151 may be tubular gate patterns surrounding the corresponding sidewalls of the gate insulating layer 149. The first gate patterns 151 in each group may be arranged in two or more rows. In one embodiment, the first gate patterns 151 may include a first tubular gate pattern 151T1 arranged in a first row, a second tubular gate pattern 151T2 arranged in a second row, a third tubular gate pattern 151T3 arranged in a third row, and a fourth tubular gate pattern 151T4 arranged in a fourth row.

[0161] Figure 14 and Figure 15 1 and 2 are respectively a plan view and a cross-sectional view showing an embodiment of a method of manufacturing a separate insulation pattern.

[0162] Reference Figure 14And Figure 15 , a second mask pattern 155 can be formed on the insulating layer 153A shown in Figure 12 and Figure 13 . The second mask pattern 155 can be a photoresist pattern.

[0163] The second mask pattern 155 can overlap with Figure 12 and Figure 13 a part of the insulating layer 153A shown. For example, the second mask pattern 155 can overlap with the part of the insulating layer 153A between the first tubular gate pattern 151T1 and the second tubular gate pattern 151T2.

[0164] The width WA of the second mask pattern 155 can be defined as a value greater than the separation distance between the first tubular gate pattern 151T1 and the second tubular gate pattern 151T2. The second mask pattern 155 can overlap with the first sidewall T1S1 of the first tubular gate pattern 151T1 and the first sidewall T2S1 of the second tubular gate pattern 151T2. The second sidewall T1S2 of the first tubular gate pattern 151T1 and the second sidewall T2S2 of the second tubular gate pattern 151T2 can be defined as the sidewalls that do not overlap with the second mask pattern 155.

[0165] Next, the insulating layer can be etched through an etching process using the second mask pattern 155 as an etching barrier, so that a separated insulating pattern 153B can be defined. The separated insulating pattern 153B can include a vertical portion 153P1 and horizontal portions 153P2 extending to both sides of the vertical portion 153P1. The vertical portion 153P1 can be defined as the part between the first tubular gate pattern 151T1 and the second tubular gate pattern 151T2. The thickness of the horizontal portion 153P2 can be defined as less than the thickness of the vertical portion 153P1.

[0166] The vertical portion 153P1 of the separated insulating pattern 153B can contact the first sidewall T1S1 of the first tubular gate pattern 151T1 and the first sidewall T2S1 of the second tubular gate pattern 151T2. A part of each of the second sidewall T1S2 of the first tubular gate pattern 151T1 and the second sidewall T2S2 of the second tubular gate pattern 151T2 can be exposed to the outside of the separated insulating pattern 153B. The third tubular gate pattern 151T3 and the fourth tubular gate pattern 151T4 can also be exposed to the outside of the separated insulating pattern 153B.

[0167] The second mask pattern 155 can be removed after the separated insulating pattern 153B is formed.

[0168] Figure 16 is a cross-sectional view showing an embodiment of a method for manufacturing a conductive layer.

[0169] Reference Figure 16 , a conductive layer 161L may be formed on the isolation insulating pattern 153B. The conductive layer 161L may include a metal layer formed of tungsten or the like. The conductive layer 161L may be formed to fill a first space WS1 between the first gate patterns 151. The conductive layer 161L may cover a vertical portion 153P1 of the isolation insulating pattern 153B and the first mask pattern 147. The conductive layer 161L may be conformally formed in a second space WS2 having a width greater than the width of the first space WS1. A central region of the second space WS2 may be opened and not filled with the conductive layer 161L.

[0170] Figure 17A 、 Figure 17B and Figure 17C are enlarged cross-sectional views showing embodiments of subsequent processes for the Figure 16 area C shown.

[0171] Reference Figure 17A , Figure 16 As shown, a portion of the conductive layer 161L may be etched by an etch-back process or the like. The conductive layer 161L may be etched such that the isolation insulating pattern 153B is exposed. Second gate patterns 161G1, 161G2, and 161G3 separated from each other may be formed by a process of etching the conductive layer 161L. The second gate patterns 161G1, 161G2, and 161G3 may be patterned into a linear shape.

[0172] According to an embodiment of the present disclosure, even without separately forming an etch barrier pattern on the Figure 16 conductive layer 161L shown, the second gate patterns 161G1, 161G2, and 161G3 separated from each other may be formed using an etch-back process.

[0173] The vertical portion 153P1 of the isolation insulating pattern 153B may be disposed between the second gate patterns 161G1, 161G2, and 161G3, or a trench 163 may be defined between the second gate patterns 161G1, 161G2, and 161G3. In one embodiment, the second gate patterns 161G1, 161G2, and 161G3 may include a first linear gate pattern 161G1, a second linear gate pattern 161G2, and a third linear gate pattern 161G3. The first linear gate pattern 161G1 and the second linear gate pattern 161G2 may be disposed on the stack 110 in the first array region AR1, and the third linear gate pattern 161G3 may be disposed on the stack 110 in the second array region AR2. The first linear gate pattern 161G1 may be spaced apart from the second linear gate pattern 161G2 by the vertical portion 153P1 of the isolation insulating pattern 153B. The second linear gate pattern 161G2 may be spaced apart from the third linear gate pattern 161G3 by the trench 163.

[0174] In one embodiment, the first gate pattern 151 may have an etching selectivity with respect to Figure 16 the conductive layer 161L shown. Thus, even if Figure 16 the conductive layer 161L shown is etched, the first gate pattern 151 will not be damaged and can be retained while protruding higher than the second gate patterns 161G1, 161G2, and 161G3 in the longitudinal direction of the upper channel portion 141C. Hereinafter, the portion of the first gate pattern 151 that protrudes higher than the second gate patterns 161G1, 161G2, and 161G3 in the longitudinal direction of the upper channel portion 141C is defined as the protruding portion 151P. The protruding portion 151P may protrude higher than the vertical portion 153P1 of the isolation insulating pattern 153B in the longitudinal direction of the upper channel portion 141C.

[0175] Referring to Figure 17B , Figure 17A the protruding portion 151P shown may be selectively removed by wet etching or the like. The gate length may be defined by the height 151H of the remaining first gate pattern after the protruding portion 151P in Figure 17A has been removed.

[0176] The first gate pattern 151R may be protected by the second gate patterns 161G1, 161G2, and 161G3 or by the vertical portion 153P1 of the isolation insulating pattern 153B. In this way, the first gate pattern 151R may provide a gate-all-around structure around each of the upper channel portions 141C.

[0177] In Figure 17AAfter the protrusion 151P shown has been removed, the gate insulating layer 149 can be retained while protruding higher than the first gate pattern 151R in the longitudinal direction of the upper channel portion 141C.

[0178] Referring to Figure 17C , an upper insulating layer 171 can be formed to cover the first gate pattern 151R, the second gate patterns 161G1, 161G2, and 161G3, and the isolation insulating pattern 153B. The upper insulating layer 171 can fill the trench 163. The upper insulating layer 171 can surround the gate insulating layer 149. The upper insulating layer 171 can extend onto the first mask pattern 147. The upper insulating layer 171 can include an oxide.

[0179] Figure 18 is a plan view taken along line IV-IV' Figure 17C shown.

[0180] Referring to Figure 18 , among the first gate patterns 151R, the tubular gate patterns arranged in two or more adjacent rows can be connected to each other by each of the second gate patterns 161G1, 161G2, and 161G3.

[0181] In one embodiment, the first linear gate pattern 161G1 can connect the first tubular gate pattern 151T1 arranged in the first row to the third tubular gate pattern 151T3 arranged in the third row. In one embodiment, the second linear gate pattern 161G2 can connect the second tubular gate pattern 151T2 arranged in the second row to the fourth tubular gate pattern 151T4 arranged in the fourth row.

[0182] The first linear gate pattern 161G1 and the second linear gate pattern 161G2 arranged on both sides of the vertical portion 153P1 of the isolation insulating pattern 153B can not only contact the isolation insulating pattern 153B, but also contact some of the first gate patterns 151R. In one embodiment, the first linear gate pattern 161G1 can contact the second sidewall T1S2 of the first tubular gate pattern 151T1. In addition, the second linear gate pattern 161G2 can contact the second sidewall T2S2 of the second tubular gate pattern 151T2.

[0183] The vertical portion 153P1 of the isolation insulating pattern 153B can be retained while contacting the first sidewall T1S1 of the first tubular gate pattern 151T1 and the first sidewall T2S1 of the second tubular gate pattern 151T2.

[0184] The upper insulating layer 171 can be disposed between the second linear gate pattern 161G2 and the third linear gate pattern 161G3.

[0185] Figure 19 It is a plan view showing a first mask pattern, an upper insulating layer, sidewall insulating layers, and a vertical source contact portion.

[0186] Referring to Figure 19 , after forming the structure shown in Figure 17C , sidewall insulating layers 181 and a vertical source contact portion 187 can be formed. Thereafter, a part of the upper insulating layer 171 can be removed to expose the first mask pattern 147. Before forming the sidewall insulating layers 181, a replacement process for forming a conductive pattern can be performed.

[0187] Figure 20A , Figure 20B , Figure 20C , Figure 20D and Figure 20E are cross-sectional views showing embodiments of a method for manufacturing the structure of Figure 19 .

[0188] Referring to Figure 20A , a slit 173 can be formed to penetrate the upper insulating layer 171 and the stack 110. The memory layer 121, the horizontal portion 153P2 of the separation insulating pattern 153B, and the stack 110 disposed between the upper insulating layer 171 and the stack 110 can be penetrated by the slit 173.

[0189] The slit 173 can penetrate the preliminary source layer 109 and the second source protection layer 107 of the preliminary source structure 100. The bottom surface of the slit 173 can be defined along the surface of the sacrificial source layer 105.

[0190] Referring to Figure 20B , the second material layer 113 shown in Figure 20A can be removed through the slit 173. In this way, an opening 175 can be defined between the first material layers 111. The memory layer 121 can be exposed through the opening 175.

[0191] Referring to Figure 20C , a barrier insulating layer 177 can be formed along the surface of each opening 175 shown in Figure 20B . The barrier insulating layer 177 can include a metal oxide. In one embodiment, the barrier insulating layer 177 can include aluminum oxide (Al 2 O 3 ). After the barrier insulating layer 177 has been deposited, an annealing process can be performed on the barrier insulating layer 177. The barrier insulating layer 177 can be conformally formed along the corresponding surfaces of the openings 175 shown in Figure 20B such that the barrier insulating layer 177 does not fill the corresponding central regions of the openings 175 shown in Figure 20B .

[0192] Thereafter, a conductive pattern 179 can be formed. The conductive pattern 179 can fill Figure 20B the corresponding central region of the opening 175 shown. The conductive patterns 179 can be separated from each other through the slit 173 and the first material layer 111.

[0193] Thereafter, a sidewall insulating layer 181 can be formed on the sidewalls of the slit 173.

[0194] Referring to Figure 20D it, the sacrificial source layer 105 shown can be removed through the slit 173. Then, a part of the memory layer 121 shown can be removed. Figure 20C When removing Figure 20C the part of the memory layer 121 shown, the first source protection layer 103 and the second source protection layer 107 shown can be removed. Figure 20C When removing Figure 20C the part of the memory layer 121 shown, the first source protection layer 103 and the second source protection layer 107 shown can be removed.

[0195] As described above, when the sacrificial source layer 105, the part of the memory layer 121, the first source protection layer 103 and the second source protection layer 107 (as Figure 20C shown) are removed, the horizontal space 183 can be opened. The sidewalls of the channel layer 123, the first doped semiconductor layer 101 and the preliminary source layer 109 can be exposed through the horizontal space 183. The memory layer can be divided into a first memory layer 121A and a second memory layer 121B through the horizontal space 183. The second memory layer 121B can be defined as a dummy memory layer.

[0196] Referring to Figure 20E it, the horizontal space 183 shown can be filled with the channel contact layer 185. The channel contact layer 185 can include a semiconductor material containing conductive impurities. The channel contact layer 185 can include conductive impurities of at least one of n-type and p-type. In one embodiment, the channel contact layer 185 can include n-type doped silicon. Figure 20D The conductive impurities of the channel contact layer 185 can diffuse into

[0197] the preliminary source layer 109 shown. In this way, the second doped semiconductor layer 109S of the source line 100S can be defined. The source line 100S can include the first doped semiconductor layer 101, the channel contact layer 185 and the second doped semiconductor layer 109S. Figure 20D The conductive impurities of the channel contact layer 185 can diffuse into

[0198] the preliminary source layer 109 shown. In this way, the second doped semiconductor layer 109S of the source line 100S can be defined. The source line 100S can include the first doped semiconductor layer 101, the channel contact layer 185 and the second doped semiconductor layer 109S. Figure 20D Thereafter, a vertical source contact portion 187 that contacts the channel contact layer 185 and fills the slit 173 shown can be formed. The vertical source contact portion 187 can include at least one of a doped semiconductor, a metal, a metal silicide, and a metal nitride.

[0199] The vertical source contact 187 may be isolated from the conductive pattern 179 by the sidewall insulating layer 181. The vertical source contact 187 and the upper insulating layer 171 may be planarized. The first mask pattern 147 may be exposed by planarizing the upper insulating layer 171. The upper insulating layer 171 may remain as a sidewall surrounding the first mask pattern 147.

[0200] Figure 21A , Figure 21B , Figure 21C , Figure 21D and Figure 21E It is shown in the formation Figure 20E sectional view of an embodiment of a subsequent process to be performed after the structure of FIG.

[0201] Reference Figure 21A , which can be selectively removed Figure 20E The first mask pattern 147 is shown. In this way, a fifth groove 189A may be defined. Each sacrificial pattern 145S may be exposed through the fifth groove 189A.

[0202] Reference Figure 21B , which can be selectively removed Figure 21A Each sacrificial pattern 145S shown. In this way, a primarily expanded fifth groove 189B can be defined. Through the primarily expanded fifth groove 189B, the top of the protection layer 143 and the top of each gate insulating layer 149 can be exposed. When the sacrificial pattern 145S is removed, a portion of the vertical source contact 187 can be removed. In this way, a recessed area 190 can be defined in the top of the remaining vertical source contact 187. The sidewall of the recessed area 190 can be defined along the sidewall insulating layer 181.

[0203] Reference Figure 21C , by performing an ion implantation process through the preliminarily enlarged fifth groove 189B, conductive impurities may be implanted into the top of the upper channel portion 141C. In one embodiment, n-type impurities may be implanted into the top of the upper channel portion 141C. Therefore, the upper channel portion 141C may be divided into a first region CA and a second region CB. The second region CB may be defined as a doped region including conductive impurities. The first region CA may be defined as a region formed of a substantially intrinsic semiconductor material. According to an embodiment of the present disclosure, the depth of the second region CB may be uniformly controlled by an ion implantation process.

[0204] Reference Figure 21D , can be Figure 21C The fifth groove 189B shown in the preliminary expansion is removed Figure 21CThe protective layer 143 is shown. Here, the top of the gate insulating layer 149 and a portion of the upper insulating layer 171 may be etched. In this way, a secondarily enlarged fifth groove 189C may be defined.

[0205] The second region CB of each upper channel portion 141C may be exposed through the second-enlarged fifth groove 189C.

[0206] When the protective layer 143 is removed, a portion of the sidewall insulating layer 181 may be etched, and thus the recessed region 190 may be expanded.

[0207] Reference Figure 21E , the conductive contact portion 191 can be used to fill Figure 21D The second expanded fifth groove 189C is shown. Here, the upper source contact 195 can be used to fill Figure 21D The recessed region 190 shown. The conductive contact 191 may contact the second region CB of each of the upper channel portions 141C. The upper source contact 195 may contact the vertical source contact 187. According to an embodiment of the present disclosure, the conductive contact 191 may be automatically aligned in the secondly enlarged fifth groove 189C opened to the upper channel portion 141C. In addition, the upper source contact 195 may be automatically aligned in the recessed region 190.

[0208] You can use the above reference Figure 7 , Figures 8A to 8C , Figure 9 , Figure 10 , Figures 11A to 11D , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figures 17A to 17C , Figure 18 , Figure 19 , Figures 20A to 20E and Figures 21A to 21E The process described above is provided by reference Figure 3A , Figure 3B and Figure 4 A semiconductor memory device is described.

[0209] In addition to the above embodiments, Figure 20CThe first gate pattern 151R and the second gate patterns 161G1, 161G2, and 161G3 shown may include refractory metals. The refractory metals may include titanium nitride, tantalum nitride, tungsten nitride, etc. The refractory metals have thermal stability. Therefore, even though an annealing process is performed on the barrier insulating layer 177 after the first gate pattern 151R and the second gate patterns 161G1, 161G2, and 161G3 have been formed, deterioration of the electrical characteristics of the first gate pattern 151R and the second gate patterns 161G1, 161G2, and 161G3 caused by heat generated during the annealing process can be alleviated.

[0210] Figure 22A and Figure 22B is an enlarged cross-sectional view showing an embodiment of a subsequent process for the Figure 16 region C shown.

[0211] Figure 16 A part of the conductive layer 161L shown may be etched by an etch-back process or the like. The conductive layer 161L may be etched such that the isolation insulating pattern 153B is exposed. Figure 16 The conductive layer 161L shown may be separated into second gate patterns 161G1', 161G2', and 161G3' by an etching process. The respective top surfaces 161TS of the second gate patterns 161G1', 161G2', and 161G3' may be set at a height lower than the height of the top surface 153TS of the vertical portion 153P1 of the isolation insulating pattern 153B.

[0212] The first gate pattern 151 may include protrusions 151P1 and 151P2 that protrude higher than the second gate patterns 161G1', 161G2', and 161G3' and the vertical portion 153P1 of the isolation insulating pattern 153B in the longitudinal direction of the upper channel portion 141C. The protrusions 151P1 and 151P2 may include a first protrusion 151P1 and a second protrusion 151P2 that is longer than the first protrusion 151P1.

[0213] As described above with reference to Figure 17A the second gate patterns 161G1', 161G2', and 161G3' may include a first linear gate pattern 161G1', a second linear gate pattern 161G2', and a third linear gate pattern 161G3'. Moreover, the first linear gate pattern 161G1' may be spaced apart from the second linear gate pattern 161G2' by the vertical portion 153P1 of the isolation insulating pattern 153B. Moreover, a trench 163 may be defined between the second linear gate pattern 161G2' and the third linear gate pattern 161G3'. The horizontal portion 153P2 of the isolation insulating pattern 153B may be exposed through the trench 163.

[0214] Referring to Figure 22B , Figure 22A the protruding portions 151P1 and 151P2 shown can be selectively removed by wet etching or the like. Here, some of the first gate patterns 151' can be left as asymmetric gate patterns. More specifically, the first and second rows of the first gate pattern 151' of the vertical portion 153P1 of the contact separation insulating pattern 153B can be left as asymmetric gate patterns. In other words, the first tubular gate pattern 151T1' arranged in the first row and the second tubular gate pattern 151T2' arranged in the second row can be asymmetric gate patterns.

[0215] The first sidewall T1S1' of the first tubular gate pattern 151T1' can be left while contacting the vertical portion 153P1 of the contact separation insulating pattern 153B, and the second sidewall T1S2' of the first tubular gate pattern 151T1' can be left while contacting the first linear gate pattern 161G1'. The first sidewall T2S1' of the second tubular gate pattern 151T2' can be left while contacting the vertical portion 153P1 of the contact separation insulating pattern 153B, and the second sidewall T2S2' of the second tubular gate pattern 151T2' can be left while contacting the second linear gate pattern 161G2'. The remaining first sidewalls T1S1' and T2S1' protrude higher than the remaining second sidewalls T1S2' and T2S2' in the longitudinal direction of the upper channel portion 141C, and thus the first tubular gate pattern 151T1' and the second tubular gate pattern 151T2' can be defined as asymmetric gate patterns.

[0216] The processes described above with reference to Figure 22A and Figure 22B can be used to provide the semiconductor memory device described above with reference to Figure 5A and 5B .

[0217] Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 23E , Figure 23F , Figure 23G and Figure 23H are cross-sectional views showing examples of subsequent processes to be performed after the process of Figure 11D .

[0218] Referring to Figure 23A , a slit 273 can be formed in a state where the first mask pattern 147 and the first gate pattern 151 are covered with the insulating layer 153. The slit 273 can penetrate the insulating layer 153 and the stack 110. The memory layer 121 between the insulating layer 153 and the stack 110 can be penetrated by the slit 273.

[0219] The slit 273 can pass through the preliminary source layer 109 and the second source protection layer 107 of the preliminary source structure 100. The bottom surface of the slit 273 can be defined along the surface of the sacrificial source layer 105.

[0220] Referring to Figure 23B , a replacement process can be performed through the slit 273 shown in Figure 23A . The replacement process can include the steps of replacing each of the second material layers 113 shown in Figure 23A with the barrier insulating layer 177″ and the conductive pattern 179″, and replacing the first source protection layer 103, the sacrificial source layer 105, and the second source protection layer 107 shown in Figure 23A with the channel contact layer 185″.

[0221] The barrier insulating layer 177″ and the conductive pattern 179″ can be formed using the processes described above with reference to Figure 20B and Figure 20C .

[0222] Before forming the channel contact layer 185″, a sidewall insulating layer 281 can be formed to cover the sidewalls of the first material layer 111 and the conductive pattern 179″.

[0223] The channel contact layer 185″ can be formed using the processes described above with reference to Figure 20D and Figure 20E . The channel contact layer 185″ can contact the first doped semiconductor layer 101 and the preliminary source layer 109 of Figure 23A . The conductive dopant can diffuse from the channel contact layer 185″ into the preliminary source layer 109 of Figure 23A . In this way, the second doped semiconductor layer 109S″ can be defined.

[0224] The channel contact layer 185″ can be disposed between the first doped semiconductor layer 101 and the second doped semiconductor layer 109S″ and can contact the sidewalls of the channel layer 123. The memory layer 121 shown in Figure 23A can be separated into a first memory layer 121A″ and a second memory layer 121B″ through the channel contact layer 185″.

[0225] After the channel contact layer 185″ has been formed, a vertical source contact portion 287 can be formed to fill the slit 273 shown in Figure 23A . The vertical source contact portion 287 can extend to the height at which the top surface of the insulating layer 153 is disposed. The vertical source contact portion 287 can include doped silicon.

[0226] Referring to Figure 23C , Figure 23BA portion of the insulating layer 153 as shown, so that the thickness of the insulating layer 153 can be reduced. The remaining insulating layer 153A″ after the etching process may have a top surface 153TS″ that is set at a height lower than the height of the top surface 141TS of each upper channel portion 141C.

[0227] When etching the portion of the insulating layer, a portion of the sidewall insulating layer 281 may be etched. Accordingly, a first protrusion 287P1 of the vertical source contact portion 287 can be defined, which protrudes upward higher than the sidewall insulating layer 281 and the insulating layer 153A″.

[0228] Referring to Figure 23D , the first protrusion 287P1 as shown can be selectively removed by an etch-back process. When removing Figure 23C the first protrusion 287P1 as shown, the sacrificial pattern 145S can be protected by the first mask pattern 147. Figure 23C When removing

[0229] Referring to Figure 23E , as described above with reference to Figure 14 and Figure 15[[ , the second mask pattern 155″ can be formed on ​ the insulating layer 153A″ as shown. Thereafter, a portion of the insulating layer 153A″ as shown can be etched by an etching process using the second mask pattern 155″ as an etching barrier. In this way, the separated insulating pattern 153B″ can be defined. As described above with reference to ​ ​ and ​ , the separated insulating pattern 153B″ may include a vertical portion 153P1″ and a horizontal portion 153P2″.

[0230] During the process of etching the insulating layer, a portion of the sidewall insulating layer 281 may be etched. Accordingly, a second protrusion 287P2 of the vertical source contact portion 287 can be defined, which protrudes upward higher than the sidewall insulating layer 281 and the horizontal portion 153P2″ of the separated insulating pattern 153B″.

[0231] Referring to ​ , the second protrusion 287P2 as shown can be selectively removed by an etch-back process. When removing ​ the second protrusion 287P2 as shown, the sacrificial pattern 145S can be protected by the first mask pattern 147. ​ When removing

[0232] the second protrusion 287P2 as shown, the sacrificial pattern 145S can be protected by the first mask pattern 147. ​ Referring to ​ , the second mask pattern 155″ as shown can be removed so that the vertical portion 153P1″ of the separated insulating pattern 153B″ is exposed.

[0233] Afterwards, you can use the above reference ​ and ​ The described process forms the second gate patterns 161G1", 161G2", and 161G3". The second gate patterns 161G1", 161G2", and 161G3" may be disposed on the horizontal portions 153P2" of the separation insulating patterns 153B".

[0234] Reference ​ , can be etched ​ The upper portion of the first gate pattern 151 is shown. The gate length may be defined by a height 151H" of the first gate pattern 151" remaining after etching.

[0235] Next, an upper insulating layer 271 may be formed. The upper insulating layer 271 may cover ​ The sidewall insulating layer 281 , the vertical source contact 287 , the gate insulating layer 149 , the first gate pattern 151 ″, the separation insulating pattern 153B″, the second gate patterns 161G1 ″, 161G2 ″ and 161G3 ″, and the first mask pattern 147 .

[0236] Thereafter, the surface of the upper insulating layer 271 may be planarized so that ​ The first mask pattern 147 is exposed. Thereafter, the above reference Figures 21A to 21C The process described above forms the concentrations of conductive impurities in the first region CA" and the second region CB" included in the upper channel portion 141C to be different from each other. In one embodiment, the second region CB" can be defined as a doped region including conductive impurities. The first region CA" can be defined as a region formed of a substantially intrinsic semiconductor material.

[0237] Afterwards, you can use the above reference Figure 21D and Figure 21E The described process forms a conductive contact 191" in contact with the second region CB" of the upper channel portion 141C.

[0238] You can use the above reference Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 23E , Figure 23F , Figure 23G and Figure 23H The process described above is provided by reference Figure 6 A semiconductor memory device is described.

[0239] According to an embodiment of the present disclosure, a separation insulating pattern may be stably disposed between a first gate pattern in a first row and a first gate pattern in a second row. According to an embodiment of the present disclosure, first gate patterns spaced apart from each other may be coupled to each other through a second gate pattern, and thus a drain selection line may be defined. According to an embodiment of the present disclosure, process variations in the length of an upper channel portion of a channel structure surrounded by a first gate pattern and process variations in the range of a dopant region in the channel structure may be reduced.

[0240] Figure 24 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0241] Referring to Figure 24 , the memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0242] The memory device 1120 may be a multi-chip package composed of a plurality of flash memory chips. The memory device 1120 may include a lower channel portion surrounded by a memory layer, an upper channel portion on the lower channel portion, a gate insulating layer surrounding the upper channel portion, a first gate pattern surrounding the gate insulating layer, a separation insulating pattern disposed on one side of the first gate pattern, and a second gate pattern disposed on the other side of the first gate pattern. The first gate pattern may include a first sidewall contacting the separation insulating pattern and a second sidewall contacting the second gate pattern.

[0243] The memory controller 1110 may control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as a working memory of the CPU 1112. The CPU 1112 may perform an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 may be equipped with a data exchange protocol for a host coupled to the memory system 1100. The error correction block 1114 may detect an error included in data read from the memory device 1120, and may correct the detected error. The memory interface 1115 may interface with the memory device 1120. The memory controller 1110 may further include a read-only memory (ROM) or the like that stores code data for docking with a host.

[0244] The above memory system 1100 may be a memory card or a solid state drive (SSD), in which the memory device 1120 and the memory controller 1110 are combined with each other. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0245] Figure 25 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure.

[0246] Referring Figure 25 , the computing system 1200 may include a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. When the computing system 1200 is a mobile device, it may further include a battery for providing an operating voltage to the computing system 1200, and may further include an application chipset, an image processor, mobile DRAM, etc.

[0247] The memory system 1210 may include a memory device 1212 and a memory controller 1211.

[0248] The memory device 1212 may include a lower channel portion surrounded by a memory layer, an upper channel portion on the lower channel portion, a gate insulating layer surrounding the upper channel portion, a first gate pattern surrounding the gate insulating layer, a separation insulating pattern provided on one side of the first gate pattern, and a second gate pattern provided on the other side of the first gate pattern. The first gate pattern may include a first sidewall contacting the separation insulating pattern and a second sidewall contacting the second gate pattern.

[0249] The memory controller 1211 may be implemented in the same manner as the memory controller 1110 described with reference to Figure 24 .

[0250] The present disclosure may improve the operational reliability of a semiconductor memory device by reducing process variations.

[0251] Cross - reference to Related Applications

[0252] This application claims priority to Korean Patent Application No. 10 - 2021 - 0028909, filed with the Korean Intellectual Property Office on March 4, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: a stack including conductive patterns and interlayer insulating layers, the conductive patterns and the interlayer insulating layers being parallel to a plane, the conductive patterns and the interlayer insulating layers being alternately arranged in a first direction intersecting the plane; a separation insulating pattern disposed above the stack, the separation insulating pattern including a horizontal portion parallel to the plane and a vertical portion continuously extending from the horizontal portion in the first direction; a first selection line and a second selection line disposed above the horizontal portion of the separation insulating pattern, the vertical portion of the separation insulating pattern being disposed between the first selection line and the second selection line; a plurality of first channel portions passing through the stack; a memory layer disposed between each of the plurality of first channel portions and the stack; a plurality of second channel portions disposed on the plurality of first channel portions and including a first group of second channel portions and a second group of second channel portions, the first group of second channel portions passing through the first selection line and the horizontal portion of the separation insulating pattern, the second group of second channel portions passing through the second selection line and the horizontal portion of the separation insulating pattern; and a gate insulating layer disposed on sidewalls of each of the plurality of second channel portions and a corresponding one of the first selection line and the second selection line.

2. The semiconductor memory device according to claim 1, wherein, the vertical portion of the separation insulating pattern includes a first surface facing the first selection line and a second surface facing the second selection line, wherein the first surface includes a first groove, and wherein the second surface includes a second groove.

3. The semiconductor memory device according to claim 2, wherein, the first group of second channel portions includes first side second channel portions in the first groove, wherein the second group of second channel portions includes second side second channel portions in the second groove, wherein the first selection line extends between the first groove and the first side second channel portions, and wherein the second selection line extends between the second groove and the second side second channel portions.

4. The semiconductor memory device according to claim 1, wherein, in the first direction, the thickness of each of the first selection line and the second selection line is greater than the thickness of each of the conductive patterns.

5. The semiconductor memory device according to claim 1, wherein, each of the plurality of first channel portions includes: a channel layer extending along an inner wall of the memory layer; a core insulating layer surrounded by the channel layer; and a semiconductor pattern disposed between each of the plurality of second channel portions and the core insulating layer.

6. The semiconductor memory device according to claim 1, wherein, each of the plurality of second channel portions protrudes in the first direction with respect to the first selection line and the second selection line.

7. The semiconductor memory device according to claim 1, wherein, each of the plurality of second channel portions protrudes in the first direction with respect to the gate insulating layer.

8. The semiconductor memory device according to claim 1, wherein, the gate insulating layer protrudes in the first direction with respect to the first selection line and the second selection line.

9. The semiconductor memory device according to claim 1, the semiconductor memory device further comprises: a conductive contact portion provided on each of the plurality of second channel portions.

10. The semiconductor memory device according to claim 9, wherein, the width of the conductive contact portion is greater than the width of each of the plurality of second channel portions.

11. The semiconductor memory device according to claim 1, wherein, each of the first selection line and the second selection line includes a first gate pattern surrounding the gate insulating layer and a second gate pattern surrounding the first gate pattern, and wherein, the first gate pattern and the second gate pattern comprise the same conductive material.

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