Stepped high electron mobility transistor and manufacturing method thereof

Abstract

The invention discloses a stepped high-electron-mobility transistor and a manufacturing method, the stepped high-electron-mobility transistor comprises a substrate layer, a buffer layer, a channel layer and a barrier layer which are stacked along a first direction, the channel layer is used for providing a conducting channel, and the barrier layer is used for providing a barrier layer; a first electrode structure, a cap layer structure and a second electrode structure which are sequentially arranged in the second direction are arranged on the surface, away from the channel layer, of the barrier layer, a gate structure is arranged on the surface, away from the barrier layer, of the cap layer structure, the cap layer structure comprises a plurality of step layers which are sequentially arranged in the first direction, each step layer is made of p-type GaN materials, and the p-type GaN materials are made of p-type GaN materials. And the lengths of the plurality of step layers in the second direction are gradually reduced along the direction far away from the barrier layer. According to the stepped high-electron-mobility transistor and the manufacturing method, the stepped high-electron-mobility transistor has the high capability of restraining dynamic on-resistance degradation so as to restrain the current collapse effect, and the grid edge electric field concentration effect can be effectively restrained.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor devices, and particularly relates to a stepped high electron mobility transistor and a manufacturing method thereof. Background Art

[0002] In semiconductor power devices, GaN HEMT (GaN High electron mobility transistor) has excellent characteristics such as low on-state loss and high switching frequency. During the application process of GaN HEMT devices, problems such as dynamic resistance degradation and electric field concentration in the gate region will occur.

[0003] Currently, a p-GaN structure connected to the drain is usually additionally introduced in the drain region of GaN HEMT devices, but this structure has limited ability to suppress on-state resistance degradation under high drain stress; or field plate technology is used to suppress the problem of electric field concentration at the gate edge, but the suppression ability of the field plate structure is limited. Summary of the Invention

[0004] This application provides a stepped high electron mobility transistor and a manufacturing method thereof, which has a strong ability to suppress dynamic on-state resistance degradation to suppress the current collapse effect, and can effectively suppress the electric field concentration effect at the gate edge.

[0005] This application provides a stepped high electron mobility transistor, which includes a substrate layer, a buffer layer, a channel layer, and a barrier layer stacked along a first direction. A two-dimensional electron gas can be polarized and generated between the buffer layer and the channel layer. The channel layer is used to provide a conductive channel. On the surface of the barrier layer far from the channel layer, a first electrode structure, a cap layer structure, and a second electrode structure are sequentially arranged along a second direction. On the surface of the cap layer structure far from the barrier layer, a gate structure is provided. The cap layer structure includes multiple stepped layers arranged in sequence along the first direction. Each stepped layer is made of p-type GaN material. Along the direction away from the barrier layer, the lengths of the multiple stepped layers in the second direction show a decreasing trend.

[0006] For the stepped high electron mobility transistor as above, the cap layer structure further includes multiple insertion layers. Each insertion layer is made of AlGaN or AlN material. A layer of insertion layer is provided between adjacent stepped layers, and each insertion layer has the same length as the stepped layer on its side far from the barrier layer in the second direction.

[0007] For the stepped high electron mobility transistor as above, the distances between the multiple stepped layers arranged along the direction away from the barrier layer and the first electrode structure are equal, and the distances between the multiple stepped layers arranged along the direction away from the barrier layer and the second electrode structure show an increasing trend; wherein, the first electrode structure is the source electrode, and the second electrode structure is the drain electrode.

[0008] The stepped high electron mobility transistor as described above, wherein, along the direction from the barrier layer to the gate structure, the thickness of the multi-layer stepped layer shows an increasing trend in the first direction.

[0009] The stepped high electron mobility transistor as described above, wherein the stepped high electron mobility transistor further includes a protective layer, the protective layer covers the surface of the barrier layer and the surface of the cap layer structure, and the protective layer is provided on the same layer as the first electrode structure, the second electrode structure and the gate structure.

[0010] The stepped high electron mobility transistor as described above, wherein one end of the stepped layer attached to the barrier layer is connected to the second electrode structure, and the other end is spaced apart from the first electrode structure 5 through the protective layer; wherein, the first electrode structure is the source electrode and the second electrode structure is the drain electrode.

[0011] The stepped high electron mobility transistor as described above, wherein the stepped high electron mobility transistor further includes two isolation regions, each isolation region extends from the surface of the barrier layer away from the channel layer into the channel layer, one isolation region is provided on the side of the first electrode structure away from the second electrode structure, and the other isolation region is provided on the side of the second electrode structure away from the first electrode structure.

[0012] The stepped high electron mobility transistor as described above, wherein the isolation region is an ion implantation region, and the isolation region includes at least one of ions of F, N, B, Ar, Fe; or, the isolation region is an etching region, and the isolation region has a groove structure formed by being recessed inward from the surface of the barrier layer.

[0013] The stepped high electron mobility transistor as described above, wherein both the channel layer and the barrier layer are made of group III nitride semiconductor materials, and the bandgap of the channel layer is smaller than the bandgap of the barrier layer.

[0014] On the other hand, the present application also provides a manufacturing method of a stepped high electron mobility transistor, which includes:

[0015] Epitaxial growth is performed on one side of the substrate layer in the first direction to form a buffer layer;

[0016] A channel layer, a barrier layer and a cap layer structure are sequentially formed on the side of the buffer layer away from the substrate layer;

[0017] The cap layer structure is etched multiple times to form a stepped cap layer structure, and along the direction away from the barrier layer, the lengths of the steps of the cap layer structure show a decreasing trend in the second direction;

[0018] A protective layer is formed on the surfaces of the barrier layer and the cap layer structure;

[0019] Etch the protective layer to form accommodation grooves on both sides of the cap layer structure, and form a first electrode structure and a second electrode structure in the two accommodation grooves respectively;

[0020] Form two isolation regions in the barrier layer and at least part of the channel layer, and the first electrode structure and the second electrode structure are arranged between the two isolation regions;

[0021] Etch the protective layer to form an accommodation groove on the top of the cap layer structure, and form a gate structure in this accommodation groove.

[0022] The manufacturing method of the stepped high electron mobility transistor as above, wherein the cap layer structure includes a stepped layer and an insertion layer that are sequentially stacked in a first direction. In the step of etching the cap layer structure multiple times to form a stepped cap layer structure,

[0023] Etch the first stepped layer of the cap layer structure by a first etching method, and the first stepped layer is arranged on the outermost layer of the cap layer structure;

[0024] Etch the first insertion layer of the cap layer structure by a second etching method until the length of the first insertion layer in a second direction is equal to the length of the first stepped layer in the second direction, and the first stepped layer and the first insertion layer form a first-level stepped structure;

[0025] Along the direction close to the barrier layer, sequentially use the first etching method and the second etching method to etch the multiple stepped layers and multiple insertion layers multiple times to form a multi-level stepped structure, and the length of the multi-level stepped structure in the second direction shows an increasing trend;

[0026] Etch the stepped layer attached to the barrier layer by the first etching method, and the length of this stepped layer in the second direction is greater than the length of the adjacent stepped structure in the second direction.

[0027] The manufacturing method of the stepped high electron mobility transistor as above, wherein in the step of forming two isolation regions in the barrier layer and at least part of the channel layer,

[0028] Perform ion implantation on a part of the protective layer on the side of the first electrode structure away from the second electrode structure, and implant from the protective layer into the channel layer to form one of the isolation regions;

[0029] Perform ion implantation on a part of the protective layer on the side of the second electrode structure away from the first electrode structure, and implant from the protective layer into the channel layer to form the other isolation region.

[0030] The manufacturing method of the stepped high electron mobility transistor as above, wherein etch a part of the protective layer on the side of the first electrode structure away from the second electrode structure and the corresponding barrier layer and channel layer to form one of the isolation regions;

[0031] Etch a part of the protective layer on the side of the second electrode structure away from the first electrode structure, as well as the corresponding barrier layer and channel layer of this part of the protective layer, to form another isolation region.

[0032] The stepped high electron mobility transistor of the present application includes a substrate layer, a buffer layer, a channel layer, and a barrier layer stacked along a first direction. On the surface of the barrier layer away from the channel layer, a first electrode structure, a cap layer structure, and a second electrode structure are sequentially arranged along a second direction. On the surface of the cap layer structure away from the barrier layer, a gate structure is provided. Among them, a polarization effect can occur between the barrier layer and the channel layer to generate a two-dimensional electron gas, and the cap layer structure can deplete the underlying two-dimensional electron gas, making the threshold voltage of the device positive.

[0033] In the cap layer structure, it includes multiple stepped layers arranged sequentially along the first direction, and each stepped layer is made of p-type GaN material. Since the cap layer structure is located between the first electrode structure and the second electrode structure in the second direction, it can cover part of the surface of the barrier layer, effectively shielding the traps on the surface of the barrier layer, suppressing the degradation of the dynamic on-resistance of the device, and thus suppressing the current collapse effect; and, along the direction away from the barrier layer, the lengths of the multiple stepped layers in the second direction show a decreasing trend, forming a stepped structure. When the device withstands voltage, due to the overall stepped structure of the cap layer structure, the thickness of the part near the edge of the electrode in the first direction is thinner, and there are fewer acceptor impurities in this part. Therefore, the depletion region can quickly expand from the edge of the cap layer structure towards the inside, effectively suppressing the gate edge electric field concentration effect. Brief Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0035] Figure 1 It is a schematic diagram of the overall structure of the stepped high electron mobility transistor according to the embodiment of the present application;

[0036] Figure 2 It is a schematic diagram of forming the cap layer structure of the stepped high electron mobility transistor according to the embodiment of the present application;

[0037] Figure 3 It is a schematic diagram of initially etching the cap layer structure of the stepped high electron mobility transistor according to the embodiment of the present application;

[0038] Figure 4 It is a schematic diagram of completely etching the cap layer structure of the stepped high electron mobility transistor according to the embodiment of the present application;

[0039] Figure 5 Schematic diagram of forming a protective layer, a first electrode structure and a second electrode structure of the stepped high electron mobility transistor according to an embodiment of the present application;

[0040] Figure 6 Schematic diagram of forming an isolation region of the stepped high electron mobility transistor according to an embodiment of the present application;

[0041] Figure 7 Schematic diagram of the structure of another embodiment of the stepped high electron mobility transistor according to an embodiment of the present application;

[0042] Figure 8 Overall flowchart of the manufacturing method of the stepped high electron mobility transistor according to an embodiment of the present application;

[0043] Figure 9 Flowchart of etching the cap layer structure in the manufacturing method of the stepped high electron mobility transistor according to an embodiment of the present application.

[0044] Explanation of the reference numerals in the drawings:

[0045] 1. Substrate layer; 2. Buffer layer; 3. Channel layer; 4. Barrier layer; 5. First electrode structure; 6. Cap layer structure; 61. Step layer; 62. Insertion layer; 7. Second electrode structure; 8. Gate structure; 9. Protective layer; 91. Accommodating groove; 10. Isolation region; 11. Connection line; X. First direction; Y. Second direction. Detailed implementation manners

[0046] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0047] As Figure 1As shown in the figure, an embodiment of the present application provides a stepped high electron mobility transistor, which includes a substrate layer 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 stacked along the first direction X. A two-dimensional electron gas can be polarized and generated between the buffer layer 2 and the channel layer 3. The channel layer 3 is used to provide a conductive channel. On the surface of the barrier layer 4 away from the channel layer 3, a first electrode structure 5, a cap layer structure 6, and a second electrode structure 7 are sequentially arranged along the second direction Y. On the surface of the cap layer structure 6 away from the barrier layer 4, a gate structure 8 is provided. The cap layer structure 6 includes multiple stepped layers 61 arranged sequentially along the first direction X. Each stepped layer 61 is made of p-type GaN material. Along the direction away from the barrier layer 4, the lengths of the multiple stepped layers 61 in the second direction Y show a decreasing trend.

[0048] It should be noted that the first direction X is Figure 1 the up and down direction in Figure 1 and the second direction Y is

[0049] Specifically, when implemented, the stepped high electron mobility transistor of the present application includes a substrate layer 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 stacked along the first direction X. On the surface of the barrier layer 4 away from the channel layer 3, a first electrode structure 5, a cap layer structure 6, and a second electrode structure 7 are also sequentially arranged along the second direction Y. The first electrode structure 5 is the source electrode, and the second electrode structure 7 is the drain electrode. A gate structure 8 is provided on the surface of the cap layer structure 6 away from the barrier layer 4. A polarization effect can occur between the barrier layer 4 and the channel layer 3 to generate a two-dimensional electron gas. The cap layer structure 6 can deplete the two-dimensional electron gas below, so that the threshold voltage of the device is positive. When the gate-source voltage between the gate structure 8 and the first electrode structure 5 is 0V, the cap layer structure 6 depletes the two-dimensional electron gas below, and the conductive channel between the first electrode structure 5 and the second electrode structure 7 is disconnected, and the device is turned off as a whole. When a positive voltage is applied to the gate structure 8, a two-dimensional electron gas appears, and a connected conductive channel appears between the first electrode structure 5 and the second electrode structure 7, and the device is in an on state.

[0050] In the cap layer structure 6, it includes multiple stepped layers 61 arranged in sequence along the first direction X. Each stepped layer 61 is made of p-type GaN material. Since the cap layer structure 6 is located between the first electrode structure 5 and the second electrode structure 7 in the second direction Y, it can cover the surface of the barrier layer 4 between the two electrodes, effectively shielding the traps on the surface of the barrier layer, suppressing the degradation of the dynamic on-resistance of the device, and thus suppressing the current collapse effect. Moreover, along the direction away from the barrier layer 4, the lengths of the multiple stepped layers 61 in the second direction Y show a decreasing trend, forming a stepped structure. When the device withstands voltage, due to the overall stepped structure of the cap layer structure 6, the thickness of the edge part near the electrode in the first direction X is relatively thin, and there are fewer acceptor impurities in this part. Therefore, the depletion region can rapidly expand from the edge of the cap layer structure 6 towards the inside, effectively suppressing the gate edge electric field concentration effect.

[0051] It should be noted that in the cap layer structure 6, the longer the length of its stepped layer 61 in the second direction Y, the better the shielding effect of the cap layer structure 6 on the traps on the surface of the barrier layer 4, improving the suppression ability of the degradation of the dynamic on-resistance of the device, and thus further enhancing the suppression effect on the current collapse effect. However, as the length of the stepped layer 61 increases, it will lead to an increase in the gate capacitance and an increase in device loss. Therefore, in practical applications, it is necessary to design the length of the stepped layer 61 according to actual requirements to achieve a balance between the suppression effect of the current collapse effect and device loss.

[0052] Specifically, the cap layer structure 6 has at least three stepped layers 61 arranged in a stepped shape in sequence. The depletion region can gradually diffuse within at least three stepped layers 61 with a decreasing length trend, ensuring the diffusion speed and diffusion effect. Therefore, a sufficient number of stepped layers 61 ensures the suppression effect of the cap layer structure 6 on the gate edge electric field concentration effect.

[0053] In the stepped high electron mobility transistor of the embodiment of the present application, along the direction from the barrier layer 4 to the gate structure 8, the thicknesses of the multiple stepped layers 61 in the first direction X show an increasing trend. When the depletion region diffuses, it can start to diffuse from the stepped layer 61 that is in contact with the barrier layer 4 and has the smallest thickness. This stepped layer 61 has a large contact area with the barrier layer 4 and a small thickness, and there are fewer acceptor impurities. Therefore, the depletion region is easy to diffuse. After completely diffusing within this stepped layer 61, it gradually diffuses upward to the multiple stepped layers 61 with an increasing thickness. The stepped layers 61 with an increasing thickness ensure the diffusion effect of the depletion region, enabling the depletion layer to diffuse step by step and rapidly, thus further enhancing the suppression effect on the gate edge electric field concentration effect.

[0054] In some optional embodiments, the thicknesses of the multiple stepped layers 61 in the first direction X are equal, or show a trend of decreasing thickness, increasing first and then decreasing, or decreasing first and then increasing along the direction from the barrier layer 4 to the gate structure 8.

[0055] In an embodiment of the present application, both the channel layer 3 and the barrier layer 4 are made of group-III nitride semiconductor materials, and the bandgap of the channel layer 3 is smaller than that of the barrier layer 4. Spontaneous polarization and piezoelectric polarization effects will occur between the channel layer 3 and the barrier layer 4 made of group-III nitride semiconductor materials, and a two-dimensional electron gas with high concentration and high mobility will be formed at the interface between the two, thereby forming a current between the first electrode structure 5 and the second electrode structure 7. Among them, the group-III nitride includes at least one of GaN, AlN, InN, and their ternary or quaternary compounds.

[0056] Specifically, the channel layer 3 is made of at least one material selected from GaN, InGaN, AlGaN, and InAlGaN; the barrier layer 4 is made of at least one material selected from GaN, AlN, AlGaN, InGaN, and InAlGaN.

[0057] Specifically, the substrate layer 1 can use a Si substrate, a SiC substrate, a Sapphire substrate, or a GaN substrate; the buffer layer 2 is made of at least one material selected from GaN, AlN, InGaN, AlGaN, and InAlGaN. By setting the buffer layer 2, it is beneficial to further perform epitaxial growth of the channel layer 3 and the barrier layer 4.

[0058] For the stepped high electron mobility transistor of the embodiment of the present application, the cap layer structure 6 further includes multiple insertion layers 62, each insertion layer 62 is made of AlGaN material, a layer of insertion layer 62 is provided between adjacent stepped layers 61, and each insertion layer 62 has the same length as the stepped layer 61 on the side away from the barrier layer 4 in the second direction Y.

[0059] In specific implementation, each insertion layer 62 of the cap layer structure 6 is made of AlGaN material or AlN, and each insertion layer 62 is disposed between adjacent stepped layers 61. When etching the cap layer structure 6, a first etching method of selective dry etching is required to etch the stepped layer 61, and a second etching method of wet etching, digital etching, low-speed dry etching or a combination of the above is used to etch the insertion layer 62. During the process of etching one of the stepped layers 61 by the first etching method, since the first etching method cannot etch the insertion layer 62, the etching will stop on the surface of the insertion layer 62 adjacent to this stepped layer 61. At this time, the second etching method is required to etch this insertion layer 62, and the length of this insertion layer 62 in the second direction Y is made the same as the length of the stepped layer 61 etched by the first etching method in the second direction Y, so as to form one-level stepped structure of the cap layer structure 6. Therefore, the setting of the insertion layer 62 can control the etching depth of the stepped layer 61, and enable the cap layer structure 6 to form a multi-level stepped structure composed of the stepped layer 61 and the insertion layer 62. Since each stepped structure has a stepped layer 61 made of p-type GaN material, the stepped cap layer structure 6 can suppress the current collapse effect and the gate edge electric field concentration effect.

[0060] Specifically, the one-level stepped structure disposed on the surface of the barrier layer 4 only includes the stepped layer 61, and the remaining stepped structures are all stepped layers 61 and insertion layers 62 that are stacked and have the same length. This can enable the barrier layer 4 to be disposed in contact with the stepped layer 61 made of p-type GaN material, thereby further enhancing the ability of the stepped high electron mobility transistor to suppress the current collapse effect and the gate edge electric field concentration effect.

[0061] In the stepped high electron mobility transistor according to the embodiment of the present application, the distances between the multiple stepped layers 61 arranged in the direction away from the barrier layer 4 and the first electrode structure 5 are equal, and the distances between the multiple stepped layers 61 arranged in the direction away from the barrier layer 4 and the second electrode structure 7 show an increasing trend; wherein, the first electrode structure 5 is the source electrode, and the second electrode structure 7 is the drain electrode.

[0062] In specific implementation, the first electrode structure 5 is the source electrode of the device, the second electrode structure 7 is the drain electrode of the device, the distances between the multiple stepped layers 61 arranged in the direction away from the barrier layer 4 and the first electrode structure 5 are equal, that is, the side of the cap layer structure 6 close to the source electrode is a planar structure; the distances between the multiple stepped layers 61 arranged in the direction away from the barrier layer 4 and the second electrode structure 7 show an increasing trend, that is, the side of the cap layer structure 6 close to the drain electrode is a stepped structure. This can ensure that when the device withstands voltage, the depletion region with a larger area close to the drain electrode can expand in the stepped cap layer structure 6, thereby effectively suppressing the gate edge electric field concentration effect.

[0063] In some optionally implemented embodiments, the first electrode structure 5 is the drain, the second electrode structure 7 is the source, the distance between the multi-layer stepped layer 61 arranged in the direction away from the barrier layer 4 and the first electrode structure 5 shows an increasing trend, and the distance between the multi-layer stepped layer 61 arranged in the direction away from the barrier layer 4 and the second electrode structure 7 is equal. In this way, it can also ensure that the side of the cap layer structure 6 close to the drain is a stepped structure, and the side close to the source is a planar structure.

[0064] The stepped high electron mobility transistor according to the embodiment of the present application, wherein the stepped high electron mobility transistor further includes a protective layer 9, the protective layer 9 covers the surface of the barrier layer 4 and the surface of the cap layer structure 6, and the protective layer 9 is arranged on the same layer as the first electrode structure 5, the second electrode structure 7 and the gate structure 8.

[0065] Specifically, during implementation, the protective layer 9 is a passivation layer covering the surface of the barrier layer 4 and the surface of the cap layer structure 6, and is formed by oxides such as SiO 2 , Si 3 N 4 and the like. It can protect the barrier layer 4 and the cap layer structure 6 from being eroded by the external environment, and can also reduce the occurrence of leakage current; moreover, the protective layer 9 is arranged on the same layer as the first electrode structure 5, the second electrode structure 7 and the gate structure 8, and the first electrode structure 5, the second electrode structure 7 and the gate structure 8 are not completely covered by the protective layer 9, and can be connected to the external circuit, so as to realize the switching effect of the stepped high electron mobility transistor in the circuit, and the protective layer 9 can isolate the first electrode structure 5, the second electrode structure 7 and the gate structure 8 to avoid short circuit between the electrodes.

[0066] Specifically, when the protective layer 9 covers the surface of the cap layer structure 6, it can completely cover the surface of the cap layer structure 6 away from the barrier layer 4, the surface facing the first electrode structure 5 and the stepped surface facing the second electrode structure 7, and when the protective layer 9 covers the planar or stepped surface, the thickness perpendicular to its extending direction always remains the same, which can avoid the reduction of the two-dimensional electron gas concentration and ensure the conduction effect between the source and the drain. Therefore, the part of the protective layer 9 covering the stepped surface has a layer structure in the same extending direction as the stepped surface, that is, it is also a stepped structure.

[0067] In the embodiment of the present application, as Figure 1 shown, both ends of the cap layer structure 6 in the second direction Y are spaced apart from the first electrode structure 5 and the second electrode structure 7 respectively through the protective layer 9.

[0068] In an alternative embodiment of the present application, one end of the stepped layer 61 attached to the barrier layer 4 is connected to the second electrode structure 7, and the other end is spaced apart from the first electrode structure 5 through the protective layer 9; wherein, the first electrode structure 5 is the source electrode, and the second electrode structure 7 is the drain electrode. Such an arrangement enables the entire side of the cap layer structure 6 close to the drain electrode to be in contact with the barrier layer 4, ensuring that there is sufficient contact area between the bottommost stepped layer 61 and the barrier layer 4. The depletion region with a larger area near the drain electrode can be fully extended in the bottommost stepped layer 61, further enhancing the suppression effect of the gate edge electric field concentration effect.

[0069] The stepped high electron mobility transistor according to the embodiment of the present application, wherein the stepped high electron mobility transistor further includes two isolation regions 10, and each isolation region 10 extends from the surface of the barrier layer 4 away from the channel layer 3 into the channel layer 3. One isolation region 10 is disposed on the side of the first electrode structure 5 away from the second electrode structure 7, and the other isolation region 10 is disposed on the side of the second electrode structure 7 away from the first electrode structure 5.

[0070] Specifically, when implemented, the two isolation regions 10 are respectively disposed at both ends of the overall device in the second direction Y. The first electrode structure 5, the cap layer structure 6, the gate structure 8, and the second electrode structure 7 are all disposed between the two isolation regions 10. The two isolation regions 10 both extend from the surface of the barrier layer 4 away from the channel layer 3 into the channel layer 3, which can block the two-dimensional electron gas connection between adjacent devices, that is, prevent the conduction of the conductive channels between adjacent devices, enabling each device to independently form a complete switching structure and avoiding the mutual influence between adjacent devices.

[0071] The stepped high electron mobility transistor according to the embodiment of the present application, wherein the isolation region 10 is an ion implantation region, and the isolation region 10 includes at least one of ions such as F, N, B, Ar, and Fe; or, the isolation region 10 is an etched region, and the isolation region 10 has a groove structure formed by being recessed inward from the surface of the barrier layer 4.

[0072] It should be noted that the implanted ions in the isolation region 10 include but are not limited to at least one of ions such as F, N, B, Ar, and Fe.

[0073] Specifically, when implemented, the isolation region 10 formed by implanting ions such as F, N, B, Ar, and Fe can isolate the two-dimensional electron gas on both sides of it, thereby preventing the two-dimensional electron gas on both sides from being connected; while the isolation region 10 with a groove structure formed by etching can cause the two-dimensional electron gas at the isolation region 10 to disappear, and can also prevent the two-dimensional electron gas on both sides from being connected.

[0074] Such as Figure 7As shown, in an alternative embodiment, the first electrode structure 5 of the stepped high electron mobility transistor is connected to the gate structure 8 through a connecting line 11, so that the overall device forms a unidirectional switching device.

[0075] As Figures 1 to 9 shown, the embodiment of the present application also provides a manufacturing method of a stepped high electron mobility transistor, which includes:

[0076] S100, as Figure 2 shown, an epitaxial growth is performed on one side of the substrate layer 1 in the first direction X to form a buffer layer 2;

[0077] S200, as Figure 2 shown, a channel layer 3, a barrier layer 4, and a cap layer structure 6 are sequentially formed on the side of the buffer layer 2 away from the substrate layer 1; among them, the channel layer 3, the barrier layer 4, and the cap layer structure 6 are all formed by epitaxial growth. When forming the cap layer structure 6, a stepped layer 61 needs to be formed on the surface of the barrier layer 4 first, and then an insertion layer 62 is continuously formed on the surface of the stepped layer 61. The subsequent formation sequence is that the stepped layer 61 and the insertion layer 62 are alternately formed, and the outermost surface layer of the final cap layer structure 6 is the stepped layer 61;

[0078] S300, as Figure 3 and Figure 4 shown, the cap layer structure 6 is etched multiple times to form a stepped cap layer structure 6. Along the direction away from the barrier layer 4, the lengths of the steps of the cap layer structure 6 in the second direction Y show a decreasing trend;

[0079] S400, as Figure 5 shown, a protective layer 9 is formed on the surfaces of the barrier layer 4 and the cap layer structure 6; among them, the protective layer 9 is a passivation layer formed by oxides such as SiO 2 、Si 3 N 4 and is formed by growing on the surfaces of the barrier layer 4 and the cap layer structure 6;

[0080] S500, as Figure 5 shown, the protective layer 9 is etched to form receiving grooves 91 provided on both sides of the cap layer structure 6, and a first electrode structure 5 and a second electrode structure 7 are respectively formed in the two receiving grooves 91; among them, the receiving grooves 91 are etched from the surface of the protective layer 9 to the surface of the barrier layer 4. The first electrode structure 5 and the second electrode structure 7 formed in the receiving grooves 91 can respectively contact the barrier layer 4 on both sides of the cap layer structure 6, and a conductive channel that is connected and communicated can be formed between the two through the barrier layer 4 and the channel layer 3, so as to achieve the conductive connection between the two and realize the internal conduction of the device;

[0081] S600, as Figure 6As shown, two isolation regions 10 are formed in the barrier layer 4 and at least a part of the channel layer 3, and the first electrode structure 5 and the second electrode structure 7 are disposed between the two isolation regions 10;

[0082] S700, such as Figure 1 As shown, the protective layer 9 is etched to form a receiving groove 91 disposed on the top of the cap layer structure 6, and a gate structure 8 is formed in the receiving groove 91; wherein, the receiving groove 91 is etched from the surface of the protective layer 9 to the surface of the cap layer structure 6, and the gate structure 8 formed in the receiving groove 91 can be in contact with the cap layer structure 6, thereby controlling the on / off of the internal conductive channel of the device.

[0083] In specific implementation, the manufacturing method of the stepped high electron mobility transistor according to the embodiment of the present application can form a stepped cap layer structure 6 on the surface of the barrier layer 4. The cap layer structure 6 is between the first electrode structure 5 and the second electrode structure 7 in the second direction Y, and it can cover the surface of the barrier layer 4 between the two electrodes, effectively shielding the traps on the barrier layer surface, suppressing the degradation of the dynamic on-resistance of the device, and thus suppressing the current collapse effect; and, along the direction away from the barrier layer 4, the lengths of the steps of the cap layer structure 6 in the second direction Y show a decreasing trend. Therefore, when the device withstands voltage, the thickness of the part near the edge of the electrode in the first direction X is thinner, and there are fewer acceptor impurities in this part. Therefore, the depletion region can quickly expand from the edge of the cap layer structure 6 towards the inside, effectively suppressing the gate edge electric field concentration effect.

[0084] Specifically, in the step of forming the first electrode structure 5 and the second electrode structure 7 in the two receiving grooves 91 respectively, it is necessary to deposit electrode metal in the receiving grooves 91, and then perform an annealing operation in nitrogen to form the first electrode structure 5 and the second electrode structure 7.

[0085] Specifically, in the step of forming the gate structure 8 in the receiving groove 91, it is only necessary to deposit electrode metal in the receiving groove 91 to form the gate structure 8.

[0086] In some optional implementation manners, the steps of setting the first electrode structure 5 and the second electrode structure 7 in S500, the step of forming the isolation region 10 in S600, and the step of setting the gate structure 8 in S700 can be in any order, such as first forming the isolation region 10, and then setting the first electrode structure 5, the second electrode structure 7 and the gate structure 8.

[0087] Such as Figure 9 As shown, the manufacturing method of the stepped high electron mobility transistor according to the embodiment of the present application, wherein the cap layer structure 6 includes a stepped layer 61 and an insertion layer 62 that are sequentially overlapped along the first direction X. In the step of etching the cap layer structure 6 multiple times to form the stepped cap layer structure 6,

[0088] S410, as shown in Figure 3 , the first etching method is used to etch the first stepped layer 61 of the cap layer structure 6. The first stepped layer 61 is disposed on the outermost layer of the cap layer structure 6. Among them, the first etching method is selective dry etching, which can only etch the stepped layer 61;

[0089] S420, as shown in Figure 3 , the second etching method is used to etch the first inserted layer 62 of the cap layer structure 6 until the length of the first inserted layer 62 in the second direction Y is equal to the length of the first stepped layer 61 in the second direction Y. The first stepped layer 61 and the first inserted layer 62 form a first-level stepped structure. Among them, the second etching method is wet etching, digital etching, low-speed dry etching or a combination of the above etching methods, which can etch the inserted layer 62;

[0090] S430, as shown in Figure 3 , along the direction close to the barrier layer 4, the first etching method and the second etching method are successively used to etch the multiple stepped layers 61 and the multiple inserted layers 62 multiple times to form a multi-level stepped structure. The length of the multi-level stepped structure in the second direction Y shows an increasing trend;

[0091] S440, as shown in Figure 4 , the first etching method is used to etch the stepped layer 61 attached to the barrier layer 4. The length of this stepped layer 61 in the second direction Y is greater than the length of the adjacent stepped structure in the second direction Y.

[0092] Specifically, when etching the first stepped layer 61 by the first etching method, the etching will self-stop at the first inserted layer 62 in contact with the first stepped layer 61. After the etching of the first stepped layer 61 is completed to reach the required length, the second etching method is used to etch the first inserted layer 62 until the length of the first inserted layer 62 is equal to that of the first stepped layer 61, forming a first-level step. After forming the first-level step, the above etching steps are repeated successively by the first etching method and the second etching method until a multi-level step is formed, and the lengths of the stepped layer 61 and the inserted layer 62 in each level of the step are equal; finally, the stepped layer 61 with the longest length is formed by the first etching method, and this stepped layer 61 is disposed in contact with the barrier layer 4. Through the setting of the multiple inserted layers 62, the etching operation is facilitated, and the thickness of each level of the step of the cap layer structure 6 along the first direction X and the length along the second direction Y can be stably controlled, improving the accuracy of the etching operation.

[0093] In the method for manufacturing a stepped high electron mobility transistor according to an embodiment of the present application, in the step of forming two isolation regions 10 in the barrier layer 4 and at least a part of the channel layer 3,

[0094] Ion implantation is performed on a part of the protective layer 9 on the side of the first electrode structure 5 away from the second electrode structure 7, and is implanted into the channel layer 3 from the protective layer 9 to form one of the isolation regions 10;

[0095] Ion implantation is performed on a part of the protective layer 9 on the side of the second electrode structure 7 away from the first electrode structure 5, and is implanted into the channel layer 3 from the protective layer 9 to form another isolation region 10.

[0096] In specific implementation, ion implantation is performed into the barrier layer 4 and the channel layer 3 under the protective layer 9, and an isolation region 10 with ions can be formed. The isolation region 10 with ions can isolate the two-dimensional electron gases on both sides thereof, thereby preventing the two-dimensional electron gases on both sides from being connected, further preventing the conduction of the conductive channels between adjacent devices, enabling each device to independently form a complete switching structure, and avoiding the mutual influence between adjacent devices.

[0097] In the manufacturing method of the stepped high electron mobility transistor according to the embodiment of the present application, wherein, the part of the protective layer 9 on the side of the first electrode structure 5 away from the second electrode structure 7 and the corresponding barrier layer 4 and channel layer 3 of this part of the protective layer 9 are etched to form one of the isolation regions 10;

[0098] The part of the protective layer 9 on the side of the second electrode structure 7 away from the first electrode structure 5 and the corresponding barrier layer 4 and channel layer 3 of this part of the protective layer 9 are etched to form another isolation region 10.

[0099] In specific implementation, the protective layer 9 and the corresponding barrier layer 4 and channel layer 3 under the protective layer 9 are etched to form an isolation region 10 with a groove structure, which can make the two-dimensional electron gas at the isolation region 10 disappear, and can also prevent the two-dimensional electron gases on both sides from being connected, further preventing the conduction of the conductive channels between adjacent devices, enabling each device to independently form a complete switching structure, and avoiding the mutual influence between adjacent devices.

[0100] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0101] As described above, this is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should be covered within the protection scope of the present application.

Claims

1. A ladder-type high electron mobility transistor, characterized in that: The invention comprises a substrate layer (1), a buffer layer (2), a channel layer (3) and a barrier layer (4) stacked along a first direction (X); the buffer layer (2) and the channel layer (3) are capable of polarization and generating a two-dimensional electron gas; the channel layer (3) is used to provide a conductive channel; a surface of the barrier layer (4) away from the channel layer (3) is provided with a first electrode structure (5), a cap layer structure (6) and a second electrode structure (7) arranged in sequence along a second direction (Y); a surface of the cap layer structure (6) away from the barrier layer (4) is provided with a gate structure (8); the cap layer structure (6) comprises a plurality of stepped layers (61) arranged in sequence along the first direction (X); each of the stepped layers (61) is made of a p-type GaN material; and along a direction away from the barrier layer (4), the length of the plurality of stepped layers (61) in the second direction (Y) is decreasing.

2. The ladder-type high electron mobility transistor according to claim 1, characterized in that: The cap layer structure (6) further comprises a plurality of insertion layers (62), each of the insertion layers (62) being made of AlGaN or AlN material, a layer of the insertion layer (62) being arranged between adjacent step layers (61), and each of the insertion layers (62) having the same length in the second direction (Y) as the step layer (61) arranged on the side thereof away from the barrier layer (4).

3. The ladder-type high electron mobility transistor according to claim 1, characterized in that: The distances between the multiple stepped layers (61) arranged in a direction away from the barrier layer (4) and the first electrode structure (5) are equal, and the distances between the multiple stepped layers (61) arranged in a direction away from the barrier layer (4) and the second electrode structure (7) are increasing; The first electrode structure (5) is a source electrode, and the second electrode structure (7) is a drain electrode.

4. The ladder-type high electron mobility transistor according to claim 1, characterized in that: Along the direction from the barrier layer (4) to the gate structure (8), the thickness of the multiple layers of the stepped layers (61) in the first direction (X) increases gradually.

5. The ladder-type high electron mobility transistor according to claim 1, characterized in that: The step-type high electron mobility transistor further comprises a protective layer (9), wherein the protective layer (9) covers the surface of the barrier layer (4) and the surface of the cap layer structure (6), and the protective layer (9) is arranged in the same layer as the first electrode structure (5), the second electrode structure (7) and the gate structure (8).

6. The ladder-type high electron mobility transistor according to claim 5, characterized in that: One end of the stepped layer (61) attached to the barrier layer (4) is connected to the second electrode structure (7), and the other end is spaced apart from the first electrode structure (5) via the protective layer (9); The first electrode structure (5) is a source electrode, and the second electrode structure (7) is a drain electrode.

7. The ladder-type high electron mobility transistor according to claim 1, characterized in that: The step-type high electron mobility transistor further comprises two isolation regions (10), each of the isolation regions (10) extending from a surface of the barrier layer (4) away from the channel layer (3) to the inside of the channel layer (3), one of the isolation regions (10) being arranged on a side of the first electrode structure (5) away from the second electrode structure (7), and the other of the isolation regions (10) being arranged on a side of the second electrode structure (7) away from the first electrode structure (5).

8. The ladder-type high electron mobility transistor according to claim 7, characterized in that: The isolation region (10) is an ion implantation region, and the isolation region (10) includes at least one ion of F, N, B, Ar, and Fe; or, the isolation region (10) is an etching region, and the isolation region (10) is a groove structure formed by the surface of the barrier layer (4) being recessed inwardly.

9. The ladder-type high electron mobility transistor according to claim 1, characterized in that: The channel layer (3) and the barrier layer (4) are both made of group III nitride semiconductor materials, and the bandgap width of the channel layer (3) is smaller than the bandgap width of the barrier layer (4).

10. A method for manufacturing a ladder-type high electron mobility transistor, characterized in that: include: Performing epitaxial growth on one side of the substrate layer (1) in the first direction (X) to form a buffer layer (2); A channel layer (3), a barrier layer (4) and a cap layer structure (6) are sequentially formed on a side of the buffer layer (2) away from the substrate layer (1); Etching the cap layer structure (6) multiple times to form a stepped cap layer structure (6), wherein the length of each step of the cap layer structure (6) in the second direction (Y) decreases in a direction away from the barrier layer (4); forming a protective layer (9) on the surfaces of the barrier layer (4) and the cap layer structure (6); Etching the protective layer (9) to form receiving grooves (91) disposed on both sides of the cap layer structure (6), and forming a first electrode structure (5) and a second electrode structure (7) in the two receiving grooves (91) respectively; Two isolation regions (10) are formed in the barrier layer (4) and at least a portion of the channel layer (3), and the first electrode structure (5) and the second electrode structure (7) are arranged between the two isolation regions (10); The protective layer (9) is etched to form a receiving groove (91) disposed on the top of the cap layer structure (6), and a gate structure (8) is formed in the receiving groove (91).

11. The method for manufacturing a ladder-type high electron mobility transistor according to claim 10, characterized in that: The cap layer structure (6) comprises a stepped layer (61) and an insertion layer (62) which are sequentially overlapped and arranged along the first direction (X), and the cap layer structure (6) is etched multiple times to form a stepped cap layer structure (6). Etching the first step layer (61) of the cap layer structure (6) by using a first etching method, wherein the first step layer (61) is arranged at the outermost layer of the cap layer structure (6); The first insertion layer (62) of the cap layer structure (6) is etched by a second etching method until the length of the first insertion layer (62) in the second direction (Y) is equal to the length of the first step layer (61) in the second direction (Y), and the first step layer (61) and the first insertion layer (62) form a primary step structure; Along a direction close to the barrier layer (4), the first etching method and the second etching method are sequentially used to perform multiple etchings on the plurality of step layers (61) and the plurality of insertion layers (62) to form a multi-level step structure, wherein the length of the multi-level step structure in the second direction (Y) is increasing; The stepped layer (61) attached to the barrier layer (4) is etched using a first etching method, wherein the length of the stepped layer (61) in the second direction (Y) is greater than the length of the adjacent stepped structure in the second direction (Y).

12. The method for manufacturing a ladder-type high electron mobility transistor according to claim 10, characterized in that: In the step of forming two isolation regions (10) in the barrier layer (4) and at least a portion of the channel layer (3), Ion implantation is performed at a portion of the protective layer (9) on a side of the first electrode structure (5) away from the second electrode structure (7), and then implanted from the protective layer (9) into the channel layer (3) to form one of the isolation regions (10); Ions are implanted in a portion of the protective layer (9) on a side of the second electrode structure (7) away from the first electrode structure (5), and then implanted from the protective layer (9) into the channel layer (3) to form another isolation region (10).

13. The method for manufacturing a ladder-type high electron mobility transistor according to claim 10, characterized in that: Etching a portion of the protective layer (9) on a side of the first electrode structure (5) away from the second electrode structure (7) and the barrier layer (4) and the channel layer (3) corresponding to the portion of the protective layer (9) to form one of the isolation regions (10); A portion of the protective layer (9) on the side of the second electrode structure (7) away from the first electrode structure (5) and the barrier layer (4) and the channel layer (3) corresponding to the portion of the protective layer (9) are etched to form another isolation region (10).

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