GaN HEMT device and manufacturing method thereof

Abstract

The invention discloses a GaN HEMT device which comprises a substrate layer, a GaN-1 layer, a GaN-2 layer and an AlGaN-1 barrier layer, the GaN-1 layer, the GaN-2 layer and the AlGaN-1 barrier layer sequentially grow, a source electrode and a drain electrode symmetrically grow on the two sides of the surface of the AlGaN-1 barrier layer, a uGaN layer, a pGaN-1 layer and a grid electrode sequentially grow between the source electrode and the drain electrode, a part of the pGaN-1 layer and a part of the uGaN layer are etched away in the same direction in the growth direction, and a part of the pGaN-1 layer and a part of the grid electrode are etched away in the same direction. A secondary epitaxial pGaN-2 layer is grown at the etching position, one end of the pGaN-2 layer extends into the AlGaN-1 barrier layer, the thickness of the AlGaN-1 barrier layer is reduced, the other end of the pGaN-2 layer is flush with the surface of the pGaN-1 layer, and the pGaN-1 layer and the pGaN-1 layer are jointly connected with the grid electrode. According to the GaN HEMT device provided by the invention, on the basis of a D-mode HEMT structure, D-mode can be changed into E-mode by utilizing a secondary growth pGaN gate mode, so that not only is a normally-closed device realized, but also the advantages of large current, low on-resistance, high frequency and the like are reserved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to GaN HEMT devices and manufacturing methods thereof. Background Art

[0002] In GaN HEMT devices, a high-density and high-mobility 2DEG is generated at the AlGaN / GaN heterojunction interface due to the polarization effect. This characteristic is an advantage that other wide-bandgap semiconductor materials do not have, making it have great potential in power semiconductor devices with high blocking voltage, large current, high switching speed, and low on-resistance.

[0003] Generally, a GaN HEMT device based on a PSJ structure includes a substrate layer and a GaN-1 layer, a GaN-2 layer, and an AlGaN-1 layer grown in sequence. Source S and drain D are grown on the surface of the AlGaN-1 layer on both sides. An uGaN layer, a pGaN-1 layer, and a gate G are grown in sequence between the two. Although the normally-on D-mode GaN HEMT device has advantages such as large current, low on-resistance, and high frequency, it cannot be directly used and needs to be made into a normally-off type by adding peripheral components. While the general E-mode GaN HEMT device can achieve normally-off, it also has problems such as low current and large on-resistance. Summary of the Invention

[0004] The embodiments of the present application provide a GaN HEMT device and a manufacturing method thereof, which can change the D-mode to the E-mode by using the method of secondary growth of the pGaN gate on the basis of the D-mode HEMT structure, realizing a normally-off device and retaining advantages such as large current, low on-resistance, and high frequency.

[0005] In the first aspect of the embodiments of the present application, a GaN HEMT device is provided, including a substrate layer and a GaN-1 layer, a GaN-2 layer, and an AlGaN-1 barrier layer grown in sequence. Source and drain are symmetrically grown on the surface of the AlGaN-1 barrier layer on both sides. An uGaN layer, a pGaN-1 layer, and a gate are grown in sequence between the source and the drain. Part of the pGaN-1 layer and the uGaN layer are etched away in the growth direction, and a secondary epitaxial pGaN-2 layer is grown at the etching position. One end of the pGaN-2 layer extends into the AlGaN-1 barrier layer to thin the thickness of the AlGaN-1 barrier layer, and the other end is flush with the surface of the pGaN-1 layer and jointly connects the gate.

[0006] In a possible implementation, the original thickness of the AlGaN-1 barrier layer is 20 - 50 nm, the thickness of the uGaN layer is 30 - 70 nm, and the thickness of the pGaN-1 layer is 60 - 100 nm.

[0007] In a possible implementation, the remaining thickness of the thinned AlGaN-1 barrier layer is 5 - 20 nm.

[0008] In a possible implementation, the pGaN-2 layer extends to the surface of the GaN-2 layer through the secondary epitaxial growth of the AlGaN-2 barrier layer penetrating the AlGaN-1 barrier layer, where the thickness of the AlGaN-2 barrier layer is 5 - 20 nm, the Al component content in the AlGaN-1 barrier layer is 20% - 27%, and the Al component content in the AlGaN-2 barrier layer is lower than that in the AlGaN-1 barrier layer.

[0009] In a possible implementation, the Al component content in the AlGaN-2 barrier layer is 1 / 3 - 3 / 4 of that in the AlGaN-1 barrier layer.

[0010] In a possible implementation, an AlN thin layer is also grown between the AlGaN-1 barrier layer and the GaN-2 layer, and the AlGaN-2 barrier layer penetrates the AlN thin layer and extends to the surface of the GaN-2 layer.

[0011] In a possible implementation, the thickness of the AlN thin layer is 0.5 - 2 nm.

[0012] The first aspect of the embodiments of the present application provides a manufacturing method of a GaN HEMT device as described above, including the following steps:

[0013] S10: Using the MOCVD method, sequentially grow a GaN-1 layer, a GaN-2 layer, an AlGaN-1 barrier layer, a uGaN layer, and a pGaN-1 layer on the substrate layer;

[0014] S20: Use a positive photoresist lithography process to lithograph the range pattern of the pGaN-2 layer, and use an etching process to remove the original pGaN-1 layer, uGaN layer, and AlGaN-1 barrier layer in this range pattern. After the etching is completed, remove the photoresist and clean;

[0015] S30: Fabricate a SiO 2 layer on the surface of the uGaN layer, use a positive photoresist lithography process to etch out the lithography range of the secondary epitaxial pGaN-2 layer on the surface of the SiO 2 layer, and then use wet HF etching to remove the SiO 2Layer, cleaning and removing photoresist;

[0016] S40, grow the secondary epitaxial pGaN-2 layer within the lithography range by means of MOCVD secondary epitaxy, and then use wet HF etching to remove the SiO part outside the secondary epitaxial pGaN-2 layer; 2 Layer;

[0017] S50, use positive photoresist lithography process to lithograph the pattern of the pGaN-1 layer, then use etching process to etch the pGaN-1 layer, remove photoresist and clean, then use positive photoresist lithography process to lithograph the pattern of the uGaN layer, and then use etching process to etch the uGaN layer, remove photoresist and clean;

[0018] S60, use positive photoresist lithography process to lithograph the pattern of the gate, then use PVD process to evaporate P ohmic contact, then strip, remove photoresist and clean, and perform RTA annealing treatment;

[0019] S70, use positive photoresist lithography process to lithograph the patterns of the source and drain, then use PVD process to evaporate N ohmic contact, strip, remove photoresist and clean, and perform RTA annealing treatment.

[0020] Beneficial effects: Compared with the prior art, the GaN HEMT device and its manufacturing method provided by this application are based on the D-mode HEMT with a traditional PSJ structure, and retain the characteristics of high breakdown voltage of the PSJ structure, large current and low on-resistance of the D-mode HEMT. By adopting the secondary epitaxy technology and designing the secondary epitaxial pGaN-2 layer, the turn-off characteristic of the channel under the selected area is realized reasonably at the same time, and a high threshold voltage can be easily achieved, solving the problems of low threshold, small current and high on-resistance of the traditional PSJ structure E-mode HEMT. Finally, an enhanced device with high threshold voltage, low on-resistance and large current can be effectively realized;

[0021] Among them, on the basis of the conventional AlGaN-1 barrier layer, the secondary epitaxial AlGaN-2 barrier layer can adjust the Al component to a lower level, so that the secondary epitaxial pGaN-2 layer can further deplete the 2DEG in the underlying channel layer better, and then can better improve the threshold voltage of the device;

[0022] Among them, by creatively growing a thin AlN layer between the AlGaN-1 barrier layer and the GaN-2 layer, the polarization effect at the interface can be effectively increased, the concentration and mobility of 2DEG in the channel layer can be improved, and thus the current of the device can be further increased and the on-resistance of the device can be reduced.

[0023] These and other objects, features and advantages of the present invention are fully embodied through the following detailed description. Description of the Drawings

[0024] Figure 1 The structural schematic diagram of an embodiment of the GaN HEMT device of the present application is shown.

[0025] Figure 2 The structural schematic diagram of the second embodiment of the GaN HEMT device of the present application is shown.

[0026] Figure 3 The structural schematic diagram of the third embodiment of the GaN HEMT device of the present application is shown. Detailed implementation manners

[0027] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments in the following description are only examples, and those skilled in the art can think of other obvious variations. The basic principles defined in the following description of the present invention can be applied to other implementation manners, variations, improvements, equivalent manners, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0028] Those skilled in the art should understand that in the disclosure of the specification, the orientation or positional relationship indicated by terms such as "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting the present invention.

[0029] It can be understood that the term "one" should be understood as "at least one" or "one or more". That is, in one embodiment, the number of an element can be one, while in other embodiments, the number of the element can be multiple. The term "one" should not be construed as limiting the quantity.

[0030] Reference Figure 1, in the first aspect of the embodiment of the present application, a GaN HEMT device is provided, which includes a sapphire substrate layer and a GaN-1 layer, a GaN-2 layer, and an AlGaN-1 barrier layer grown in sequence. The substrate layer can be a sapphire substrate. Source S and drain D are symmetrically grown on the surface of the AlGaN-1 barrier layer on both sides, and a uGaN layer, a pGaN-1 layer, and a gate G are sequentially grown between the source S and the drain D. Part of the pGaN-1 layer and the uGaN layer are etched away in the growth direction, and a secondary epitaxial pGaN-2 layer is grown at the etching position. One end of the pGaN-2 layer extends into the AlGaN-1 barrier layer to reduce the thickness of the AlGaN-1 barrier layer. As an optional option, the remaining thickness of the AlGaN-1 barrier layer after thinning is 5-20 nm; the other end of the pGaN-2 layer is flush with the surface of the pGaN-1 layer and jointly connects to the gate G.

[0031] The traditional D-mode GaN HEMT is normally on and cannot be directly used. Although the traditional E-mode GaN HEMT is normally off, it has problems such as low current and large on-resistance. The GaN HEMT device provided in this application creatively combines the advantages of both the D-mode GaN HEMT and the E-mode GaN HEMT. On the basis of the D-mode GaN HEMT structure, the D-mode is changed to the E-mode by using the method of secondary growth of the pGaN gate. At the same time, the AlGaN-1 barrier layer is thinned, so that the GaN HEMT device not only realizes the normally-off type but also retains the advantages of large current and low on-resistance, greatly improving the practical use value and commercial value of the GaN HEMT device. The pGaN-1 layer, the uGaN layer, the AlGaN-1 barrier layer, and the GaN-1 layer form a D-mode PSJ GaN HEMT epitaxial structure. The secondary epitaxial pGaN-2 layer can deplete the 2DEG in the following channel layer, thereby pinching off the channel to form an E-mode HEMT device, which can significantly improve the performance of the device.

[0032] In one embodiment, the original thickness of the AlGaN-1 barrier layer is 20-50 nm. The thickness of the uGaN layer is 30-70 nm. The thickness of the pGaN-1 layer is 60-100 nm.

[0033] During the test, for different remaining thicknesses of the AlGaN-1 barrier layer after thinning, the concentration of 2DEG in the channel layer (cm -3 ) also has slight differences. See the following table:

[0034]

[0035] It can be seen that the thinner the remaining thickness of the AlGaN-1 barrier layer, the lower the 2DEG concentration generated between the AlGaN-1 barrier layer and the GaN-2 channel layer. The electric field generated by growing pGaN can more easily deplete the 2DEG, thus achieving the purpose of device turn-off. If the device is to be turned on, a higher voltage (threshold voltage) needs to be applied to the gate G.

[0036] Further preferably, in combination with Figure 2 , the pGaN-2 layer extends through the AlGaN-1 barrier layer to the surface of the GaN-2 layer by secondary epitaxy of the AlGaN-2 barrier layer, where the thickness of the AlGaN-2 barrier layer is 5-20 nm, the Al component content in the AlGaN-1 barrier layer is 20%-27%, and at the same time, the Al component content in the AlGaN-2 barrier layer is lower than that in the AlGaN-1 barrier layer. Usually, in order to maintain the advantages of high current and low on-resistance of the D-mode HEMT device, the Al component content in the once-epitaxied AlGaN-1 barrier layer is relatively high. In this application, by adopting the design method of secondary epitaxy of the AlGaN-2 barrier layer, the Al component content in the secondary epitaxied AlGaN-2 barrier layer can be adjusted to be lower, so that the secondary epitaxied pGaN-2 layer can further better deplete the 2DEG in the underlying channel layer, and thus can better improve the threshold voltage of the device.

[0037] In one embodiment, the Al component content in the AlGaN-2 barrier layer is 1 / 3-3 / 4 of the Al component content in the AlGaN-1 barrier layer, such as 1 / 3, 1 / 2, 3 / 4, etc. When the Al component content is low, the 2DEG concentration generated by the polarization effect between AlGaN and GaN in the GaN channel layer will be lower, and it will be easier to deplete the 2DEG after growing pGaN.

[0038] In one embodiment, in combination with Figure 3 , an AlN thin layer is also grown between the AlGaN-1 barrier layer and the GaN-2 layer, where the AlGaN-2 barrier layer extends through the AlN thin layer to the surface of the GaN-2 layer. In this way, the newly designed AlN thin layer between the AlGaN-1 barrier layer and the GaN-2 layer can effectively increase the polarization effect at the interface, improve the 2DEG concentration and mobility in the channel layer, and thus can further increase the current of the GaN HEMT device and reduce the on-resistance of the GaN HEMT device.

[0039] In one embodiment, the thickness of the AlN thin layer is 0.5 - 2 nm. It should be noted that with different thicknesses of the AlN thin layer, the concentration of 2DEG in the channel layer also varies slightly, as shown in the following table:

[0040] AlN thickness (nm) <![CDATA[2DEG concentration (cm -3 )]]> 0.5 1.1E+13 1.0 1.3E+13 1.5 1.35E+13 2.0 1.4E+13

[0041] When the AlN thin layer is not added, the 2DEG concentration is 8.1E+12 cm -3 -2. From this comparison, it can be seen that the AlN thin layer, as a newly designed insertion layer, can increase the polarization effect between the AlGaN-1 barrier layer and the GaN-2 layer, generating more 2DEG, thereby effectively increasing the current of the device and reducing the on-resistance of the device.

[0042] The first aspect of the embodiment of the present application provides a manufacturing method of the GaN HEMT device as described above, including the following steps:

[0043] S10, using the MOCVD method, sequentially grow a GaN-1 layer, a GaN-2 layer, an AlGaN-1 barrier layer, a uGaN layer, and a pGaN-1 layer on the substrate layer;

[0044] S20, using the positive photoresist lithography process to lithograph the range pattern of the pGaN-2 layer, and using the ICP etching process to remove the original pGaN-1 layer, uGaN layer, and AlGaN-1 barrier layer within this range pattern. After the etching is completed, remove the photoresist and clean;

[0045] S30, fabricate a SiO 2 layer on the surface of the uGaN layer using processes such as ALD / PVD / CVD. Use the positive photoresist lithography process to etch out the lithography range for the secondary epitaxial pGaN-2 layer on the surface of the SiO 2 layer, and then use wet HF etching to remove the SiO 2 layer within the lithography range, and clean and remove the photoresist;

[0046] S40, grow the secondary epitaxial pGaN-2 layer in the lithography range through the MOCVD secondary epitaxy method, and then use wet HF etching to remove the SiO 2 layer outside the secondary epitaxial pGaN-2 layer;

[0047] S50, use the positive photoresist lithography process to lithograph the pattern of the pGaN-1 layer, and then use the ICP etching process to etch out the pGaN-1 layer, remove the photoresist and clean. Subsequently, use the positive photoresist lithography process to lithograph the pattern of the uGaN layer, and then use the ICP etching process to etch out the uGaN layer, remove the photoresist and clean;

[0048] S60, lithographically pattern the gate using a positive photoresist lithography process, then deposit the P ohmic contact (Ni / Au) by PVD process, then strip the photoresist and clean, and perform RTA annealing treatment (in an atmospheric environment, anneal at 600 - 650 °C);

[0049] S70, lithographically pattern the source and drain using a positive photoresist lithography process, then deposit the N ohmic contact (Ni / Al / Ni / Au) by PVD process, strip the photoresist and clean, and perform RTA annealing treatment (in an N2@1SLM environment, anneal at 750 °C - 950 °C).

[0050] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the drawings are only examples and do not limit the present invention. The advantages of the present invention have been fully and effectively realized. The functions and structural principles of the present invention have been demonstrated and explained in the embodiments, and the embodiments of the present invention can have any deformation or modification without departing from the said principles.

Claims

1. A GaN HEMT device comprising a substrate layer and a GaN-1 layer, a GaN-2 layer and an AlGaN-1 barrier layer grown in sequence, characterized in that: The surface of the AlGaN-1 barrier layer is symmetrically grown with a source and a drain on both sides, and a uGaN layer, a pGaN-1 layer and a gate are sequentially grown between the source and the drain, wherein the pGaN-1 layer and the uGaN layer are partially etched in the same direction in the growth direction, and a secondary epitaxial pGaN-2 layer is grown at the etched position, one end of the pGaN-2 layer extends into the AlGaN-1 barrier layer to reduce the thickness of the AlGaN-1 barrier layer, and the other end is flush with the surface of the pGaN-1 layer and is jointly connected to the gate.

2. The GaN HEMT device according to claim 1, characterized in that: The original thickness of the AlGaN-1 barrier layer is 20-50 nm, the thickness of the uGaN layer is 30-70 nm, and the thickness of the pGaN-1 layer is 60-100 nm.

3. The GaN HEMT device according to claim 2, characterized in that: The remaining thickness of the AlGaN-1 barrier layer after thinning is 5 to 20 nm.

4. The GaN HEMT device according to claim 3, characterized in that: The pGaN-2 layer penetrates the AlGaN-1 barrier layer through a secondary epitaxial AlGaN-2 barrier layer and extends to the surface of the GaN-2 layer, wherein the thickness of the AlGaN-2 barrier layer is 5 to 20 nm, wherein the Al component content in the AlGaN-1 barrier layer is 20% to 27%, and the Al component content in the AlGaN-2 barrier layer is lower than the Al component content in the AlGaN-1 barrier layer.

5. The GaN HEMT device according to claim 4, characterized in that: The Al content in the AlGaN-2 barrier layer is 1 / 3-3 / 4 of the Al content in the AlGaN-1 barrier layer.

6. The GaN HEMT device according to claim 4 or 5, characterized in that: An AlN thin layer is also grown between the AlGaN-1 barrier layer and the GaN-2 layer, and the AlGaN-2 barrier layer penetrates the AlN thin layer and extends to the surface of the GaN-2 layer.

7. The GaN HEMT device according to claim 6, characterized in that: The thickness of the AlN thin layer is 0.5-2 nm.

8. The method for manufacturing a GaN HEMT device according to any one of claims 1 to 3, characterized in that: The following steps are involved: S10, using an MOCVD method, sequentially growing a GaN-1 layer, a GaN-2 layer, an AlGaN-1 barrier layer, a uGaN layer, and a pGaN-1 layer on the substrate layer; S20, using a positive photolithography process to photolithograph the range pattern of the pGaN-2 layer, and using an etching process to remove the original pGaN-1 layer, uGaN layer, and AlGaN-1 barrier layer of the range pattern, and after the etching is completed, remove the photoresist and clean; S30, forming a SiO2 layer on the surface of the uGaN layer, etching a photolithography range of the secondary epitaxial pGaN-2 layer on the surface of the SiO2 layer using a positive photolithography process, and then removing the SiO2 layer in the photolithography range using a wet HF etching process, and cleaning and removing the photolithography; S40, growing a secondary epitaxial pGaN-2 layer in the photolithography range by a MOCVD secondary epitaxial method, and then removing the SiO2 layer outside the secondary epitaxial pGaN-2 layer by wet HF etching; S50, using a positive photolithography process to photolithograph a pattern of the pGaN-1 layer, then using an etching process to etch out the pGaN-1 layer, removing the resist and cleaning, then using a positive photolithography process to photolithograph a pattern of the uGaN layer, then using an etching process to etch out the uGaN layer, removing the resist and cleaning; S60, using a positive photolithography process to photolithograph the gate pattern, then using a PVD process to evaporate the P ohmic contact, then stripping and cleaning, and performing RTA annealing; S70, using a positive photolithography process to photolithograph the source and drain patterns, then using a PVD process to evaporate the N-ohm contact, stripping and cleaning, and performing RTA annealing.

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