Hybrid gate structure, high electron mobility transistor and manufacturing method

Abstract

The invention relates to the technical field of transistor structures, and provides a mixed gate structure, a high electron mobility transistor and a manufacturing method. A gate depletion layer disposed on the substrate structure; the source electrode and the drain electrode are arranged on the substrate structure, the gate depletion layer comprises a middle part and an edge part, and the middle part is located between the source electrode and the drain electrode; the Schottky contact layer is arranged on the gate depletion layer and located in the middle part; and the charge release layer is arranged on the depletion layer and is positioned at the edge part. The gate depletion layer is provided with a middle part and an edge part, the middle part is provided with a Schottky contact layer, the edge part is provided with an ohmic contact layer, the Schottky contact layer of the middle part guarantees the gate performance, the edge part is not located between the source electrode and the drain electrode, and the influence of the charge release layer on the gate performance is reduced. The charge release layer of the edge portion provides a path for releasing trapped charges more quickly, and the condition of threshold voltage drift is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor structures, and in particular, to a hybrid gate structure, a high electron mobility transistor, and a manufacturing method thereof. Background Art

[0002] A HEMT (High Electron Mobility Transistor) is a heterojunction-based field effect transistor that utilizes a high-concentration, high-mobility 2DEG (two-dimensional electron gas) formed at the heterojunction interface to achieve high-frequency, high-power, and low-loss performance.

[0003] In the prior art, the gate structure of an enhancement-mode HEMT is as Figure 5 shown, which is equivalently composed of two back-to-back diodes in series. When a gate stress voltage or a drain (400) stress voltage is applied to the HEMT, a large number of trap charges will exist in the P-GaN (P-doped gallium nitride) of the gate. The trap charges will affect the 2DEG and thus affect the threshold voltage. Due to the influence of the back-to-back diodes in series, the trap charges cannot be quickly released, resulting in the problem of threshold voltage drift. The threshold voltage drift and the 2DEG concentration fluctuation increase during the switching process of the HEMT, affecting the stability of the HEMT. Summary of the Invention

[0004] The present invention provides a hybrid gate structure, a high electron mobility transistor, and a manufacturing method thereof to solve the defect in the prior art that the gate structure is equivalently two back-to-back diodes in series, resulting in the inability to quickly release trap charges.

[0005] The present invention provides a hybrid gate structure, comprising: a substrate structure for forming a conductive channel; a gate depletion layer disposed on the substrate structure, the gate depletion layer being used to consume the carriers of the conductive channel to keep the conductive channel normally closed; a source electrode and a drain electrode, the source electrode and the drain electrode being disposed on the substrate structure, the gate depletion layer including an intermediate portion and an edge portion, the intermediate portion being located between the source electrode and the drain electrode; a Schottky contact layer disposed on the gate depletion layer and located at the intermediate portion, the Schottky contact layer forming a Schottky contact with the gate depletion layer; a charge release layer disposed on the depletion layer and located at the edge portion, the gate leakage current of the charge release layer being greater than the gate leakage current of the Schottky contact layer.

[0006] According to the hybrid gate structure provided by the present invention, the charge release layer is an ohmic contact layer, and the ohmic contact layer forms an ohmic contact with the gate depletion layer.

[0007] According to a hybrid gate structure provided by the present invention, the Schottky contact layer includes a first layer portion located on the middle portion and a second layer portion located on the edge portion, and the second layer portion surrounds the ohmic contact layer.

[0008] According to a hybrid gate structure provided by the present invention, the second layer portion is connected to the ohmic contact layer.

[0009] According to a hybrid gate structure provided by the present invention, it further includes a first lead-out layer disposed on the ohmic contact layer, and the resistivity of the first lead-out layer is less than that of the ohmic contact layer.

[0010] According to a hybrid gate structure provided by the present invention, there are two source electrodes. One of the two source electrodes is located on one side of the drain electrode and the other source electrode is located on the other side of the drain electrode. The gate depletion layer includes two middle portions, and the middle portions are disposed between the drain electrode and the two source electrodes, and Schottky contact layers are disposed on both of the two middle portions.

[0011] According to a hybrid gate structure provided by the present invention, the gate depletion layer includes two edge portions. One of the two edge portions is connected to one side of the two middle portions and the other edge portion is connected to the other side of the two middle portions.

[0012] According to a hybrid gate structure provided by the present invention, it further includes a passivation layer, a source electrode lead-out layer, a drain electrode lead-out layer, and a second lead-out layer. The passivation layer covers the substrate structure, the gate depletion layer, the source electrode, and the drain electrode. The passivation layer is provided with a source via corresponding to the source electrode, a drain via corresponding to the drain electrode, a middle via corresponding to the middle portion, and an edge via corresponding to the edge portion. The source electrode lead-out layer is disposed in the source via and the source electrode lead-out layer is connected to the source electrode. The drain electrode lead-out layer is disposed in the drain via and the drain electrode lead-out layer is connected to the drain electrode. The second lead-out layer is disposed in the middle via and the second lead-out layer is connected to the Schottky contact layer. The first lead-out layer is disposed in the edge via.

[0013] The present invention further provides a high electron mobility transistor including the above-mentioned hybrid gate structure. The substrate structure includes a substrate layer, a GaN buffer layer, and an AlGaN layer stacked in sequence from bottom to top. A two-dimensional electron gas is formed between the GaN layer and the AlGaN layer as the conductive channel.

[0014] According to a high electron mobility transistor provided by the present invention, the gate depletion layer is a P-GaN layer, the Schottky contact layer is a TiN layer, and the ohmic contact layer is a Ti layer.

[0015] The present invention also provides a method for manufacturing a transistor, including: Manufacturing a substrate structure; Defining a gate depletion layer pattern on the substrate structure and manufacturing a gate depletion layer; Defining a Schottky contact layer pattern on the gate depletion layer and manufacturing a Schottky contact layer; Through a first etching process, an etching opening exposing the edge portion of the gate depletion layer is formed on the Schottky contact layer; Manufacturing a first passivation layer to cover the substrate structure, the gate depletion layer, and the Schottky contact layer; Through a second etching process, a source opening and a drain opening exposing the substrate structure are formed, and the middle portion of the gate depletion layer is located between the source opening and the drain opening; Through a first metal deposition process, a source is manufactured in the source opening and a drain is manufactured in the drain opening; Manufacturing a second passivation layer to cover the first passivation layer, the source, and the drain; Through a third etching process, a source via exposing the source, a drain via exposing the drain, an edge via exposing the edge portion of the gate depletion layer, and an intermediate via exposing the middle portion of the gate depletion layer are formed; Through a second metal deposition process, a source lead layer is formed in the source via, a drain lead layer is formed in the drain via, an ohmic contact layer is formed in the edge via, and a second lead layer is formed in the intermediate via.

[0016] A hybrid gate structure, a high electron mobility transistor, and a manufacturing method provided by the present invention at least have the following beneficial effects: The middle portion of the gate depletion layer is located between the source and the drain, and the substrate structure forms a conductive channel. The gate depletion layer normally closes the conductive channel between the source and the drain, realizing an enhancement-type function. A Schottky contact is formed by a Schottky contact layer provided on the middle portion of the gate depletion layer, and a charge release layer is provided at the edge portion of the gate depletion layer. Since the gate leakage current of the charge release layer is greater than the gate leakage current of the Schottky contact layer, it is beneficial for the trapped charges in the gate depletion layer to be released more easily and quickly through the charge release layer. Thus, by providing a middle portion and an edge portion in the gate depletion layer, a Schottky contact layer is provided on the middle portion and a charge release layer is provided on the edge portion. The Schottky contact layer in the middle portion ensures the gate performance, and the edge portion is not located between the source and the drain, reducing the influence of the charge release layer on the gate performance. The charge release layer at the edge portion provides a path for releasing trapped charges more quickly than the Schottky contact layer, reducing the influence of the trapped charges and improving the threshold voltage drift situation. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a top view schematic diagram of one embodiment of a hybrid gate structure provided by the present invention.

[0019] Figure 2 It is a hybrid gate structure provided by the present invention Figure 1 A cross-sectional schematic diagram at location A in the embodiment.

[0020] Figure 3 It is a hybrid gate structure provided by the present invention Figure 1 A cross-sectional schematic diagram at location B in the embodiment.

[0021] Figure 4 It is a method for manufacturing a transistor provided by the present invention and Figure 1 A process schematic diagram corresponding to the embodiment (the left side is the process schematic diagram of the cross-section at location A, and the right side is the process schematic diagram of the cross-section at location B).

[0022] Figure 5 It is a schematic diagram of the gate structure and equivalent circuit of a conventional enhancement-mode HEMT.

[0023] Reference numerals: 100: Substrate structure; 110: Substrate layer; 120: GaN buffer layer; 130: AlGaN layer; 200: Gate depletion layer; 210: Intermediate part; 220: Edge part; 300: Source electrode; 400: Drain electrode; 500: Schottky contact layer; 510: First layer part; 520: Second layer part; 600: Ohmic contact layer; 700: First lead-out layer; 800: Passivation layer; 810: Drain via hole; 820: Intermediate via hole; 830: Edge via hole; 910: Source electrode lead-out layer; 920: Drain electrode lead-out layer; 930: Second lead-out layer. Detailed implementation manners

[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention with reference to the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts fall within the scope of protection of the present invention.

[0025] The following combines Figures 1 - 3Describe a hybrid gate structure of the present invention, including: A substrate structure 100 for forming a conductive channel; A gate depletion layer 200 disposed on the substrate structure 100, and the gate depletion layer 200 is used to consume the carriers of the conductive channel to keep the conductive channel normally closed; A source electrode 300 and a drain electrode 400, the source electrode 300 and the drain electrode 400 are disposed on the substrate structure 100, the gate depletion layer 200 includes a middle portion 210 and an edge portion 220, and the middle portion 210 is located between the source electrode 300 and the drain electrode 400; A Schottky contact layer 500 disposed on the gate depletion layer 200 and located at the middle portion 210, and the Schottky contact layer 500 forms a Schottky contact with the gate depletion layer 200; A charge release layer disposed on the depletion layer 200 and located at the edge portion 220, and the gate leakage current of the charge release layer is greater than the gate leakage current of the Schottky contact layer 500.

[0026] The middle portion 210 of the gate depletion layer 200 is located between the source electrode 300 and the drain electrode 400. The substrate structure 100 forms a conductive channel. The gate depletion layer 200 keeps the conductive channel between the source electrode 300 and the drain electrode 400 normally closed, realizing an enhancement-type function. A Schottky contact layer 500 is disposed on the middle portion 210 of the gate depletion layer 200 to form a Schottky contact, and a charge release layer is disposed on the edge portion 220 of the gate depletion layer 200. Since the gate leakage current of the charge release layer is greater than the gate leakage current of the Schottky contact layer 500, it is beneficial for the trapped charges in the gate depletion layer 200 to be released more easily and quickly through the charge release layer.

[0027] Thus, by providing the middle portion 210 and the edge portion 220 in the gate depletion layer 200, with a Schottky contact layer 500 disposed on the middle portion 210 and a charge release layer disposed on the edge portion 220, the Schottky contact layer 500 on the middle portion 210 ensures the gate performance, and the edge portion 220 is not located between the source electrode 300 and the drain electrode 400, reducing the influence of the charge release layer on the gate performance. The charge release layer on the edge portion 220 provides a path for releasing trapped charges more quickly than the Schottky contact layer, reducing the influence of trapped charges and improving the threshold voltage drift situation.

[0028] In some embodiments of the present invention, the charge release layer can form an ohmic contact or an incomplete ohmic contact with the gate depletion layer 200, such that the gate leakage current is greater than the gate leakage current of the Schottky contact layer 500 that forms a Schottky contact with the gate depletion layer 200, thereby achieving the purpose of providing a path for more quickly releasing trapped charges.

[0029] Reference Figures 1 to 3 In some embodiments of a hybrid gate structure of the present invention, the charge release layer is an ohmic contact layer 600, which is disposed on the gate depletion layer 200 and located at the edge portion 220, and the ohmic contact layer 600 forms an ohmic contact with the gate depletion layer 200.

[0030] An ohmic contact layer 600 is provided at the edge portion 220 of the gate depletion layer 200 to form an ohmic contact. The equivalent structure of the ohmic contact does not form a diode, enabling the trap charges in the gate depletion layer 200 to be quickly released through the ohmic contact layer 600.

[0031] It can be understood that the gate depletion layer 200, the Schottky contact layer 500, and the ohmic contact layer 600 form a hybrid gate structure. By applying a voltage to the Schottky contact layer 500, the conduction channel between the source 300 and the drain 400 can be controlled to conduct. The trap charges in the gate depletion layer 200 can be quickly released through the ohmic contact layer 600, avoiding the accumulation that causes the threshold voltage drift.

[0032] A Schottky contact layer 500 is provided on the gate depletion layer 200, that is, the gate forms a Schottky contact, which has low capacitance characteristics, can shorten the switching time, improve the switching dynamic performance, reduce the gate leakage current at the same time, and has a large voltage swing for easy control.

[0033] Reference Figure 1 and Figure 2 In some embodiments of a hybrid gate structure of the present invention, the Schottky contact layer 500 includes a first layer portion 510 located on the middle portion 210 and a second layer portion 520 located on the edge portion 220, and the second layer portion 520 surrounds the ohmic contact layer 600.

[0034] In addition to the first layer portion 510 provided on the middle portion 210, the Schottky contact layer 500 also has a second layer portion 520 extending to the edge portion 220, and the second layer portion 520 of the Schottky contact layer 500 surrounds the ohmic contact layer 600. By using the modulation of the electric field by the Schottky contact layer 500, the electric field peak value at the edge is evenly dispersed, avoiding the breakdown caused by local electric field concentration, which is beneficial to further reducing the influence of the ohmic contact layer 600 on the gate leakage performance and improving the reliability and safety of the gate.

[0035] Reference Figure 1 and Figure 2 In some embodiments of a hybrid gate structure of the present invention, the second layer portion 520 is connected to the ohmic contact layer 600.

[0036] Such as Figure 2, the second layer portion 520 of the Schottky contact layer 500 surrounds the ohmic contact layer 600 and is in side contact connection with each other, so that the Schottky contact layer 500 and the ohmic contact layer 600 have the same electric potential, which is beneficial to making the electric field of the overall gate more uniform.

[0037] In some embodiments of the present invention, in addition to the direct connection between the Schottky contact layer 500 and the ohmic contact layer 600, they can also be connected to each other when led out through the Schottky contact layer 500 and the ohmic contact layer 600, so that the Schottky contact layer 500 and the ohmic contact layer 600 are at the same electric potential.

[0038] Reference Figure 1 and Figure 2 , in some embodiments of a hybrid gate structure of the present invention, it further includes a first lead-out layer 700, the first lead-out layer 700 is disposed on the ohmic contact layer 600, and the resistivity of the first lead-out layer 700 is less than the resistivity of the ohmic contact layer 600.

[0039] Since the material selection range of the ohmic contact layer 600 is limited in order to form an ohmic contact with the gate depletion layer 200, for example, for the gate depletion layer 200 of P-GaN, materials such as nickel and titanium can be selected to form the ohmic contact layer 600, but the resistivity of materials such as nickel and titanium is relatively high. By providing the first lead-out layer 700 on the ohmic contact layer 600, the resistivity of the first lead-out layer 700 is less than the resistivity of the ohmic contact layer 600, thereby reducing the overall resistance value, which is beneficial to reducing heat generation and power consumption.

[0040] It should be noted that, in some embodiments of the present invention, only the ohmic contact layer 600 can be provided, that is, the ohmic contact layer 600 is directly led out and connected.

[0041] Reference Figure 1 , in some embodiments of a hybrid gate structure of the present invention, there are two source electrodes 300, one of the two source electrodes 300 is located on one side of the drain electrode 400 and the other source electrode 300 is located on the other side of the drain electrode 400, the gate depletion layer 200 includes two intermediate portions 210, the intermediate portions 210 are provided between the drain electrode 400 and the two source electrodes 300, and the Schottky contact layer 500 is provided on both of the two intermediate portions 210.

[0042] By providing source electrodes 300 on both sides of the drain electrode 400, and the intermediate portions 210 of the gate depletion layer 200 are provided between the two source electrodes 300 and the drain electrode 400, and the Schottky contact layer 500 is provided on both of the two intermediate portions 210. Thus, by applying a voltage to the Schottky contact layer 500, conductive channels can be respectively formed on both sides of the drain electrode 400, which is beneficial to increasing the maximum current and maximum power consumption and improving the performance of the transistor.

[0043] In some embodiments of the present invention, a plurality of drain electrodes 400 and source electrodes 300 may be provided. The drain electrodes 400 and the source electrodes 300 are arranged at intervals, and an intermediate portion 210 of the gate depletion layer 200 is provided between each group of the drain electrodes 400 and the source electrodes 300. With this structure, the maximum current and the maximum power consumption can be further increased.

[0044] Reference Figure 1 , in some embodiments of a hybrid gate structure of the present invention, the gate depletion layer 200 includes two of the edge portions 220. One of the two edge portions 220 is connected to one side of the two intermediate portions 210, and the other edge portion 220 is connected to the other side of the two intermediate portions 210.

[0045] By providing edge portions 220 at both ends of the intermediate portion 210 of the gate depletion layer 200, and connecting both ends of the intermediate portion 210 to the edge portions 220 respectively, it is beneficial to shorten the moving distance of the trap charges released by the gate depletion layer 200, improve the efficiency of trap charge release, and further reduce the influence of trap charges.

[0046] Reference Figures 1 to 3 , in some embodiments of a hybrid gate structure of the present invention, it further includes a passivation layer 800, a source lead layer 910, a drain lead layer 920, and a second lead layer 930. The passivation layer 800 covers the substrate structure 100, the gate depletion layer 200, the source electrode 300, and the drain electrode 400. The passivation layer 800 is provided with a source via corresponding to the source electrode 300, a drain via 810 corresponding to the drain electrode 400, an intermediate via 820 corresponding to the intermediate portion 210, and an edge via 830 corresponding to the edge portion 220. The source lead layer 910 is disposed in the source via and the source lead layer 910 is connected to the source electrode 300. The drain lead layer 920 is disposed in the drain via 810 and the drain lead layer 920 is connected to the drain electrode 400. The second lead layer 930 is disposed in the intermediate via 820 and the second lead layer 930 is connected to the Schottky contact layer 500. The first lead layer 700 is disposed in the edge via 830.

[0047] By providing a passivation layer 800, the passivation layer 800 is provided with source vias, drain vias 810, intermediate vias 820, and edge vias 830, which respectively correspond to the source electrode 300, drain electrode 400, Schottky contact layer 500, and ohmic contact layer 600. A source lead layer 910 is disposed in the source via to lead out the source electrode 300, a drain lead layer 920 is disposed in the drain via 810 to lead out the drain electrode 400, a second lead layer 930 is disposed in the intermediate via 820 to lead out the Schottky contact layer 500, and a first lead layer 700 is disposed in the edge via 830 to lead out the ohmic contact layer 600. In this way, the passivation layer 800 covers and protects the substrate structure 100, gate depletion layer 200, source electrode 300, and drain electrode 400, enabling the structures covered by the passivation layer 800 to avoid oxidation and corrosion, and improving the reliability and safety of the structures.

[0048] A high electron mobility transistor provided by the present invention will be described below. A high electron mobility transistor described below can be correspondingly referred to the hybrid gate structure described above.

[0049] Reference Figures 1 to 3 , the present invention further provides a high electron mobility transistor, including the above-mentioned hybrid gate structure. The substrate structure 100 includes a substrate layer 110, a GaN buffer layer 120, and an AlGaN layer 130 that are sequentially stacked from bottom to top. A two-dimensional electron gas is formed between the GaN layer and the AlGaN layer 130 as the conductive channel.

[0050] A GaN (gallium nitride) buffer layer is epitaxially grown on the substrate layer 110, and an AlGaN (aluminum gallium nitride) layer is epitaxially grown on the GaN buffer layer 120. The GaN layer and the AlGaN layer 130 form a heterojunction, and a 2DEG (two-dimensional electron gas) is formed at the interface between the two as the conductive channel.

[0051] The middle part 210 of the gate depletion layer 200 is located between the source electrode 300 and the drain electrode 400. The gate depletion layer 200 consumes the electrons of the 2DEG to normally turn off the 2DEG between the source electrode 300 and the drain electrode 400, realizing the function of an enhancement-mode HEMT. A Schottky contact layer 500 is provided on the middle part 210 of the gate depletion layer 200 to form a Schottky contact, and an ohmic contact layer 600 is provided on the edge part 220 of the gate depletion layer 200 to form an ohmic contact. The equivalent structure of the ohmic contact does not form a diode, enabling the trap charges in the gate depletion layer 200 to be quickly released through the ohmic contact layer 600.

[0052] Thus, in the HEMT, the gate depletion layer 200 is provided with a middle portion 210 and an edge portion 220. A Schottky contact layer 500 is provided on the middle portion 210 and an ohmic contact layer 600 is provided on the edge portion 220. The Schottky contact layer 500 of the middle portion 210 ensures the gate performance, and the edge portion 220 is not located between the source 300 and the drain 400, reducing the influence of the ohmic contact layer 600 on the gate performance. The ohmic contact layer 600 of the edge portion 220 provides a path for quickly releasing trapped charges, reducing the influence of the trapped charges and improving the threshold voltage drift situation.

[0053] Reference Figures 1 to 3 , in some embodiments of a high electron mobility transistor of the present invention, the gate depletion layer 200 is a P-GaN layer, the Schottky contact layer 500 is a TiN layer, and the ohmic contact layer 600 is a Ti layer.

[0054] The P-GaN (P-doped gallium nitride) layer consumes the electrons of the 2DEG to achieve the purpose of normal off, and the P-GaN layer has the advantages of high breakdown voltage and strong reliability. In some embodiments of the present invention, the first lead layer 700 may be formed by laminating TiN (titanium nitride) and W (tungsten). The source lead layer 910, the drain lead layer 920, and the second lead layer 930 may be formed by laminating Ti, TiN, and W. Thus, the material structure of the combination of the ohmic contact layer 600 and the first lead layer 700 is the same as the material structures of the source lead layer 910, the drain lead layer 920, and the second lead layer 930, facilitating the simplification of the processing process.

[0055] A method for manufacturing a transistor provided by the present invention will be described below. A method for manufacturing a transistor described below can be mutually referred to with a hybrid gate structure and a high electron mobility transistor described above.

[0056] Reference Figures 1 to 4 , the present invention also provides a method for manufacturing a transistor, including: Manufacturing a substrate structure 100; Defining a pattern of the gate depletion layer 200 on the substrate structure 100 and manufacturing the gate depletion layer 200; Defining a pattern of the Schottky contact layer 500 on the gate depletion layer 200 and manufacturing the Schottky contact layer 500; Through a first etching process, an etching opening exposing the edge portion 220 of the gate depletion layer 200 is formed on the Schottky contact layer 500; Manufacturing a first passivation layer to cover the substrate structure 100, the gate depletion layer 200, and the Schottky contact layer 500; Through a second etching process, source openings and drain openings exposing the substrate structure 100 are formed, and the middle portion 210 of the gate depletion layer 200 is located between the source openings and the drain openings; Through a first metal deposition process, a source electrode 300 is fabricated in the source opening, and a drain electrode 400 is fabricated in the drain opening; A second passivation layer is fabricated to cover the first passivation layer, the source electrode 300, and the drain electrode 400; Through a third etching process, a source via exposing the source electrode 300, a drain via 810 exposing the drain electrode 400, an edge via 830 exposing the edge portion 220 of the gate depletion layer 200, and an intermediate via 820 exposing the middle portion 210 of the gate depletion layer 200 are formed; Through a second metal deposition process, a source lead layer 910 is formed in the source via, a drain lead layer 920 is formed in the drain via 810, an ohmic contact layer 600 is formed in the edge via 830, and a second lead layer 930 is formed in the intermediate via 820.

[0057] After fabricating the substrate structure 100, the gate depletion layer 200, and the Schottky contact layer 500, through a first etching process, an etching opening is formed on the edge portion 220 of the Schottky contact layer 500, so as to facilitate the subsequent direct contact between the ohmic contact layer 600 and the gate depletion layer 200 to achieve the purpose of ohmic contact. After fabricating the first passivation layer, through a second etching process, source openings and drain openings exposing the substrate structure 100 are formed, and the source electrode 300 and the drain electrode 400 are fabricated by a metal deposition method, such that both the source electrode 300 and the drain electrode 400 are in direct contact with the substrate structure 100 to form an ohmic contact. Then, a second passivation layer is fabricated to cover the first passivation layer, the source electrode 300, and the drain electrode 400 for protection. Through a third etching process, a source via exposing the source electrode 300, a drain via 810 exposing the drain electrode 400, an edge via 830 exposing the edge portion 220 of the gate depletion layer 200, and an intermediate via 820 exposing the middle portion 210 of the gate depletion layer 200 are formed. By a metal deposition method, a source lead layer 910 is simultaneously fabricated in the source via, a drain lead layer 920 is fabricated in the drain via 810, a second lead layer 930 is fabricated in the intermediate via 820, and an ohmic contact layer 600 is fabricated in the edge via 830.

[0058] It can be understood that the fabricated first passivation layer and second passivation layer form the passivation layer 800 in the above-mentioned hybrid gate structure. In some embodiments of the present invention, the first passivation layer and the second passivation layer may be formed of the same material, such as materials like silicon oxide, silicon nitride, etc.; in some embodiments of the present invention, the first passivation layer and the second passivation layer may also be formed of different materials, such as the first passivation layer being made of silicon oxide and the second passivation layer being made of silicon nitride.

[0059] It should be noted that the second metal deposition process can be depositing multiple layers of via metals. For example, if Ti, TiN, and W are stacked in sequence, then in the edge via 830, Ti serves as the ohmic contact layer 600, and TiN and W serve as the first lead layer 700, while the source lead layer 910, the drain lead layer 920, and the second lead layer 930 all include Ti, TiN, and W. In this way, source vias, drain vias 810, edge vias 830, and middle vias 820 are formed through the via process, and the effects of fabricating the ohmic contact layer 600 and the lead layer can be achieved during the metal deposition process, which is beneficial to simplifying the processing procedures and improving the processing efficiency.

[0060] Fabricating the substrate structure 100 may include: epitaxially growing a GaN buffer layer 120 on a substrate; and epitaxially growing an AlGaN layer 130 on the GaN buffer layer 120.

[0061] It can be understood that after forming the ohmic contact layer 600 and the lead layer through the second metal deposition process, processing steps such as bonding and encapsulation may also be included.

[0062] It should be noted that the source vias, drain vias 810, edge vias 830, and middle vias 820 only expose corresponding partial regions for the purpose of connecting the lead layer and do not need to be completely exposed.

[0063] For a transistor fabricated by a transistor manufacturing method provided by the present invention, the middle part 210 of the gate depletion layer 200 is located between the source 300 and the drain 400. The substrate structure 100 forms a conductive channel. The gate depletion layer 200 normally closes the conductive channel between the source 300 and the drain 400 to achieve the enhancement-mode function. A Schottky contact layer 500 is provided on the middle part 210 of the gate depletion layer 200 to form a Schottky contact, and an ohmic contact layer 600 is provided on the edge part 220 of the gate depletion layer 200 to form an ohmic contact. The ohmic contact equivalent structure does not form a diode, enabling the trap charges in the gate depletion layer 200 to be quickly released through the ohmic contact layer 600. In this way, by providing a middle part 210 and an edge part 220 in the gate depletion layer 200, with a Schottky contact layer 500 provided on the middle part 210 and an ohmic contact layer 600 provided on the edge part 220, the Schottky contact layer 500 on the middle part 210 ensures the gate performance, and the edge part 220 is not located between the source 300 and the drain 400, reducing the influence of the ohmic contact layer 600 on the gate performance. The ohmic contact layer 600 on the edge part 220 provides a path for quickly releasing trap charges, reducing the influence of trap charges and improving the threshold voltage drift situation.

[0064] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0065] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A hybrid gate structure, characterized in that: include: A substrate structure (100) for forming a conductive channel; A gate depletion layer (200) is disposed on the substrate structure (100), the gate depletion layer (200) being used to consume carriers of the conductive channel so as to normally close the conductive channel; A source electrode (300) and a drain electrode (400), wherein the source electrode (300) and the drain electrode (400) are arranged on the base structure (100), the gate depletion layer (200) comprises a middle portion (210) and an edge portion (220), and the middle portion (210) is located between the source electrode (300) and the drain electrode (400); A Schottky contact layer (500) is arranged on the gate depletion layer (200) and is located in the middle portion (210), wherein the Schottky contact layer (500) forms a Schottky contact with the gate depletion layer (200); A charge release layer is arranged on the depletion layer (200) and is located at the edge portion (220), and a gate leakage current of the charge release layer is greater than a gate leakage current of the Schottky contact layer (500).

2. The hybrid gate structure according to claim 1, characterized in that: The charge release layer is an ohmic contact layer (600), and the ohmic contact layer (600) forms an ohmic contact with the gate depletion layer (200).

3. The hybrid gate structure according to claim 2, characterized in that: The Schottky contact layer (500) comprises a first layer portion (510) located on the middle portion (210) and a second layer portion (520) located on the edge portion (220), wherein the second layer portion (520) surrounds the ohmic contact layer (600).

4. The hybrid gate structure according to claim 3, characterized in that: The second layer portion (520) is connected to the ohmic contact layer (600).

5. The hybrid gate structure according to claim 2, characterized in that: It also comprises a first lead-out layer (700), wherein the first lead-out layer (700) is arranged on the ohmic contact layer (600), and the resistivity of the first lead-out layer (700) is smaller than the resistivity of the ohmic contact layer (600).

6. A hybrid gate structure according to claim 1 or 2, characterized in that: There are two source electrodes (300), one of the two source electrodes (300) is located on one side of the drain electrode (400) and the other source electrode (300) is located on the other side of the drain electrode (400), the gate depletion layer (200) comprises two intermediate portions (210), the intermediate portions (210) are each provided between the drain electrode (400) and the two source electrodes (300), and the Schottky contact layer (500) is provided on each of the two intermediate portions (210).

7. The hybrid gate structure according to claim 6, characterized in that: The gate depletion layer (200) comprises two edge portions (220), one of the two edge portions (220) is connected to one side of the two middle portions (210) and the other edge portion (220) is connected to the other side of the two middle portions (210).

8. The hybrid gate structure according to claim 5, characterized in that: The invention also comprises a passivation layer (800), a source lead-out layer (910), a drain lead-out layer (920) and a second lead-out layer (930), wherein the passivation layer (800) covers the base structure (100), the gate depletion layer (200), the source (300) and the drain (400), and the passivation layer (800) is provided with a source through hole corresponding to the source (300), a drain through hole (810) corresponding to the drain (400), a middle through hole (820) corresponding to the middle portion (210) and a drain through hole (810) corresponding to the edge portion (220). The source lead-out layer (910) is arranged in the source through hole and the source lead-out layer (910) is connected to the source (300), the drain lead-out layer (920) is arranged in the drain through hole (810) and the drain lead-out layer (920) is connected to the drain (400), the second lead-out layer (930) is arranged in the middle through hole (820) and the second lead-out layer (930) is connected to the Schottky contact layer (500), and the first lead-out layer (700) is arranged in the edge through hole (830).

9. A high electron mobility transistor, characterized in that: Comprising a hybrid gate structure as claimed in any one of claims 1 to 8, the base structure (100) comprising a substrate layer (110), a GaN buffer layer (120) and an AlGaN layer (130) stacked in sequence from bottom to top, and a two-dimensional electron gas is formed between the GaN layer and the AlGaN layer (130) as the conductive channel.

10. A high electron mobility transistor according to claim 9, characterized in that: The gate depletion layer (200) is a P-GaN layer, the Schottky contact layer (500) is a TiN layer, the charge release layer is an ohmic contact layer (600), and the ohmic contact layer (600) is a Ti layer.

11. A method for manufacturing a transistor, characterized in that: include: Making a base structure (100); Defining a gate depletion layer (200) pattern on the substrate structure (100) to produce the gate depletion layer (200); Defining a Schottky contact layer (500) pattern on the gate depletion layer (200) to produce the Schottky contact layer (500); By means of a first etching process, an etching opening is formed on the Schottky contact layer (500) to expose an edge portion (220) of the gate depletion layer (200); Manufacturing a first passivation layer to cover the base structure (100), the gate depletion layer (200) and the Schottky contact layer (500); Through a second etching process, a source opening and a drain opening are formed to expose the substrate structure (100), and the middle portion (210) of the gate depletion layer (200) is located between the source opening and the drain opening; Through a first metal deposition process, a source electrode (300) is formed in the source electrode opening, and a drain electrode (400) is formed in the drain electrode opening; Making a second passivation layer to cover the first passivation layer, the source electrode (300) and the drain electrode (400); Through a third etching process, a source through hole exposing the source (300), a drain through hole (810) exposing the drain (400), an edge through hole (830) exposing the edge portion (220) of the gate depletion layer (200), and a middle through hole (820) exposing the middle portion (210) of the gate depletion layer (200) are formed; Through a second metal deposition process, a source lead-out layer (910) is formed in the source through hole, a drain lead-out layer (920) is formed in the drain through hole (810), an ohmic contact layer (600) is formed in the edge through hole (830), and a second lead-out layer (930) is formed in the middle through hole (820).

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