IC substrate with embedded bridge element, arrangement and method of manufacturing

Abstract

An integrated circuit (IC) substrate (100) is described, the IC substrate comprising: i) a reinforced fiber-free dielectric material (110); ii) a bridging element (120) comprising: iia) at least two electrically conductive terminals (121a, 121b), iib) an electrical interconnect (125) electrically interconnecting the at least two electrically conductive terminals (121a, 121b), and iic) a dielectric protective material (122) encapsulating the electrical interconnect (125), the bridge element (120) is embedded in the reinforced, fiber-free dielectric material (110) such that the at least two components (140a, 140b) are electrically connected to the at least two electrically conductive terminals (121a, 121b), respectively, when surface mounted to the first main surface (101) of the IC substrate (100); and iii) a redistribution layer (RDL) structure (130) arranged at a second main surface (102) of the IC substrate (100) opposite the first main surface (101) and capable of being electrically connected to the at least two components (140a, 140b) by further electrical interconnects (105).

Description

Technical Field

[0001] The present invention relates to an integrated circuit (IC) substrate, an IC substrate arrangement structure, an electronic component, and a method for manufacturing an IC substrate. In addition, the present invention also relates to the use of an organic bridging element in a silicon-free IC substrate.

[0002] Thus, the present invention may relate to the technical field of component carriers, in particular interposers such as IC substrates. Background Art

[0003] Against the background of the increasing product functionality of component carriers equipped with one or more electronic components, the ever-decreasing size of such electronic components, and the increasing number of electronic components to be mounted on component carriers such as printed circuit boards, more and more powerful array-like components or packages with multiple electronic components are being employed, which have multiple contact parts or connection parts, wherein the pitch between these contact parts is getting smaller and smaller. Removing the heat generated during operation by such electronic components and the component carriers themselves has become an ever-increasing problem. In addition, effective protection against electromagnetic interference (EMI) has become an ever-increasing problem. At the same time, the component carrier should be mechanically stable and electromagnetically reliable so that it can operate even under harsh conditions.

[0004] In the component carrier industry, there may be a trend to mount two or more electronic components on a circuit board, wherein these electronic components are interconnected by electrical connection parts, in particular wherein the electrical connection parts are embedded in the circuit board. In other words, instead of embedding the electronic components in the circuit board, only the electrical connection parts between the electronic components are embedded in the circuit board. Such an embedded interconnection part may be referred to as a bridge and is typically provided by copper traces encapsulated in a silicon material.

[0005] However, providing high-density graphic structures (e.g., very small line / space ratios) in this regard, especially in an economical way, may be regarded as a challenge. Summary of the Invention

[0006] There may be a need to provide an IC substrate, in particular an interposer, with high functionality (and / or high density) in an efficient and economical manner.

[0007] According to one aspect of the present invention, an integrated circuit (IC) substrate, in particular a silicon-free IC substrate, is described, which includes:

[0008] i) a reinforced fiber-free dielectric material (e.g., Ajinomoto stacked film);

[0009] ii) a bridging element, which includes:

[0010] iia) At least two electrically conductive terminals (exposed at the top surface),

[0011] iib) An electrical interconnect (e.g., a trace of electrically conductive material) that electrically interconnects the at least two electrically conductive terminals, and

[0012] iic) A dielectric protection material (especially an organic dielectric protection material) that encapsulates the electrical interconnect.

[0013] The bridging element is at least partially embedded in the fiber - free dielectric material such that at least two (active / passive, electrical / electronic) components (e.g., integrated circuits) are electrically connected / can be electrically connected to the at least two electrically conductive terminals when surface - mounted to the first major surface (parallel to the major extension directions along the x - axis and y - axis) of the IC substrate.

[0014] The IC substrate further comprises:

[0015] iii) A redistribution layer (RDL) structure that is disposed at the second major surface (opposite to the first major surface) of the IC substrate and that is electrically connected / can be electrically connected to the at least two components through additional electrical interconnects (vias).

[0016] According to a further aspect of the invention, an IC substrate arrangement is described, which comprises:

[0017] i) An IC substrate as described above; and

[0018] ii) The at least two components surface - mounted to the first major surface;

[0019] wherein a first component is electrically connected to a first terminal of the bridging element, and wherein a second component is electrically connected to a second terminal of the bridging element such that the at least two components are electrically interconnected through the bridging element.

[0020] According to a further aspect of the invention, an electronic assembly is described, which comprises:

[0021] i) An IC substrate as described above and / or an IC substrate arrangement as described above; and

[0022] ii) A component carrier, in particular, the component carrier is a printed circuit board or another IC substrate or an interposer, wherein the IC substrate or the IC substrate arrangement is surface - mounted to the component carrier.

[0023] According to a further aspect of the present invention, a method of manufacturing an integrated circuit substrate is described, the method comprising:

[0024] i) providing a bridging element comprising at least two conductive terminals, an electrical interconnect portion electrically interconnecting the at least two conductive terminals, and a dielectric protective material encapsulating the electrical interconnect portion;

[0025] ii) at least partially embedding the bridging element in a fiberless dielectric material reinforced such that at least two components are electrically connected to the at least two conductive terminals when surface-mounted to a first major surface of the IC substrate; and

[0026] iii) forming a redistribution layer structure at a second major surface of the IC substrate opposite the first major surface, and the redistribution layer structure being electrically connectable to the at least two components.

[0027] According to a further aspect of the present invention, a use (method of use) of an organic (silicon-free) bridging element in a (substantially) silicon-free IC substrate (except for possible embedded components including silicon) is described, wherein the organic bridging element is embedded in a fiberless dielectric material reinforced (of the IC substrate).

[0028] In the context of this document, the term "fiberless dielectric material reinforced" or "fiberless dielectric material non-woven reinforced" may in particular refer to a dielectric material not fiber-reinforced (re-reinforced), such as a resin. In the technical field of component carriers, resins fiber-reinforced with fibers such as glass fibers or carbon fibers may typically be applied. Important examples may be the widely used FR4 material comprising an epoxy resin with embedded fibers. In this regard, the fibers may be natural or artificial structures with a length significantly greater than the width. In particular, the fibers may be at least partially flexible / bendable. Thus, a "fiberless dielectric material reinforced" may be any dielectric material reinforced but not using fiber reinforcement. In an example, the fiberless dielectric material reinforced is reinforced by spherical elements, such as glass spherical elements. Thus, a preferred example may be the Ajinomoto Build-up Film (ABF) comprising a resin with embedded glass spherical elements. Alternatively, the fiberless dielectric material reinforced may be completely without any reinforcing structure.

[0029] In the context of this document, the term "bridging element" may particularly refer to any element that can be used as an electrical interconnection between (active / passive) components, particularly electrical / electronic components. In an example, a bridging element may require at least two (exposed) electrically conductive terminals to be connected to the components respectively. In a more complex example, a bridging element may include multiple terminals for connecting (interconnecting) two or more components. The electrically conductive terminals (preferably, these terminals are exposed at the same major surface (top major surface) of the bridging element) may be interconnected by electrical interconnections arranged in the bridging element. Thus, when observed from a (specific) cross-section of the bridging element (e.g., from a side view cross-section, see e.g. Figure 1 ), the electrically conductive terminals and the electrical interconnections may be arranged in a "U" shape. In particular, a bridging element may include multiple "U" shapes, where a larger "U" shape surrounds a smaller "U" shape. An (organic) bridging element may include additional structures that have functions such as resistance measurement, grounding, heat dissipation, etc. in addition to the function of interconnecting between ICs.

[0030] In the context of this document, the term "dielectric protection material" may particularly refer to such a dielectric material that is suitable for embedding / encapsulating the electrical interconnections of the bridging element (and optionally, embedding / encapsulating the electrically conductive terminals at least partially), thereby protecting the interconnections. The dielectric protection material may be the same as or different from the dielectric material (particularly a reinforced fiberless dielectric material) of the IC substrate in which the bridging element is (partially) embedded. In a preferred embodiment, the dielectric protection material may be composed of an organic material, such as a resin, or include an organic material, such as a resin. In this example, the dielectric protection material may not include silicon. In an example, the dielectric protection material may not contain inorganic materials, particularly, the dielectric protection material may not contain metals and / or ceramics. In another example, the dielectric protection material may include glass.

[0031] In the context of this document, the term "silicon" may particularly refer to elemental silicon and / or metallic silicon. Even though glass may include silicon dioxide (SiO2), in the context of this application, silicon dioxide (SiO2) may not be considered silicon. For example, the core layer structure of an IC substrate may be reinforced by glass fibers. However, since the glass may not contain elemental silicon / metallic silicon, this IC substrate may still be considered silicon-free.

[0032] In the context of this document, the term "organic bridging element" may particularly refer to the dielectric protection material. This means that when the dielectric protection material includes an organic material, the bridging element may be considered an organic bridging element. The electrically conductive parts (terminals, electrical interconnections) of the bridging element may include metals such as copper, and in evaluating whether the bridging element is organic, in an example, these electrically conductive parts of the bridging element may not be considered.

[0033] In the context of this document, the term "redistribution layer (RDL) structure" can particularly refer to such an electrically conductive structure that is designed to convert a small electrical contact at a first surface into a large electrical contact at a second surface, in particular where the first surface and the second surface are arranged opposite to each other. In an example, the redistribution layer structure includes a plurality of vertical structures (vias) and horizontal structures (pads) to enlarge the size of a first electrical contact (i.e., a terminal of an IC) to the size of a second electrical contact (i.e., a solder ball to be mounted on a larger component carrier entity). In an example, the redistribution layer structure extends through the entire IC substrate. In another example, the redistribution layer structure is arranged under a bridging element in the IC substrate. However, the redistribution layer structure can be electrically connected vertically to an electrical contact on the (upper) main surface of the IC substrate by means of (relatively long) vias.

[0034] In the context of this document, the term "component carrier" can particularly denote any support structure capable of accommodating one or more components on and / or in the component carrier to provide mechanical support and / or electrical connection. In other words, the component carrier can be configured as a mechanical and / or electronic carrier for components. In particular, the component carrier can be one of the following: a printed circuit board, an organic interposer, a metal core substrate, an organic substrate, and an IC (integrated circuit) substrate.

[0035] In the context of this document, the term "IC substrate" can particularly denote a small component carrier. In comparison with a PCB, the IC substrate can be a relatively small component carrier on which one or more components can be mounted and which can be used as a connection medium between one or more chips and another PCB. More specifically, the IC substrate can be understood as such a carrier: a carrier for electrical connection parts or electrical grids, and a component carrier comparable to a printed circuit board (PCB) but having a relatively high density of lateral and / or vertical connections. Lateral connections are, for example, conductive paths, and vertical connections can be, for example, drilled holes. These lateral and / or vertical connections are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections for accommodated or non-accommodated components (such as bare wafers), in particular IC chips, to a printed circuit board or an intermediate printed circuit board. In an example, the IC substrate can be regarded as an interposer, for example, located between an electronic component and a printed circuit board.

[0036] In the context of this document, an IC substrate should not be understood as any substrate suitable for carrying an IC. Instead, the term "IC substrate" can be a technical term for a specific high-density PCB including common PCB materials. For example, a silicon substrate may not be regarded as an IC substrate in the context of this application.

[0037] According to an exemplary embodiment, the present invention is based on the idea that in the case where both a bridging element and a redistribution layer structure are integrated in an IC substrate, an IC substrate with high functionality and / or high density can be provided in an efficient and economical manner, wherein the bridging element is embedded in a fiberless dielectric material with reinforcement. The IC substrate can be flexibly used as a multifunctional interposer between two or more electronic components and a printed circuit board in a variety of different applications.

[0038] Although an interposer can generally include bridging elements for interconnecting surface-mounted components or a redistribution layer for connecting surface-mounted components to a larger entity, the inventors have now found that a particularly efficient IC substrate can be obtained when integrating both functions into the same interposer. For example, additional vias can connect the redistribution layer structure to a first part of the component, while a second part is connected to the bridging element. Thus, high functionality can be provided through different electrical connection portions between the component and the redistribution layer structure (the upper and lower main surfaces of the IC substrate).

[0039] In particular, by interacting with the fiberless dielectric material with reinforcement, an efficient manufacturing method that results in a high-density pattern can be achieved. In a preferred example, an organic bridging element can be embedded in a silicon-free IC substrate, thus saving the cost of silicon materials. In addition, in this way, existing component carrier (resin-based) technologies can be directly applied so that the IC substrate can be manufactured in the same component carrier manufacturing process / equipment.

[0040] Exemplary Embodiment

[0041] According to an embodiment, the (fiberless dielectric material with reinforcement) dielectric material is reinforced by spherical materials. In particular, the (fiberless dielectric material with reinforcement) dielectric material is reinforced by glass spheres or carbon spheres. More particularly, wherein the dielectric material includes Ajinomoto Build-up Film ABF. This can provide the advantage that strong and mature materials can be applied to increase the pattern density (especially the line pitch). Although fiber-reinforced materials such as prepregs have been well established in the component carrier industry, the fibers may form multiple elongated structures, which may hinder the manufacture of high-density patterns. Therefore, especially in the case of an IC substrate, using spheres as the filler material may be more preferable than using fibers. In addition, in a resin reinforced with spheres, the embedding of the bridging element can be completed more efficiently and precisely.

[0042] In an example, the adhesion between the reinforced silica-free dielectric material and the bridging element (to be embedded in the reinforced silica-free dielectric material) would be particularly stable, especially when the bridging element is an organic / silica-free bridging element. Without being bound by a particular theory, it is currently believed that the joint between the resin materials (the resin material of the reinforced silica-free dielectric material and the resin material of the dielectric protection material of the bridging element) is more uniform (e.g., in terms of the coefficient of thermal expansion) and more stable compared to, for example, the joint between a resin material and a silica material. Additionally, the coefficient of thermal expansion (CTE) may be more favorable (more easily adjustable), and the filling performance of the cavity can be improved. Thus, the formation of relatively small vias can also be achieved.

[0043] According to a further embodiment, the bridging element is (substantially) silica-free. In other words, the bridging element (in particular, the bridging element referred to as the dielectric protection material) (substantially) does not include silicon or a silicon-based component. This can provide the following advantages: cost savings can be achieved (silicon can be rather expensive compared to resin materials), while the entire manufacturing process can be carried out within a component carrier manufacturing device that applies resin instead of silicon. Additionally, the resin / resin joint may be more stable and stronger than the resin / silica joint.

[0044] According to a further embodiment, the IC substrate itself is (substantially) silica-free. In other words, the IC substrate substantially comprises metal and a silica-free dielectric (resin) material. In an example, in the case where an electronic component (e.g., a semiconductor) can be embedded in the IC substrate, the potential silicon content of the electronic component may be disregarded when evaluating whether the IC substrate is silica-free.

[0045] According to a further embodiment, the dielectric protection material comprises an organic material (e.g., a carbon-based compound) or consists of an organic material (e.g., a carbon-based compound). In this example, the dielectric protection material may be silica-free.

[0046] According to a further embodiment, the dielectric protection material is different from the reinforced silica-free dielectric material. For example, the dielectric protection material may be a non-reinforced resin material, such as a photosensitive dielectric (PID) material and polyimide. Depending on the required application, it may be more advantageous to use a less reinforced material to encapsulate the electrical interconnections of the bridging element (e.g., to provide higher flexibility).

[0047] According to a further embodiment, the dielectric protection material is equivalent to (i.e., substantially the same as) the reinforced silica-free dielectric material, in particular, the dielectric protection material is similar to (the same as) the reinforced silica-free dielectric material. Depending on the required application, it may be more advantageous to use a similar material, for example, to reduce material damage caused by different thermal expansions. The amounts of the reinforced silica-free materials may vary respectively.

[0048] According to a further embodiment, the IC substrate further includes a core layer structure, and the bridging element is at least partially embedded in the core layer structure. Such a core layer structure can provide the following advantages: the IC substrate can be more stable, more robust, and more easily achieve bump pitch to prevent warping. In an example, the core layer structure may include a cured resin material during manufacturing, while other dielectric layer structures of the IC substrate may not be fully cured during manufacturing. In an embodiment, when the bridging element is embedded in the core layer structure, the bridging element can be well protected.

[0049] In the context of this document, the term "core layer structure" may particularly refer to a fully cured framework (dielectric layer structure), in particular, a fully cured framework (dielectric layer structure) having two conductive layer structures in direct contact with the opposite surfaces of the dielectric layer structure, respectively.

[0050] In addition or alternatively, the core layer structure may include a plurality of alternating fully cured frameworks and a plurality of conductive layer structures ("any laminate") sandwiched in the stacking direction of the laminate.

[0051] According to a further embodiment, a reinforced fiberless dielectric material forms the core layer structure. Thus, the bridging element can be directly embedded in the core layer structure, enabling a strong bond to be achieved.

[0052] According to a further embodiment, a reinforced fiberless dielectric material is provided in another core layer structure, in particular, a reinforced fiberless dielectric material is provided in a fiber-reinforced dielectric material such as a prepreg. In this example, the reinforced fiberless dielectric material may be different from the material of the other core layer structure and may itself be embedded in the core in a well-protected manner. In an example, when considering whether the IC substrate is silicon-free, glass fibers may be disregarded.

[0053] According to a further embodiment, the IC substrate is a coreless (i.e., without a core layer structure) IC substrate. This can provide the following advantages: the IC substrate can be designed in a particularly thin (but still robust) manner. In an example, the manufacturing process may include an additive process, such as (m)SAP / NIL (nanoimprint lithography). In another example, NIL may also be used to manufacture the bridging element. In this context, the term "NIL" may particularly refer to a method of manufacturing nanoscale patterns. The nano-lithography process creates patterns through mechanical deformation of an imprint resist layer and subsequent processes. The imprint resist layer is typically a monomer or polymer formulation that is cured by heat or ultraviolet light during or after imprinting. The adhesion between the resist and the mold can be controlled to allow proper peeling.

[0054] According to a further embodiment, the further electrical interconnects include a plurality of vias that at least partially extend vertically through the IC substrate, and the plurality of vias can be electrically connected to components and / or a redistribution layer structure, in particular where bridging elements are arranged between the plurality of vias (in particular in the horizontal direction (parallel to the main extension directions x, y), more particularly in the middle / central part of the IC substrate in the horizontal and / or vertical directions).

[0055] In this preferred embodiment, both the bridging elements and the RDL structure can be efficiently embedded in the IC substrate. Thereby, the embedded bridging elements can be surrounded by further electrical (vertical) interconnects from the RDL structure to surface-mounted components. The vias can simultaneously form efficient electrical connections and a protective cage for the embedded bridging elements. Such a protective cage can also have a shielding function, for example, electromagnetic shielding with respect to an antenna. In addition, the protective cage can also provide a heat dissipation function.

[0056] According to a further embodiment, the thickness of the (further) core layer structure is greater than the thickness of the bridging elements. This can provide the advantage that the bridging elements are encapsulated and protected in a robust manner. The stable material of the (further) core layer structure can support the bridging elements from below and from the sides.

[0057] According to a further embodiment, the IC substrate further includes an upper dielectric layer structure located on top of the bridging elements and on top of the dielectric material. This can provide the following advantages: additional stack-ups can be provided in a flexible manner. The upper dielectric member can be the same as or different from the reinforced fiberless dielectric material. Vias can be formed through the upper dielectric material to establish electrical through-connections between the components and the bridging elements / redistribution layer structure.

[0058] In an example, the upper dielectric layer structure includes a material different from the dielectric material. For example, the upper dielectric layer structure includes a non-reinforced dielectric material (resin, such as PID or polyimide). In another example, the upper dielectric layer structure can include a fiber-reinforced dielectric material.

[0059] In an example, the upper dielectric layer structure includes a material equivalent / similar to the dielectric material.

[0060] In the context of this document, the term "equivalent" can particularly refer to the situation where two materials (and / or layer structures) are substantially similar. For example, two reinforced fiberless layer structures can be equivalent but not similar when the resin materials are different. In another example, two reinforced fiber layer structures can be equivalent when they are reinforced by (glass) fibers but include different resin materials. In another example, two reinforced fiberless layer structures can be equivalent but not similar when the respective contents of the reinforcing materials are different.

[0061] In the example, the upper dielectric layer structure includes a plurality of upper dielectric layer structure vias that extend vertically through the upper dielectric layer structure, and the plurality of upper dielectric layer structure vias can be electrically connected to components, and / or the plurality of upper dielectric layer structure vias are electrically connected to the plurality of vias (additional electrical interconnections).

[0062] According to another embodiment, the redistribution layer structure includes RDL dielectric material different from the dielectric material. In particular, the redistribution layer structure includes a fiber-reinforced dielectric material. According to another embodiment, the redistribution layer structure includes RDL dielectric material equivalent / similar to the dielectric material.

[0063] Depending on the required application, similar or different materials may be preferred in different examples.

[0064] According to another embodiment, the IC substrate includes at least one embedded (electronic) component (active or passive). In a preferred example, the component is (at least partially) embedded in an (additional) core layer structure, particularly where the upper main surface is flush with the (additional) core layer structure. This can provide the advantage of better protecting additional functionality. Thus, the embedded component can be electrically connected at the top main surface and / or the bottom main surface via vias.

[0065] According to another embodiment, one or more components are embedded at a vertical height (in the stack) equivalent (particularly the same) to that of the bridging element. In the example, the component can be encapsulated in a fiberless material (e.g., ABF) on the same layer as the bridging element.

[0066] According to another embodiment, the IC arrangement includes additional (electronic) components (active or passive) surface-mounted to the IC substrate. The components can be arranged adjacent (side by side) to the at least two components. In the example, the additional component is not electrically connected to the bridging element. However, in another example, the additional component is electrically connected to the bridging element.

[0067] According to another embodiment, the at least two components include three or more components. In particular, the at least two components include four or more components, and each of the at least two components is electrically connected to the bridging element / can be electrically connected to the bridging element (particularly, all components are interconnected via the bridging element).

[0068] According to another embodiment, the IC substrate includes two or more bridging elements. In this example, the at least two components can include three or more components (see above).

[0069] According to a further embodiment, the method further comprises: placing (directly) a bridging element on a temporary carrier, in particular, the bridging element having a terminal main surface at which the terminals are exposed. The temporary carrier can be an established concept in component carrier manufacturing: part of the manufacturing can be done on a temporary carrier (e.g., one or more electrically insulating layer structures and / or electrically conductive layer structures), and thereafter, the temporary carrier can be removed.

[0070] According to a further embodiment, embedding the bridging element further comprises: laminating a dielectric material on the bridging element.

[0071] According to a further embodiment, embedding the bridging element further comprises: placing the bridging element in a cavity of a core layer structure and encapsulating the bridging element in the cavity with a dielectric material.

[0072] In these embodiments, the bridging element can be mounted (e.g., using an adhesive) on the temporary carrier and / or mounted in a cavity of a stack preform (e.g., using an adhesive). The dielectric material can be in an uncured form so that the sidewalls of the bridging element can also be effectively covered and protected.

[0073] According to a further embodiment, the method further comprises: forming a plurality of vias through the dielectric material and / or through the core layer structure. This can be done by established component carrier manufacturing techniques such as mechanical drilling and / or laser drilling.

[0074] According to a further embodiment, the method further comprises: forming an upper dielectric layer structure on top of the dielectric material, and in particular, forming a plurality of upper dielectric layer structure vias through the upper dielectric layer structure.

[0075] According to a further embodiment, the IC substrate comprises a solder mask portion and / or a layer structure of a surface treatment portion (e.g., ENIPEG).

[0076] According to a further embodiment, a plurality of IC substrates can be manufactured (at least partially) simultaneously. Thereafter, a singulation step (e.g., dicing and / or deep routing) can be performed to manufacture individual IC substrates.

[0077] According to a further embodiment, the IC substrate is connected to the at least one component and / or connected to a component carrier by a metal structure, in particular, the metal structure is a metal column, and more particularly, the metal structure is a copper column.

[0078] According to a further embodiment, at least two mounted components include similar or different bump pitches (e.g., one of standard flip chip bumps, fine pitch bumps, micro bumps, columnar bumps).

[0079] In the following, some embodiments of the component carrier are described in detail. These descriptions apply to IC substrates and to printed circuit boards.

[0080] In an embodiment, the component carrier is configured as one of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.

[0081] In an embodiment, the component carrier is shaped as a plate. This contributes to a compact design, in which, nevertheless, the component carrier still provides a large substrate for the mounting components on the component carrier. In addition, in particular, a die, as an example of an embedded electronic component, can be conveniently embedded into a thin plate such as a printed circuit board due to the small thickness of the die.

[0082] In an embodiment, the stack of the component carrier includes at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier can be a laminate of one or more of the mentioned electrically insulating layer structures and one or more of the mentioned electrically conductive layer structures, in particular a laminate formed by applying mechanical pressure and / or thermal energy. The mentioned stack can provide a plate-shaped component carrier that can provide a large mounting surface for additional components and is still very thin and compact.

[0083] In the context of the present application, the term "printed circuit board (PCB)" can particularly denote a plate-shaped component carrier formed by laminating a plurality of electrically conductive layer structures and a plurality of electrically insulating layer structures, for example by applying pressure and / or by supplying thermal energy. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures can include resin and / or glass fiber, a so-called prepreg, or FR4 material. By forming holes through the laminate, for example in a way of laser drilling or mechanical drilling, and by partially or completely filling these holes with an electrically conductive material (in particular copper) to form vias or any other through-hole connections, the individual electrically conductive layer structures can be connected to each other in a desired manner. The filled holes connect the entire stack (i.e., through-hole connections extending through multiple layers or the entire stack), or the filled holes connect at least two electrically conductive layers, i.e., so-called vias. Similarly, optical interconnects can be formed through the respective layers of the stack to accommodate an electro-optical circuit board (EOCB). In addition to one or more components that can be embedded in the printed circuit board, the printed circuit board is generally configured to accommodate one or more components on one surface or on opposite two surfaces of the plate-shaped printed circuit board. The one or more components can be connected to the respective main surfaces by soldering. The dielectric part of the PCB can include a resin with reinforcing fibers (such as glass fibers).

[0084] In the context of the present application, the term "substrate" may particularly denote a small component carrier. Relative to a PCB, the substrate may be a relatively small component carrier on which one or more components can be mounted and which can serve as a connection medium between one or more chips and another PCB. For example, the substrate may have approximately the same dimensions as the components to be mounted thereon (in particular, electronic components) (e.g., in the case of a chip-scale package (CSP)). In another embodiment, the substrate may be substantially larger than the specified components (e.g., in a flip chip ball grid array (FCBGA) configuration). More specifically, the substrate may be understood as such a carrier: a carrier for electrical connection parts or electrical networks, and a component carrier comparable to a printed circuit board (PCB) but having a relatively high density of lateral and / or vertical connections. Lateral connections are, for example, conduction paths, and vertical connections may be, for example, drilled holes. These lateral and / or vertical connections are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections for accommodated or non-accommodated components (such as, for example, bare wafers), in particular IC chips, to a printed circuit board or an intermediate printed circuit board. Thus, the term "substrate" also includes an "IC substrate". The dielectric part of the substrate may include a resin having reinforcing particles (such as, for example, reinforcing spheres, in particular glass spheres).

[0085] The substrate or the interposer may include or be composed of at least one layer of at least one of the following: glass; silicon (Si) and / or a photosensitive or dry-etchable organic material, such as an epoxy-based stacked material (such as, for example, an epoxy-based stacked film); or a polymer compound (the polymer compound may or may not include photosensitive and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0086] In an embodiment, the at least one electrically insulating layer structure (e.g., dielectric material) comprises at least one of the following: a resin or polymer, such as an epoxy resin, a cyanate resin, a benzocyclobutene resin, a bismaleimide-triazine resin; polyphenylene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), and / or combinations thereof. Reinforcing structures made of, for example, glass (multi-layer glass) - such as meshes, fibers, spheres, or other types of filler particles - can also be used to form composites. A semi-cured resin combined with a reinforcing agent, for example, a fiber impregnated with the above resin, is called a prepreg. These prepregs are usually named after their properties, such as FR4 or FR5, and the properties of these prepregs describe their flame retardant properties. Although prepregs, especially FR4, are generally preferred for rigid PCBs, other materials, especially epoxy-based stack materials (such as stack films) or photosensitive dielectric materials, can also be used. For high-frequency applications, high-frequency materials, such as polytetrafluoroethylene, liquid crystal polymer, and / or cyanate resin, may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials can be used as the electrically insulating structure in the component carrier.

[0087] In an embodiment, the at least one electrically conductive layer structure (e.g., electrical interconnections, terminals, pads, vias, etc.) comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, magnesium, carbon, (especially doped) silicon, titanium, and platinum. Although copper is generally preferred, other materials or their coated variants, especially those coated with superconducting materials or conductive polymers, are also possible, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT) for superconducting materials or conductive polymers, respectively.

[0088] At least one additional component can be embedded in the stack and / or surface-mounted on the stack.

[0089] The component(s) and / or the at least one additional component(s) may be selected from at least one of the following: a non-conductive inlay, a conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (e.g., a heat pipe), an optical guiding element (e.g., an optical waveguide or an optical conductor connection), an electronic component, or a combination thereof. The inlay may be, for example, a metal block (IMS-inlay) with or without a coating of insulating material, which may be embedded or surface-mounted for the purpose of promoting heat dissipation. Suitable materials are defined by the thermal conductivity of the material, which should be at least 2 W / mK (milli-Kelvin). Such materials are typically, but not limited to, metals, metal oxides, and / or ceramics, such as copper, aluminum oxide (Al2O3), or aluminum nitride (AlN). To increase the heat exchange capacity, other geometries with an increased surface area are also often used. Additionally, the component may be an active electronic component (having at least one implemented p-n junction), a passive electronic component such as a resistor, an inductor, or a capacitor, an electronic chip, a storage device (e.g., DRAM or other data memories), a filter, an integrated circuit (such as a field programmable gate array (FPGA), a programmable array logic (PAL), a generic array logic (GAL), and a complex programmable logic device (CPLD)), a signal processing component, a power management component (such as a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), a junction field effect transistor (JFET), or an insulated gate field effect transistor (IGFET), which are based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP), etc. and / or any other suitable inorganic compound), an optoelectronic interface element, a light-emitting diode, an optical coupler, a voltage converter (e.g., a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or a receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may also be embedded on the component carrier. For example, a magnetic element may be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element, or a ferrimagnetic element, e.g., a ferrite core) or may be a paramagnetic element. However, the component may also be an IC substrate, an interposer, or other component carriers such as in a board-in-board configuration. The component may be surface-mounted on the component carrier and / or may be embedded inside the component carrier. Additionally, other components, especially components that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, may be used as components.

[0090] In an embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a composite of a multi-layer structure that is stacked and connected together by applying pressure and / or heat.

[0091] After the internal layer structure of the component carrier has been processed, one or more additional electrically insulating layer structures and / or electrically conductive layer structures (in particular, by lamination) can symmetrically or asymmetrically cover one major surface or the opposite two major surfaces of the processed layer structure. In other words, stacking can continue until the desired number of layers is obtained.

[0092] After the formation of the stack having the electrically insulating layer structure and the electrically conductive layer structure is completed, the obtained layer structure or component carrier can be surface-treated.

[0093] In particular, in terms of surface treatment, an electrically insulating solder mask can be applied to one major surface or the opposite two major surfaces of the layer stack or component carrier. For example, such a solder mask can be formed over the entire major surface and subsequently the layer of the solder mask can be patterned to expose one or more electrically conductive surface portions that will be used to electrically couple the component carrier to an electronic periphery. The surface portions of the component carrier that are kept covered by the solder mask, in particular the surface portions containing copper, can be effectively protected against oxidation or corrosion.

[0094] In terms of surface treatment, a surface treatment portion can also be selectively applied to the exposed electrically conductive surface portions of the component carrier. Such a surface treatment portion can be an electrically conductive covering material on the exposed electrically conductive layer structures (such as pads, conductive traces, etc., in particular including copper or consisting of copper) on the surface of the component carrier. If the exposed electrically conductive layer structures are not protected, the exposed electrically conductive component carrier material (in particular copper) will be oxidized, resulting in a lower reliability of the component carrier. In addition, the surface treatment portion can be formed as, for example, a joint between a surface-mounted component and the component carrier. The surface treatment portion has the function of protecting the exposed electrically conductive layer structures (in particular copper circuits), and the surface treatment portion can, for example, be joined to one or more components by soldering. Examples of suitable materials for the surface treatment portion are organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), electroless nickel electroless palladium immersion gold (ENEPIG), gold (in particular hard gold), electroless tin plating (electroless and electroplating), nickel gold, nickel palladium, etc. Nickel-free materials can also be used for the surface treatment portion, especially for high-speed applications. Examples are ISIG (immersion silver immersion gold) and EPAG (electroless palladium autocatalytic gold). Description of the Drawings

[0095] The above-defined aspects and further aspects of the present invention will become apparent from the following examples of embodiments and will be illustrated with reference to the examples of these embodiments.

[0096] Figures 1 to 4 IC substrate arrangement structures according to exemplary embodiments of the present invention are shown respectively.

[0097] Figure 5 An electronic component according to an exemplary embodiment of the present invention is shown.

[0098] Figure 6 from a to Figure 6 from e illustrate a method of manufacturing an IC substrate according to an exemplary embodiment of the present invention.

[0099] Figure 7 from a to Figure 7 from f illustrate a method of manufacturing an IC substrate according to another exemplary embodiment of the present invention.

[0100] Figure 8 from a to Figure 8 from f illustrate a method of manufacturing an IC substrate according to another exemplary embodiment of the present invention. Detailed Description

[0101] The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference numerals.

[0102] Figure 1 An integrated circuit (IC) substrate arrangement structure 150 according to an exemplary embodiment of the present invention is shown. The arrangement structure 150 includes an IC substrate 100 having two surface-mounted components 140a, 140b and additional surface-mounted components 108.

[0103] The IC substrate 100 includes a central layer (which can be regarded as a core layer structure 103), and the central layer is made of a reinforced non-fibrous dielectric material 110. In this example, the reinforced non-fibrous dielectric material 110 is a stacked film of Ajinomoto having glass spheres embedded in a resin. A bridging element 120 is embedded in the reinforced non-fibrous dielectric material 110 such that the top main surface of the bridging element 120 is flush with the top main surface of the reinforced non-fibrous dielectric material 110.

[0104] The bridging element 120 includes a plurality of electrically conductive terminals 121a and 121b, and all of the plurality of electrically conductive terminals 121a and 121b are exposed at the top main surface of the bridging element 120. An electrical interconnect portion 125 (the electrical interconnect portion 125 includes a plurality of sub-interconnect portions) electrically connects the electrically conductive terminals 121a and 121b in pairs. Here, an organic dielectric protective material 122 encapsulates the electrical interconnect portion 125. In this example, the organic dielectric protective material 122 and the reinforced fiberless dielectric material 110 are shown as being different. However, in another example, the materials 110 and 122 may be the same. In this example, the dielectric protective material 122 includes a non-reinforced resin, such as a photosensitive dielectric (PID) material or polyimide.

[0105] In this example, two components 140a, 140b of an integrated circuit are surface-mounted to the first (upper) main surface 101 of the IC substrate 100 adjacent to each other (i.e., side by side, without physical contact but without other structures between the two components). Each component 140a, 140b is electrically connected to the plurality of electrically conductive terminals 121a, 121b of the bridging element 120.

[0106] The upper dielectric layer structure 115 (e.g., an ABF layer, a PID layer (photosensitive dielectric layer), a NIL layer) forms the outermost layer of the IC substrate 100 and is thus disposed on the reinforced fiberless dielectric material 110 and the bridging element 120 (the bridging element 120 is flush with the dielectric material 110). The plurality of electrically conductive terminals 121a, 121b of the bridging element 120 are connected through the bridging element vias 123 (here, tapered vias and columnar structures) through the upper dielectric layer 115. These vias 123 are further electrically connected to the component bridging solder balls 144, and the bridging solder balls 144 are in turn connected to the component bridging terminals 143.

[0107] In addition to the components 140a, 140b, additional components (active or passive) 108 are surface-mounted adjacent to the component 140a on the left but are not connected to the bridging element 120.

[0108] The IC substrate 100 further includes a redistribution layer structure 130, which is disposed / exposed at the second main surface 102 of the IC substrate 100 opposite to the first main surface 101. The redistribution layer structure (RDL) 130 includes a plurality of RDL pads 131 and a plurality of RDL vias 133 for converting the size of the component solder balls 142 (small IC pads) to the size of the RDL solder balls 132 (large additional solid pads), and the plurality of RDL vias 133 are embedded in the RDL dielectric material 135. The RDL dielectric material 135 may be the same as or different from the reinforced fiberless dielectric material 110 and / or the bridging element 120.

[0109] The IC substrate 100 includes a plurality of additional electrical interconnects 105 (vias) for electrically connecting the RDL structure 130 to components 140a and 140b, in particular to component solder balls 142, through the enhanced fiberless dielectric material 110. The plurality of vias 105 extend at least partially vertically through the IC substrate 100 and are electrically connected to components 140a and 140b and the redistribution layer structure 130. Here, the bridging element 120 is arranged between the plurality of vias 105 (in the horizontal direction, in particular at the central part of the plurality of vias 105). The redistribution layer structure 103 includes an RDL dielectric material 135, which in this example is shown as different from the dielectric material 110. In particular, the RDL dielectric material 135 is a fiber-reinforced dielectric material 135.

[0110] In this example, the bridging element 120 and the IC substrate 100 itself are made of an organic material and do not contain silicon. Components 140a, 140b may include silicon, but are not considered part of the IC substrate 100. In particular, in the case where components 140a, 140b are configured as semiconductor chips, components 140a, 140b may include silicon, but are not considered part of the IC substrate 100.

[0111] The IC substrate 100 further includes a core layer structure 103, and the bridging element 120 is completely embedded in the core layer structure 103. In this example, the enhanced fiberless dielectric material 110 forms the core layer structure 103. Further, in this example, the thickness of the core layer structure 103 is greater than the thickness of the bridging element 120.

[0112] Figure 2 An IC arrangement structure 150 having an IC substrate 100 according to another embodiment of the present invention is shown. Figure 2 The IC substrate 100 of Figure 1 is very similar to the IC substrate 100 shown in Figure 1 , but the upper dielectric layer structure 115 includes a plurality of upper dielectric layer structure vias 116 that extend from the vias 105 through the upper dielectric layer structure 115. In contrast, in

[0113] Figure 3 An IC arrangement structure 150 having an IC substrate 100 according to another embodiment of the present invention is shown. Figure 3 The IC substrate 100 of Figure 2 includes the same plurality of features as the IC substrate 100 shown in

[0114] In Figure 3

[0114] , the enhanced fiberless dielectric material 110 is only disposed in the area around the bridging element 120, thus surrounding (encapsulating) the bridging element 120. The core layer structure 103 is formed by another core layer structure 118 different from the enhanced fiberless dielectric material 110. In this example, the other core layer structure 118 includes (cured or not fully cured) enhanced fiber dielectric material, such as prepreg.

[0115] The IC substrate 100 further includes an embedded component 109, which is embedded in the upper part of the other core layer structure 118 and is electrically connected to the upper dielectric layer structure via hole 116.

[0116] Although the via holes 105 passing through the core layer structure 103 are shown as tapering from top to bottom in Figure 1 and Figure 2

[0114] , in Figure 3

[0114] , these via holes 105 include hourglass-shaped portions 106. In other words, the via holes 105 taper from top to the middle (vertical central part) and the via holes 105 also taper from bottom to the middle, so that a narrowing portion is formed at the (vertical) central part of each via hole 105.

[0117] In this example, the dielectric RDL material 136 is similar to (rather than different from 135) the dielectric protection material 122.

[0118] Figure 4 An IC arrangement structure 150 with an IC substrate 100 according to another embodiment of the present invention is shown. Figure 4 The IC substrate 100 of Figure 3

[0114] is very similar to the IC substrate 100 shown in Figure 4

[0114] , but the core layer structure 118 of

[0119] Figure 5 Figure 4 is significantly thinner, only slightly thicker than the bridging element 120. Figures 1 to 4 Figures 1 to 4 An electronic component 200 according to an exemplary embodiment of the present invention is shown. The electronic component 200 includes the IC arrangement structure 150 as described above with reference to

[0120] Figure 6 Figures 1 to 4 . In addition, the electronic component 200 further includes an additional component carrier 250 configured as a printed circuit board, wherein the IC substrate arrangement structure 150 is surface-mounted to the component carrier 250. Here, the IC substrate 100 serves as an interposer that i) converts the small electrical connection portions of the components 140a, 140b to the large electrical pads of the component carrier 250, and ii) functionally interconnects the components 140a, 140b via the bridging element 120. Figure 6e shows a method of manufacturing an IC substrate 100 according to an exemplary embodiment of the present invention.

[0121] Figure 6 a: Provide a temporary carrier 170 on which a bridging element 120 is disposed / formed. The first bridging terminal 121a and the second bridging terminal 121b are oriented towards the temporary carrier 170 and are in direct physical contact with the temporary carrier 170. The terminals 121a and 121b are electrically interconnected via an electrical interconnect portion 125 located in a dielectric protection material 122.

[0122] Figure 6 b: Set the reinforced fiberless dielectric material 110 (in an uncured form) on top of the bridging element 120 to encapsulate the bridging element 120.

[0123] Figure 6 c: Remove the encapsulated bridging element 120 from the temporary carrier 170 (and in this example, the encapsulated bridging element 120 is flipped) and cover (laminate) it with an upper dielectric layer structure / material 115 disposed on top of the terminals 121a, 121b. On the upper main surface, the fiberless dielectric material 110 is flush with the first bridging terminal 121a and the second bridging terminal 121b of the bridging element 120.

[0124] Figure 6 d: Form vias 105 through the upper dielectric layer structure 115 and the reinforced fiberless dielectric material 110. This can be done by laser drilling to form a taper from the upper main surface to the lower main surface. At the respective main surfaces, each via 105 is covered by a pad. The first bridging terminal 121a and the second bridging terminal 121b are electrically connected through the upper dielectric layer structure 115 by a plurality of bridging element vias 123, and the plurality of bridging element vias 123 are respectively elongated by additional electrically conductive columns (in the thickness direction of the stack).

[0125] Figure 6 e: Form a redistribution layer structure 130 at the bottom of the IC substrate 100. The redistribution layer structure 130 includes a plurality of traces 131 and vias 133 located in a dielectric material 135. The redistribution structure 130 is directly located below the reinforced fiberless dielectric material 110 but does not contact the embedded bridging element 120. The final IC substrate 100 is equivalent to the IC substrate 100 described with reference to Figure 1 described IC substrate 100.

[0126] Figure 7 a to Figure 7 f shows a method of manufacturing an IC substrate 100 according to another exemplary embodiment of the present invention.

[0127] Figure 7 a: Provide a temporary carrier 170 on which the bridging element 120 is disposed / formed. The first bridging terminal 121a and the second bridging terminal 121b are oriented towards the temporary carrier 170 and are in direct physical contact with the temporary carrier 170. The terminals 121a and 121b are electrically interconnected via electrical interconnections 125 located in the dielectric protection material 122.

[0128] Figure 7 b: Set the reinforced fiberless dielectric material 110 (in an uncured form) on top of the bridging element 120 to encapsulate the bridging element 120.

[0129] Figure 7 c: Remove the encapsulated bridging element 120 from the temporary carrier 170 (and in this example, the encapsulated bridging element 120 is flipped). Through-holes 105 are formed through the reinforced fiberless dielectric material 110. This can be done by laser drilling to form a taper from the upper main surface to the lower main surface. At the corresponding main surfaces, each through-hole 105 is covered by a pad. The fiberless dielectric material 110 is flush with the connection pads 121a and 121b. Considering that the thickness of the exposed pads 121a and 121b may increase during the plating of the through-holes around the bridging element 120, two additional options (a. and b.) are given. This can bring two positive effects:

[0130] i) Laser through-hole formation and plating can be more uniform and consistent with the surrounding area of the bridging element, while the geometry of the holes is the same;

[0131] ii) Due to the thickening of the metal / copper, the stress on the bridging element pads 121a, 121b during laser through-hole formation is reduced.

[0132] Figure 7 d: The encapsulated bridging element 120 is covered (laminated) by an upper dielectric layer structure 115 disposed on top of the terminals 121a, 121b.

[0133] Figure 7 e: The first bridging terminal 121a is electrically connected to the second bridging terminal 121b by a plurality of bridging element through-holes 123 through the upper dielectric layer structure 115. In addition, the through-holes 105 are electrically connected by a plurality of upper dielectric layer through-holes 116 through the upper dielectric layer structure 115 respectively.

[0134] Figure 7f: A redistribution layer structure 130 is formed at the bottom of the IC substrate 100. The redistribution layer structure 130 includes a plurality of traces 131 and vias 133 located in the dielectric material 135. The redistribution structure 130 is directly located below the reinforced fiberless dielectric material 110 but does not contact the embedded bridging element 120. The final IC substrate 100 is equivalent to the IC substrate 100 described with reference to Figure 2 The IC substrate 100 described is comparable.

[0135] Figure 8 a to Figure 8 f shows a method of manufacturing an IC substrate 100 according to another exemplary embodiment of the present invention.

[0136] Figure 8 a: Provide a temporary carrier 170 on which the bridging element 120 is disposed / formed. The first bridging terminal 121a and the second bridging terminal 121b are oriented towards the temporary carrier 170 and are in direct physical contact with the temporary carrier 170. The terminals 121a and 121b are electrically interconnected via electrical interconnections 125 located in the dielectric protection material 122. The bridging element 120 is placed in a cavity 126 of another core layer structure 118 (e.g., prepreg), which is also disposed on the temporary carrier 170. A plurality of hourglass-shaped vias 106 are formed through the other core layer structure 118. In addition, other components 109 are embedded in the other core layer structure 118.

[0137] Figure 8 b: Set the reinforced fiberless dielectric material 110 (in an uncured form) on top of the bridging element 120 and the other core layer structure 118. The reinforced fiberless dielectric material 110 fills the portion of the cavity 126 not occupied by the bridging element 120, thereby encapsulating the bridging element 120.

[0138] Figure 8 c and d: Remove the encapsulated bridging element 120 and the other core layer structure 118 from the temporary carrier 170 (and in this example, the encapsulated bridging element 120 and the other core layer structure 118 are flipped) and cover (laminate) them with an upper dielectric layer structure 115 disposed on top of the terminals 121a, 121b, and the plurality of hourglass-shaped vias 116. On the upper main surface, the fiberless dielectric material 110 is flush with the first bridging terminal 121a and the second bridging terminal 121b of the bridging element 120.

[0139] Figure 8e: The first bridging terminal 121a is electrically connected to the second bridging terminal 121b by a plurality of bridging element vias 123 passing through the upper dielectric layer structure 115. In addition, the vias 105 are electrically connected by a plurality of upper dielectric layer vias 116 passing through the upper dielectric layer structure 115 respectively.

[0140] Figure 8 f: A redistribution layer structure 130 is formed at the bottom of the IC substrate 100. The redistribution layer structure 130 includes a plurality of traces 131 and vias 133 located in a dielectric material 135 (similar to the dielectric protection material 122). The redistribution layer structure 130 is directly located below the enhanced fiberless dielectric material 110 and the additional core layer structure 118. The final IC substrate 100 is equivalent to the IC substrate 100 described with reference to Figure 4 the IC substrate 100 described.

[0141] Reference Numeral

[0142] 100 IC substrate

[0143] 101 First major surface

[0144] 102 Second major surface

[0145] 103 Core layer structure

[0146] 105 Additional electrical interconnection part, via

[0147] 106 Hourglass-shaped via

[0148] 108 Additional component

[0149] 109 Embedded component

[0150] 110 Enhanced fiberless dielectric material

[0151] 115 Upper dielectric layer structure

[0152] 116 Upper dielectric layer via

[0153] 118 Additional core layer structure, prepreg

[0154] 120 Bridging element

[0155] 121a First bridging terminal

[0156] 121b Second bridging terminal

[0157] 122 Dielectric protection material

[0158] 123 Bridging element via

[0159] 125 Electrical interconnection part

[0160] 126 cavities

[0161] 130 Redistribution layer structure, RDL

[0162] 131 RDL pad

[0163] 132 RDL solder ball

[0164] 133 RDL via

[0165] 135 RDL dielectric material

[0166] 136 Additional RDL dielectric material, fiberless material enhancement

[0167] 140a First component

[0168] 140b Second component

[0169] 141 Component terminal

[0170] 142 Component solder ball

[0171] 143 Component bridging terminal

[0172] 144 Component bridging solder ball

[0173] 150 IC substrate layout structure

[0174] 170 Temporary carrier

[0175] 200 Electronic component

[0176] 250 Component carrier.

Claims

1. An integrated circuit IC substrate (100), the integrated circuit IC substrate (100) comprises: a reinforced fiberless dielectric material (110); a bridging element (120), the bridging element (120) comprising: at least two conductive terminals (121a, 121b); an electrical interconnect portion (125) that electrically connects the at least two conductive terminals (121a, 121b); and a dielectric protection material (122) that encapsulates the electrical interconnect portion (125), wherein the bridging element (120) is embedded in the reinforced fiberless dielectric material (110) such that at least two components (140a, 140b) can be electrically connected to the at least two conductive terminals (121a, 121b) when surface-mounted to a first major surface (101) of the IC substrate (100), in particular, at least two of the components (140a, 140b) are active components and / or passive components; and a redistribution layer RDL structure (130) disposed at a second major surface (102) of the IC substrate (100) opposite the first major surface (101), and the redistribution layer RDL structure (130) can be electrically connected to at least two of the components (140a, 140b) via additional electrical interconnect portions (105).

2. The IC substrate (100) according to claim 1, wherein, the reinforced fiberless dielectric material (110) is reinforced by spherical materials, in particular, the reinforced fiberless dielectric material (110) is reinforced by glass spheres or carbon spheres, and more particularly wherein the dielectric material (100) comprises Ajinomoto Build-up Film ABF.

3. The IC substrate (100) according to claim 1 or 2, wherein, the bridging element (120) does not contain silicon, in particular, except for the embedded component (109), the IC substrate (100) itself does not contain silicon.

4. The IC substrate (100) according to any one of the preceding claims, wherein, the dielectric protection material (122) is an organic material, in particular, the dielectric protection material (122) is different from the reinforced fiberless dielectric material (110), more particularly wherein the dielectric protection material (122) comprises a non-reinforced resin, more particularly wherein the dielectric protection material (122) comprises at least one of a photosensitive dielectric PID material and polyimide.

5. The IC substrate (100) according to any one of the preceding claims, the IC substrate (100) further comprises: a core layer structure (103), the bridging element (120) being at least partially embedded in the core layer structure (103), in particular, wherein the dielectric material (110) forms the core layer structure (103), and / or Wherein, the dielectric material (110) is disposed in the core layer structure (103), in particular, the dielectric material (110) is disposed in the fiber-reinforced dielectric material (118), and / or Wherein, the additional electrical interconnections (105) are configured as a plurality of vias that at least partially extend vertically through the IC substrate (100), and the plurality of vias can be electrically connected to the components (140a, 140b) and / or the redistribution layer structure (130). In particular, wherein the bridging element (120) is arranged between the plurality of vias (105) in the horizontal directions (x, y).

6. The IC substrate (100) according to claim 5, Wherein, The thickness of the core layer structure (103) is greater than the thickness of the bridging element (120).

7. The IC substrate (100) according to any one of the preceding claims, the IC substrate (100) further Comprises: An upper dielectric layer structure (115) that is located on top of the bridging element (120) and on top of the fiberless reinforced dielectric material (110), wherein in particular, the upper dielectric layer structure (115) comprises a material different from the fiberless reinforced dielectric material (110). In particular, wherein The upper dielectric layer structure (115) comprises a plurality of upper dielectric layer structure vias (116) that extend vertically through the upper dielectric layer structure (115), and the plurality of upper dielectric layer structure vias (116) can be electrically connected to the components (140a, 140b) and / or the plurality of upper dielectric layer structure vias (116) are electrically connected to the additional electrical interconnections (105).

8. The IC substrate (100) according to any one of the preceding claims, Wherein, The redistribution layer structure (103) comprises an RDL dielectric material (136) different from the dielectric material (110), in particular, the redistribution layer structure (103) comprises a fiber-reinforced dielectric material (135).

9. An IC substrate arrangement (150), the IC substrate arrangement (150) Comprises: The IC substrate (100) according to any one of the preceding claims; And At least two of the components (140a, 140b) that are surface-mounted to the first major surface (101); Wherein, a first component (140a) is electrically connected to a first terminal (121a) of the bridging element (120), and Wherein, a second component (140b) is electrically connected to a second terminal (121b) of the bridging element (120), Such that: at least two of the components (140a, 140b) are electrically interconnected by the bridging element (120).

10. An electronic assembly (200), the electronic assembly (200) Comprises: IC substrate (100) according to any one of claims 1 to 8; or IC substrate arrangement structure (150) according to claim 9; and a component carrier (250), in particular, the component carrier (250) is a printed circuit board or another IC substrate, wherein the IC substrate (100) or the IC substrate arrangement structure (150) is surface-mounted to the component carrier (250).

11. A method of manufacturing an integrated circuit IC substrate (100), the method comprising: providing a bridging element (120) comprising at least two conductive terminals (121a, 121b), an electrical interconnect portion (125) electrically interconnecting the at least two conductive terminals (121a, 121b), and a dielectric protective material (122) encapsulating the electrical interconnect portion (125); at least partially embedding the bridging element (120) in a reinforced fiberless dielectric material (110) such that at least two components (140a, 140b) can be electrically connected to the at least two conductive terminals (121a, 121b) when surface-mounted to a first major surface (101) of the IC substrate (100); and forming a redistribution layer structure (130) at a second major surface (102) of the IC substrate (100) opposite the first major surface (101), and the redistribution layer structure (130) can be electrically connected to at least two of the components (140a, 140b).

12. The method according to claim 11, wherein providing the bridging element (120) further comprises: placing the bridging element (120) on a temporary carrier (170), in particular, the bridging element has a terminal major surface at which the terminals (121a, 121b) are exposed.

13. The method according to claim 11 or 12, wherein embedding the bridging element (120) further comprises: laminating the dielectric material (110) on the bridging element (110), or placing the bridging element (120) in a cavity (126) of a core layer structure (103, 118) and encapsulating the bridging element (120) in the cavity (126) with the reinforced fiberless dielectric material (110).

14. The method according to any one of claims 11 to 13, the method further comprising: forming a plurality of additional electrical interconnect portions (105) through the reinforced fiberless dielectric material (110) and / or through the core layer structure (103, 118); and / or forming an upper dielectric layer structure (115) on top of the reinforced fiberless dielectric material (110), and in particular, forming a plurality of upper dielectric layer structure vias (116) through the upper dielectric layer structure (115).

15. Use of an organic bridging element (120) in a silicon-free IC substrate (100), wherein The organic bridging element (120) is embedded in the fiberless dielectric material (110) for reinforcement.

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