Data erasing method and device, computer device and storage medium

Abstract

The application discloses a data erasing method and device, computer equipment and a storage medium, and relates to the technical field of flash memories. The application comprises the following steps: since the cache idle rate can reflect the load condition, the command idle duration can reflect the storage task density, the data stored in the preset type of flash memory block is relatively important, and needs to be timely erased to reduce the risk of data damage, and the condition that the command idle duration is greater than the idle duration threshold means that the current storage task density is relatively low. Therefore, by comprehensively considering the above factors, when the command idle duration is greater than the idle duration threshold (determined in real time according to the cache idle rate) and the target flash memory block is not the preset type of flash memory block, the performance index value of the target flash memory block is acquired in real time, and a corresponding setting strategy is selected according to the performance index value, so that different erasing modes are set for different flash memory blocks. In this way, the erasing operation is dynamically adjusted by combining various factors to adjust the erasing mode of the flash memory block, and the flexibility is relatively high.

Description

Technical Field

[0001] This application relates to the field of flash memory technology, and in particular to data erasure methods, apparatus, computer equipment and storage media. Background Technology

[0002] In the field of flash memory technology, when erasing data stored in a flash memory block, a voltage is generally applied to all the memory cells in the flash memory block to migrate electrons in the floating gate of the memory cell to the substrate, thereby releasing the electrons originally stored in the floating gate and completing the erasure operation.

[0003] However, the current method uses a fixed erasure mode (i.e., a fixed erasure voltage and erasure duration) to perform the erasure operation, which has low flexibility. Summary of the Invention

[0004] This application provides data erasure methods, apparatus, computer equipment, storage media, and program products to at least address the problem of low flexibility in erasure operations.

[0005] This application provides a data erasure method, including:

[0006] Get the command idle time, cache idle rate, and the flag of at least one flash block included in the flash memory;

[0007] Based on the cache idle rate, obtain the idle duration threshold that matches the cache idle rate;

[0008] When it is determined that the idle time of the command is greater than the idle time threshold, and it is determined that the target flash block is not marked as a preset type according to the marking of the target flash block, the performance index value of the target flash block is obtained, wherein the target flash block is any one of at least one flash block;

[0009] Select the setting strategy corresponding to the erase mode of the target flash memory block based on the number of performance index values ​​of the target flash memory block;

[0010] Set the erase mode for the target flash memory block according to the configuration policy;

[0011] Based on the erase mode of the target flash memory block, perform the data erase operation corresponding to the erase mode on the target flash memory block.

[0012] This application also provides a data erasure device, comprising:

[0013] The acquisition module is used to acquire the command idle duration, cache idle rate, and the tags corresponding to at least one flash block included in the flash memory; based on the cache idle rate, acquire an idle duration threshold that matches the cache idle rate; when it is determined that the command idle duration is greater than the idle duration threshold, and based on the tag of the target flash block, it is determined that the target flash block is not tagged as a preset type, acquire the performance index value of the target flash block, wherein the target flash block is any one of at least one flash block;

[0014] The selection module is used to select the setting strategy corresponding to the erase mode of the target flash memory block based on the number of performance index values ​​of the target flash memory block;

[0015] The settings module is used to set the erase mode of the target flash memory block according to the settings policy;

[0016] The erase module is used to perform data erase operations on the target flash memory block according to the erase mode of the target flash memory block.

[0017] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above data erasure methods.

[0018] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described data erasure methods.

[0019] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described data erasure methods.

[0020] This application utilizes the cache idle rate to reflect the load on the device executing the solution and the command idle duration to reflect the current storage task density. Therefore, this solution obtains the command idle duration and cache idle rate for subsequent analysis. Furthermore, to enhance flexibility, this solution does not use a fixed idle duration threshold for comparison, but rather determines the corresponding idle duration threshold based on the cache idle rate. Since the data stored in the preset type of flash memory blocks is relatively important and needs to be erased promptly to reduce the risk of data corruption, and since a command idle duration exceeding the idle duration threshold indicates a low current storage task density, eliminating the need for rapid erasure, this solution, considering these factors, selects to acquire the performance index value of the target flash memory block in real time when the command idle duration exceeds the idle duration threshold and the target flash memory block is not of the preset type. Based on the performance index value, a corresponding setting strategy is selected, and then, according to the setting strategy, different erasure modes are set for different flash memory blocks for subsequent erasure operations. In this way, by dynamically adjusting the erase mode of the flash memory block in combination with various factors, the flexibility of the erase operation can be improved, allowing different erase modes to be used under different load conditions, which can improve flash memory lifespan, overall performance and user experience. Attached Figure Description

[0021] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a data erasure system provided in an embodiment of this application;

[0023] Figure 2 A flowchart illustrating a data erasure method provided in an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of another data erasure system provided in an embodiment of this application;

[0025] Figure 4 A flowchart illustrating another data erasure method provided in this application embodiment;

[0026] Figure 5 This is a schematic diagram of the data erasure device provided in the embodiments of this application;

[0027] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0029] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0030] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] The embodiments of this application can be implemented by a data erasure system, such as... Figure 1 As shown, the data erasure system may include flash memory and a flash memory controller. The flash memory may include at least one flash memory block, and each flash memory block may include at least one memory cell. The flash memory block is the basic unit for performing the erasure operation. During the erasure process, the flash memory controller may apply a 0V voltage to the control electrodes of all word lines (WL) of the flash memory block, and apply a constant high voltage (e.g., 20V) to the substrate. In this way, under the effect of tunneling, electrons in the floating gate of each memory cell migrate to the substrate, causing the electrons originally stored in the floating gate to be released, resulting in the threshold voltage of the memory cell decreasing to the erased state, thus achieving the purpose of clearing all the electrons in the memory cell.

[0032] Embodiments of this application provide a data erasure method, which can be executed by the aforementioned flash memory controller, such as... Figure 2 As shown, the data erasure method may include the following steps:

[0033] Step S201: Obtain the command idle time, cache idle rate, and the flags corresponding to at least one flash block included in the flash memory.

[0034] The flash controller can periodically acquire command idle time, cache idle rate, and the flags corresponding to at least one flash block included in the flash memory.

[0035] Obtaining the command idle time for the current period may include the following steps:

[0036] Step 1: Obtain the timestamps corresponding to the multiple write commands recorded in the current period.

[0037] Step 2: Calculate the idle time between two adjacent write commands based on their respective timestamps.

[0038] Step 3: Determine the average idle time based on each idle time period.

[0039] Step 4: Determine the average idle time as the command idle time.

[0040] Specifically, the flash controller records the timestamp of each received write command. During the current cycle's operation, the flash controller calculates the interval (idle time) between all adjacent write commands based on the timestamps of all written commands recorded in the current cycle. Then, the flash controller calculates the average idle time based on each idle time and determines the average idle time as the command idle time. The flash controller can monitor its own cache idle rate in real time and read the latest cache idle rate at the trigger time of the current cycle. Additionally, the flash controller can read the markers of each flash block recorded in the firmware. In this way, the flash controller obtains the command idle time, the cache idle rate, and the markers corresponding to at least one flash block included in the flash memory.

[0041] Step S202: Based on the cache idle rate, obtain the idle time threshold that matches the cache idle rate.

[0042] Specifically, the flash memory controller can determine the target preset cache idle rate range into which the cache idle rate falls based on multiple preset cache idle rate ranges and cache idle rates, and determine the idle time threshold corresponding to the target preset cache idle rate range as the target idle time threshold.

[0043] For example, multiple preset cache free rate ranges can include "greater than 80%", "50%-80%", and "less than 50%", with the corresponding idle duration thresholds decreasing from high to low. Since a higher cache free rate indicates a higher current load, the idle duration threshold can be increased to reduce the probability of command idle time exceeding the threshold. This allows for erasing of flash memory blocks with higher erase voltage and shorter erase duration, completing write operations as quickly as possible and reducing performance impact. Conversely, a lower cache free rate indicates a lower current load, so the idle duration threshold can be decreased to increase the probability of command idle time exceeding the threshold. This allows for different erase modes to be used on flash memory blocks based on their performance metrics, balancing the load and extending flash memory lifespan.

[0044] Step S203: When it is determined that the command idle time is greater than the idle time threshold, and it is determined that the target flash block is not marked as a preset type based on the target flash block's marking, the performance index value of the target flash block is obtained.

[0045] The target flash block refers to any one of at least one flash block. Performance metrics for the target flash block may include one or more performance metrics such as erase count, access frequency, and invalid data ratio. The preset type indicates that the data stored in the flash block is critical data, i.e., data considered highly important by the user, or data belonging to a specified type as determined by the storage software according to preset rules. The invalid data ratio refers to the proportion of invalid data to all data in the flash block. Invalid data refers to data that has been deleted, overwritten, or is corrupted; firmware typically marks this unwanted data.

[0046] Specifically, the flash memory controller can first determine whether the command idle time is greater than the idle time threshold. If so, it indicates that the current processing task density is low, and analysis operations can continue to be performed on each flash memory block to determine the priority. For each flash memory block, the flash memory controller can determine whether the data stored in the flash memory block is critical data based on the markings on the flash memory block. When the data stored in the flash memory block is determined to be critical data, the erase count and access frequency of the target flash memory block are read from the flash memory controller's memory, and the proportion of data marked as invalid in the flash memory block is determined.

[0047] Each time the flash memory controller performs an erase operation on a flash memory block, it increments the erase count for that block and records the block's identification information and erase count in its own memory. Furthermore, for each flash memory block, the controller can periodically count the access frequency (including read, write, and erase operations) and record the block's identification information and access frequency in its own memory. This allows the controller to directly read this data from memory during each cycle's erase mode setting process for subsequent priority determination.

[0048] In some optional implementations, when it is determined that the command idle time is greater than the idle time threshold, and it is determined that the target flash block has been marked as a preset type based on the marking of the target flash block, the erase mode of the target flash block is set to the first erase mode.

[0049] The first erase mode has the shortest erase duration among all erase modes, and the first erase mode has the highest erase voltage among all erase modes.

[0050] Specifically, when the flash controller determines that the command idle time is greater than the idle time threshold, it indicates that the flash controller is currently processing tasks at a low frequency. However, for the target flash block, since the data it stores is critical data, the target flash block can be erased first to reduce the risk of data corruption and improve erasure stability.

[0051] In some optional implementations, when the command idle time is determined to be greater than the idle time threshold, and the target flash memory block is determined to be marked as a preset type based on its markings, the priority of the target flash memory block is set to the highest priority. The flash memory controller can determine whether the priority of the target flash memory block in the current cycle is consistent with the priority in the previous cycle. If they are consistent, the erase operation continues in the current cycle according to the original erase mode. If they are inconsistent, the corresponding first erase mode is determined based on the highest priority, and then the erase operation is performed on the target flash memory block in the current cycle according to the first erase mode.

[0052] In some alternative implementations, when the flash controller determines that the command idle time is less than or equal to the idle time threshold, it indicates that the flash controller is currently processing tasks at a high frequency, that is, the data of the flash blocks needs to be erased in a short period of time. Therefore, the flash controller can set the erase mode of all flash blocks to the first erase mode described above.

[0053] Step S204: Select a setting strategy corresponding to the erase mode of the target flash memory block based on the number of performance index values ​​of the target flash memory block.

[0054] Specifically, when the target flash block has only one performance metric value, the selected setting strategy is to set the erase mode of the target flash block based on its performance metric value. Alternatively, when the target flash block has multiple performance metric values, the selected setting strategy is to set the erase mode of the target flash block based on both its performance metric value and cache free rate.

[0055] Step S205: Set the erase mode of the target flash memory block according to the setting strategy.

[0056] Each erase mode includes an erase duration and an erase voltage.

[0057] Scenario 1: When the target flash memory block has only one performance metric value, the erase mode of the target flash memory block is set according to the performance metric value. This may include the following steps:

[0058] Step 1: Based on the performance index value, determine the performance index value range that the performance index value falls into from multiple preset performance index value ranges.

[0059] Step two: Determine the priority of the target flash memory block as the priority of the performance index value that falls within the performance index value range.

[0060] When the performance metric is the invalid data ratio, the performance metric value is directly proportional to the priority; that is, the higher the invalid data ratio, the higher the priority, and the lower the invalid data ratio, the lower the priority. Since flash memory blocks with higher invalid data ratios complete the erase operation faster, setting higher priorities for flash memory blocks with higher invalid data ratios can improve the overall erase efficiency, which in turn can improve the overall read and write performance.

[0061] When the performance metric is access frequency, the performance metric value is directly proportional to the priority; that is, the higher the access frequency, the higher the priority, and the lower the access frequency, the lower the priority. Generally, flash memory blocks with high access frequency are called hot blocks, and flash memory blocks with low access frequency are called cold blocks. Since high-access-frequency blocks usually store "hot data," these types of flash memory blocks can be prioritized for erasure operations to optimize space utilization.

[0062] When the performance metric is the number of erases, the performance metric is directly proportional to the priority; that is, the more erases, the higher the priority, and the fewer erases, the lower the priority. Since blocks with more erases may be in worse physical condition or nearing the end of their lifespan, they should be prioritized for erasure and used while they are still usable.

[0063] Step 3: Set the erase mode corresponding to the priority of the target flash memory block to the erase mode of the target flash memory block.

[0064] Specifically, the flash memory controller can store a first mapping relationship between performance index value ranges and priorities, and a second mapping relationship between priorities and erase modes. The flash memory controller can determine which performance index range a performance index value falls into based on multiple preset performance index value ranges. Then, based on the performance index value range the performance index value falls into and the first mapping relationship, it determines the priority corresponding to that performance index value range and sets the priority corresponding to that performance index value range as the priority of the target flash memory block. Next, the flash memory controller can determine the erase mode corresponding to the target flash memory block based on its priority and the second mapping relationship. Finally, the erase mode corresponding to the priority of the target flash memory block can be set as the erase mode of the target flash memory block.

[0065] For example, the second mapping relationship can be shown in Table 1.

[0066] Table 1

[0067] Priority Erase mode First Mode1 second Mode2 third Mode3

[0068] For example, the specific settings for the erase mode can be shown in Table 2.

[0069] Table 2

[0070] Erase mode Erasure voltage Erasure time Mode1 20V 6ms Mode2 18V 8ms Mode3 16V 10ms

[0071] Scenario 2: When the target flash block has multiple performance metrics, the erase mode of the target flash block is set based on the performance metrics and cache free rate. This may include the following steps:

[0072] Step 1: Based on the cache idle rate, obtain the weight value of each performance metric corresponding to the cache idle rate.

[0073] Step 2: Determine the priority of the target flash memory block based on each performance metric value and its weight.

[0074] Step 3: Set the erase mode corresponding to the priority of the target flash memory block to the erase mode of the target flash memory block.

[0075] For example, when the performance metrics of the target flash memory block include the erase count, access frequency, and invalid data ratio mentioned above, step one may specifically include:

[0076] When the cache free rate is determined to be greater than a preset threshold, a first preset weight value is assigned to the erase count, and a second preset weight value is assigned to the access frequency and invalid data ratio, respectively, where the first preset weight value is less than the second preset weight value. Alternatively, when the cache free rate is determined to be less than or equal to a preset threshold, a third preset weight value is assigned to the erase count, and a fourth preset weight value is assigned to the access frequency and invalid data ratio, respectively, where the third preset weight value is greater than the fourth preset weight value. Since a low cache free rate indicates a high current load, assigning greater weights to the access frequency and invalid data ratio can quickly free up space to respond to a large number of write requests. Conversely, a high cache free rate indicates a low current load, and assigning a greater weight to the erase count can prioritize processing flash blocks with high erase counts, thereby reducing further wear and extending flash memory lifespan.

[0077] Step two above can specifically include the following two methods:

[0078] Method 1: Based on the target performance index value and the pre-acquired maximum and minimum performance index values ​​corresponding to the target performance index value, determine the normalized value corresponding to the target performance index value, where the target performance index value is any one of multiple performance index values ​​for the target flash memory block. Based on the normalized value and weight value corresponding to each performance index value, determine the performance score of the target flash memory block. Based on the performance score of the target flash memory block and the mapping relationship between the performance score range and priority, determine the priority of the target flash memory block.

[0079] Specifically, the flash memory controller can determine the maximum and minimum erase counts based on the erase counts of all flash memory blocks, the maximum and minimum access frequencies based on the access frequencies of all flash memory blocks, and the maximum and minimum invalid data ratios based on the invalid data ratios of all flash memory blocks. For the erase counts of the target flash memory block, the flash memory controller can calculate the difference between the maximum and minimum erase counts and determine the ratio of the target flash memory block's erase counts to this difference as a normalized value corresponding to the target flash memory block's erase counts. For the access frequencies of the target flash memory block, the flash memory controller can calculate the difference between the maximum and minimum access frequencies and determine the ratio of the target flash memory block's access frequencies to this difference as a normalized value corresponding to the target flash memory block's access frequencies. For the invalid data ratios of the target flash memory block, the flash memory controller can calculate the difference between the maximum and minimum invalid data ratios and determine the ratio of the target flash memory block's invalid data ratios to this difference as a normalized value corresponding to the target flash memory block's invalid data ratios.

[0080] After calculating the normalized value for each performance metric, the flash memory controller can calculate the product of each performance metric value and its corresponding weight value, and then sum all the products to obtain the performance score of the target flash memory block. The flash memory controller's memory can store the mapping relationship between performance score ranges and priorities. In this way, the flash memory controller can determine the priority of the target flash memory block based on the priority corresponding to the performance score falling within its range.

[0081] Method 2 involves determining the performance index range into which the target performance index value falls, based on the target performance index value and multiple preset performance index value ranges. The target performance index value is any one of the multiple performance index values ​​for the target flash memory block. The priority corresponding to the performance index value range into which the target performance index value falls is determined as the priority corresponding to the target performance index value. The priority of the target flash memory block is determined based on the priority and weight values ​​corresponding to each performance index value (for example, first determining a priority score based on the priority and weight values ​​corresponding to each performance index value, then determining the priority score range into which the priority score falls, and finally determining the priority corresponding to that priority score range as the priority of the target flash memory block). This method improves the efficiency of priority determination and reduces resource consumption.

[0082] After determining the priority of the target flash memory block, the flash memory controller can determine the corresponding erase mode based on the priority and the second mapping relationship. Finally, the erase mode corresponding to the priority of the target flash memory block can be set as the erase mode of the target flash memory block.

[0083] In some optional implementations, after determining the priority of the target flash memory block in the current cycle, the flash memory controller can determine whether the priority of the target flash memory block in the current cycle is consistent with the priority of the previous cycle. If they are consistent, there is no need to perform subsequent matching and switching of erase modes. If they are inconsistent, then the subsequent matching and switching of erase modes are performed. This saves resources.

[0084] Step S206: Based on the erase mode of the target flash memory block, perform a data erase operation corresponding to the erase mode on the target flash memory block.

[0085] Specifically, in the current cycle, the flash memory controller can apply voltage to the target flash memory block according to the erase duration and erase voltage included in the erase mode of the target flash memory block, so as to complete the erase operation of the target flash memory block.

[0086] In some optional implementations, when the cache free rate is detected to be less than a preset free rate threshold, the erase mode of each flash block is set to the first erase mode.

[0087] Specifically, if the flash memory controller detects that the cache free rate is less than the preset free rate threshold, it can set the erase mode of all flash memory blocks to the first erase mode to complete the erase operation as soon as possible and perform subsequent read and write operations.

[0088] The data erasure method provided in this application's embodiments uses the cache idle rate to reflect the load of the device executing the solution and the command idle duration to reflect the current storage task density. Therefore, this solution obtains the command idle duration and cache idle rate for subsequent analysis. Furthermore, to enhance flexibility, this solution does not use a fixed idle duration threshold for comparison, but rather determines the corresponding idle duration threshold based on the cache idle rate. Since the data stored in the preset type of flash memory blocks is relatively important and needs to be erased promptly to reduce the risk of data corruption, and since a command idle duration greater than the idle duration threshold indicates a low current storage task density, this solution comprehensively considers both points. When the command idle duration is greater than the idle duration threshold and the target flash memory block is not a preset type of flash memory block, the performance index value of the target flash memory block is obtained in real time. Based on the performance index value, a corresponding setting strategy is selected. Then, based on the setting strategy, different erasure modes are set for different flash memory blocks for subsequent erasure operations. In this way, by dynamically adjusting the erasure mode of the flash memory block by combining various factors, flexibility can be improved, allowing different erasure modes to be used in different situations, thereby improving overall performance and user experience. In addition, the fixed erase mode used in related technologies has a high erase voltage and a short erase time, which leads to a large loss of the insulating layer of the storage cells in the flash memory block, resulting in a low lifespan of the flash memory. However, this solution can use different erase modes for different flash memory blocks according to their performance, which can improve the lifespan of the flash memory.

[0089] The following example illustrates the data erasure method. Figure 3 As shown, the flash memory controller may specifically include multiple hardware modules such as an idle detection module, a priority setting module, an access counting module, an erase counting module, a data monitoring module, a cache management module, a mode selection module, and an erase execution module.

[0090] The idle detection module calculates the idle time between two consecutive write commands and determines the corresponding idle time threshold based on the obtained cache idle rate, then compares the command idle time with the idle time threshold. The erase counting module counts the number of erases for each flash block. The access counting module counts the access frequency for each flash block. The data monitoring module records the invalid data ratio for each flash block. The cache management module monitors the cache idle rate. The priority setting module determines the priority of each flash block based on whether it is marked as a preset type, and based on the number of erases, access frequency, and invalid data ratio, and establishes a priority queue. Elements in the priority queue can include the flash block's identification information, number of erases, access frequency, invalid data ratio, and priority. The mode selection module sets the erase mode for each flash block based on its priority. The erase execution module performs the erase operation corresponding to the erase mode for each flash block.

[0091] like Figure 4 As shown, the idle detection module can obtain the cache idle rate from the cache management module, and based on the cache idle rate, obtain the corresponding idle duration threshold and calculate the command idle duration. When it is determined that the command idle duration is less than or equal to the idle duration threshold, it can send a notification to the mode selection module. After receiving the notification, the mode selection module can choose to set all flash memory modules to the first erase mode (e.g., Mode1 in Table 1) to complete the erase operation as soon as possible for subsequent write operations. When it is determined that the command idle duration is greater than the idle duration threshold, it can send a notification to the priority setting module. After receiving the notification, the priority setting module can create a priority queue. The priority setting module can obtain the judgment result of whether each flash memory block is critical data from the data monitoring module. If the judgment result is yes, the priority of the flash memory block can be set to the highest priority (e.g., the first priority in Table 1). If the judgment result is no, the priority of each flash memory block can be further determined by combining the number of erases, access frequency, data invalidity ratio, and cache idle rate. The priority setting module can send the priority of each flash memory block to the mode selection module. In this way, the mode selection module can set the erase mode for each flash memory block based on its priority and the mapping relationship between priority and erase mode. The erase execution module can then perform the erase operation according to the set erase mode. Furthermore, when the priority of a flash memory block changes, the erase mode can be switched promptly, achieving dynamic erasure.

[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0093] Embodiments of this application also provide a data erasure device, such as... Figure 5 As shown, it includes:

[0094] The acquisition module 510 is used to acquire the command idle duration, cache idle rate, and the tags corresponding to at least one flash block included in the flash memory; acquire an idle duration threshold that matches the cache idle rate; when it is determined that the command idle duration is greater than the idle duration threshold, and it is determined that the target flash block is not marked as a preset type according to the tag of the target flash block, acquire the performance index value of the target flash block, wherein the target flash block is any one of the at least one flash blocks;

[0095] Selection module 520 is used to select a setting strategy corresponding to the erase mode of the target flash memory block based on the number of performance index values ​​of the target flash memory block;

[0096] Setting module 530 is used to set the erase mode of the target flash memory block according to the setting strategy;

[0097] The erase module 540 is used to perform data erase operations on the target flash memory block according to the erase mode of the target flash memory block.

[0098] In some optional implementations, when the target flash block has only one performance metric value, the selected setting strategy is to set the erase mode of the target flash block based on the performance metric value of the target flash block; or, when the target flash block has multiple performance metric values, the selected setting strategy is to set the erase mode of the target flash block based on the performance metric value of the target flash block and the cache free rate.

[0099] In some optional implementations, when the performance metric value of the target flash memory block includes one, the setting module 530 is specifically used for:

[0100] Based on the performance index value, determine the performance index value range that the performance index value falls into from multiple preset performance index value ranges;

[0101] The priority of the target flash memory block is determined by the priority of the performance index value that falls into the performance index value range;

[0102] Set the erase mode corresponding to the priority of the target flash block to the erase mode of the target flash block.

[0103] In some optional implementations, when the performance metric values ​​of the target flash memory block include multiple values; the setting module 530 is specifically used for:

[0104] Based on the cache free rate, obtain the weight value of each performance metric value corresponding to the cache free rate;

[0105] The priority of the target flash memory block is determined based on each performance metric value and its weight.

[0106] Set the erase mode corresponding to the priority of the target flash block to the erase mode of the target flash block.

[0107] In some optional implementations, the performance metrics of the target flash memory block include erase count, access frequency, and invalid data ratio; the setting module 530 is specifically used for:

[0108] When it is determined that the cache free rate is greater than the preset threshold, the first preset weight value is determined as the weight value of the number of erases, and the second preset weight value is determined as the weight value of the access frequency and the weight value of the invalid data ratio, respectively, wherein the first preset weight value is less than the second preset weight value;

[0109] or,

[0110] When the cache free rate is determined to be less than or equal to a preset threshold, the third preset weight value is determined as the weight value of the number of erases, and the fourth preset weight value is determined as the weight value of the access frequency and the weight value of the invalid data ratio, respectively. The third preset weight value is greater than the fourth preset weight value.

[0111] In some alternative implementations, the setting module 530 is specifically used for:

[0112] Based on the target performance index value, and the pre-acquired maximum and minimum performance index values ​​corresponding to the target performance index value, determine the normalized value corresponding to the target performance index value, wherein the target performance index value is any one of the multiple performance index values ​​of the target flash memory block.

[0113] The performance score of the target flash memory block is determined based on the normalized value and weight value corresponding to each performance metric value.

[0114] The priority of the target flash memory block is determined based on its performance score and the mapping relationship between the performance score range and the priority.

[0115] In some optional implementations, each erasure mode includes an erasure duration and an erasure voltage; the setting module 530 is also used for:

[0116] When the idle time of the command is determined to be less than or equal to the idle time threshold, and the target flash memory block is determined to be marked as a preset type according to the marking of the target flash memory block, the erase mode of the target flash memory block is set to the first erase mode. The erase time included in the first erase mode is the shortest among the erase times included in all erase modes, and the erase voltage included in the first erase mode is the highest among the erase voltages included in all erase modes.

[0117] For a description of the features in the embodiment corresponding to the data erasure device, please refer to the relevant description of the embodiment corresponding to the data erasure method, which will not be repeated here.

[0118] Embodiments of this application also provide an electronic device, such as... Figure 6 As shown, it includes a processor 10 and a memory 20, in which a computer program is stored. The processor 10 is configured to run the computer program to perform the steps in any of the above-described data erasure method embodiments.

[0119] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described data erasure method embodiments when running.

[0120] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0121] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described data erasure method embodiments.

[0122] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described data erasure method embodiments.

[0123] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0124] The foregoing has provided a detailed description of a data erasure method, apparatus, computer device, storage medium, and program product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data erasure method, characterized in that, include: Get the command idle time, cache idle rate, and the flag of at least one flash block included in the flash memory; Based on the cache idle rate, obtain an idle duration threshold that matches the cache idle rate; When it is determined that the idle time of the command is less than or equal to the idle time threshold, and the target flash memory block is marked as a preset type according to the marking of the target flash memory block, the erase mode of the target flash memory block is set to the first erase mode, wherein the erase time included in the first erase mode is the shortest among the erase times included in all erase modes, and the erase voltage included in the first erase mode is the highest among the erase voltages included in all erase modes; When it is determined that the idle time of the command is greater than the idle time threshold, and it is determined that the target flash block is not marked as the preset type according to the marking of the target flash block, the performance index value of the target flash block is obtained, wherein the target flash block is any one of at least one of the flash blocks; Based on the number of performance index values ​​of the target flash memory block, select a setting strategy corresponding to the erase mode of the target flash memory block; According to the setting strategy, set the erase mode of the target flash memory block; According to the erase mode of the target flash memory block, perform a data erase operation on the target flash memory block corresponding to the erase mode.

2. The data erasure method according to claim 1, characterized in that, When the target flash block has only one performance metric value, the selected setting strategy is to set the erase mode of the target flash block according to the performance metric value of the target flash block; or, when the target flash block has multiple performance metric values, the selected setting strategy is to set the erase mode of the target flash block according to the performance metric value of the target flash block and the cache free rate.

3. The data erasure method according to claim 2, characterized in that, When the performance metric value of the target flash memory block includes one, setting the erase mode of the target flash memory block according to the setting strategy includes: Based on the performance index value, determine the performance index value range into which the performance index value falls within a plurality of preset performance index value ranges; The priority corresponding to the performance index value range that the performance index value falls into is determined as the priority of the target flash memory block; Set the erase mode corresponding to the priority of the target flash memory block as the erase mode of the target flash memory block.

4. The data erasure method according to claim 2, characterized in that, When the performance metric values ​​of the target flash memory block include multiple values; setting the erase mode of the target flash memory block according to the setting strategy includes: Based on the cache idle rate, obtain the weight value of each of the performance metrics corresponding to the cache idle rate; The priority of the target flash memory block is determined based on each of the performance metric values ​​and the weight value of each of the performance metric values. Set the erase mode corresponding to the priority of the target flash memory block as the erase mode of the target flash memory block.

5. The data erasure method according to claim 4, characterized in that, The performance metrics of the target flash memory block include erase count, access frequency, and invalid data ratio; obtaining the weight value of each performance metric corresponding to the cache free rate based on the cache free rate includes: When it is determined that the cache free rate is greater than a preset threshold, the first preset weight value is determined as the weight value of the number of erases, and the second preset weight value is determined as the weight value of the access frequency and the weight value of the invalid data ratio, respectively, wherein the first preset weight value is less than the second preset weight value. or, When it is determined that the cache idle rate is less than or equal to the preset threshold, the third preset weight value is determined as the weight value of the number of erases, and the fourth preset weight value is determined as the weight value of the access frequency and the weight value of the invalid data ratio, respectively, wherein the third preset weight value is greater than the fourth preset weight value.

6. The data erasure method according to claim 4, characterized in that, Determining the priority of the target flash memory block based on each performance metric value and its weight value includes: Based on the target performance index value, and the pre-acquired maximum and minimum performance index values ​​corresponding to the target performance index value, a normalized value corresponding to the target performance index value is determined, wherein the target performance index value is any one of the multiple performance index values ​​of the target flash memory block. The performance score of the target flash memory block is determined based on the normalized value and weight value corresponding to each of the performance index values; The priority of the target flash memory block is determined based on its performance score and the mapping relationship between the performance score range and the priority.

7. A data erasure device, characterized in that, include: The acquisition module is used to acquire the command idle time, cache idle rate, and the flags corresponding to at least one flash block included in the flash memory; Based on the cache idle rate, an idle duration threshold matching the cache idle rate is obtained; when it is determined that the command idle duration is less than or equal to the idle duration threshold, and based on the marking of the target flash block, it is determined that the target flash block has been marked as a preset type, the erase mode of the target flash block is set to a first erase mode, wherein the erase duration included in the first erase mode is the shortest among the erase durations included in all erase modes, and the erase voltage included in the first erase mode is the highest among the erase voltages included in all erase modes; when it is determined that the command idle duration is greater than the idle duration threshold, and based on the marking of the target flash block, it is determined that the target flash block has not been marked as the preset type, the performance index value of the target flash block is obtained, wherein the target flash block is any one of at least one of the flash blocks; The selection module is used to select a setting strategy corresponding to the erase mode of the target flash memory block based on the number of performance index values ​​of the target flash memory block; The setting module is used to set the erase mode of the target flash memory block according to the setting strategy; The erase module is used to perform a data erase operation on the target flash memory block according to the erase mode of the target flash memory block.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the data erasure method as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data erasure method as described in any one of claims 1 to 6.

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