Method and device for acquiring data in chip, electronic equipment and storage medium
By receiving data acquisition instructions in the chip and triggering interrupt instructions, the target CPU core enters the highest privilege level, thereby obtaining chip data, solving the debugging inconvenience in the existing technology that requires physical contact, and achieving more convenient data acquisition and debugging.
Patent Information
- Application Number
- CN202510191103.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-06-17
AI Technical Summary
Existing debugging tools need to physically contact the debugged chip when obtaining chip data, resulting in inconvenient debugging.
By receiving data acquisition instructions, parsing the instructions to determine the CPU core where the target data is located, and triggering an interrupt instruction, gradually causing the target CPU core to enter the highest privilege level, thereby obtaining the target data in this state.
The target data in the chip can be obtained without physical connection, simplifying the debugging process of the chip CPU core.
Smart Images
Figure CN120162290A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular, to a method, apparatus, electronic device, and storage medium for obtaining data in a chip. Background Art
[0002] Debugging is an important process in the software and hardware life cycle. According to different focuses, debugging tools can be roughly divided into software-oriented debugging tools and hardware-oriented debugging tools. For software debugging tools, the operating system generally provides debugging capabilities. Hardware in-circuit debugging tools are mainly used for bare-metal debugging.
[0003] When each debugging tool debugs a chip, it needs to read the data in the chip. Existing debugging tools need to physically contact the chip being debugged when obtaining data, which brings inconvenience to debugging. Summary of the Invention
[0004] Embodiments of the present disclosure provide a method, apparatus, electronic device, and storage medium for obtaining data in a chip.
[0005] In a first aspect, embodiments of the present disclosure provide a method for obtaining data in a chip, including: in response to receiving a data acquisition instruction, parsing the data acquisition instruction to determine a target CPU core in the chip where target data is located, and triggering a first interrupt instruction; triggering a second interrupt instruction according to the first interrupt instruction; sending a fast interrupt request to the target CPU core according to the second interrupt instruction to make the target CPU core enter the highest privilege level; and obtaining the target data in the target CPU core in the highest privilege level state according to the data acquisition instruction.
[0006] In a second aspect, embodiments of the present disclosure provide an apparatus for obtaining data in a chip, including: a first interrupt unit configured to, in response to receiving a data acquisition instruction, parse the data acquisition instruction to determine a target CPU core in the chip where target data is located, and trigger a first interrupt instruction; a second interrupt unit configured to trigger a second interrupt instruction according to the first interrupt instruction; a privilege level change unit configured to send a fast interrupt request to the target CPU core according to the second interrupt instruction to make the target CPU core enter the highest privilege level; and a data acquisition unit configured to obtain the target data in the target CPU core in the highest privilege level state according to the data acquisition instruction.
[0007] In a third aspect, embodiments of the present disclosure provide an electronic device, including a memory, a processor, a bus, and a computer program stored on the memory and executable on the processor, where the processor implements the method for obtaining data in a chip as described in the first aspect when executing the computer program.
[0008] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the method for obtaining data in a chip as described in the first aspect.
[0009] By applying the technical solution of the present disclosure, when a data acquisition instruction is received through a serial port, the target CPU core where the target data in the chip is located can be determined, and at the same time, a first interrupt instruction is triggered. A second interrupt instruction is triggered according to the first interrupt instruction. Further, a fast interrupt request is sent to the target CPU core according to the second interrupt instruction, so that the target CPU core enters the highest privilege level, thereby enabling the target data in the target CPU core to be obtained in the highest privilege level state. Through the technical solution of the present disclosure, it is possible to obtain the data in the target CPU core of the chip without physically connecting to the chip, which is more convenient for debugging the CPU core in the chip.
[0010] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them:
[0012] Figure 1 FIG. is an exemplary system architecture diagram to which an embodiment of the method for obtaining data in a chip according to the present disclosure can be applied;
[0013] Figure 2 FIG. is a flowchart of an embodiment of the method for obtaining data in a chip according to the present disclosure;
[0014] Figure 3 FIG. is a flowchart of another embodiment of the method for obtaining data in a chip according to the present disclosure;
[0015] Figure 4 FIG. is a schematic diagram of signal flow in the method for obtaining data in a chip according to the present disclosure;
[0016] Figure 5 FIG. is a schematic structural diagram of an embodiment of the device for obtaining data in a chip according to the present disclosure;
[0017] Figure 6 FIG. is a schematic structural diagram of an embodiment of an electronic device according to the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0018] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs.
[0019] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0020] In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other.
[0021] To make the technical solutions and advantages of the present disclosure more clear and understandable, the following further describes the present disclosure in detail with reference to the accompanying drawings and specific embodiments.
[0022] Figure 1 An exemplary system architecture 100 showing an embodiment of a method for obtaining data in a chip or an apparatus for obtaining data in a chip to which the present disclosure can be applied is shown.
[0023] As Figure 1 shown, the system architecture 100 may include a terminal device 101, a server 102, a network 103, and a target chip 104. The network 103 is used to provide a medium for communication links between the terminal device 101, the server 102, and the target chip 104. The network 103 may include various connection types, such as wired, wireless communication links, or fiber optic cables, etc.
[0024] A user can use the terminal device 101 to interact with the server 102 or the target chip 104 through the network 103 to receive or send messages, etc. Various communication client applications, such as chip debugging applications, etc., may be installed on the terminal device 101. The user can send a data acquisition instruction to the server 102 or the target chip 104 through the terminal device 101.
[0025] The terminal device 101 can be hardware or software. When the terminal device 101 is hardware, it can be various electronic devices, including but not limited to smart phones, tablet computers, laptop portable computers, and desktop computers, etc. When the terminal device 101 is software, it can be installed in the above-listed electronic devices. It can be implemented as multiple software or software modules (for example, used to provide distributed services), or can be implemented as a single software or software module. No specific limitation is made herein.
[0026] Server 102 can be a server that provides various services, such as a background server that provides debugging support for target chip 104. The background server can be communicatively connected to terminal device 101 through network 103 via a network interface, and can be communicatively connected to target chip 104 via a serial port through a universal asynchronous receiver / transmitter.
[0027] It should be noted that server 102 can be hardware or software. When server 102 is hardware, it can be implemented as a distributed server cluster composed of multiple servers, or as a single server. When server 102 is software, it can be implemented as multiple software or software modules (such as those used to provide distributed services), or as a single software or software module. Specific limitations are not made here.
[0028] Target chip 104 can be a chip for which data is to be acquired or a chip to be debugged. Target chip 104 can be various types of chips, such as an ARM chip, an FPGA chip, etc. Target chip 104 can include multiple CPU cores, and each CPU core can work independently.
[0029] It should be noted that the method for acquiring data in the chip provided by the embodiments of the present disclosure is generally executed by target chip 104. Correspondingly, the device for acquiring data in the chip is generally arranged in target chip 104.
[0030] It should be understood that Figure 1 the numbers of the terminal device, server, network, and target chip in
[0031] Figure 2 are merely illustrative. According to the implementation requirements, there can be any number of terminal devices, servers, networks, and target chips. In some specific applications, the server and network may not be included in the above system architecture, so that the terminal device can be connected to the target chip through a serial port.
[0032] As Figure 2 shown, the method for acquiring data in the chip of this embodiment can include the following steps:
[0033] Step 201, in response to receiving a data acquisition instruction, determine the target CPU core in the chip where the target data is located, and trigger a first interrupt instruction.
[0034] In this embodiment, the execution entity of the method for acquiring data in the chip (such as Figure 1 the target chip 104 shown) can receive a data acquisition instruction. This data acquisition instruction can be issued by a user through a terminal device (such as Figure 1Sent by the terminal device 101 shown, or can be forwarded to the target chip by the server (such as Figure 1 the server 102 shown). Specifically, the target chip can receive the above data acquisition instruction through the serial port, so that there is no need for a debugging tool to be physically connected to the target chip.
[0035] The above data acquisition instruction can include the location information of the target data, the corresponding CPU core information, the interrupt number, etc. The above location information can include physical address, virtual address, register address, etc. The interrupt number can represent the identifier of the first interrupt instruction. The serial port interrupt handling function can be called according to the interrupt number to trigger the first interrupt instruction.
[0036] After receiving the data acquisition instruction, the data acquisition instruction can be parsed to determine the target CPU core in the chip where the target data is located. At the same time, the first interrupt instruction can be triggered. Here, the first interrupt instruction can be an RX interrupt. The first interrupt instruction can be triggered by the interrupt handling function on the system-level chip.
[0037] Step 202, trigger a second interrupt instruction according to the first interrupt instruction.
[0038] After triggering the first interrupt instruction, the second interrupt instruction can be triggered. Here, the second interrupt instruction can be an SPI interrupt. After the system-level chip enters the interrupt state by triggering the first interrupt instruction, the second interrupt instruction can be triggered. At the same time, the second interrupt instruction is sent to the Interrupt Controller (Generic Interrupt Controller, GIC) in the chip.
[0039] Step 203, send a fast interrupt request to the target CPU core according to the second interrupt instruction, so that the target CPU core enters the highest privilege level.
[0040] In this embodiment, after triggering the second interrupt instruction, a Fast Interrupt Request (FIQ) can be sent to the target CPU core. In an ARM chip, the FIQ mode is one of the privileged modes and also belongs to the exception mode category. It is used for high-speed data transfer or channel processing and enters when a fast interrupt request (FIQ) is triggered. After sending the fast interrupt request to the target CPU core, the target CPU core enters the highest privilege level. In the ARM architecture, the exception levels increase gradually from 0 to 3, and the permissions also increase accordingly. EL0 is the lowest level and is used for application programs in the user space; EL1 is used for the operating system kernel mode; EL2 supports virtualization; and EL3 is used for the highest-level security and system services. When an exception occurs at a lower level, it may be passed to a higher level for processing, and the execution state of the higher level is used to handle the exception. Here, the highest privilege level is the EL3 level. Making the target CPU core enter the highest privilege level can handle errors generated at any level, so that error data at any level can be read.
[0041] Step 204, according to the data acquisition instruction, acquire the target data in the target CPU core in the highest privilege level state.
[0042] After the target CPU core enters the highest privilege level, the target data in the target CPU core can be acquired in the highest privilege level state according to the data acquisition instruction. Specifically, the corresponding target data can be read according to the location information included in the data acquisition instruction.
[0043] The method for acquiring data in the chip provided by the above embodiments of the present disclosure can determine the target CPU core where the target data is located in the chip when receiving a data acquisition instruction through a serial port, and at the same time trigger the first interrupt instruction. The second interrupt instruction is triggered according to the first interrupt instruction. Further, a fast interrupt request is sent to the target CPU core according to the second interrupt instruction, so that the target CPU core enters the highest privilege level, so that the target data in the target CPU core can be acquired in the highest privilege level state. Through the technical solution of the present disclosure, it is possible to acquire the data in the target CPU core in the chip without physically connecting to the chip, which is more convenient for debugging the CPU core in the chip.
[0044] Continue to participate Figure 3 , which shows the flow 300 of another embodiment of the method for acquiring data in the chip according to the present disclosure. As Figure 3 shown, the method in this embodiment may include the following steps:
[0045] Step 301, in response to receiving a data acquisition instruction, parse the data acquisition instruction, determine the target CPU core where the target data is located in the chip, and trigger the first interrupt instruction.
[0046] Step 302: Trigger a second interrupt instruction according to the first interrupt instruction.
[0047] Step 303: In response to the target CPU core not being the currently working CPU core, interrupt the serial port of the currently working CPU core, bind the serial port to the target CPU core; according to the second interrupt instruction, send a fast interrupt request to the target CPU core to make the target CPU core enter the highest privilege level.
[0048] In this embodiment, before sending a data acquisition instruction to the chip, an initialization operation can be performed. The initialization operation here refers to setting each component in the chip with default parameters. For example, the serial port controller can be set, the RX interrupt function of the serial port can be registered into the interrupt vector table of EL3, and the RX interrupt of the serial port can be registered as a FIQ interrupt, so that the fast interrupt request can be routed to EL3 for interrupt processing.
[0049] Through the initialization settings, a default CPU core can be set. After receiving the data acquisition instruction, it can first be determined whether the default CPU core or the currently working CPU core is the same as the target CPU core. If they are the same, the fast interrupt request can be directly routed to the target CPU core. If they are not the same, the serial port first needs to be unbound from the default CPU core or the currently working CPU core and then bound to the target CPU core before the fast interrupt request can be routed to the target CPU core.
[0050] Step 304: Parse the data acquisition instruction to determine the address information of the target data; according to the address information, obtain the target data in the highest privilege level state.
[0051] In this embodiment, after the target CPU enters the highest privilege level, the address information in the data acquisition instruction can be parsed. The above address information can include virtual address, physical address, register address, etc. Then, according to the above address information, the target data in the above address information is accessed.
[0052] In some alternative implementation manners of this embodiment, if the address information is a physical address, the physical address can be mapped to a virtual address of the highest privilege level, so that the target CPU core can access the above virtual address in the highest privilege level state to obtain the target data.
[0053] In some alternative implementation manners of this embodiment, after the CPU obtains the target data through the above virtual address, the mapping between the physical address and the virtual address can be released to free the virtual address space.
[0054] In some alternative implementation manners of this embodiment, if the address information is a virtual address, the exception level (for example, EL2) corresponding to the virtual address may be determined by first parsing the data acquisition instruction. Then, the page table of the exception level is queried, and the physical address corresponding to the virtual address may be determined through this page table. Then, in the state of the highest privilege level (i.e., EL3), the physical address is mapped to a virtual address, and then the virtual address is accessed in the EL3 state to obtain the target data.
[0055] In some alternative implementation manners of this embodiment, if the address information is a register address, the target CPU core may be controlled to access the register according to the register address to obtain the target data.
[0056] Step 305: In response to determining that the target CPU core enters the highest privilege level, determine the return address before entering the highest privilege level; modify the return address; in response to determining that the acquisition of the target data is completed, exit the highest privilege level, trigger a panic event according to the modified return address, and output an error message.
[0057] In this embodiment, data may also be acquired in another way, that is, after the target CPU core enters the highest privilege level, the return address before entering the highest privilege level is determined. Modify the above return address so that an error occurs when the ERET instruction is executed at the highest privilege level to return to the original exception level, thereby causing the target CPU core to trigger a panic event, and thus output an error message (such as a vmcore file). Thus, the target data may be obtained through the above error message. In this way, the EL2 / EL1 call stack, registers, and memory data are not damaged, and no modification needs to be made to the EL2 / EL1 software. Specifically, the ERET instruction is used to return from an exception, especially to return to the previous execution context from an interrupt or trap handler. When modifying the return address, 1 may be added to the last bit of the return address, resulting in an unaligned access to the instruction. An unaligned access to an instruction means that when executing certain instructions, the address of the data is not set according to the alignment principle, causing the processor to be unable to correctly process the data when reading or writing the data, and an exception or error may be thrown.
[0058] In some alternative implementation manners of this embodiment, the user's permission may also be verified before acquiring the target data to ensure that a user with permission can acquire the target data. That is to say, corresponding permissions may be set for different users.
[0059] Combined Figure 4 , which shows a signal flow diagram of the method for acquiring data in the chip of the present disclosure. In Figure 4Among them, the chip may include the serial port of the system-on-chip, the GIC controller, and each CPU core. Among them, the serial port of the system-on-chip can receive data acquisition instructions from the outside, trigger an RX interrupt, and then send an SPI interrupt to the GIC controller. The GIC controller further triggers a fast interrupt request and sends it to the target CPU core, so as to realize the acquisition of data in the chip.
[0060] The method for acquiring data in the chip provided by the above embodiments of the present disclosure can trigger a fast interrupt to enter the EL3 state through the serial port, so as to obtain the access rights of EL2 / EL1 / EL0 and realize the acquisition of data at the EL2 / EL1 / EL0 level.
[0061] Further referring to Figure 5 , as an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a device for acquiring data in a chip. This device embodiment corresponds to Figure 2 the method embodiment shown, and this device can be specifically applied to various electronic devices.
[0062] As shown in Figure 5 , the device 500 for acquiring data in the chip in this embodiment includes: a first interrupt unit 501, a second interrupt unit 502, a privilege level change unit 503, and a data acquisition unit 504.
[0063] The first interrupt unit 501 is configured to, in response to receiving a data acquisition instruction, parse the data acquisition instruction, determine the target CPU core where the target data in the chip is located, and trigger a first interrupt instruction.
[0064] The second interrupt unit 502 is configured to trigger a second interrupt instruction according to the first interrupt instruction.
[0065] The privilege level change unit 503 is configured to send a fast interrupt request to the target CPU core according to the second interrupt instruction, so that the target CPU core enters the highest privilege level.
[0066] The data acquisition unit 504 is configured to acquire the target data in the target CPU core in the highest privilege level state according to the data acquisition instruction.
[0067] In addition, in the technical solution of this application, an electronic device is also proposed.
[0068] Figure 6 shows a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
[0069] As shown in Figure 6As shown, the electronic device may include a processor 601, a memory 602, a bus 603, and a computer program stored in the memory 602 and executable on the processor 601. Among them, the processor 601 and the memory 602 communicate with each other through the bus 603. When the processor 601 executes the computer program, the steps of the above method are implemented, for example, including: in response to receiving a data acquisition instruction, parsing the data acquisition instruction, determining the target CPU core where the target data is located in the chip, and triggering a first interrupt instruction; according to the first interrupt instruction, triggering a second interrupt instruction; according to the second interrupt instruction, sending a fast interrupt request to the target CPU core to make the target CPU core enter the highest privilege level; according to the data acquisition instruction, acquiring the target data in the target CPU core in the highest privilege level state.
[0070] In addition, in an embodiment of the present disclosure, a non-transitory computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented, for example, including: in response to receiving a data acquisition instruction, parsing the data acquisition instruction, determining the target CPU core where the target data is located in the chip, and triggering a first interrupt instruction; according to the first interrupt instruction, triggering a second interrupt instruction; according to the second interrupt instruction, sending a fast interrupt request to the target CPU core to make the target CPU core enter the highest privilege level; according to the data acquisition instruction, acquiring the target data in the target CPU core in the highest privilege level state.
[0071] In summary, in the technical solution of the present disclosure, when a data acquisition instruction is received through the serial port, the target CPU core where the target data is located in the chip can be determined, and at the same time, a first interrupt instruction is triggered. A second interrupt instruction is triggered according to the first interrupt instruction. Further, a fast interrupt request is sent to the target CPU core according to the second interrupt instruction to make the target CPU core enter the highest privilege level, so that the target data in the target CPU core can be acquired in the highest privilege level state. Through the technical solution of the present disclosure, it is possible to acquire the data in the target CPU core of the chip without physically connecting to the chip, which is more convenient for debugging the CPU core in the chip.
[0072] The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the scope of protection of the present disclosure.
Claims
1. A method for acquiring data in a chip, comprising: In response to receiving the data acquisition instruction, parsing the data acquisition instruction, determining the target CPU core where the target data is located in the chip, and triggering a first interrupt instruction; According to the first interrupt instruction, triggering a second interrupt instruction; According to the second interrupt instruction, a fast interrupt request is sent to the target CPU core to make the target CPU core enter the highest privilege level; According to the data acquisition instruction, the target data in the target CPU core is acquired in the highest privilege level state.
2. The method according to claim 1, wherein: The step of acquiring data in the target CPU core in a state of the highest privilege level according to the data acquisition instruction includes: Parsing the data acquisition instruction to determine the address information of the target data; The target data is acquired in a highest privilege level state according to the address information.
3. The method according to claim 1, wherein: The address information includes a physical address; as well as The step of acquiring the target data in a state of the highest privilege level according to the address information includes: Mapping the physical address to a virtual address of the highest privilege level; The target data is acquired by accessing the virtual address through the target CPU core.
4. The method according to claim 3, wherein: The method further comprises: After the target data is acquired, the address mapping is released to release the space corresponding to the virtual address.
5. The method according to claim 1, wherein: The address information includes an exception level and a virtual address; as well as The step of acquiring the target data in a state of the highest privilege level according to the address information includes: Converting the virtual address to a physical address corresponding to the exception level according to a page table corresponding to the exception level; According to the page table corresponding to the highest privilege level, the physical address corresponding to the exception level is mapped to the virtual address of the highest privilege level. The target data is acquired by the target CPU core through a virtual address of the highest privilege level.
6. The method according to claim 1, wherein: The step of sending a fast interrupt request to the target CPU core according to the second interrupt instruction so that the target CPU core enters the highest privilege level includes: In response to the target CPU core not being the currently working CPU core, interrupting the serial port of the currently working CPU core and binding the serial port to the target CPU core; According to the second interrupt instruction, a fast interrupt request is sent to the target CPU core, so that the target CPU core enters the highest privilege level.
7. The method according to claim 1, wherein: The method further comprises: In response to determining that the target CPU core enters the highest privilege level, determining a return address before entering the highest privilege level; modifying the return address; In response to determining that the acquisition of the target data is completed, the highest privilege level is exited, a panic event is triggered according to the modified return address, and an error message is output.
8. A device for acquiring data in a chip, comprising: A first interrupt unit is configured to, in response to receiving a data acquisition instruction, parse the data acquisition instruction, determine a target CPU core in the chip where the target data is located, and trigger a first interrupt instruction; A second interrupt unit is configured to trigger a second interrupt instruction according to the first interrupt instruction; a level changing unit, configured to send a fast interrupt request to the target CPU core according to the second interrupt instruction, so that the target CPU core enters the highest privilege level; The data acquisition unit is configured to acquire the target data in the target CPU core in a highest privilege level state according to the data acquisition instruction.
9. An electronic device comprising a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method for acquiring data in a chip as described in any one of claims 1 to 7 is implemented.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for acquiring data in a chip as described in any one of claims 1 to 7 is implemented.