Modular HIL cabinet design method and system based on public design

Abstract

The invention provides a modular HIL cabinet design method and system based on a public design, and relates to the field of HIL cabinet design, and the method comprises the steps: obtaining a functional domain of a to-be-designed HIL cabinet; the method comprises the following steps: performing independent function division and parameter design on a function domain of a cabinet by adopting a decoupling architecture based on a public design theory to form a modularized HIL cabinet initial design scheme; and based on the initial design scheme of the HIL cabinet, defining a dynamic hardware resource allocation mechanism, and based on a topological optimization algorithm, performing path planning on wiring of cables in the cabinet to obtain a final design scheme of the HIL cabinet. According to the invention, independent maintenance and upgrading of each functional module are realized, and the maintenance cost is reduced; different test requirements can be flexibly met through an extensible rack structure; and cable connection and electromagnetic interference design are optimized, the space utilization rate of the cabinet is improved, the complexity of the system is reduced, and the reliability of the system is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of HIL cabinet design, and particularly to a modular HIL cabinet design method and system based on axiomatic design. Background Art

[0002] In traditional testing technologies, system verification highly relies on physical prototypes or real physical environments (such as a whole vehicle, an aircraft), and it is necessary to complete the testing by repeatedly building experimental benches and adjusting working condition parameters, resulting in a long testing cycle, low efficiency, high costs, and it is difficult to cover extreme scenarios (such as high temperature, high pressure, fault injection).

[0003] Hardware-in-the-loop (HIL) testing technology constructs a semi-physical simulation closed-loop system, replaces some physical entities with real-time simulation models, solves the limitations of physical testing, significantly improves the testing safety, repeatability, and scenario coverage ability, and is widely applied in fields such as automotive electronics and aerospace; its core advantage lies in realizing the closed-loop verification of complex dynamic behaviors through the interaction between high-precision models and real hardware (such as controllers, sensors), and becoming a key supporting technology for the development of modern complex systems.

[0004] However, there are significant defects in the cabinet architecture design of existing HIL testing systems, restricting the further release of their technical potential: First, the problem of functional coupling is prominent: Hardware modules (such as IO boards, signal conditioning units), power supply systems, heat dissipation devices, etc. are highly integrated in a closed cabinet, resulting in difficult maintenance when a single module fails, and the cost increases sharply when hardware upgrades require overall replacement.

[0005] Second, the scalability is insufficient: In the case of limited channel numbers, when facing different test scenario requirements, traditional HIL cabinets need to stop the machine to replace software and hardware, resulting in insufficient scalability of the cabinets when facing multiple test requirements.

[0006] In addition, the cable distribution is unreasonable: Complex cable connections (signal cables, high-power cables, low-power cables) are cross-arranged in a limited space, the wiring is chaotic, the space utilization rate is low, and at the same time, it is easy to cause problems such as electromagnetic interference and uneven heat dissipation.

[0007] Therefore, existing traditional HIL cabinets have problems of high functional coupling, poor scalability, and unreasonable cable distribution. Summary of the Invention

[0008] To solve the above problems, the present disclosure proposes a modular HIL cabinet design method and system based on axiomatic design, which realizes the independent maintenance and upgrade of each functional module, reduces the maintenance cost; through an extensible rack structure, it can flexibly adapt to different test requirements; optimizes the cable connection and electromagnetic interference design, improves the utilization rate of the cabinet space, reduces the system complexity, and improves the reliability of the system.

[0009] According to some embodiments, the present disclosure adopts the following technical solutions: A modular HIL cabinet design method based on axiomatic design, comprising: Obtaining the functional domain of the HIL cabinet to be designed; Adopting a decoupled architecture based on axiomatic design theory to divide the independent functions of the functional domain of the cabinet and design the parameters, so as to form an initial design scheme of the modular HIL cabinet; Based on the initial design scheme of the HIL cabinet, defining a dynamic hardware resource allocation mechanism for allocating hardware resources for real-time computing functions, and based on a topology optimization algorithm, performing path planning on the wiring of the cables in the cabinet to obtain the final design scheme of the HIL cabinet.

[0010] According to some embodiments, the present disclosure adopts the following technical solutions: A modular HIL cabinet design system based on axiomatic design, comprising: A function acquisition module configured to: obtain the functional domain of the HIL cabinet to be designed; An initial design module configured to: adopt a decoupled architecture based on axiomatic design theory to divide the independent functions of the functional domain of the cabinet and design the parameters, so as to form an initial design scheme of the modular HIL cabinet; A final design module configured to: based on the initial design scheme of the HIL cabinet, define a dynamic hardware resource allocation mechanism for allocating hardware resources for real-time computing functions, and based on a topology optimization algorithm, perform path planning on the wiring of the cables in the cabinet to obtain the final design scheme of the HIL cabinet.

[0011] According to some embodiments, the present disclosure adopts the following technical solutions: A computer program product comprising a computer program, where when the computer program is executed by a processor, it implements the above-mentioned modular HIL cabinet design method based on axiomatic design.

[0012] According to some embodiments, the present disclosure adopts the following technical solutions: A non-transitory computer-readable storage medium for storing computer instructions, where when the computer instructions are executed by a processor, they implement the above-mentioned modular HIL cabinet design method based on axiomatic design.

[0013] According to some embodiments, the present disclosure adopts the following technical solutions: An electronic device, comprising: a processor, a memory, and a computer program; wherein, the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device runs, the processor executes the computer program stored in the memory, so that the electronic device executes the modular HIL cabinet design method based on axiomatic design as described above.

[0014] Compared with the prior art, the beneficial effects of the present disclosure are as follows: Decoupled design: Each functional module can be independently maintained / upgraded. After actual testing, compared with traditional HIL cabinets, the maintenance cost is reduced by more than 20%; during the maintenance process, there is no need to completely stop production and debug as in traditional cabinets. Only the layer where the faulty module is located needs to be maintained, reducing the downtime and maintenance workload.

[0015] Rapid deployment: The module replacement time is shortened from the traditional hour level to the minute level. For example, when replacing the computing unit, through magnetic rails and standard slots, technicians can complete the replacement and debugging within 5 minutes, greatly improving the test efficiency.

[0016] High compatibility: It supports cross-industry test requirements (such as from automotive ECUs to avionics). Due to the adoption of standardized interface boards and hierarchical decoupled design, this cabinet system can easily adapt to the test requirements of different industries without the need to separately design test equipment for different industries, reducing the enterprise's test cost.

[0017] Design matrix verification: By analyzing the relationship between the functional requirements FRs and design parameters DPs of each layer through the design matrix, ensuring that the matrix is a diagonal or triangular matrix, which theoretically guarantees the rationality and stability of the system design.

[0018] Application of information axiom: Select standardized components (such as general interface boards, modular power supplies) to replace customized designs, reducing system complexity. According to the information axiom formula, the information quantity I = -log2(P) is minimized. The adoption of standardized components reduces the uncertainty in design and improves the reliability and maintainability of the system. Description of the Drawings

[0019] The specification drawings forming a part of the present disclosure are used to provide a further understanding of the present disclosure. The schematic embodiments and descriptions thereof of the present disclosure are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure.

[0020] Figure 1 It is a flowchart of the method for Embodiment 1.

[0021] Figure 2It is a tree diagram of the mapping relationship of the functional structure of the modular HIL cabinet in Embodiment 1.

[0022] Figure 3 It is a design flow chart of the modular HIL cabinet in Embodiment 1.

[0023] Figure 4 It is a diagram of the modular hardware resource allocation mechanism in Embodiment 1.

[0024] Figure 5 It is a schematic diagram of the corner angle in Embodiment 1. Specific implementation manners

[0025] The present disclosure will be further described below in conjunction with the accompanying drawings and embodiments.

[0026] It should be noted that the following detailed description is exemplary and is intended to provide further description of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs.

[0027] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "include" and / or "comprise" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0028] Embodiment 1 In one embodiment of the present disclosure, a design method for a modular HIL cabinet based on axiomatic design is provided, including: Step S1: Obtain the functional domain of the HIL cabinet to be designed; Step S2: Adopt a decoupled architecture based on axiomatic design theory to divide the functional domain of the cabinet into independent functions and perform parameter design to form an initial design scheme of the modular HIL cabinet; Step S3: Based on the initial design scheme of the HIL cabinet, define a dynamic hardware resource allocation mechanism for allocating hardware resources for real-time computing functions, and based on a topology optimization algorithm, perform path planning for the wiring of the cables in the cabinet to obtain the final design scheme of the HIL cabinet.

[0029] As an embodiment, a modular HIL cabinet design method based on axiomatic design of the present disclosure realizes independent maintenance and upgrade of each functional module, reduces maintenance costs; through an extensible rack structure, it can flexibly adapt to different test requirements; optimizes cable connection and electromagnetic interference design, improves the utilization rate of cabinet space, reduces system complexity, and improves system reliability. The specific implementation process is as follows: (1) Aiming at the functional coupling problem proposed in the background art, this embodiment proposes a four-layer decoupling architecture based on the axiomatic design theory. Through independent functional mapping and orthogonal design of the high-performance computing function layer, multi-interface expansion function layer, stable power management function layer, and dynamic heat flow self-balancing function layer, functional coupling is eliminated.

[0030] Based on the independence axiom and information axiom of axiomatic design, the requirements of the HIL cabinet are decomposed into independent functional layers, and decoupling design is realized through standardized interfaces and a hierarchical architecture; the cabinet is divided into a high-performance computing function layer, a multi-interface expansion function layer, a stable power management function layer, and a dynamic heat flow self-balancing function layer, corresponding to the functional domains FRs. Physical modules are designed for the four independent functional layers respectively, and the physical modules are divided into sub-functional modules and the corresponding sub-physical modules are designed, and finally the independent design parameters DPs of each layer are obtained.

[0031] Among them, the high-performance computing function layer adopts a pluggable computing unit (FPGA module), which supports hot plugging and dynamic expansion; the FPGA is responsible for real-time processing of high-frequency signals, and the multi-core processor runs complex dynamics models (such as vehicle dynamics, aero-engine simulation) to form a "hardware acceleration + general computing" collaborative architecture; in this way, when additional computing power is required, new computing units can be directly inserted without large-scale transformation of the entire system; when a computing unit fails, it can also be easily replaced without affecting the normal operation of other layers.

[0032] The multi-interface expansion function layer is configured with standardized interface boards (such as CAN, LIN, Ethernet) and communicates with the computing layer through the backplane bus; the standardized interface boards can support multiple signal types to meet the interface requirements in different test scenarios; the design of the backplane bus ensures fast and stable data transmission between the computing layer and the interface layer.

[0033] The stable power management function layer uses independent power modules to supply power to each layer, supporting redundant backup and load balancing. The redundant backup function ensures that when a certain power module fails, other power modules can continue to supply power to the system, improving the stability of the system; load balancing ensures that each power module can reasonably distribute the load and extends the service life of the power module.

[0034] The dynamic heat flow self - balancing functional layer achieves local precise heat dissipation through distributed temperature sensors and a micro piezoelectric fan array, replacing the traditional fully redundant fan design.

[0035] Figure 2 It is a tree - shaped diagram of the mapping relationship of the modular HIL cabinet functional structure. "Total function FR real - time simulation and verification" and "Design parameter DP systematic integration" are the overall layers, and the following FRs and DPs have a hierarchical decomposition relationship. The overall layer FR defines the system goal, and DP gives the top - level solution; it is decomposed layer by layer to ensure that each level of FR - DP satisfies the independence axiom; the optimal DP combination is selected through the information axiom. Therefore, the mapping relationship between the independent functional layer, physical modules, sub - functional modules, and sub - physical modules is shown in the figure. Based on Figure 2 the presented mapping relationship, the entire decomposition process is as follows: Take the mapping between the independent functional layer and the physical module as the first - level decomposition. The design equation matrix obtained in the first - level decomposition:

[0036] Among them, FR1 is the high - performance computing functional layer, FR2 is the multi - interface expansion functional layer, FR3 is the stable power management functional layer, FR4 is the dynamic heat flow self - balancing functional layer, DP1 is the computing unit, DP2 is the interface unit, DP3 is the power module, and DP4 is the heat dissipation duct.

[0037] In linear design, when the design matrix is a triangular matrix, it is a quasi - coupled design. The independence can be ensured by changing the order of the design parameters to meet the axiomatic design criterion. Therefore, through transformation, the above matrix is converted into a triangular matrix.

[0038] During the transformation process, the order of the design parameters DP3 and DP4 is adjusted to make the design process reasonable and meet the axiomatic design criterion.

[0039] Similarly, take the mapping between the sub - functional module and the sub - physical module as the second - level decomposition. The design equation matrix obtained in the second - level decomposition includes:

[0040] Among them, FR11 is the real - time computing function, FR12 is the coordinated computing function, DP11 is the FPGA, and DP12 is the multi - core processor.

[0041]

[0042] Among them, FR21 is the communication function, FR22 is the IO function, DP21 is the CAN interface, and DP22 is the TIF interface.

[0043]

[0044] Among them, FR31 is the strong power supply function, FR32 is the weak power supply function, DP31 is the PDU, and DP32 is the programmable power supply.

[0045] FR41 = DP41 Among them, FR41 is the strong wind heat dissipation function, and DP41 is the cooling fan.

[0046] The design matrices of the above secondary decomposition are all diagonal matrices or triangular matrices. The design process is reasonable and conforms to the axiomatic design criteria.

[0047] Based on the results of the design matrices in the above analysis process, a design process that conforms to the axiomatic design concept can be obtained. The design sequence in the primary decomposition is DP1, DP2, DP4, DP3. The same applies to the secondary decomposition process, and the overall design process as shown in Figure 3 is obtained. The HIL cabinet is designed according to the design process obtained above.

[0048] (2) To address the problem of insufficient scalability proposed in the background technology, in this embodiment, a software-defined modular hardware resource allocation mechanism is adopted to dynamically adapt to the requirements of different test scenarios, and resources are allocated to the FPGA of the real-time computing function in the high-performance computing function layer FR1, as shown in Figure 4 . The modular hardware resource allocation mechanism is divided into four areas, namely the signal selection area, the signal protocol area, the virtual interface area, and the real interface area.

[0049] The signal selection area stores the unique encodings of different signal protocols (such as PWM corresponding to 0x01, SENT corresponding to 0x02, etc.). Each encoding is mapped one-to-one with the specific module in the signal protocol area; the processing operations include encoding generation and encoding switching. The encoding generation operation generates the encoding corresponding to the signal protocol according to the test requirements, and the encoding switching generates the real-time switching instruction of the signal protocol by modifying the currently activated encoding.

[0050] The signal protocol area encapsulates the signal protocol implementation units (such as the PWM generator module, the SENT encoder module) as independent modules, including protocol parsing logic and signal generation algorithms, and establishes a one-to-one correspondence between the encoded signals and the protocol modules (such as 0x01 → PWM module, 0x02 → SENT module); the processing operations include module switching and signal generation. The module selection receives the encoded signal from the signal selection area through the software programming interface and triggers the activation of the corresponding protocol module. The signal generation is that the activated module generates a signal data stream in a specific format according to the input parameters.

[0051] The virtual interface area stores the interface types required for each signal protocol. The processing operations include interface configuration and signal routing. Interface configuration is to complete the configuration of the interface type at the software layer according to the output requirements of the signal protocol, and signal routing is to route the signal data stream generated by the protocol module to the corresponding virtual interface.

[0052] The real interface area stores the types (such as AI / AO / DI / DO, etc.), quantities, and electrical characteristics of the actual physical interfaces. The processing operations include interface matching and signal output. Interface matching is to complete the physical mapping between the virtual interface and the real interface through hardware, and signal output is to convert the digital / analog signals of the virtual interface into real physical signals. The quantity and type of the actual physical interfaces stored in the real interface area are the maximum values of the quantities and types required by each of the n communication protocols in the virtual interface area. It is expressed by the formula:

[0053] In the formula, N is the quantity of a certain type of interface in the real interface area, is the number of channels of the same type of interface in the n communication protocols in the virtual interface area.

[0054] The modular hardware resource allocation mechanism realizes channel multiplexing through the above four areas, reduces channel resource waste, and when facing different test scenario requirements, there is no need to stop the HIL device to replace software and hardware. While using a small amount of resources, it increases the expandability of the HIL cabinet when facing different test requirements.

[0055] (3) Aiming at the problem of unreasonable cable distribution proposed in the background technology, this embodiment proposes to use a topology optimization algorithm to perform three-dimensional space planning on the cables in the cabinet, making the wiring reasonable, greatly improving the space utilization rate, and avoiding cross interference.

[0056] The cables in the cabinet mainly include the high-voltage cables, low-voltage cables of the stable power management function layer FR3, and the signal cables of the multi-interface expansion function layer FR2. The signal cables are further divided into high-speed signal cables and low-speed signal cables according to the transmission rate. Therefore, the classification constraints for cable types are as follows: (1) The distance between the high-voltage cables and the other two types of cables (low-voltage cables, signal cables) is greater than or equal to 50 mm to avoid electromagnetic interference caused by the high-voltage cables. If it cannot be satisfied, a metal shielding sleeve is installed.

[0057] (2) The high-speed signal cables are planned separately to avoid sharing the same slot with the power lines, and a 45° arc transition is used at the turning points to reduce reflection noise.

[0058] The improved A* algorithm is used to perform path planning for cables. The improvement is to convert engineering constraints (stress cost, electromagnetic interference cost, space occupancy cost) into computable quantitative indicators and introduce them into the evaluation function. The priority is dynamically adjusted through weight coefficients (β, γ, δ), and the current cost g(n) and the target heuristic h(n) are balanced through the evaluation function, enabling the efficient finding of the optimal path in a complex grid space. The improved evaluation function is as follows:

[0059] where n is the path node currently being evaluated, i.e., the current state or position; g*(n) is the actual cost; S(n) is the stress cost, calculated based on the fixed-point spacing and bending radius. For example, when the fixed points are too sparse, the tension increases; E(n) is the electromagnetic interference cost, calculated based on the cable type spacing and shielding measures. For example, when strong electricity / weak electricity cross, a penalty value is increased; V(n) is the space occupancy cost, which counts the number of three-dimensional grids occupied by the path and the distance from obstacles. When close to the cable tray, the cost is reduced; β, γ, δ are weight coefficients, adjusted according to the cabinet type.

[0060] Based on the above evaluation function, the specific process of optimizing the cable routing path is as follows: Step 1: Initialization and data modeling Input data, including the three-dimensional model of the cabinet, containing the coordinates of equipment, cable trays, and obstacles; the cable parameter table, containing type, diameter, and flexibility coefficient , shielding level ; constraint parameters: the minimum distance D between strong electricity and weak electricity EMC = 50 mm, the maximum fixed-point spacing L MAX = 300 mm, and the weights of each target, such as β = 0.3, γ = 0.4, δ = 0.3.

[0061] Based on the above data, space discretization is performed, and the cabinet is divided into three-dimensional grids (granularity k = 10 mm). Each grid is marked with the following attributes: whether it is an obstacle, whether it belongs to the cable tray, and whether it is a dedicated layer for strong electricity / weak electricity / signal.

[0062] Step 2: Set the initial node and Open / Closed tables Starting point: the coordinates of the source device's terminal (such as the strong electricity starting point (100, 50, 20)); End point: the coordinates of the target device's terminal (such as the signal end point (800, 700, 800)).

[0063] Open table: a priority queue (sorted in ascending order), initially adding the starting point node; Closed table: records the visited nodes to avoid repeated searches.

[0064] ​Step 3: Node Expansion and Generation of Adjacent Nodes Perform 8-direction expansion (in three-dimensional space). Each node expands in 6 orthogonal directions: (±1, 0, 0), (0, ±1, 0), (0, 0, ±1), and also in the diagonal directions to generate adjacent nodes.

[0065] During the expansion process, the following two points should be noted: Obstacle avoidance: If the adjacent grid is occupied by a device or a column, skip this node; Minimum bending radius: Calculate the turning angle. If the bending radius < the allowable value of the cable (such as for high-voltage cables = 6D), mark it as an invalid node.

[0066] Step 4: Multi-objective Cost Calculation ① Consider the shortened path of the cable trough bend and calculate the actual cost g*(n). The formula is: g*(n) = straight-line segment length - Δg(θ) Where, Δg(θ) is the shortened path of the cable trough bend, calculated according to the corner angle. For example, Figure 5 as shown, if the corner is 90°, then Δg(θ) = (2 - π / 2)(R + r), where R represents the bending radius of the cable trough, used to describe the arc bending size of the cable bundle at the corner, and r represents the equivalent radius of the cable bundle.

[0067] ② Based on the three-dimensional Euclidean distance, define the target heuristic function h(n). The formula is:

[0068] Where, (x n , y n , z n ) represents the three-dimensional coordinates of the current node, and (x end , y end , z end ) represents the three-dimensional coordinates of the target node.

[0069] Guide the search to approach the target point and reduce blind exploration.

[0070] ③ The cost of the cable trough bend s(n). The formula is:

[0071] Where, l is the length of the cable trough bend, is the unit cost coefficient, is the material cost, is the process cost, is the weight cost. For example, when the corner is 90°, the length of the cable trough bend l is π / 2(R + r), multiplied by the unit cost coefficient.

[0072] ④ The stress cost S(n) has the formula: S(n)=S 间距 (n)+S 弯曲 (n) where S 间距 (n) is the fixed - point spacing penalty, and S 弯曲 (n) is the bending stress penalty.

[0073] If the distance L between the current node and the previous fixed point is greater than the maximum fixed - point spacing L MAX , then the fixed - point spacing penalty is: S 间距 (n)=k f ×(L−L max ) where k f is the cable flexibility coefficient. The better the flexibility, the larger the value of k f , and the higher the penalty. This is to prevent a cable with good flexibility (such as a flexible wire) from being over - stretched due to too large a fixed - point spacing and to ensure the mechanical stability of the cable.

[0074] If the actual bending radius R b < the minimum allowable bending radius R of the cable min , then the bending stress penalty is:

[0075] This formula normalizes the penalty value to 0 - 100 points. The closer R b is to the lower limit of R min , the higher the penalty, aiming to ensure that the cable bending radius is within a safe range and prevent cable damage caused by excessive bending.

[0076] ⑤ The electromagnetic interference cost E(n) has the formula: E(n)=E 间距 (n)+E 平行 (n) where E 间距 (n) is the type - spacing penalty, and E 平行 (n) is the parallel - laying penalty.

[0077] If the distance d between the high - voltage node and the signal node is less than the safety - spacing threshold D EMC , then the type - spacing penalty is:

[0078] where S L represents the signal shielding level. This formula indicates that the smaller the distance d, the greater the interference risk and the higher the penalty value; S L is used to adjust the penalty intensity according to the shielding situation of the signal line. For example, when the distance between the high - voltage and the non - shielded signal line is relatively close, E(n) will be affected by SL It is larger, resulting in a higher penalty value, prompting the algorithm to plan a path away from the high-voltage electricity.

[0079] The penalty for parallel laying is as follows:

[0080] If the parallel length L with the high-voltage line p > 100 mm, then 1 is added for every 10 mm As the parallel length increases, the risk of electromagnetic interference increases, thus increasing the penalty value and making the algorithm try to avoid long-distance parallel laying of signals and high-voltage lines.

[0081] ⑥ Spatial occupancy cost V(n), the formula is: V(n)=V 栅格 (n)+V 障碍 (n)

[0082] Among them, V 栅格 (n) is the grid occupancy rate, and V 障碍 (n) is the obstacle proximity.

[0083] The spatial occupancy is measured by calculating the number of three-dimensional grids occupied by the path and normalizing it to the range of 0 - 1 to obtain the grid occupancy rate, which is expressed by the formula:

[0084] Its meaning is the ratio of the actually occupied grids to the grids available for occupancy in the wiring duct. The lower this ratio, the more reasonable the path's occupancy of space and the lower the cost.

[0085] The calculation method of the obstacle proximity is: if the distance between the node and the metal obstacle < 5 mm (such as heat dissipation holes, etc.), a fixed penalty of 0.5 is added (to avoid cable abrasion), otherwise no penalty is added, which is expressed by the formula:

[0086] It mainly considers the influence of the distance between the cable and the metal obstacle (such as heat dissipation holes, etc.) on the spatial occupancy cost. If the distance between the node and the metal obstacle is less than 5 mm, a fixed penalty value of 0.5 will be added; this is to avoid the cable being too close to the metal obstacle and prevent possible abrasion. For example, when the distance between the nodes on a certain cable path and the metal obstacle is less than 5 mm, regardless of the V(n) calculated by the grid occupancy rate, an additional penalty value of 0.5 will be added, making the spatial occupancy cost of this path higher, thus guiding the algorithm to try to plan a path for the cable away from the metal obstacle.

[0087] Step 5: Evaluation function integration and node sorting The total cost is calculated through an evaluation function, which is expressed by the formula:

[0088] Based on the total cost, the priority queue is updated: The Open table always selects the node with the smallest value for expansion to ensure multi-objective balance (e.g., in a high EMC scenario, give priority to reducing E(n)).

[0089] Step 6: Closed-loop verification and path correction Fixed points are inserted at the path inflection points and every L = 200×k f mm on the straight line segments, such as for hard wires k f = 1, with a spacing of 200 mm; for soft wires k f = 0.5, with a spacing of 100 mm. If the insertion point causes a space conflict, backtrack to the previous node and search again.

[0090] If the path in the strong electrical layer crosses the signal layer area, the penalty value of E(n) is forced to increase, triggering local replanning.

[0091] Step 7: Path generation and physical verification Trace back to the parent node from the Closed table, extract the coordinates of the inflection points and fixed points, and generate the central line path.

[0092] The central line path is verified by finite element simulation. Input the cable material parameters (such as Young's modulus, conductivity of the shielding layer), and simulate the stress distribution and electromagnetic radiation under different working conditions. If the threshold is exceeded, adjust the weight coefficient (such as increasing β) and recalculate.

[0093] Through the topology optimization algorithm, the three-dimensional space planning of the cables in the cabinet is carried out. The stress is reduced by 15% compared with manual wiring, the amplitude of electromagnetic interference is decreased by 10%, and the space occupation is reduced by 25%.

[0094] This embodiment successfully solves the problems of functional coupling, poor scalability, and unreasonable cable distribution in the traditional HIL cabinet design, realizes the independent maintenance and upgrade of each functional module, and reduces the maintenance cost; through the scalable rack structure, it can flexibly adapt to different test requirements; optimizes the cable connection and electromagnetic interference design, improves the space utilization rate of the cabinet, reduces the system complexity, and improves the reliability of the system.

[0095] Embodiment 2 In an embodiment of the present disclosure, a modular HIL cabinet design system based on axiomatic design is provided, including: A function acquisition module, configured to: acquire the function domain of the HIL cabinet to be designed; The initial design module is configured to: adopt a decoupled architecture based on the axiomatic design theory, divide the functional domains of the cabinet into independent functions and perform parameter design, so as to form an initial modular HIL cabinet design scheme; The final design module is configured to: based on the initial HIL cabinet design scheme, define a dynamic hardware resource allocation mechanism for allocating hardware resources for real-time computing functions, and based on a topology optimization algorithm, perform path planning on the wiring of the cables in the cabinet to obtain the final HIL cabinet design scheme.

[0096] Example 3 In an embodiment of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, it implements the described modular HIL cabinet design method based on axiomatic design.

[0097] Example 4 In an embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium is used to store computer instructions, and when the computer instructions are executed by a processor, it implements the described modular HIL cabinet design method based on axiomatic design.

[0098] Example 5 In an embodiment of the present disclosure, an electronic device is provided, including: a processor, a memory, and a computer program; wherein, the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device runs, the processor executes the computer program stored in the memory, so that the electronic device executes and implements the described modular HIL cabinet design method based on axiomatic design.

[0099] The present disclosure is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in one Figure 1 one or more flows and / or blocks Figure 1 one or more blocks specified in the block or blocks.

[0100] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable apparatus to generate a computer-implemented process, thereby providing instructions for implementing the process Figure 1 one process or a plurality of processes and / or blocks Figure 1 steps for the functions specified in one block or a plurality of blocks.

[0101] Although the specific embodiments of the present disclosure have been described above in conjunction with the accompanying drawings, they are not intended to limit the scope of protection of the present disclosure. Those skilled in the art should understand that, based on the technical solutions of the present disclosure, various modifications or variations that can be made by those skilled in the art without creative efforts are still within the scope of protection of the present disclosure.

Claims

1. A modular HIL cabinet design method based on axiomatic design, characterized in that: include: Obtain the functional domain of the HIL cabinet to be designed; Adopting a decoupled architecture based on axiomatic design theory, the functional domain of the cabinet is divided into independent functions and parameterized to form a modular HIL cabinet initial design scheme; Based on the initial design of the HIL cabinet, a dynamic hardware resource allocation mechanism is defined to allocate hardware resources for real-time computing functions. Based on the topology optimization algorithm, the path planning of the cable wiring in the cabinet is carried out to obtain the final HIL cabinet design.

2. A modular HIL cabinet design method based on axiomatic design as claimed in claim 1, characterized in that: The decoupling architecture based on axiomatic design theory divides the functional domain of the HIL cabinet into independent functions based on the independence axiom and information axiom of axiomatic design, and realizes decoupling design through a layered architecture; The division into independent functions is to divide the cabinet into four functional layers: a high-performance computing functional layer, a multi-interface expansion functional layer, a stable power management functional layer, and a dynamic heat flow self-balancing functional layer, and each layer has independent design parameters.

3. A modular HIL cabinet design method based on axiomatic design as claimed in claim 2, characterized in that: The layered architecture is to design physical modules for the four functional layers respectively, divide the physical modules into sub-functional modules and design corresponding sub-physical modules.

4. The modular HIL cabinet design method based on axiomatic design as claimed in claim 1, characterized in that: The hardware resource allocation mechanism is to allocate hardware resources for real-time computing functions by means of the signal selection area, signal protocol area, virtual interface area, and real interface area, specifically: Signal selection area, select the signal protocol according to the current test requirements, and encode and send it to the signal protocol area; The signal protocol area matches the received signal protocol with specific protocol content, and generates a signal through the matched protocol content; The virtual interface area configures the corresponding interface according to the selected signal protocol and the generated signal; The real interface area sends the generated signal to the real physical hardware corresponding to the interface.

5. The modular HIL cabinet design method based on axiomatic design as claimed in claim 1, characterized in that: The path planning for the wiring of cables in the cabinet adopts the A* algorithm, introduces stress cost, electromagnetic interference cost, and space occupancy cost into the evaluation function, and searches for the optimal wiring path in the grid space of the cabinet through the evaluation function.

6. A modular HIL cabinet design method based on axiomatic design as claimed in claim 5, characterized in that: The formula of the valuation function is specifically: Among them, g*(n) is the actual cost, which is calculated based on the wiring length; S(n) is the stress cost, which is calculated based on the fixed point spacing and the bending radius; E(n) is the electromagnetic interference cost, which is calculated based on the cable type spacing and shielding measures; V(n) is the space occupancy cost, which is calculated based on the number of three-dimensional grids occupied by the statistical path and the distance to obstacles; β, γ, and δ are weight coefficients.

7. A modular HIL cabinet design system based on axiomatic design, characterized in that: include: The function acquisition module is configured to: acquire the function domain of the HIL cabinet to be designed; The initial design module is configured as follows: using a decoupled architecture based on axiomatic design theory, dividing the functional domain of the cabinet into independent functions and performing parameter design, thus forming a modular HIL cabinet initial design scheme; The final design module is configured as follows: based on the initial design of the HIL cabinet, a dynamic hardware resource allocation mechanism is defined to allocate hardware resources for real-time computing functions, and based on the topology optimization algorithm, the path planning of the cable wiring in the cabinet is performed to obtain the final HIL cabinet design.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for designing a modular HIL cabinet based on axiomatic design as described in any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by the processor, the modular HIL cabinet design method based on axiomatic design as described in any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: include: A processor, a memory and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory so that the electronic device executes a modular HIL cabinet design method based on axiomatic design as described in any one of claims 1-6.

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