Scattering strip placement method, medium, product and equipment

Abstract

The invention provides a scattering strip placing method, a medium, a product and equipment. The method comprises the following steps: acquiring global layout data corresponding to a target semiconductor chip to be operated; splitting the global layout data into a preset number of sub-graphs, and distributing the preset number of sub-graphs to a plurality of processors; a plurality of processors execute scattering bar placement tasks on respective sub-graphs step by step, after execution of each step is completed, execution results of the processors are integrated, and when the next operation is executed, each processor reads layout data corresponding to the sub-graphs processed by the processor in the integrated global layout data. By means of the method, on the premise that the placing speed of the scattering strips is guaranteed, more scattering strips conforming to the technological parameters can be placed and reserved, global layout data are integrated and updated after each step of operation is executed, boundary information in the subgraph can be prevented from being lost, and therefore the problem that the boundary of the scattering strips violates the mask manufacturing rule is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a method for placing scattering bars, a medium, a product, and a device. Background Art

[0002] With the research and development of advanced nodes of integrated circuits, the graphic feature size is continuously reduced. The traditional method of placing scattering bars based on rules faces the problem of difficulty in placing the most ideal scattering bars. Because the rule-based methods are all placed according to the distance between main graphics, scattering bars cannot be placed in many close-range environments or are cleaned up later due to violation of mask manufacturing rules (MRC).

[0003] Moreover, the traditional methods for supporting the placement of scattering bars generally divide the entire layout into equal-sized small chips (Tiles), then allocate the Tiles to multiple CPUs to execute tasks in parallel, and finally merge the results. However, due to the independent operation of the small chips, the main graphic information obtained near their respective boundaries is inconsistent. Therefore, boundary problems that violate mask manufacturing rules are likely to occur, and conflict problem handling needs to be carried out again. Among them, the problem of the boundary of the scattering bar violating mask manufacturing rules is a difficult point in the industry. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a method for placing scattering bars, a medium, a product, and a device that overcome the above problems or at least partially solve the above problems.

[0005] One object of the present invention is to optimize the method for placing scattering bars, so as to place more scattering bars that do not violate mask manufacturing rules on the premise of ensuring the placement speed of the scattering bars;

[0006] Another further object of the present invention is to solve the problem that the boundary of the scattering bar violates mask manufacturing rules.

[0007] In particular, the present invention provides a method for placing scattering bars, including:

[0008] Obtaining global layout data corresponding to a target semiconductor chip to be operated;

[0009] Splitting the global layout data into a preset number of subgraphs, and allocating the preset number of subgraphs to multiple processors;

[0010] Gradually performing scattering bar placement tasks on their respective subgraphs by multiple processors, and after each step is completed, integrating the execution results of the multiple processors. When performing the next operation, each processor reads the layout data corresponding to the subgraph it processes from the integrated global layout data.

[0011] Optionally, the step of gradually performing scattering bar placement tasks on their respective subgraphs by multiple processors includes:

[0012] Determine the target pattern in the sub-pattern where the scattering bars need to be placed;

[0013] Place seed scattering bars with a preset number of turns outside the target pattern;

[0014] Screen the seed scattering bars to obtain the scattering bars to be operated on, and the scattering bars to be operated on are the seed scattering bars that do not conflict with the target pattern;

[0015] Grow the scattering bars to be operated on.

[0016] Optionally, the steps of growing the scattering bars to be operated on include:

[0017] Execute the growing operation on the scattering bars to be operated on following the preset manufacturing rules, and the preset manufacturing rules include: the manufacturability rules between the scattering bars to be operated on and other scattering bars and the manufacturability rules between the scattering bars to be operated on and the target pattern.

[0018] Optionally, after the steps of growing the scattering bars to be operated on, the following steps are further included:

[0019] Judge whether there are target scattering bars that violate the mask manufacturing rules among the scattering bars to be operated on after growth, and the target scattering bars are the scattering bars with a square shape;

[0020] If so, adjust the size and position of the target scattering bars so that the target scattering bars avoid violating the mask manufacturing rules while maintaining the square characteristics.

[0021] Optionally, the steps of integrating the execution results of multiple processors include: after each step of execution of multiple processors is completed, output the sub-patterns obtained by the processors to a preset database; integrate the layout data in the sub-patterns in the preset database and perform design rule checks to obtain the updated global layout data;

[0022] The steps for each processor to read the layout data corresponding to the sub-pattern it processes in the integrated global layout data when performing the next operation include: each processor reads the updated layout data of the sub-pattern it processes in the preset database; continue to perform the next operation based on the updated layout data.

[0023] Optionally, a version management mechanism for the global layout data is established in the preset database;

[0024] After the steps of integrating the execution results of multiple processors, the following steps are further included: generate a corresponding version identifier for the integrated global layout data.

[0025] Optionally, after the steps of multiple processors gradually performing the scattering bar placement tasks on their respective sub-patterns, the following steps are further included:

[0026] Expose the placed scattering bars under simulated abnormal exposure conditions for inspection;

[0027] In the case where the inspection result shows that the scattering bars have an exposure risk, adjust the scattering bars. The adjustment includes one or more adjustment methods such as offset, interruption, and reduction.

[0028] According to another aspect of the present invention, there is also provided a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above-mentioned scattering bar placement methods are implemented.

[0029] According to yet another aspect of the present invention, there is also provided a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any one of the above-mentioned scattering bar placement methods are implemented.

[0030] According to still another aspect of the present invention, there is also provided a computer device, including a memory, a processor, and a machine-executable program stored on the memory and running on the processor. When the processor executes the machine-executable program, the steps of any one of the above-mentioned scattering bar placement methods are implemented.

[0031] For the scattering bar placement method of the present invention, first obtain the global layout data corresponding to the target semiconductor chip to be operated; then split the global layout data into a preset number of sub-graphs, and allocate the preset number of sub-graphs to multiple processors; then the multiple processors gradually execute the scattering bar placement tasks for their respective sub-graphs, and after each step is completed, integrate the execution results of the multiple processors. When performing the next operation, each processor reads the layout data corresponding to the sub-graph it processes from the integrated global layout data. Through this method, it is possible to place and retain more scattering bars that meet the process parameters while ensuring the scattering bar placement speed, thereby increasing the process window, and integrating and updating the global layout data after each step of operation is completed, which can avoid the loss of boundary information in the sub-graph, thereby solving the problem that the boundary of the scattering bar violates the mask manufacturing rules.

[0032] Based on the following detailed description of the specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will more clearly understand the above and other objects, advantages, and features of the present invention. Description of the Drawings

[0033] Some specific embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0034] Figure 1It is a flowchart of a method for placing scattering bars according to an embodiment of the present invention;

[0035] Figure 2 It is a schematic diagram of the global layout data update process in the method for placing scattering bars according to an embodiment of the present invention;

[0036] Figure 3 It is a schematic diagram of the states of a target scattering bar before and after adjustment in the method for placing scattering bars according to an embodiment of the present invention;

[0037] Figure 4 It is a schematic diagram of the states of a target scattering bar before and after adjustment in the method for placing scattering bars according to another embodiment of the present invention;

[0038] Figure 5 It is a schematic diagram of the states of a seed scattering bar before and after growth in the method for placing scattering bars according to an embodiment of the present invention;

[0039] Figure 6 It is a flowchart of a processor executing a scattering bar placement task in the method for placing scattering bars according to an embodiment of the present invention;

[0040] Figure 7 It is a schematic diagram of a computer program product according to an embodiment of the present invention;

[0041] Figure 8 It is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and

[0042] Figure 9 It is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed implementation manners

[0043] Those skilled in the art should understand that the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments of the present invention. This part of the embodiments is intended to explain the technical principle of the present invention, rather than to limit the protection scope of the present invention. Based on the embodiments provided by the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts should still fall within the protection scope of the present invention.

[0044] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch instructions from the instruction execution system, apparatus, or device and execute the instructions), or in combination with these instruction execution systems, apparatuses, or devices.

[0045] In the current semiconductor manufacturing field, scatter bars are placed based on rules. Because the rules are clear, the placement speed is fast, and they have been widely used in mature nodes. However, for the development of advanced nodes, since clear placement rule parameters need to be provided, obtaining the rules requires continuous test pattern verification and continuous learning cycles to get a good parameter feedback. Placing scatter bars based on models is generally only used to solve some hotspot areas in advanced nodes because it requires a large amount of computing resources and is slow. Finally, how to optimize the scatter bar placement process based on existing rules highlights the economy.

[0046] And with the research and development of advanced nodes of integrated circuits, the graphic feature size is continuously decreasing. The traditional method of placing scatter bars based on rules faces the problem of being difficult to place the most ideal scatter bars. Because the rule-based methods place according to the distance between main graphics, scatter bars cannot be placed in many close-proximity environments or are cleared later due to violating the mask manufacturing rules (MRC). For this reason, the present invention proposes a scatter bar placement method. The purpose of the present invention is to optimize the scatter bar placement process in advanced nodes, which can not only maintain the speed of the traditional placement method but also place more scatter bars that do not violate the mask manufacturing rules based on the existing process parameters.

[0047] Optionally, Figure 1 is a schematic flowchart of a scatter bar placement method according to an embodiment of the present invention. As Figure 1 shown, the scatter bar placement method at least includes the following steps S101 to step S103.

[0048] Step S101, obtain the global layout data corresponding to the target semiconductor chip to be operated. The global layout data generally includes information such as the positions, shapes, sizes of various graphics in the target semiconductor chip, and their connection relationships, etc., which is the basis for subsequent scatter bar placement tasks.

[0049] Step S102, split the global layout data into a preset number of subgraphs and allocate the preset number of subgraphs to multiple processors. The reason for performing the splitting operation is that as the integration degree of semiconductor chips becomes higher and higher, the amount of layout data becomes extremely large. If only a single processor is used for processing, problems such as insufficient computing resources and slow processing speed will be faced, seriously affecting work efficiency. Therefore, the global layout data is split into a preset number of subgraphs and allocated to multiple processors for parallel processing. The splitting process needs to follow certain rules. For example, it can be divided according to the functional areas of the chip, dividing the logic circuit area, storage area, etc. into different subgraphs; it can also be divided according to a fixed grid size. After the division is completed, these subgraphs are evenly allocated to each processor through a task scheduling system to ensure that each processor has an appropriate workload, giving full play to the advantages of parallel computing and greatly shortening the processing time.

[0050] Step S103: Multiple processors gradually perform the scattering bar placement task on their respective sub - graphs. After each step is completed, the execution results of the multiple processors are integrated. When performing the next operation, each processor reads the layout data corresponding to the sub - graph it processes from the integrated global layout data.

[0051] In the traditional process supporting scattering bar placement, the entire layout is generally cut into equal - sized small chips, and then the obtained small chips are distributed to multiple CPUs to perform tasks in parallel. Finally, the results are merged. At the same time, corresponding boundary processing technical measures are taken to avoid problems violating mask manufacturing rules encountered during the merging process between different small chips. However, due to the independent operation of different small chips, the main graphic information obtained near their respective boundaries is inconsistent. Therefore, the boundary is prone to problems violating mask manufacturing rules and needs to be processed for conflict problems. And because there are multiple steps in the scattering bar placement process, the traditional scattering bar placement method will cause the problems of boundary violations of mask manufacturing rules caused by each step of operation to be passed to the next step of operation. Such repeated passing will cause the next step of operation to continue to be processed based on the wrong boundary, resulting in difficult - to - solve boundary MRC problems. Therefore, the boundary MRC problem of the scattering bar is a difficult point in the industry.

[0052] To solve this problem, in step S103 of the present invention, after each step is completed, the execution results of multiple processors are integrated. When performing the next operation, each processor reads the layout data corresponding to the sub - graph it processes from the integrated global layout data. This can avoid the repeated transmission of incomplete boundary information, thereby avoiding difficult - to - solve boundary MRC problems during boundary merging.

[0053] In some optional embodiments, the step of integrating the execution results of multiple processors generally may include: after each step of execution of multiple processors is completed, output the sub - graphs obtained by the processors to a preset database; integrate the layout data in the sub - graphs in the preset database and perform design rule checks to obtain updated global layout data; the step of each processor reading the layout data corresponding to the sub - graph it processes from the integrated global layout data when performing the next operation generally may include: each processor reads the updated layout data of the sub - graph it processes from the preset database; continue to perform the next operation based on the updated layout data.

[0054] An optional example of its execution process is Figure 2 as shown Figure 2It is a schematic diagram of the global layout data update process in the scattering bar placement method according to an embodiment of the present invention. After Tile1 (i.e., the sub-graph processed by the current processor) performs an operation in placing the scattering bar (abbreviated as SBAR), the sub-graph after the execution will be saved to the database. Subsequently, a design rule check (abbreviated as DRC) is performed. After eliminating the problem of boundary violation of the mask manufacturing rule caused by the previous operation through this operation, the latest sub-graph is saved to the database. Then, when performing the next operation in placing the scattering bar, the latest layout data corresponding to Tile1 will be read. In this way, when performing the next operation in the scattering bar placement task, it can be processed based on the latest global layout data. Since the layout data at this time has been integrated and checked, the processor can perform subsequent work on a more accurate and manufacturing requirement-compliant basis, which helps to improve the quality and efficiency of the entire chip layout design, avoid the transmission of boundary problems caused by the previous operation to the next operation, and ensure that the finally manufactured chip can meet the performance and function requirements. Figure 2 The process shown can generally be called the full layout preview technology. By using the full layout preview technology to automatically save and load the global layout data, the loss of the split Tile boundary information can be avoided. In this way, it can not only retain the advantage of distributed computing to improve the operation speed, but also solve the MRC problem of the scattering bar boundary.

[0055] Optionally, in order to further facilitate the management of the global layout data, a version management mechanism for the global layout data can also be established in the preset database; after the step of integrating the execution results of multiple processors, it generally further includes: generating a corresponding version identifier for the integrated global layout data.

[0056] Through this method, it is possible to place and retain more scattering bars that meet the process parameters while ensuring the scattering bar placement speed, thereby increasing the process window. And after each operation is completed, the global layout data is integrated and updated, which can avoid the loss of boundary information in the sub-graph, thus solving the problem of boundary violation of the mask manufacturing rule of the scattering bar.

[0057] In some alternative embodiments, the steps of gradually performing the scatter bar placement task on respective sub - graphs by multiple processors generally may include: determining the target pattern in the sub - graph where scatter bars need to be placed; placing a preset number of turns of seed scatter bars outside the target pattern; screening the seed scatter bars to obtain the scatter bars to be operated on, where the scatter bars to be operated on are the seed scatter bars that do not conflict with the target pattern; and performing a growth operation on the scatter bars to be operated on. The selection of the target pattern generally includes determination based on graphic feature analysis and determination based on lithography process window requirements. First is determination based on graphic feature analysis. Generally speaking, when the width of the graphic line is less than a specific threshold, or the graphic pitch is too small, problems such as diffraction and interference are likely to occur during the lithography process, resulting in a decline in imaging quality. These graphics generally will be determined as target patterns. Secondly is determination based on lithography process window requirements. The lithography process window refers to the range of process parameters that can ensure lithography quality during the lithography process. Different graphics have different requirements for the lithography process window. The processor will compare the lithography process window required by each graphic with the process window actually provided by the current lithography equipment. If the process window required by a certain graphic exceeds the actual range, then this graphic will be marked as a target pattern because it requires scatter bars to improve the lithography effect and broaden its acceptable process window range.

[0058] Secondly, the size of the seed scatter bars can generally be 1nm * 1nm, and the number of turns of the seed scatter bars is not set arbitrarily, but is based on a large amount of experimental data and lithography simulation results. If the number of turns is too small, it may not provide sufficient scattering effect to improve the imaging of the target pattern; if the number of turns is too large, it will increase the complexity and cost of the lithography process and may also introduce new interference factors. Generally speaking, for simple target patterns, perhaps only 1 - 2 turns of seed scatter bars need to be placed; for complex integrated circuit modules, 3 - 4 turns or even more may be required. For example, for a simple rectangular pattern, placing 1 turn of seed scatter bars may meet the imaging requirements; but for a logic circuit area containing multiple complex geometric shapes, more turns are needed to ensure that each part can obtain appropriate scattering enhancement.

[0059] When placing the seed scatter bars, the principle of uniform distribution also needs to be followed, and they are evenly arranged around the perimeter of the target pattern. This is done to ensure that all parts of the target pattern can receive uniform scattered light, thereby achieving a uniform imaging effect. If the seed scatter bars are unevenly distributed, it may cause some parts of the target pattern to be over - imaged or under - imaged, affecting the performance of the entire chip.

[0060] After placing the seed scattering bars, it is necessary to screen the seed scattering bars to obtain the scattering bars to be operated on. This is because among the placed seed scattering bars, some may conflict with the target pattern, affecting the imaging quality, and not all of them can be directly used in the subsequent lithography process. Therefore, screening is required. The screening method generally selects the seed scattering bars that will not conflict with the current main pattern according to the mask manufacturing rules, or a dedicated conflict detection model can be established to detect potential conflicts between the seed scattering bars and the target pattern using geometric calculations and lithography simulation techniques. This model calculates parameters such as the minimum distance and angular relationship between the seed scattering bars and the target pattern. If the distance between the seed scattering bar and the target pattern is less than the minimum spacing allowed by the lithography process, or their angular relationship will cause unnecessary interference or diffraction during lithography, then this seed scattering bar is determined to have a conflict. For example, when the minimum distance between a seed scattering bar and the target pattern is less than 50 nanometers (depending on the specific lithography process), it may be regarded as a conflict and needs to be excluded. After conflict detection, the seed scattering bars that will not conflict with the target pattern are screened out, and these screened scattering bars are the scattering bars to be operated on. They meet the basic requirements of the lithography process and can be safely used for subsequent operations, ensuring that while enhancing the imaging of the target pattern, it will not have a negative impact on the target pattern itself.

[0061] Optionally, the steps for growing the scattering bars to be operated on generally may include: performing a growing operation on the scattering bars to be operated on in accordance with preset manufacturing rules, and the preset manufacturing rules generally include: the manufacturable rules between the scattering bars to be operated on and other scattering bars and the manufacturable rules between the scattering bars to be operated on and the target pattern. The growing operation mainly increases the size of the scattering bars on the premise of not violating the lithography process manufacturing rules (such as the manufacturable rules between the scattering bars to be operated on and other scattering bars and the manufacturable rules between the scattering bars to be operated on and the target pattern, etc.). Generally, it can be achieved by increasing the length, width or area of the scattering bars. For example, for linear scattering bars, they can be appropriately elongated along their length direction; for rectangular scattering bars, both the length and width can be increased. However, during the growing process, it is necessary to constantly monitor the relationship between the scattering bars and the surrounding patterns to ensure that no new conflicts will occur due to the increase in size.

[0062] Therefore, in some alternative embodiments, after the step of growing the scatter bars to be operated on, the following steps may generally be further included: determining whether there are target scatter bars that violate the mask manufacturing rules in the scatter bars to be operated on after growth, where the target scatter bars are scatter bars with a square shape; if so, adjusting the size and position of the target scatter bars so that, while maintaining the square characteristics, the target scatter bars avoid violating the mask manufacturing rules. The mask manufacturing rules are important specifications to ensure the quality of mask manufacturing and the success of subsequent lithography processes, and they include various restrictive rules, mainly including the rules between scatter bars and target patterns, such as the mask manufacturing distance between scatter bars and target patterns. An alternative example of a conflict where the mask manufacturing distance between scatter bars and target patterns is violated is as Figure 3 shown, Figure 3 is a schematic diagram of the states before and after adjustment of the target scatter bars in the scatter bar placement method according to an embodiment of the present invention. Among them, 310 is the corner scatter bar after growth, and 320 is the target pattern. Generally, corner scatter bars are prone to conflicts violating the mask manufacturing distance. From Figure 3 it can be seen that the part of the corner scatter bar 310 inside the dotted line conflicts with the target pattern 320, so it is dynamically adjusted. The dynamic adjustment process needs to ensure its square characteristics. Therefore, after adjustment, the corner scatter bar 311 is obtained. At this time, the corner scatter bar 311 can both retain the square characteristics and not conflict with the target pattern 320.

[0063] In some special cases, square edge scatter bars may also appear around the target pattern, as Figure 4 shown, Figure 4 is a schematic diagram of the states before and after adjustment of the target scatter bars in the scatter bar placement method according to another embodiment of the present invention. Among them, square edge scatter bars 410 appear around the target pattern 420. For such edge scatter bars, the adjustment method of the present invention can also be used. In the case where the dotted part of the edge scatter bar 410 conflicts with the target pattern 420, the edge scatter bar 410 is adjusted. After adjustment, the edge scatter bar 411 is obtained. At this time, the edge scatter bar 411 can both retain the square characteristics and not conflict with the target pattern 420.

[0064] In addition, during semiconductor lithography, the actual exposure environment may be interfered by various factors, resulting in abnormal exposure conditions. Therefore, it is very necessary to perform an exposure check on the placed scatter bars under simulated abnormal exposure conditions. So, in some alternative embodiments, after the step of gradually performing the scatter bar placement task on their respective subgraphs by multiple processors, the following steps may generally be further included: simulating abnormal exposure conditions to perform an exposure check on the placed scatter bars; and adjusting the scatter bars in the case where the inspection result shows that the scatter bars have an exposure risk.

[0065] The simulation of abnormal exposure conditions generally includes: simulation of light source fluctuations, simulation of changes in photoresist characteristics, and simulation of optical system aberrations, etc. Among them, the simulation of light source fluctuations means that the light source intensity of the lithography machine may experience slight fluctuations, which will affect the lithography effect. By simulating the random changes in light source intensity within a certain range, the imaging situation of the scattering bars under such an unstable light source is detected. For example, simulate the light source intensity fluctuating within ±5% of the normal intensity, and observe the influence of the scattering bars on the imaging of the target pattern. The simulation of changes in photoresist characteristics means that the performance of the photoresist is affected by environmental factors such as temperature and humidity. Simulate the characteristic changes of the photoresist under different temperature and humidity conditions, such as changes in parameters such as the sensitivity and contrast of the photoresist, so as to evaluate whether the scattering bars can still function properly under these circumstances. The simulation of optical system aberrations means that there may be aberrations in the optical system of the lithography machine, resulting in inaccurate light focusing. By simulating different degrees and types of aberrations, the imaging quality of the scattering bars in the optical system with aberrations is checked.

[0066] The adjustment operations generally can include one or more adjustment methods such as offset, break, and reduction. When the relative position between the scattering bar and the target pattern may cause poor imaging under abnormal exposure conditions, the position of the scattering bar can generally be offset to improve. For example, if it is simulated that the light of the scattering bar in a certain direction interferes with the imaging of the target pattern, the scattering bar is offset a certain distance in the opposite direction; if a certain part of the scattering bar causes serious exposure problems under abnormal exposure conditions, such as generating unnecessary diffraction or interference, affecting the clarity of the target pattern, the scattering bar can be considered to be broken. After breaking, the part causing the problem is removed or adjusted to reduce the negative impact on lithography; when the size of the scattering bar is too large and it is easy to generate excessive scattering or interfere with the surrounding patterns under abnormal exposure conditions, reducing the size of the scattering bar can reduce this risk. The reduced scattering bar has a relatively weakened scattering effect on light and may be more suitable for abnormal exposure conditions.

[0067] Finally, an example after adjustment by the scattering bar placement method of the present invention is Figure 5 shown as Figure 5 a schematic diagram of the states before and after the growth of the seed scattering bar in the scattering bar placement method of an embodiment of the present invention. Among them, state A is a schematic diagram of placing the seed scattering bar around the target pattern. After screening the seed scattering bar by the scattering bar placement method of the present invention, the scattering bar to be operated that will not conflict with the target pattern is obtained. Subsequently, the growth operation is performed on the scattering bar to be operated strictly in accordance with the manufacturability rules between the scattering bar and the main pattern and between the scattering bars. The final result is shown in state B. In this way, it can be ensured that denser scattering bars are inserted, and at the same time, the problem of inconsistent scattering bars placed by the same type of main pattern due to the cleaning rules is also avoided.

[0068] Figure 6 It is a schematic flowchart of a processor executing a scattering bar placement task in a scattering bar placement method according to an embodiment of the present invention. As Figure 6 shown, the scattering bar placement method at least includes the following steps S601 to step S610.

[0069] Step S601, determine the target pattern in the sub - graph where the scattering bar needs to be placed. The selection of the target pattern generally includes determination based on graphic feature analysis and determination based on lithography process window requirements. First, it is determination based on graphic feature analysis. Generally speaking, when the width of the graphic line is less than a specific threshold, or the graphic spacing is too small, problems such as diffraction and interference are likely to occur during lithography, resulting in a decline in imaging quality. These graphics are generally determined as target patterns. Secondly, it is determination based on lithography process window requirements. The lithography process window refers to the range of process parameters that can ensure lithography quality during lithography. Different graphics have different requirements for the lithography process window. The processor will compare the lithography process window required by each graphic with the process window actually provided by the current lithography equipment. If the process window required by a certain graphic exceeds the actual range, then this graphic will be marked as a target pattern because it requires a scattering bar to improve the lithography effect and broaden its acceptable process window range.

[0070] Step S602, place a preset number of turns of seed scattering bars outside the target pattern. Among them, the size of the seed scattering bars can generally be 1nm * 1nm, and the number of turns of the seed scattering bars is not set randomly, but is based on a large amount of experimental data and lithography simulation results. If the number of turns is too small, it may not provide enough scattering effect to improve the imaging of the target pattern; if the number of turns is too large, it will increase the complexity and cost of the lithography process, and may also introduce new interference factors. Generally speaking, for simple target patterns, only 1 - 2 turns of seed scattering bars may be needed; for complex integrated circuit modules, 3 - 4 turns or more may be required. For example, for a simple rectangular pattern, placing 1 turn of seed scattering bars may meet the imaging requirements; but for a logic circuit area containing multiple complex geometric shapes, more turns are needed to ensure that each part can obtain appropriate scattering enhancement.

[0071] Step S603, output the execution result to a preset database for integration.

[0072] Step S604, read the updated layout data corresponding to the sub - graph processed by itself in the preset database.

[0073] Step S605: Screen the seed scattering bars to obtain the scattering bars to be operated on, and perform a growing operation on the scattering bars to be operated on. This is because among the placed seed scattering bars, some may conflict with the target pattern, affecting the imaging quality. Not all of them can be directly used in the subsequent lithography process, so screening is required. The screening method generally selects the seed scattering bars that will not conflict with the current main pattern according to the mask manufacturing rules, or a dedicated conflict detection model can be established to detect the potential conflicts between the seed scattering bars and the target pattern using geometric calculations and lithography simulation techniques. This model calculates parameters such as the minimum distance and angular relationship between the seed scattering bars and the target pattern. If the distance between the seed scattering bar and the target pattern is less than the minimum spacing allowed by the lithography process, or their angular relationship will cause unnecessary interference or diffraction during lithography, then this seed scattering bar is determined to have a conflict. For example, when the minimum distance between a seed scattering bar and the target pattern is less than 50 nanometers (depending on the specific lithography process), it may be regarded as a conflict and needs to be excluded. After conflict detection, the seed scattering bars that will not conflict with the target pattern are screened out, and these screened scattering bars are the scattering bars to be operated on. They meet the basic requirements of the lithography process and can be safely used for subsequent operations to ensure that while enhancing the imaging of the target pattern, it will not have a negative impact on the target pattern itself.

[0074] Step S606: Output the execution result to a preset database for integration.

[0075] Step S607: Read the updated layout data corresponding to the sub-graph processed by itself in the preset database.

[0076] Step S608: Determine whether there are target scattering bars that violate the mask manufacturing rules among the scattering bars to be operated on after growth. Among them, the target scattering bar is a scattering bar with a square shape.

[0077] Step S609: In the case where the determination in Step S608 is yes, adjust the size and position of the target scattering bar. The purpose of the adjustment is to avoid violating the mask manufacturing rules while maintaining the square characteristics of the target scattering bar.

[0078] Step S610: In the case where the determination in Step S608 is no or after Step S608 is completed, output the execution result to a preset database for integration.

[0079] Figure 6The process shown is the placement process of scatter bars applying the full layout preview technology of the present invention. It automatically saves and loads global layout data using the full layout preview technology after each operation, avoiding the loss of sliced Tile boundary information. This can not only retain the advantage of distributed computing in improving the operation speed but also solve the MRC problem of scatter bar boundaries.

[0080] Through this method, it is possible to place and retain more scatter bars that meet the process parameters while ensuring the placement speed of scatter bars, thereby increasing the process window. And after each operation is completed, the global layout data is integrated and updated, which can avoid the loss of boundary information in the sub-graph, thus solving the problem that the boundaries of scatter bars violate the mask manufacturing rules.

[0081] It should be noted that the present invention does not limit the execution order and number of each operation in the scatter bar placement process. Those skilled in the art can determine the specific content of each operation in the scatter bar placement process according to the actual situation. However, the full layout preview technology of the present invention needs to be applied after each operation is completed. That is, after each operation is completed, the execution result is output to a preset database for integration. Subsequently, when each processor executes the next operation, it reads the updated layout data corresponding to the sub-graph it processes in the preset database, so as to ensure the accuracy of the boundary information in the sub-graph, avoid the repeated transmission of incomplete boundary information, and thus avoid the difficult-to-solve boundary MRC problem during boundary merging.

[0082] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be executed in any specific order, or that all operations of the method are included in every case. In addition, the method may include additional operations. Within the scope of the technical idea provided by the method in this embodiment, additional changes can be made to the above method.

[0083] It should be understood that in some embodiments, each part can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system.

[0084] This embodiment also provides a computer program product 10, a computer-readable storage medium 20, and a computer device 30. Figure 7 is a schematic diagram of a computer program product 10 according to an embodiment of the present invention, Figure 8 is a schematic diagram of a computer-readable storage medium 20 according to an embodiment of the present invention, Figure 9It is a schematic diagram of a computer device 30 according to an embodiment of the present invention. The computer program product 10 includes a computer program 11, and when the computer program 11 is executed by the processor 32, it implements the steps of any one of the above-mentioned scattering bar placement methods. The computer-readable storage medium 20 stores the above-mentioned computer program 11, and when the computer program 11 is executed by the processor 32, it implements the steps of the scattering bar placement method of any one of the above-mentioned embodiments. The computer device 30 may include a memory 31, a processor 32, and a computer program 11 stored on the memory 31 and running on the processor 32.

[0085] The computer program 11 for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, status setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer program 11 may be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., using an Internet service provider via the Internet). In some embodiments, in order to perform various aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing the status information of the computer-readable program instructions to personalize the electronic circuit.

[0086] For the description of this embodiment, the computer program product 10 is a related product containing the computer program 11. For the description of this embodiment, the computer-readable storage medium 20 is a tangible device capable of retaining and storing the computer program 11, which can be any device that can contain, store, communicate, propagate, or transmit the program 11 for use by an instruction execution system, apparatus, or device or in combination with these instruction execution systems, apparatuses, or devices. More specific examples (non-exhaustive list) of the computer-readable storage medium 20 include the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanically encoded device, and any suitable combination of the above.

[0087] The computer device 30 can be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smartphone. In some examples, the computer device 30 can be a cloud computing node. The computer device 30 can be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. The computer device 30 can be implemented in a distributed cloud computing environment where tasks are executed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0088] The computer device 30 can include a processor 32 suitable for executing stored instructions and a memory 31 that provides temporary storage space for the operation of the instructions during operation. The processor 32 can be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. The memory 31 can include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0089] The computer device 30 can also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows data to be input and output with external devices that can be connected to the computer device. The network adapter / interface can provide communication between the computer device and a network, which is typically shown as a communication network.

[0090] At this point, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications that conform to the principles of the present invention can still be directly determined or derived from the disclosed content of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and construed to cover all such other variations or modifications.

Claims

1. A scattering strip placement method, comprising: Acquire global layout data corresponding to the target semiconductor chip to be operated; Splitting the global layout data into a preset number of sub-graphs, and allocating the preset number of sub-graphs to a plurality of processors; The multiple processors gradually execute the scattering bar placement task on their respective sub-graphs, and after each step is completed, the execution results of the multiple processors are integrated. When executing the next step, each processor reads the layout data corresponding to the sub-graph processed by itself in the integrated global layout data.

2. The scattering strip placement method according to claim 1, wherein: The step of performing the scatter bar placement task on respective sub-graphs step by step by the plurality of processors comprises: Determine a target graphic in the sub-graph where a scattering bar needs to be placed; Placing a preset number of seed scattering strips outside the target pattern; Screening the seed scattering bars to obtain the scattering bars to be operated, wherein the scattering bars to be operated are the seed scattering bars that will not conflict with the target pattern; A growing operation is performed on the scattering strip to be operated.

3. The scattering strip placement method according to claim 2, wherein: The step of performing a growing operation on the scattering strip to be operated comprises: The growing operation is performed on the scattering strip to be operated according to preset manufacturing rules, wherein the preset manufacturing rules include: a manufacturable rule between the scattering strip to be operated and other scattering strips and a manufacturable rule between the scattering strip to be operated and the target pattern.

4. The scattering strip placement method according to claim 3, wherein: After the step of performing a growing operation on the scattering strip to be operated, the step further includes: Determining whether there is a target scattering strip that violates the mask manufacturing rule in the grown scattering strips to be operated, wherein the target scattering strip is a scattering strip with a square shape; If yes, the size and position of the target scattering strip are adjusted so that the target scattering strip avoids violating the mask manufacturing rules while maintaining the square feature.

5. The scattering strip placement method according to claim 1, wherein: The step of integrating the execution results of the plurality of processors comprises: after each step of the plurality of processors is completed, outputting the sub-graphs obtained by the processors to a preset database; integrating the layout data in the sub-graphs in the preset database and performing a design rule check to obtain the updated global layout data; The step in which each processor reads the layout data corresponding to the sub-image processed by itself in the integrated global layout data when executing the next operation includes: each processor reads the updated layout data of the sub-image processed by itself in the preset database; and continues to execute the next operation based on the updated layout data.

6. The scattering strip placement method according to claim 5, wherein: A version management mechanism for the global layout data is established in the preset database; After the step of integrating the execution results of the plurality of processors, the method further includes: generating a corresponding version identifier for the integrated global layout data.

7. The scattering strip placement method according to claim 1, wherein: After the step of the plurality of processors gradually performing the scatter bar placement task on the respective sub-graphs, the step further includes: Simulating abnormal exposure conditions to perform exposure inspection on the placed scattering strips; When the inspection result shows that the scattering strip has an exposure risk, the scattering strip is adjusted, and the adjustment includes one or more adjustment methods of offset, interruption and reduction operations.

8. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the scattering strip placement method according to any one of claims 1 to 7 are implemented.

9. A computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the scattering strip placement method according to any one of claims 1 to 7.

10. A computer device comprising a memory, a processor, and a machine executable program stored in the memory and running on the processor, wherein the processor implements the steps of the scattering strip placement method according to any one of claims 1 to 7 when executing the machine executable program.

Images