High bandwidth memory device and method of operating same

Abstract

An operating method of a high bandwidth memory (HBM) device includes receiving a mode register setup (MRS) command through a row command / address signal line in an idle mode, performing an MRS operation in response to the MRS command, receiving an active (ACT) command through the row command / address signal line in the idle mode, and switching to an active mode in response to the ACT command. Switching to the active mode includes switching one or more memory buffers of the HBM device to an active state.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0182026, filed with the Korean Intellectual Property Office on December 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure described herein relate to a semiconductor memory, and more particularly, to a high - bandwidth memory device and an operation method thereof. Background art

[0004] As the speed of a central processing unit (CPU) increases and the use of a graphics processing unit (GPU) or a neural processing unit (NPU) increases, there is an increasing need for a high - bandwidth memory device capable of keeping up with its speed. A typical example of a high - bandwidth memory device is a high - bandwidth memory (HBM) device. The high - bandwidth memory device may have a higher bandwidth than a conventional memory device and may provide data in line with the operating speed of the above - mentioned processors.

[0005] As the bandwidth of the high - bandwidth memory device gradually increases, the number of channels in the memory device may increase. To address the above - mentioned problem, the number of command / address (CA) buffers provided within the memory device channels for providing commands may increase. As the number of CA buffers increases, the current consumption of the CA buffers increases. Therefore, it is desirable to reduce the amount of current to improve the performance of the memory device. Summary of the invention

[0006] Embodiments of the present disclosure provide a memory system capable of improving the performance of a memory device by reducing the amount of current used by the memory device.

[0007] According to some embodiments, an operation method of a high - bandwidth memory (HBM) device includes receiving a mode register set (MRS) command through a row command / address signal line in an idle mode, performing an MRS operation in response to the MRS command, receiving an activate (ACT) command through the row command / address signal line in the idle mode, and switching to an active mode in response to the ACT command, wherein switching to the active mode includes switching one or more memory buffers of the HBM device to an active state.

[0008] According to some embodiments, a method of operating a high bandwidth memory (HBM) device includes selecting one of a first mode and a second mode in an idle mode, wherein a column command / address (CA) buffer configured to buffer column command / address signals is inactive in the first mode and active in the second mode, performing a mode register set (MRS) operation in the idle mode, and in the idle mode, receiving an activate (ACT) command via a row command / address signal line and switching to an active mode in response to the ACT command, wherein switching to the active mode includes setting one or more memory buffers of the HBM device to an active state.

[0009] According to some embodiments, a high bandwidth memory (HBM) device configured to store data includes a row command buffer buffering row command / address signals, a column command buffer buffering column command / address signals, a command / address (CA) buffer decoding the row command / address signals and the column command / address signals, and a memory cell array storing data, and the HBM device is configured to receive a mode register set (MRS) command and an activate (ACT) command via the row command / address signals. And the ACT command instructs to switch one or more memory buffers of the HBM device to an active state. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram showing a memory system according to some embodiments of the present disclosure.

[0012] Figure 2 is a detailed illustration of Figure 1 a memory device according to some embodiments of the present disclosure.

[0013] Figure 3 is a diagram showing Figure 2 the structure of a memory device according to some embodiments of the present disclosure.

[0014] Figure 4A is a diagram showing Figure 1 an example of a row command truth table of a memory system according to some embodiments of the present disclosure.

[0015] Figure 4B is a diagram showing Figure 1 an example of a column command truth table of a memory system according to some embodiments of the present disclosure.

[0016] Figure 5A is a diagram showing a memory device in an idle mode according to some embodiments of the present disclosureFigure 1 Block diagram of command / address (CA) unit

[0017] Figure 5B is a block diagram of a CA unit in an active mode of a memory device according to some embodiments of the present disclosure Figure 1 Block diagram of CA unit

[0018] Figure 6 is a flowchart showing an operation sequence of a memory system according to some embodiments of the present disclosure Figure 1 Flowchart of operation sequence of memory system

[0019] Figure 7 is a diagram showing an example of a row command truth table according to some embodiments of the present disclosure

[0020] Figure 8 is a detailed block diagram of a CA decoder according to some embodiments of the present disclosure Figure 1 Block diagram of CA decoder

[0021] Figure 9 is a diagram showing an example of a row command truth table of a memory system including a CA decoder according to some embodiments of the present disclosure Figure 1 Example of row command truth table of memory system including CA decoder

[0022] Figure 10 is a detailed block diagram of a CA decoder according to some embodiments of the present disclosure Figure 1 Block diagram of CA decoder

[0023] Figure 11 is a flowchart showing an operation sequence of a memory system according to some embodiments of the present disclosure Figure 1 Flowchart of operation sequence of memory system

[0024] Figure 12 is a block diagram of an electronic system according to some embodiments of the present disclosure Detailed Description of the Invention

[0025] Hereinafter, embodiments of the present disclosure will be described in detail and clearly so that those of ordinary skill in the art can easily implement the present disclosure

[0026] Figure 1 is a block diagram of a memory system according to some embodiments of the present disclosure. Referring to Figure 1 , the memory system 100 may include a host 110 and a memory device 120, and the host 110 may include a memory controller 115. The operation of the memory system 100 according to some embodiments of the present disclosure will be described with reference to Figure 1 Description of operation of memory system 100 according to some embodiments of the present disclosure

[0027] The memory system 100 can store data, manage the stored data, and provide information required by a user. In some embodiments, the memory system 100 may be included in an electronic device, such as a personal computer (PC), a laptop computer, a tablet PC, a personal digital assistant (PDA), a wearable device, or a camera. However, this is provided as an example, and the present disclosure is not limited to the case where the memory system 100 is included in the above-described electronic devices.

[0028] The host 110 may exchange data with the memory device 120. In some embodiments, the host 110 may send a request to the memory device 120 and may receive a response corresponding to the request from the memory device 120. For example, the host 110 may send a request through the memory controller 115 and may receive a response (e.g., data corresponding to the request) corresponding to the request through the memory controller 115. Figure 1 Some embodiments in which the host 110 is included in the memory system 100 are shown, but it should be understood that various embodiments in which the host 110 is located outside the memory system 100 are within the scope and spirit of the present invention.

[0029] The memory controller 115 may control the memory device 120. In some embodiments, the memory controller 115 may control the memory device 120 based on a plurality of signals. For example, the memory controller 115 may control the memory device 120 based on a row command / address (CA) signal R[9:0], a column command / address (CA) signal C[7:0], or a control signal CTRL. The command / address signal may indicate the row command / address signal R[9:0] or the column command / address signal C[7:0]. In some embodiments, the memory controller 115 may provide a clock CK required for the operation of the memory device 120 to the memory device 120. For example, the memory controller 115 may provide two clocks CK (e.g., CK_c and CK_t) required for the operation of the memory device 120.

[0030] In some embodiments, the memory controller 115 may exchange data “DATA” with the memory device 120. For example, in response to a request from the host 110, the memory controller 115 may write the data “DATA” into the memory device 120 or may read the data “DATA” from the memory device 120. Figure 1 Some embodiments in which the memory controller 115 is included in the host 110 are shown, but it should be understood that some embodiments in which the memory controller 115 is located outside the host 110 are also within the scope and spirit of the present invention.

[0031] The memory device 120 may store data of the memory system 100. In some embodiments, the memory device 120 may operate under the control of the memory controller 115. For example, the memory device 120 may operate in response to the row command / address signals R[9:0], the column command / address signals C[7:0], and the control signal CTRL of the memory controller 115. The row command / address signals R[9:0] will be described in detail with reference to Figure 4A and the column command / address signals C[7:0] will be described in detail with reference to Figure 4B . In some embodiments, the memory device 120 may operate synchronously with the host 110 or the memory controller 115. For example, the memory device 120 may operate synchronously with the clock CK received from the memory controller 115.

[0032] The memory device 120 may include multiple memory channels, and similarly, the host 110 may include multiple memory controllers 115. For example, the memory device 120 may include 16 memory channels. Each of the multiple memory channels of the memory device 120 may correspond to one of the memory controllers 115. For example, one memory channel of the memory device 120 may correspond to one memory controller 115, or one or more memory channels of the memory device 120 may correspond to one memory controller 115. Specifically, the memory device 120 may include 16 memory channels, and the host 110 may include 16 memory controllers 115 respectively corresponding to the memory channels.

[0033] Hereinafter, for convenience of description, the present disclosure will be described based on the memory system 100 in which one memory channel is included in the memory device 120 and the memory controller 115 controls one memory channel, but the present disclosure is not limited thereto. It should be understood that some embodiments of the memory system 100 including the memory device 120 having multiple memory channels and multiple memory controllers 115 controlling at least one memory channel also fall within the scope and spirit of the present invention.

[0034] In some embodiments, the memory device 120 may be a high-bandwidth memory device. For example, the memory device 120 may be a high-bandwidth memory (HBM) device or may include HBM. Hereinafter, a description will be given based on the case where the memory device 120 is an HBM device, but the present disclosure should not be limited thereto. For example, it should be understood that the technical concept of some embodiments to be described later can be applied to another type of memory device.

[0035] Figure 2 is a block diagram of a memory device Figure 1 detailedly showing some embodiments according to the present disclosure. Refer toFigure 2 ,the memory device 120 may include a memory cell array 121, a row command / address (CA) buffer 122, a column command / address (CA) buffer 123, a command / address (CA) decoder 124, a row decoder 125, a column decoder 126, and an input / output (I / O) circuit 127. Reference will be made to Figure 2 describe in detail the memory device 120 according to some embodiments of the present disclosure.

[0036] The memory cell array 121 may store data of the memory device 120. In some embodiments, the memory cell array 121 may read or write data depending on the address received from the CA decoder 124. For example, depending on the column address CADD and the row address RADD received from the CA decoder 124, the memory cell array 121 may write data to or read data from a relevant location. Reference will be made to Figure 3 describe in detail the detailed structure of the memory cell array 121.

[0037] The row CA buffer 122 may receive a row command / address signal R[9:0] from the memory controller 115. In some embodiments, the row CA buffer 122 may buffer the row command / address signal R[9:0]. For example, the row CA buffer 122 may buffer the row command / address signal R[9:0] and may generate a buffered row command / address signal BR[9:0]. The row CA buffer 122 may provide the buffered row command / address signal BR[9:0] to the CA decoder 124. Figure 2 The example in which each of the row command / address signal R[9:0] and the buffered row command / address signal BR[9:0] is a 10-bit signal is shown, but the present disclosure should not be limited thereto. Hereinafter, for convenience, a description will be given based on the case where the row command / address signal R[9:0] is a 10-bit signal and the buffered row command / address signal BR[9:0] is also a 10-bit signal.

[0038] The column CA buffer 123 may receive a column command / address signal C[7:0] from the memory controller 115. In some embodiments, the column CA buffer 123 may buffer the column command / address signal C[7:0]. For example, the column CA buffer 123 may buffer the column command / address signal C[7:0] and may generate a buffered column command / address signal BC[7:0]. The column CA buffer 123 may provide the buffered column command / address signal BC[7:0] to the CA decoder 124. Figure 2An example is shown in which each of the column command / address signals C[7:0] and the buffered column command / address signals BC[7:0] is an 8-bit signal, but the present disclosure should not be limited thereto. Hereinafter, for convenience, a description will be given based on the case where the column command / address signal C[7:0] is an 8-bit signal and the buffered column command / address signal BC[7:0] is also an 8-bit signal.

[0039] The CA decoder 124 may decode the CA signal. The buffered column command / address (CA) signal may indicate the buffered row command / address signal BR[9:0] or the buffered column command / address signal BC[7:0]. The CA decoder 124 may decode the received CA signal to decode the CA signal. In some embodiments, the CA decoder 124 may decode the buffered CA signal to provide an address value to the memory cell array 121 or to allow the memory device 120 to perform an operation indicated by a command received via a command signal. For example, the CA decoder 124 may receive and decode the buffered row command / address signal BR[9:0] generated based on the row command / address signal R[9:0] corresponding to the self-refresh command, and may allow the memory device 120 to perform a self-refresh operation.

[0040] The row decoder 125 may provide access to the row elements of the memory cell array 121. For example, the row decoder 125 may access the row elements of the memory cell array 121 based on the row address RADD from the CA decoder 124. The column decoder 126 may provide access to the column elements of the memory cell array 121. For example, the column decoder 126 may access the column elements of the memory cell array 121 based on the column address CADD from the CA decoder 124. In some embodiments, the row address RADD or the column address CADD may include information (e.g., a bank address) of the bank in the memory cell array 121 to be accessed.

[0041] The input / output circuit 127 may also control data input / output of the memory cell array 121. The input / output circuit 127 may provide data (e.g., via the memory controller 115) in response to a request from Figure 1 the host 110. In some embodiments, the input / output circuit 127 may temporarily store data read from the memory cell array 121 or data to be written to the memory cell array 121. For example, the input / output circuit 127 may also temporarily store data received from the storage controller 115 to be written to the memory cell array 121.

[0042] Figure 3 is a diagram showing the structure of a Figure 2 memory device according to some embodiments of the present disclosure. Refer to Figure 3, the memory device 120 may include a base die BD and a memory cell array 121. According to some embodiments of the present disclosure, reference will be made to Figure 3 to describe the structure on the semiconductor substrate of the memory device 120.

[0043] The memory cell array 121 may include memory dies MD1 to MD4 sequentially stacked on the base die BD in a vertical direction perpendicular to the top surface of the base die BD. The memory dies MD1 to MD4 may store data. Each of the memory dies MD1 to MD4 may include a terminal MB. For example, the terminal MB may be a micro-bump. Each of the terminals MB may include a data terminal for exchanging data with the memory dies MD1 to MD4, and may include a command / address terminal for performing access to the memory dies MD1 to MD4.

[0044] The memory cell array 121 may exchange data with the base die BD through the data terminals among the terminals MB. The memory cell array 121 may receive command / address information (e.g., internal addresses of the memory dies MD1 to MD4, at which the operation indicated by the command will be performed) through the command / address terminals among the terminals MB. The memory cell array 121 may include through-silicon vias TSVs that connect the terminals MB to the base die BD in the vertical direction and penetrate or extend into the memory dies MD1 to MD4.

[0045] The base die BD may provide command / address information or data to the memory cell array 121. In some embodiments, the base die BD may include Figure 2 a row CA buffer 122, a column CA buffer 123, a CA decoder 124, a row decoder 125, a column decoder 126, or an input / output circuit 127. The base die BD may receive the row command / address signal R[9:0], the column command / address signal C[7:0], the control signal CTRL, the clock CK, or the data “DATA” to be stored, as described with reference to Figure 1 from the memory controller 115, and may output the data “DATA” to the memory controller 115 or receive the data “DATA” from the memory controller 115. Figure 1 described, and may output the data “DATA” to the memory controller 115 or receive the data “DATA” from the memory controller 115.

[0046] Reference Figure 3 to the structure on the semiconductor substrate of the memory device 120 described is an example, and the present disclosure should not be limited thereto. It should be understood that the general structure of the semiconductor substrate of HBM also belongs to the scope and spirit of the present invention.

[0047] Figure 4A is a diagram showing a row command truth table RCT according to some embodiments of the present disclosure, andFigure 4B FIG. is a diagram showing a column command truth table CCT according to some embodiments of the present disclosure. Figure 4A and Figure 4B may be collectively referred to as "FIG. 4", and the command truth table may indicate a row command truth table RCT or a column command truth table CCT.

[0048] Referring Figure 4A and Figure 4B , values of each bit corresponding to the CA signal and commands of the clock timing are shown, as well as addresses of the memory cell array 121 that executes the commands. The clock timing may be Figure 2 either the rising (R) edge (or timing) or the falling (F) edge (or timing) of one of the clocks CK. In Figure 4A and Figure 4B , the shaded bit values among the bit values of each CA signal may correspond to the bits for identifying the commands transmitted through the CA signal. Reference will be made to Figure 1 , Figure 4A and / or Figure 4B to describe examples of the command truth table according to some embodiments of the present disclosure. In Figure 4A and Figure 4B and the following drawings, "H" may indicate a logic high, "L" may indicate a logic low, and "V" may indicate any valid signal (i.e., don't care). In Figure 4A and Figure 4B , BA0, BA1, BA2, and BA3 may respectively indicate the values of the bits constituting the bank address (i.e., the bank address may be a 4-bit address, and BA3 may be the most significant bit (MSB) of the bank address). PC may indicate the selected pseudo-channel, and SID may mean stack ID. PC and SID may be used to identify one of the multiple banks and the bank addresses BA0, BA1, BA2, and BA3. RA0 to RA14 may respectively indicate the values of the bits constituting the row address, and CA0 to CA4 may respectively indicate the values of the bits constituting the column address.

[0049] Referring Figure 4A , the memory device 120 may receive a row command / address signal R[9:0] corresponding to a precharge (PREpb) command at the rising (R) or falling (F) edge of the clock. The row command / address signal R[9:0] corresponding to the precharge command may provide a command through the 0th row bit R[0] to the second row bit R[2] (R[2:0] = LLH), and may provide Figure 2 the location of the operation to be performed on the memory cell array 121 of. Similarly, for another example, an activation (ACT) operation may be performed through the rising (R), falling (F), and rising (R) timings of the clock, and may depend on the corresponding clock timing when receivingFigure 4A When the row command / address signal R[9:0] shown in

[0050] Reference Figure 4B , the memory device 120 can receive the column command / address signal C[7:0] corresponding to the read command at the rising (R) and falling (F) timings of the clock. For example, the column command / address signal C[7:0] corresponding to the read command can provide the read command through the 0th column bit C[0] to the third column bit C[3] at the rising (R) edge of the clock, and can provide the location where the operation will be performed through the remaining column bits C[4:7] and the entire column command / address signal C[7:0] received at the falling (F) edge. Similar to the read operation, the write operation can also be performed through the rising (R) and falling (F) timings of the clock, and can be performed when receiving Figure 4B the bits of the column command / address signal C[7:0] shown in

[0051] It should be understood that Figure 4A and Figure 4B shown in Figure 4A and Figure 4B The commands described are provided as examples. The row command truth table RCT can include the clock timings and bit values of the row command / address signal R[9:0] corresponding to any other operation other than the above operations. Specifically, the row command truth table RCT can include the mapping between the bit positioning and clock timings of the row command / address signal R[9:0] and the command or the location where the operation indicated by the command will be performed. Similarly, the column command truth table CCT can include the clock timings and bit values of the column command / address signal C[7:0] corresponding to any other operation other than the above operations. In detail, the column command truth table CCT can include the mapping between the bit positioning and clock timings of the column command / address signal C[7:0] and the command and the location where the operation indicated by the command will be performed. Based on various combinations of the bits of the row command / address signal R[9:0] or the column command / address signal C[7:0], the memory controller 115 can specify the operation of the memory device 120 or can control the memory device 120, and can provide the location (e.g., address) where the operation will be performed on the memory cell array 121.

[0052] For ease of description, the CA signal can indicate the row command / address signal R[9:0] or the column command / address signal C[7:0], the buffered CA signal can indicate the buffered row command / address signal BR[9:0] or the buffered column command / address signal BC[7:0], and the CA buffer can indicate the row CA buffer 122 or the column CA buffer 123.

[0053] Memory device 120 may provide an idle mode or an active mode. In memory device 120, a transition from the idle mode to the active mode may be made through an activation operation, and a transition from the active mode to the idle mode may be made through a precharge operation. A first operation may indicate an operation to be performed by memory device 120 in the idle mode, and a second operation may indicate an operation to be performed by memory device 120 in the active mode. For example, the first operation includes a mode register set (MRS) operation, an activation operation, etc. The second operation may include a read operation, a write operation, etc. A third operation may indicate an operation to be included in both the first operation and the second operation. The third operation may include a precharge (PREpb or PREab) operation or a power down enter or power down exit (PDE or PDX) operation, etc.

[0054] Referring together Figure 1 、 Figure 2 、 Figure 4A and Figure 4B , memory device 120 may receive a CA signal and may generate a buffered CA signal through a corresponding CA buffer. In this case, the current consumption of the CA buffer may account for a significant portion of the entire current consumption of memory device 120. The current consumption may cause an increase in heat generation of memory device 120 and may cause a decrease in the performance of memory device 120. In addition, a current consumption exceeding the limit of the device for testing memory device 120 may impede the smooth testing of memory device 120. Hereinafter, a memory device 120 capable of reducing the amount of current consumed during operation and providing a smooth test will be described with reference to the accompanying drawings.

[0055] Figure 5A is a block diagram of a command / address (CA) unit 200 when Figure 2 memory device 120 according to some embodiments of the present disclosure is in the idle mode, and Figure 5B is a block diagram of CA unit 200 when Figure 2 memory device 120 according to some embodiments of the present disclosure is in the active mode. CA unit 200 may correspond to Figure 2 CA unit CA of Figure 5A and Figure 5B may be collectively referred to as "Figure 5". Referring to Figure 5A and Figure 5B , CA unit 200 may include a row CA buffer 210, a column CA buffer 220, and a CA decoder 230. CA unit according to some embodiments of the present disclosure will be described with reference to Figure 5A and Figure 5B .

[0056] Row CA buffer 210 may correspond to Figure 2Row CA buffer 122. The row CA buffer 210 may receive the row command / address signal R[9:0] and may buffer the received row command / address signal R[9:0] to generate a buffered row command / address signal BR[9:0]. In some embodiments, the row CA buffer 210 may be activated regardless of the state of the memory device 120. For example, referring to Figure 5A and Figure 5B , the row CA buffer 210 may be active in both the idle mode and the active mode. That is, an operating voltage may be applied to the row CA buffer 210, and current may flow within the row CA buffer 210.

[0057] The column CA buffer 220 may correspond to Figure 2 the column CA buffer 123. The column CA buffer 220 may receive the column command / address signal C[7:0] and may buffer the received column command / address signal C[7:0] to generate a buffered column command / address signal BC[7:0]. In some embodiments, whether the column CA buffer 220 is activated may be determined according to the memory state. For example, referring to Figure 5A , when the memory device 120 is in the idle mode, the column CA buffer 220 may be in an inactive state. That is, an operating voltage is not applied to the column CA buffer 220 such that current may not flow within the column CA buffer 220. Referring to Figure 5B , when the memory device 120 is in the active mode, the column CA buffer 220 may be in an active state. When the column CA buffer 220 is in the inactive state, the column CA buffer 220 may not be able to generate a buffered column command / address signal BC[7:0].

[0058] The CA decoder 230 may correspond to Figure 2 the CA decoder 124. The CA decoder 230 may receive the buffered CA signal and may decode the received buffered CA signal. In this case, the CA decoder 230 may allow the memory device 120 to perform an operation indicated by a command corresponding to the CA signal, or may provide a row address RADD and a column address CADD to the row decoder 125 and the column decoder 126, respectively, such that a position on the memory cell array 121 indicated by the CA signal is selected.

[0059] Figure 6 is a flowchart showing an operation sequence of Figure 1 the memory system 100 according to some embodiments of the present disclosure. The operation sequence of the memory system 100 according to some embodiments of the present disclosure will be described with reference to Figure 1 , Figure 5A , Figure 5B and Figure 6 .

[0060] In operation S110, the memory system 100 may be powered on. In some embodiments, after the memory device 120 is powered on, the memory device 120 may enter an idle state depending on a given sequence. For example, after the memory device 120 is powered on, the memory device 120 may enter an idle mode through a reset process. In some embodiments, when the memory device 120 enters the idle mode, the memory device 120 may set the CA buffer to an active state. For example, as Figure 5A shown, the memory device 120 may allow the row CA buffer 210 to be in an active state and may maintain the column CA buffer 220 in an inactive state.

[0061] In operation S120, the memory device 120 may perform an MRS operation in the idle mode. Operation S120 may include operations S121, S122, S123, and S124. In some embodiments, the memory device 120 may include a CA unit 200 set in the idle mode as shown by Figure 5A the figure. The description is based on the case where the memory device 120 performs an MRS operation, Figure 6 but this is provided as an example. It should be understood that the first operation of the memory device 120 can be performed according to the order of operation S120.

[0062] In operation S121, the memory controller 115 may send the row command / address signals R[9:0] corresponding to the MRS command to the memory device 120. Similarly, the memory controller 115 may send the row command / address signals R[9:0] corresponding to a command indicating a first operation different from the MRS operation to the memory device 120 in the same manner.

[0063] In operation S122, the memory device 120 may receive the row command / address signals R[9:0] corresponding to the MRS command. Similarly, the memory device 120 may receive the row command / address signals R[9:0] corresponding to a command indicating a first operation other than the MRS operation in the same manner.

[0064] In operation S123, the memory device 120 may decode the row command / address signal R[9:0] corresponding to the MRS command. In some embodiments, the memory device 120 may decode the row command / address signal R[9:0] corresponding to the MRS command through the CA decoder 230. For example, the memory device 120 may decode the MRS command by generating a buffered row command / address signal BR[9:0] corresponding to the MRS command via the row CA buffer 210 and decoding the buffered row command / address signal BR[9:0] via the CA decoder 230. Similarly, the memory device 120 may decode the row command / address signal R[9:0] corresponding to a command indicating a first operation other than the MRS operation in the same manner.

[0065] In operation S124, the memory device 120 may perform the MRS operation based on the decoding result. Similarly, the memory device 120 may perform the first operation other than the MRS operation in the same manner.

[0066] The memory device 120 may perform the first operation including the MRS operation until operation S120. In operation S120, the memory device 120 may perform the first operation when the column CA buffer 220 is in an inactive state, and thus, the amount of current unnecessarily consumed by the column CA buffer 220 may be reduced. Compared with a memory device that receives the MRS command through the column command / address signal C[7:0], the memory device 120 according to some embodiments of the present disclosure may reduce the current consumption of the CA buffer. The memory system 100 may repeat operation S120 or may proceed to operation S130 after operation S120.

[0067] In operation S130, the memory device 120 may be activated. Operation S130 may include operation S131 and operation S132. In operation S130, the memory device 120 may be activated and may enter the active mode.

[0068] In operation S131, the memory controller 115 may send an activate (ACT) command to the memory device 120. In some embodiments, the memory controller 115 may send the row command / address signal R[9:0] corresponding to the activate command to the memory device 120. For example, the memory controller 115 may send the row command / address signal R[9:0] corresponding to the activate (ACT) command described in the reference Figure 4A during 1.5 cycles of the clock.

[0069] In operation S132, the memory device 120 may perform an activation operation in response to an activation command. For example, the memory device 120 may perform the activation operation by decoding the row command / address signal R[9:0] corresponding to the activation command via the CA decoder 230. In operation S133, the memory device 120 may allow the column CA buffer 220 to enter an active state. For example, in response to the activation command, the memory device 120 may allow the column CA buffer 220 to enter an active state. For ease of description, operations S132 and S133 are disclosed sequentially, and the present disclosure is not limited thereto. For example, it should be understood that in some embodiments, operations S132 and S133 can be performed simultaneously, or the order of operations S132 and S133 can be changed.

[0070] After operation S130 ends, the memory device 120 may set all CA buffers to an active state. That is, the CA unit 200 of the memory device 120 may be the same as the CA unit 200 described with reference Figure 5B to. The memory system 100 may proceed to operation S140.

[0071] In operation S140, the memory device 120 may be in an activation mode and may perform a second operation. Operation S140 may include operations S141, S142, S143, and S144. In some embodiments, the memory device 120 may include a CA unit 200 set as shown in operation S140 Figure 5B by.

[0072] In operation S141, the memory controller 115 may send a command indicating the second operation to the memory device 120. In some embodiments, the memory controller 115 may send a command indicating the second operation to the memory device 120 via the row command / address signal R[9:0] or the column command / address signal C[7:0]. For example, the memory controller 115 may send the column command / address signal C[7:0] corresponding to a read command to the memory device 120, and may send the row command / address signal R[9:0] corresponding to a precharge command to the memory device 120.

[0073] In operation S142, the memory device 120 may receive a command indicating the second operation. For example, the memory device 120 may receive the row command / address signal R[9:0] or the column command / address signal C[7:0] corresponding to a command indicating the second operation from the memory controller 115.

[0074] In operation S143, the memory device 120 may decode a command indicating a second operation. In some embodiments, the memory device 120 may decode a command indicating a second operation through the CA decoder 230. For example, the memory device 120 may decode a command indicating a second operation by generating a buffered CA signal from a CA signal corresponding to the command indicating the second operation via the CA buffer and decoding the buffered CA signal via the CA decoder 230.

[0075] In operation S144, the memory device 120 may perform a second operation based on the decoding result. For example, the memory device 120 may perform a read operation or a write operation corresponding to the decoding result.

[0076] In some embodiments, after operation S140 ends, the memory device 120 may proceed to operation S120 while entering an idle mode. In this case, the CA unit 200 of the memory device 120 may switch from Figure 5B the state of the CA unit 200 of Figure 5A to the state of the CA unit 200 of

[0077] Figure 7 FIG. is a diagram showing a row command truth table RCT of a memory system according to some embodiments of the present disclosure. Some embodiments of the row command / address signal R[9:0] indicating the MRS operation and the row command / address signal R[9:0] of the first operation will be described with reference to Figure 6 and Figure 7 FIG.

[0078] Referring to Figure 7 FIG., a row command truth table RCT of the MRS operation and the precharge all (PREab) operation is shown. In Figure 7 and hereinafter, MA0, MA1, MA2, MA3, and MA4 may indicate bits corresponding to the address values of the mode registers to be set (e.g., MA4 is the MSB of the address value of the mode register), and OP0, OP1, OP2, OP3, OP4, OP5, OP6, and OP7 may indicate values to be set in the respective mode registers.

[0079] The MRS operation can be performed by the rising (R) and falling (F) timings of a clock. The row command / address signal R[9:0] corresponding to the MRS command can indicate the MRS operation to row bits R[2:0] from row 0 to the second row and row bit R[8] at the rising (R) timing of the clock, and can indicate the MRS operation to row bits R[2:0] from row 0 to the second row at the falling (F) timing of the clock (R[2:0]=HLH). The row command / address signal R[9:0] corresponding to the MRS command can provide the mode register addresses MA0, MA1, MA2, MA3, and MA4 to be set and the values OP0, OP1, OP2, OP3, OP4, OP5, OP6, and OP7 to be set at the rising (R) and falling (F) timings of the clock through the remaining bits other than the above bits.

[0080] Reference Figure 7 The row command / address signal R[9:0] described is provided as an example, and the present disclosure is not limited to Figure 7 the truth table illustrated therein. It should be understood that any row command truth table RCT of the row command / address signal R[9:0] that allows the memory system 100 to perform the operations described with reference to FIGS. 5 and Figure 6 is within the scope and spirit of the present invention. In some embodiments, the truth table of the row command / address signal R[9:0] can include the clock timing and bit values of the row command / address signal R[9:0] corresponding to a command indicating a first operation.

[0081] Reference FIGS. 5 to Figure 7 describes an embodiment of setting the CA unit 200 included in the memory device 120 as shown in Figure 5B the activation mode, but the present disclosure is not limited thereto. The memory device 120 can include a CA unit 200 set to the idle mode as shown in Figure 5A the activation mode, the memory device 120 can include a row CA buffer 210 in an inactive state and a column CA buffer 220 in an active state. In this case, in operation S130, after the activation operation, the memory system 100 can allow the row CA buffer 210 to enter the inactive state while changing the state of the column CA buffer 220 to the active state. In addition, reference Figure 4BThe truth table describing the column command / address signals C[7:0] may further include the clock timing of each of the commands indicating the third operation and the bit values or information of the column command / address signals C[7:0] indicating the third operation. That is, in the memory system 100, in operation S140, only the column CA buffer 220 may be active. After that, when the memory device 120 enters the idle mode (i.e., when the memory device 120 returns to operation S120), the memory device 120 may change the state of the row CA buffer 210 to active and may change the state of the column CA buffer 220 to inactive. Thus, compared with the embodiment described with reference to Figure 6 the current consumption of the CA buffer during all operations can be further reduced in the memory device 120.

[0082] Referring to FIGS. 5 to Figure 7 the described memory system 100 can remove or reduce the current consumption of the column CA buffer 220 in the idle mode by allowing the column CA buffer 220 to remain inactive in the idle mode. This can mean reducing the current consumption during all operations of the memory system 100. In other words, this can mean reducing the heat generation during all operations of the memory system 100. Also, in the memory system 100, even if the number of memory controllers 115 and the number of channels of the memory devices 120 increase, the increase in current can be reduced during the operation of the memory system 100. As another example, the memory system 100 can allow the test of the memory system 100 to be performed more effectively by referring to the operations described with reference to FIGS. 5 to Figure 7 and thus, the performance of the operation of the memory system 100 can be improved.

[0083] Hereinafter, for ease of description, referring together to Figure 1 , the memory device 120 may include a first mode and a second mode. In the case of the first mode, the memory device 120 may include the CA unit 200 set as shown in Figure 5A in the idle mode and may include the CA unit 200 set as shown in Figure 5B in the active mode. In the case of the second mode, in both the idle mode and the active mode, the memory device 120 may include as shown in Figure 5BThe CA unit 200 set as shown. In the case of the first mode, the memory device 120 may receive a command indicating a first operation through the row command / address signal R[9:0]. For example, the memory device 120 may receive a command indicating an MRS operation through the row command / address signal R[9:0] in the first mode. In the case of the second mode, the memory device 120 may receive a command indicating a first operation through the row command / address signal R[9:0] or the column command / address signal C[7:0]. For example, the memory device 120 may receive a command indicating an MRS operation through the column command / address signal C[7:0] in the second mode. In some embodiments, the memory device 120 may switch between the first mode and the second mode under the control of the memory controller 115. In some embodiments, the memory device 120 may switch between the first mode and the second mode in response to the control signal CTRL of the memory controller 115. In some embodiments, the memory device 120 may switch between the first mode and the second mode based on the MRS operation.

[0084] Figure 8 is a block diagram showing a CA decoder according to some embodiments of the present disclosure. The CA decoder 300 may correspond to Figure 2 the CA decoder 124. Referring to Figure 8 , the CA decoder 300 may include a decoding circuit 310 and a selection circuit 320. The CA decoder 300 according to some embodiments of the present disclosure will be described with reference to Figure 2 and Figure 8 .

[0085] The decoding circuit 310 may decode the buffered CA signal. The decoding circuit 310 may include a row command / address (CA) decoding circuit 311 and a column command / address (CA) decoding circuit 312. The row CA decoding circuit 311 may decode the buffered row command / address signal BR[9:0] received from the row CA buffer 122, and may allow the memory device 120 to perform an operation indicated by a command corresponding to the row command / address signal R[9:0]. The column CA decoding circuit 312 may decode the buffered column command / address signal BC[7:0] received from the column CA buffer 123, and may allow the memory device 120 to perform an operation indicated by a command corresponding to the column command / address signal C[7:0].

[0086] In some embodiments, the column CA decoding circuit 312 may receive and decode the selection signal SE[7:0] from the selection circuit 320. For example, the column CA decoding circuit 312 may decode the selection signal SE[7:0] and may allow the memory device 120 to perform an operation corresponding to the command used to generate the selection signal SE[7:0]. The selection signal SE[7:0] will be described in detail through the selection circuit 320.

[0087] The selection circuit 320 can selectively transfer the buffered row command / address signal BR[9:0] from the row CA buffer 122 to the row CA decoding circuit 311 or the column CA decoding circuit 312. In some embodiments, the selection circuit 320 can operate in response to Figure 1 the control signal CTRL of the memory controller 115. For example, in response to the control signal CTRL, the selection circuit 320 can transfer the received buffered row command / address signal BR[9:0] to the row CA decoding circuit 311 or the column CA decoding circuit 312.

[0088] In some embodiments, the selection circuit 320 can generate a selection signal SE[7:0] having the same bit length as the column command / address signal C[7:0] based on the buffered row command / address signal BR[9:0] for providing to the column CA decoding circuit 312. For example, the selection circuit 320 can generate the remaining bits of the buffered row command / address signal BR[9:0] except for the ninth bit BR[9] and the eighth bit BR[8] as the selection signal SE[7:0], and can provide the generated selection signal SE[7:0] to the column CA decoding circuit 312. Specifically, to allow the memory device 120 to perform the MRS operation, the selection circuit 320 can generate the selection signal SE[7:0] based on the buffered row command / address signal BR[9:0] indicating the MRS operation for providing it to the column CA decoding circuit 312.

[0089] Providing the generation of the selection signal SE[7:0] from the buffered row command / address signal BR[9:0] is an example, and the present disclosure should not be limited thereto. For another example, the selection circuit 320 can generate the selection signal SE[7:0] by excluding the eighth bit BR[8] and the first bit BR[1] of the buffered row command / address signal BR[9:0].

[0090] Figure 9 is a diagram showing an example of a truth table of row commands corresponding to a first operation according to some embodiments of the present disclosure. Refer to Figure 9 , a truth table MRS of the row command / address signal R[9:0] indicating the MRS operation of the first operation is shown. In Figure 9 , the shaded bit values may mean the values of the bits specifying a certain command. According to some embodiments, the operation commands of the memory device 120 corresponding to the CA decoder 300 including Figure 9 will be described with reference to Figure 8 .

[0091] Refer to Figure 9, the MRS operation can be performed by the rising (R) and falling (F) edges of the clock. The 0th to second row bits R[2:0] of the row command / address signal R[9:0] indicating the MRS operation can indicate the MRS operation at the rising (R) edge (R[2:0]=LLL) of the clock. The row command / address signal R[9:0] indicating the MRS operation can provide the address of the mode register to be set and the value to be set through the 0th to seventh row bits R[7:0] at the falling (F) edge of the clock and the third to seventh row bits R[7:3] at the rising (R) edge of the clock.

[0092] Reference together Figure 8 , can be done by using the row command / address signal R[9:0] Figure 9 The MRS command is provided to the memory device 120. The MRS command can be provided to the selection circuit 320 in the form of a buffered row command / address signal BR[9:0] through the row CA buffer 210 so as to be generated as a selection signal SE[7:0] by the selection circuit 320 and the control signal CTRL, and the selection signal SE[7:0] thus generated can be provided to the column CA decoding circuit 312. In some embodiments, Figure 9 , the remaining bits of the MRS command except the bit "V" may be the same as those of the column command / address signal C[7:0] corresponding to the command indicating the MRS operation. For example, the 0th to 7th row bits R[7:0] of the row command / address signal R[9:0] corresponding to the MRS operation may be the same as those of the column command / address signal C[7:0] corresponding to the MRS operation.

[0093] As an example, the corresponding MRS operation Figure 9 The row command / address signal R[9:0] of the MRS command is not limited thereto. It should be understood that any truth table MRS for the MRS command, in which the remaining bits except the bit "V" can be the same as those of the column command / address signal C[7:0] corresponding to the MRS operation, belongs to the scope and spirit of the present invention. Moreover, it should be understood that the above-described embodiment can be applied to the first operation other than the MRS operation.

[0094] Figure 10 is a block diagram illustrating in detail the CA decoder 400 according to some embodiments of the present disclosure.

[0095] The CA decoder 400 may correspond to Figure 2 CA decoder 124. Reference Figure 10 , CA decoder

[0096] 400 may include a decoding circuit 410 and a selection circuit 420. Figure 2 and Figure 10Describe the CA decoder 400 according to some embodiments of the present disclosure.

[0097] The decoding circuit 410 may decode a command to allow an operation indicated by the command to be performed by the memory device 120, or may decode a command to specify a location of the memory cell array 121 where the operation indicated by the command will be performed.

[0098] The decoding circuit 410 may include a row CA decoding circuit 411 and a column CA decoding circuit 412. The row CA decoding circuit 411 may receive buffered row command / address signals BR[9:0] corresponding to a command from the row CA buffer 122, and may decode the received buffered row command / address signals BR[9:0] to allow the memory device 120 to perform an operation indicated by the command.

[0099] The column CA decoding circuit 412 may receive selection signals SE[7:0] from the selection circuit 420, and may decode the received selection signals SE[7:0] to allow the memory device 120 to perform an operation indicated by a command corresponding to the selection signals SE[7:0]. In some embodiments, the selection signals SE[7:0] may be generated based on one of the buffered column command / address signals BC[7:0] and the buffered row command / address signals BR[9:0]. The selection signals SE[7:0] will be described in detail together with the selection circuit 420.

[0100] The selection circuit 420 may generate selection signals SE[7:0] based on one of the buffered row command / address signals BR[9:0] and the buffered column command / address signals BC[7:0]. In some embodiments, the selection circuit 420 may operate in response to a control signal CTRL received from Figure 1 the memory controller 115. For example, the selection circuit 420 may generate selection signals SE[7:0] based on one of the buffered row command / address signals BR[9:0] and the buffered column command / address signals BC[7:0] in response to the control signal CTRL, and may provide the generated selection signals SE[7:0] to the column CA decoding circuit 412.

[0101] In some embodiments, the selection circuit 420 may generate a selection signal SE[7:0] having the same bit length as the buffered column command / address signal BC[7:0] based on the buffered row command / address signal BR[9:0] for providing to the column CA decoding circuit 412. For example, the selection circuit 420 may generate the remaining bits of the buffered row command / address signal BR[9:0] except the eighth and ninth buffered row bits BR[9:8] as the selection signal SE[7:0], and may provide the generated selection signal SE[7:0] to the column CA decoding circuit 412. Specifically, the selection circuit 420 may receive the buffered row command / address signal BR[9:0] corresponding to Figure 9 the MRS command, and may generate a selection signal SE[7:0] corresponding to the MRS command for providing to the column CA decoding circuit 412.

[0102] Providing the change from the buffered row command / address signal BR[9:0] to the selection signal SE[7:0] is taken as an example, and the present disclosure should not be limited thereto. For another example, other bits of BR[9:0] may be excluded, such as the selection circuit 320 may generate the selection signal SE[7:0] by excluding the seventh bit BR[7] and the fourth bit BR[4] of the buffered row command / address signal BR[9:0].

[0103] Figure 11 is a flowchart showing an operation sequence of a memory system 100 including a Figure 2 memory device 120 according to some embodiments of the present disclosure, Figure 2 the memory device 120 includes a Figure 8 CA decoder 300 or Figure 10 a CA decoder 400. Reference will be made to Figure 1 Figure 4, Figure 5, and Figures 8 to 11 Figure 6 to describe the operation sequence of the memory system 100 according to some embodiments of the present disclosure.

[0104] In operation S210, the memory system 100 may be powered on. Similar to Figure 6 operation S110, the memory device 120 may enter the idle mode depending on a given sequence. In some embodiments, when the memory device 120 enters the idle mode, the memory device 120 may set the CA buffer to an active state. For example, as Figure 5A illustrated in Figure 4, the memory device 120 may set only the row CA buffer 210 to the active state.

[0105] In operation S220, the memory system 100 may select one of a first mode and a second mode of the memory device 120. Operation S220 may include operation S221, operation S222, and operation S223.

[0106] In operation S221, the memory controller 115 may send a mode selection signal to the memory device 120. In some embodiments, the mode selection signal may be included in the control signal CTRL. In some embodiments, the memory controller 115 may send the mode selection signal to the memory device 120 through the CA decoder 230. For example, the memory controller 115 may send the control signal CTRL including the mode selection signal to the CA decoder 230.

[0107] In operation S222, the memory device 120 may select an operation mode (e.g., a first mode or a second mode) in response to the mode selection signal. In some embodiments, the memory device 120 may determine the active state of the CA buffer of the memory device 120 in response to the mode selection signal. For example, when the memory device 120 receives the mode selection signal corresponding to the first mode, the memory device 120 may enter the first mode.

[0108] The memory device 120 may set the active state of the CA buffer differently depending on the first mode or the second mode. For example, when the memory device 120 enters the first mode, such as Figure 5A the CA unit 200, the memory device 120 may allow the row CA buffer 210 to be set to the active state and may allow the column CA buffer 220 to be set to the inactive state. For another example, when the memory device 120 enters the second mode, such as Figure 5B the CA unit 200, the memory device 120 may allow the row CA buffer 210 and the column CA buffer 220 to be set to the active state.

[0109] In operation S223, the memory system 100 may execute programs differently depending on whether the memory device 120 enters the first mode or the second mode. When the memory device 120 enters the first mode, the memory system 100 may execute operation S230, and when the memory device 120 enters the second mode, the memory system 100 may execute operation S240.

[0110] In operation S230, the memory device 120 may perform an MRS operation in the first mode. Operation S230 may include operation S231 and operation S232. Operation S230 will be described based on the MRS operation, but it should be understood that the first operation of the memory device 120 is the same as the MRS operation or can be performed in a method similar to the method of the MRS operation.

[0111] In operation S231, the memory controller 115 may send the row command / address signal R[9:0] corresponding to the MRS command to the memory device 120. Similarly, the memory controller 115 may send the row command / address signal R[9:0] indicating a first operation other than the MRS operation to the memory device 120.

[0112] In operation S232, the memory device 120 may perform the MRS operation by decoding the row command / address signal R[9:0] corresponding to the MRS operation. For example, the memory device 120 may perform the MRS operation by decoding the row command / address signal R[9:0] corresponding to the MRS command via the row CA buffer 210 and the CA decoder 230. Similarly, the memory device 120 may perform the first operation other than the MRS operation in the same or similar manner as the above method.

[0113] In some embodiments, the memory device 120 may use the reference Figure 8 or Figure 10 described CA decoder 300 or 400 to decode the MRS command received through the row command / address signal R[9:0], and may allow the memory device 120 to perform the MRS operation. In some embodiments, the memory device 120 may perform the MRS operation in the same or similar manner as the method described in operations S122, S123, and S124 of the reference Figure 6 . After operation S230, the memory system 100 may repeat operation S230 again or may proceed to operation S250.

[0114] In operation S240, the memory device 120 may perform the MRS operation in a second mode. In some embodiments, the memory device 120 may receive the column command / address signal C[7:0] corresponding to the MRS operation and may perform the MRS operation. In this case, as described above, both the row CA buffer 210 and the column CA buffer 220 of the memory device 120 may be set to an active state.

[0115] In the case of performing a first operation other than the MRS operation, the memory device 120 may receive the row command / address signal R[9:0] or the column command / address signal C[7:0] indicating a first operation other than the MRS operation, and may perform the first operation other than the MRS operation. When the memory device 120 performs the first operation indicated by the row command / address signal R[9:0], the memory device 120 may perform the first operation indicated by the row command / address signal R[9:0] in the same or similar manner as the method described by operation S230. Operation S240 may include operations S241 and S242.

[0116] In operation S241, the memory controller 115 may send the column command / address signals R[7:0] corresponding to the MRS operation to the memory device 120. Similarly, the memory controller 115 may send the column command / address signals C[7:0] indicating the first operation to the memory device 120.

[0117] In operation S242, the memory device 120 may perform the MRS operation based on decoding the column command / address signals C[7:0] corresponding to the MRS operation. For example, the memory device 120 may perform the MRS operation by buffering the column command / address signals C[7:0] received through the column CA buffer 220 and decoding the received column command / address signals C[7:0] through the CA decoder 230. Similarly, the memory device 120 may perform the first operation other than the MRS operation in the same or similar manner as the above method, and the column command / address signals C[7:0] indicate the MRS operation. After operation S240, the memory system 100 may repeat operation S240 again or may proceed to operation S250.

[0118] In operation S250, the memory device 120 may be activated. The memory device 120 may be activated and may enter the active mode. The activation operation of the memory device 120 may be performed to be the same or similar to the activation operation in Figure 6 operation S130. In some embodiments, when the memory device 120 is powered on from operation S230, the memory device 120 may allow the column CA buffer 220 to be set to the active state. After operation S250 ends, the memory device 120 may set all CA buffers to the active state. That is, the CA unit 200 of the memory device 120 may be the same as the CA unit 200 described with reference to Figure 5B . The memory system 100 may proceed to operation S260.

[0119] In operation S260, the memory device 120 may be in the active mode and may perform the second operation in response to the row command / address signals R[9:0] or the column command / address signals C[7:0]. The memory system 100 may perform the second operation in the same or similar manner as the manner in Figure 6 operation S140. After operation S260 ends, the memory system 100 may repeat operation S260 again or may return to the idle mode. When the memory device 120 is in the first mode, the memory system 100 may return to operation S230, and when the memory device 120 is in the second mode, the memory system 100 may return to operation S240.

[0120] Reference Figure 5A 、Figure 5B , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 describe embodiments of setting the CA unit 200 to be included in the memory device 120 to an active mode as shown in Figure 5B , but the present disclosure is not limited thereto. In the idle mode, the memory device 120 may include the CA unit 200 set as shown in Figure 5A . In the active mode, the memory device 120 may include a row CA buffer 210 in an inactive state and a column CA buffer 220 in an active mode. In this case, in operation S250, after the activation operation, the memory system 100 may allow the row CA buffer 210 to enter the inactive state while changing the state of the column CA buffer 220 to the active state. In addition, the truth table of the column command / address signal C[7:0] described with reference to Figure 4B may further include the clock timing of each command indicating the third operation and the bit values or information of the column command / address signal C[7:0] indicating the third operation. That is, in the memory system 100, in operation S260, only the column CA buffer 220 may be in the active state. After that, when the memory device 120 returns to the idle mode (i.e., when the memory device 120 returns to operation S230 or operation S240), the memory device 120 may change the state of the CA buffer to the active state to correspond to each of the first mode and the second mode. Therefore, compared with the embodiment described with reference to Figure 11 , the memory device 120 may further reduce the current consumption of the CA buffer during all operations.

[0121] In some embodiments, the operation mode may be changed during the period when the memory device 120 proceeds from operation S230 or operation S240 to operation S250. For example, after the memory device 120 completes operation S230 in the first mode, the memory device 120 may enter the second mode before proceeding to operation S250. Specifically, after the memory device 120 completes operation S230, the memory controller 115 may send a control signal CTRL to the memory device 120 such that the memory device 120 enters the second mode, and the memory device 120 may then proceed to operation S250 in the second mode. Similarly, in some embodiments, after operation S250, the memory device 120 may enter the first mode or the second mode and may then proceed to operation S230 or operation S240.

[0122] Referring to Figure 1 , Figure 2 , Figure 3, Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 8 , Figure 9 , Figure 10 and Figure 11 Describe an operation method of the memory system 100 according to some embodiments of the present disclosure. According to the above embodiments, the memory system 100 can select one of a first mode or a second mode and can operate in the selected mode. When the memory system 100 is in the first mode, similar to the memory system 100 described with reference to Figure 6 , the column CA buffer 220 can be set to an inactive state, and thus, unnecessary current consumption can be removed or reduced.

[0123] Figure 12 is a block diagram showing an electronic system according to some embodiments of the present disclosure. Referring to Figure 12 , the electronic system 1000 may include a main processor 1100, a user interface 1200, a communication block 1300, an HBM device 1400, a graphics processing unit (GPU) core 1500, and a non-volatile memory (NVM) 1600. For example, the electronic system 1000 may be one of electronic devices such as a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a video game console, a workstation, and a server, or may be one of processing units such as a neural processing unit (NPU) and a graphics processing unit (GPU).

[0124] The main processor 1100 may control all operations of the electronic system 1000. The main processor 1100 may perform various arithmetic operations and / or logical operations. To this end, the main processor 1100 may include a dedicated circuit (e.g., a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC)). For example, the main processor 1100 may include one or more processor cores and may be implemented with a general purpose processor, a dedicated processor, or an application processor. In some embodiments, the main processor 1100 may include the memory controller described with reference to Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 to control the HBM device 1400. Figure 1 (e.g., the memory controller 115 of

[0125] The communication block 1300 can communicate with external devices / systems of the electronic system 1000. For example, the communication block 1300 can support at least one of various wireless communication protocols, such as Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WIMAX), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), and Radio Frequency Identification (RFID), and / or at least one of various wired communication protocols, such as Transmission Control Protocol / Internet Protocol (TCP / IP), Universal Serial Bus (USB), and / or FireWire.

[0126] The user interface 1200 can arbitrate communication between the user and the electronic system 1000. For example, the user interface 1200 can include an input interface, such as a keyboard, mouse, keypad, button, touch panel, touch screen, touchpad, trackball, camera, microphone, gyro sensor, or vibration sensor. For example, the user interface 1200 can include an output interface, such as a Liquid Crystal Display (LCD) device, Light Emitting Diode (LED) display device, Organic LED (OLED) display device, Active Matrix OLED (AMOLED) display device, speaker, or motor.

[0127] The HBM device 1400 can store data or instructions required for the operation of the electronic system 1000. For example, the HBM device 1400 can store data or instructions required for the operation of the main processor 1100, communication block 1300, or GPU core 1500 of the electronic system 1000, and can provide the data or instructions to the corresponding device in response to a request. Each of the HBM devices 1400 can be a memory device 120 included in the memory system 100 described in Figure 1 、 Figure 2 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 and Figure 11 or can include the memory device 120.

[0128] The GPU core 1500 can execute various operations at high speed. In some embodiments, the GPU core 1500 can perform graphics processing, machine learning and inference, or artificial intelligence inference operations. The GPU core 1500 can execute operations in parallel. In some embodiments, the GPU core 1500 can receive data or instructions required for operations from the HBM device 1400 and can send the processing results back to the HBM device 1400 again. In some embodiments, the GPU core 1500 can include the memory controllers described in Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 (e.g., the memory controller 115 of Figure 1 ) to control the HBM device 1400.

[0129] The NVM 1600 can store data required for the operation of the electronic system 1000 or data generated as a result of the operation. In some embodiments, the NVM 1600 can store data generated by the operation of the main processor 1100 or the GPU core 1500. In some embodiments, the NVM 1600 can store data present in the HBM device 1400 or can provide the stored data to the HBM device 1400. The NVM 1600 can be controlled by the main processor 1100.

[0130] The bus 1700 can provide a communication path between the components of the electronic system 1000. The components of the electronic system 1000 can exchange data with each other based on the bus format of the bus 1700. For example, the bus format can include at least one or more of various interface protocols, such as USB, Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE), Non-Volatile Memory Express (NVMe), and / or Universal Flash Storage (UFS).

[0131] According to Figure 12An electronic system 1000 can reduce the current consumption of a memory device by means of an HBM device 1400 according to some embodiments of the present disclosure. Additionally, in addition to the reduced current consumption, the electronic system 1000 can also reduce the power consumption amount and the heat generation amount, and can allow each component (e.g., the main processor 1100 or the GPU core 1500) to operate smoothly. Figure 12 shown and referred to in Figure 12 The electronic system 1000 described can include some or all of the above components, and the present disclosure is not limited to some embodiments including all of the above components. For example, the electronic system 1000 may not include the user interface 1200 or the NVM 1600.

[0132] According to an embodiment of the present disclosure, there is provided a memory system capable of reducing the current consumption of a memory device and improving performance.

[0133] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for operating a high bandwidth memory (HBM) device, the method comprising: Receive the mode register set MRS command through the row command / address signal line in idle mode; performing an MRS operation in response to the MRS command; receiving an activation ACT command through the row command / address signal line in the idle mode; as well as In response to the ACT command switching to active mode, The switching to the active mode includes switching one or more memory buffers of the HBM device to an active state.

2. The method according to claim 1, wherein: The HBM device includes a column command / address CA buffer configured to buffer a column command / address signal, and In the idle mode, the column CA buffer is in an inactive state, so that current does not flow in the column CA buffer.

3. The method according to claim 2, further comprising: In response to the ACT command, the state of the column CA buffer is changed to an active state in which current flows.

4. The method according to claim 3, wherein: The MRS operation includes: decoding the MRS command; and Based on a decoding result of the decoding of the MRS command, the MRS operation is performed.

5. The method according to claim 3, further comprising: receiving a precharge command in the active mode; as well as A precharge operation is performed in response to the precharge command, and switching to the idle mode is performed.

6. The method according to claim 5, wherein: The HBM device further includes a row CA buffer configured to buffer a row command / address signal, and Wherein, in the idle mode and the active mode, the row CA buffer is in the active state.

7. The method according to claim 3, further comprising: A data read operation is performed by the HBM device in the active mode.

8. A method for operating a high bandwidth memory (HBM) device, the method comprising: selecting one of a first mode and a second mode in an idle mode, wherein a column command / address CA buffer configured to buffer a column command / address signal is inactive in the first mode and active in the second mode; performing a mode register set (MRS) operation in the idle mode; and In the idle mode, an activation ACT command is received through a row command / address signal line, and in response to the ACT command, the active mode is switched to the active mode. The switching to the active mode includes setting one or more memory buffers of the HBM device to the active state.

9. The method according to claim 8, wherein: The MRS operation is performed in response to an MRS command, and the method further includes: In the first mode, the MRS command is received through the row command / address signal line.

10. The method according to claim 8, wherein: The performing of the MRS operation in the idle mode comprises: receiving an MRS command via a column command / address signal line; and The MRS operation is performed in response to the MRS command.

11. The method according to claim 8, further comprising: receiving a control signal from a memory controller configured to control the HBM device; as well as In response to the control signal received from the memory controller, switching is performed between the first mode and the second mode.

12. The method according to claim 9, further comprising: In response to the ACT command, the state of the column CA buffer is changed to an active state.

13. The method according to claim 9, further comprising: receiving a precharge command in the active mode; as well as A precharge operation is performed on the HBM device in response to the precharge command, and switching to the idle mode is performed.

14. The method according to claim 9, wherein: The HBM device includes a row CA buffer configured to buffer a row command / address signal, and Wherein, in the idle mode and the active mode, the row CA buffer is in the active state.

15. A high bandwidth memory (HBM) device configured to store data, comprising: a row command buffer configured to buffer row command / address signals; a column command buffer configured to buffer column command / address signals; a command / address CA buffer configured to decode the row command / address signal and the column command / address signal; as well as a memory cell array configured to store the data, wherein the HBM device is configured to receive a mode register set MRS command and an activate ACT command through the row command / address signal, and The ACT command instructs one or more memory buffers of the HBM device to switch to an active state.

16. The HBM device according to claim 15, wherein: In the idle mode, the column command buffer is configured to be in an inactive state so that current does not flow in the column command buffer.

17. The HBM device according to claim 16, wherein: The HBM device is configured to switch to an active mode in response to the ACT command, and Wherein, in the active mode, the HBM device is configured to switch to the idle mode in response to a precharge command.

18. The HBM device according to claim 16, wherein: In the active mode, the column command buffer is configured to be in an active state.

19. The HBM device according to claim 16, wherein: In the idle mode and the active mode, the row command buffer is configured to be in an active state.

20. The HBM device according to claim 19, wherein: In the active mode, the HBM device is configured to perform a read operation of the data.

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