Method for producing semiconductor element and resulting semiconductor element

Abstract

The invention relates to a method for preparing a semiconductor element and the obtained semiconductor element, and the method comprises the following steps: S1, providing a substrate comprising a plurality of gaps, and forming a first silica layer in the plurality of gaps in a flowing type chemical vapor deposition mode; s2, forming a second silicon oxide layer on the first silicon oxide layer by adopting a flowing type chemical vapor deposition mode; the second silica layer covers the surface of the first silica layer; the flow of the silicon-containing material forming the second silica layer is greater than that of the silicon-containing material forming the first silica layer; the time for forming the first silica layer is more than 40s; the maximum width of the gap is 60 nm or less, and the depth of the gap is 200-600 nm. According to the method, the production efficiency and the productivity of the semiconductor element can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor fabrication, and more particularly, to a method for fabricating semiconductor components and the resulting semiconductor components. Background Art

[0002] Currently, microelectronics technology has become the foundation of the entire information industry and an important symbol reflecting a country's comprehensive strength and economic development level. With the development of integrated circuit technology, chips with high speed, high device density, low power consumption, and low cost have increasingly become the main products of very large scale integrated circuit manufacturing.

[0003] Flowable Chemical Vapor Deposition (FCVD) is a chemical vapor deposition process carried out at relatively low temperatures and pressures, capable of fabricating nano-thin film materials with high crystal quality and crystallinity. Due to its excellent gap and trench filling capabilities, it is widely used. Currently, the FCVD time in processes below 14 nm is relatively long, resulting in low production efficiency. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a method for fabricating semiconductor components and the resulting semiconductor components.

[0005] To achieve the above objective, in a first aspect of the present disclosure, a method for fabricating semiconductor components is provided, the method comprising the following steps:

[0006] S1. Provide a substrate including a plurality of gaps, and form a first silicon oxide layer in the plurality of gaps by means of flowable chemical vapor deposition;

[0007] S2. Form a second silicon oxide layer on the first silicon oxide layer by means of flowable chemical vapor deposition;

[0008] The second silicon oxide layer covers the surface of the first silicon oxide layer;

[0009] The flow rate of the silicon-containing material for forming the second silicon oxide layer is greater than the flow rate of the silicon-containing material for forming the first silicon oxide layer;

[0010] The time for forming the first silicon oxide layer is 40 s or more;

[0011] The maximum width of the gap is 60 nm or less, and the depth of the gap is 200 - 600 nm.

[0012] Optionally, the ratio of the flow rate of the silicon-containing material for forming the second silicon oxide layer to the flow rate of the silicon-containing material for forming the first silicon oxide layer is 1.1:1 or more.

[0013] Optionally, in step S1, the conditions for forming the first silicon oxide layer include: a temperature of 50 to 400 °C, a pressure of 0.5 to 5 Torr, a time of 40 to 50 s, and a flow rate of the silicon-containing material of 100 to 1000 sccm.

[0014] Optionally, in step S2, the conditions for forming the second silicon oxide layer include: a temperature of 50 to 400 °C, a pressure of 0.5 to 5 Torr, and a flow rate of the silicon-containing material of 1000 to 5000 sccm.

[0015] Optionally, the silicon-containing material is trimethylsilylamine.

[0016] Optionally, the raw materials for forming the first silicon oxide layer and the second silicon oxide layer further include ammonia, and the flow rate of the ammonia is below 5000 sccm.

[0017] Optionally, after step S2, the first silicon oxide layer and the second silicon oxide layer are cured and annealed to form a silicon oxide layer.

[0018] Optionally, the method further includes: chemically mechanically planarizing the silicon oxide layer by chemical mechanical polishing, with a pressure of 1 to 3 PSI.

[0019] Optionally, the method is used for a process below 14 nm.

[0020] The second aspect of the present disclosure provides a semiconductor device prepared by using the method described in the first aspect of the present disclosure.

[0021] Through the above technical solutions, the method of the present disclosure forms a silicon oxide layer step by step, and controls the flow rates of the materials for forming the first silicon oxide layer and the second silicon oxide layer and the time for forming the first silicon oxide layer, so as to avoid the formation of holes while obtaining high production efficiency and production capacity (WPH).

[0022] Other features and advantages of the present disclosure will be described in detail in the subsequent specific implementation section. Description of the Drawings

[0023] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification, and are used to explain the present disclosure together with the following specific implementation, but do not constitute a limitation to the present disclosure. In the drawings:

[0024] Figure 1 is a flowchart of a specific implementation of the method for preparing a semiconductor device according to the present disclosure.

[0025] Figure 2 is a schematic diagram of the structure after forming the first silicon oxide layer according to the present disclosure.

[0026] Figure 3It is a schematic diagram of the structure after the second silicon oxide layer is formed in the present disclosure.

[0027] Figure 4 It is a schematic diagram of the structure obtained after chemical mechanical planarization in the present disclosure.

[0028] Explanation of reference numerals

[0029] 1 Substrate

[0030] 2 First silicon oxide layer

[0031] 3 Second silicon oxide layer

[0032] 4 Silicon oxide layer Detailed implementation manners

[0033] The following details the specific implementation manners of the present disclosure with reference to the accompanying drawings. It should be understood that the specific implementation manners described herein are only for explaining and illustrating the present disclosure, and are not used to limit the present disclosure.

[0034] As Figure 1 shown, the first aspect of the present disclosure provides a method for fabricating a semiconductor device, the method including the following steps:

[0035] S1. Provide a substrate including a plurality of gaps, and form a first silicon oxide layer in the plurality of gaps by a flow-type chemical vapor deposition method;

[0036] S2. Form a second silicon oxide layer on the first silicon oxide layer by a flow-type chemical vapor deposition method;

[0037] The second silicon oxide layer covers the surface of the first silicon oxide layer;

[0038] The flow rate of the silicon-containing material for forming the second silicon oxide layer is greater than the flow rate of the silicon-containing material for forming the first silicon oxide layer;

[0039] The time for forming the first silicon oxide layer is 40 s or more;

[0040] The maximum width of the gap is 60 nm or less, and the depth of the gap is 200 - 600 nm.

[0041] In the present disclosure, the substrate can be a substrate for forming STI (Shallow Trench Isolation) or ILD (Inter Layer Dielectric), and the formed silicon oxide layer can be used as an isolation layer.

[0042] In the process of fabricating semiconductor devices, gap-fill of the generated trench structures is required; during the filling process, to avoid the generation of voids, a relatively small material flow rate needs to be controlled, which results in a relatively low overall production efficiency; in order to achieve higher production efficiency and wafer per hour (WPH), the present disclosure forms the first silicon oxide layer and the second silicon oxide layer in segments, increases the material flow rate for forming the second silicon oxide layer, and controls the time for forming the first silicon oxide layer, thereby improving production efficiency and WPH while avoiding the generation of voids.

[0043] In the present disclosure, the thicknesses of the first silicon oxide layer and the second silicon oxide layer may be uniform or non-uniform.

[0044] In the present disclosure, the first silicon oxide layer fills multiple gaps.

[0045] In the present disclosure, after step S1, a first silicon oxide layer is also formed on the upper surface of the substrate.

[0046] In the present disclosure, after steps S1 and S2, multiple gaps on the substrate are filled.

[0047] In the present disclosure, steps S1 and S2 may be carried out in the same chamber.

[0048] In the present disclosure, the maximum width of the gap is not zero.

[0049] In the present disclosure, during the formation of the first silicon oxide layer and the second silicon oxide layer, except for the formation time and the flow rate of the silicon-containing material, other conditions may be the same or different.

[0050] In the present disclosure, both the "time for forming the first silicon oxide layer" and the "time for forming the second silicon oxide layer" are deposition times.

[0051] According to an embodiment of the present disclosure, the ratio of the flow rate of the silicon-containing material for forming the second silicon oxide layer to the flow rate of the silicon-containing material for forming the first silicon oxide layer is 1.1:1 or more, for example, it may be 1.1:1, 1.5:1, 1.8:1, 2.0:1, 2.5:1, 3.0:1, etc.

[0052] According to an embodiment of the present disclosure, in step S1, the conditions for forming the first silicon oxide layer include: the temperature is 50 to 400 °C, for example, it can be 50 °C, 80 °C, 100 °C, 150 °C, 200 °C, 220 °C, 250 °C, 300 °C, 400 °C, etc.; the pressure is 0.5 to 5 Torr, for example, it can be 0.5 Torr, 1 Torr, 2.3 Torr, 3 Torr, 4 Torr, 5 Torr, etc.; the time is 40 to 50 s, for example, it can be 40 s, 43 s, 45 s, 50 s, etc.; the flow rate of the silicon-containing material is 100 to 1000 sccm, for example, it can be 100 sccm, 200 sccm, 300 sccm, 500 sccm, 800 sccm, 1000 sccm, etc. Except for the above conditions, other conditions are conventional in the art and will not be elaborated in the present disclosure; the thickness of the first silicon oxide layer can be controlled by the deposition time.

[0053] According to an embodiment of the present disclosure, in step S2, the conditions for forming the second silicon oxide layer include: the temperature is 50 to 400 °C, for example, it can be 50 °C, 80 °C, 100 °C, 150 °C, 200 °C, 220 °C, 250 °C, 300 °C, 400 °C, etc.; the pressure is 0.5 to 5 Torr, for example, it can be 0.5 Torr, 1 Torr, 2.3 Torr, 3 Torr, 4 Torr, 5 Torr, etc.; the flow rate of the silicon-containing material is 1000 to 5000 sccm, for example, it can be 1000 sccm, 2000 sccm, 3000 sccm, 3500 sccm, 4000 sccm, 4200 sccm, 5000 sccm, etc. Except for the above conditions, other conditions are conventional in the art and will not be elaborated in the present disclosure. The thickness of the second silicon oxide layer can be controlled by the deposition time, and the thickness of the second silicon oxide layer is set according to process requirements.

[0054] According to an embodiment of the present disclosure, the silicon-containing material is trimethylsilylamine.

[0055] According to an embodiment of the present disclosure, the raw materials for forming the first silicon oxide layer and the second silicon oxide layer further include ammonia, and the flow rate of ammonia is less than 5000 sccm and not zero, for example, it can be 100 sccm, 200 sccm, 300 sccm, 500 sccm, 800 sccm, 1000 sccm, 2000 sccm, 3000 sccm, 3500 sccm, 4000 sccm, 4200 sccm, 5000 sccm, etc.; the method of the present disclosure is carried out under the condition of the presence of oxygen, and the flow rate of oxygen can be, for example, 100 to 1000 sccm.

[0056] According to an embodiment of the present disclosure, the method further includes: after step S2, curing and annealing the first silicon oxide layer and the second silicon oxide layer to form a silicon oxide layer; the manner of curing and annealing is conventional in the art and is not specifically limited by the present disclosure. After curing and annealing, the silicon oxide layer mainly contains silicon dioxide.

[0057] According to an embodiment of the present disclosure, the method further includes: performing chemical mechanical planarization on the silicon oxide layer by chemical mechanical polishing until the silicon oxide layer on the upper surface of the substrate is removed, and the pressure is 1 to 3 PSI.

[0058] According to an embodiment of the present disclosure, the method is used for a process below 14 nm.

[0059] According to a specific embodiment of the present disclosure, the method for preparing a semiconductor element may include the following steps:

[0060] S1. Provide a substrate 1 including a plurality of gaps, the maximum width of the gaps is below 60 nm, and the depth of the gaps is 200 - 600 nm;

[0061] Form a first silicon oxide layer 2 in the plurality of gaps by flowing chemical vapor deposition (FCVD), as Figure 2 shown;

[0062] The conditions include: the temperature is 50 - 400 °C, the pressure is 0.5 - 5 Torr, the time is 40 - 50 s, the flow rate of trimethylsilylamine is 100 - 1000 sccm, and the flow rate of ammonia is below 5000 sccm and not zero;

[0063] S2. Form a second silicon oxide layer 3 on the first silicon oxide layer 2 by flowing chemical vapor deposition (FCVD), as Figure 3 shown;

[0064] The conditions include: the temperature is 50 - 400 °C, the pressure is 0.5 - 5 Torr, the flow rate of trimethylsilylamine is 1000 - 5000 sccm, and the flow rate of ammonia is below 5000 sccm and not zero;

[0065] The second silicon oxide layer covers the surface of the first silicon oxide layer;

[0066] The material flow rate for forming the first silicon oxide layer is less than the material flow rate for forming the second silicon oxide layer;

[0067] S3. Cure and anneal the first silicon oxide layer and the second silicon oxide layer to form a silicon oxide layer;

[0068] S4. Perform chemical mechanical planarization on the silicon oxide layer by chemical mechanical polishing, the pressure is 1 - 3 PSI, as Figure 4 shown.

[0069] By adopting the above specific implementation manners, it is possible to avoid the formation of holes while obtaining high production efficiency and production capacity (WPH).

[0070] The second aspect of the present disclosure provides a semiconductor element prepared by using the method described in the first aspect of the present disclosure.

[0071] The preferred implementation manners of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the present disclosure is not limited to the specific details in the above implementation manners. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0072] In addition, it should be noted that, among the various specific technical features described in the above specific implementation manners, they can be combined in any appropriate manner without conflict. To avoid unnecessary repetition, the present disclosure will not separately describe various possible combination manners.

[0073] Furthermore, any combination can be made among various different implementation manners of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes the following steps: S1. Provide a substrate including a plurality of gaps, and form a first silicon oxide layer in the plurality of gaps by a flowing chemical vapor deposition method; S2. Form a second silicon oxide layer on the first silicon oxide layer by a flowing chemical vapor deposition method; The second silicon oxide layer covers the surface of the first silicon oxide layer; The flow rate of the silicon-containing material for forming the second silicon oxide layer is greater than the flow rate of the silicon-containing material for forming the first silicon oxide layer; The time for forming the first silicon oxide layer is 40 s or more; The maximum width of the gap is 60 nm or less, and the depth of the gap is 200 - 600 nm.

2. The method according to claim 1, wherein, The ratio of the flow rate of the silicon-containing material for forming the second silicon oxide layer to the flow rate of the silicon-containing material for forming the first silicon oxide layer is 1.1:1 or more.

3. The method according to claim 1, wherein, In step S1, the conditions for forming the first silicon oxide layer include: the temperature is 50 - 400 °C, the pressure is 0.5 - 5 Torr, the time is 40 - 50 s, and the flow rate of the silicon-containing material is 100 - 1000 sccm.

4. The method according to claim 1, wherein, In step S2, the conditions for forming the second silicon oxide layer include: the temperature is 50 - 400 °C, the pressure is 0.5 - 5 Torr, and the flow rate of the silicon-containing material is 1000 - 5000 sccm.

5. The method according to claim 1, wherein, The silicon-containing material is trimethylsilylamine.

6. The method according to claim 1, wherein, The raw materials for forming the first silicon oxide layer and the second silicon oxide layer further include ammonia, and the flow rate of the ammonia is 5000 sccm or less.

7. The method according to claim 1, wherein, After step S2, the first silicon oxide layer and the second silicon oxide layer are cured and annealed to form a silicon oxide layer.

8. The method according to claim 7, wherein, The method further includes: chemically mechanically planarizing the silicon oxide layer by a chemical mechanical polishing method, and the pressure is 1 - 3 PSI.

9. The method according to any one of claims 1 to 8, wherein, The method is used for a process below 14 nm.

10. A semiconductor device manufactured by the method according to any one of claims 1 to 9.

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