Substrate structure and manufacturing method thereof

Abstract

The invention provides a substrate structure. The substrate structure comprises a substrate and a vertical conductive connecting piece, the substrate includes a material having a heat resistance temperature of 300 DEG C or higher. The vertical conductive connector penetrates through the substrate. The vertical conductive connecting piece is provided with a bonding structure extending towards the direction of the substrate. The invention further provides a manufacturing method of the substrate structure.

Description

Technical Field

[0001] The present invention relates to a substrate structure and a manufacturing method thereof Background Art

[0002] In substrate technology, in order to enable circuits to be interconnected with each other in the thickness direction, vertical conductive connectors (such as plating through holes (PTHs)) are often formed. However, problems such as low adhesion strength may occur due to the difference in material properties between the vertical conductive connectors and other components. Therefore, how to improve the adhesion strength of the vertical conductive connectors in the substrate to enhance the product reliability is actually a challenge Summary of the Invention

[0003] The present invention provides a substrate structure and a manufacturing method thereof, which can effectively enhance the product reliability

[0004] A substrate structure of the present invention includes a substrate and vertical conductive connectors. The substrate includes a material with a heat-resistant temperature of 300 °C or higher. The vertical conductive connectors penetrate through the substrate. The vertical conductive connectors have a bonding structure extending towards the substrate

[0005] A manufacturing method of a substrate structure of the present invention at least includes the following steps. Provide a substrate with a plurality of through holes and a conductive layer; bond the substrate to the conductive layer; perform an electroplating process to form vertical conductive connectors in the plurality of through holes respectively; and perform an annealing process to cause a plurality of first atoms in the vertical conductive connectors to diffuse towards the substrate to form a bonding structure

[0006] Based on the above, the present invention introduces an annealing process to cause the atoms in the vertical conductive connectors to diffuse and form a bonding structure extending towards the substrate. In this way, the adhesion strength between it and adjacent components can be enhanced, and thus the product reliability can be effectively improved

[0007] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows Brief Description of the Drawings

[0008] Figures 1A to 1L is a partial cross-sectional schematic view of a partial manufacturing method of a substrate structure according to an embodiment of the present invention

[0009] Figures 2A to 2L is a partial cross-sectional schematic view of a partial manufacturing method of a substrate structure according to another embodiment of the present invention

[0010] Figures 3A to 3E is a partial cross-sectional schematic view of a partial manufacturing method of a substrate structure according to still another embodiment of the present invention

[0011] Figures 4A to 4E is a partial cross-sectional view of a partial manufacturing method of a substrate structure according to another embodiment of the present invention. Detailed Embodiments

[0012] In the following detailed description, for purposes of illustration and not limitation, exemplary embodiments revealing specific details are set forth in order to provide a thorough understanding of the various principles of the present invention. However, it will be apparent to those of ordinary skill in the art that the present invention may be practiced in other embodiments without these specific details. Additionally, descriptions of well-known devices, methods, and materials may be omitted so as not to obscure the description of the various principles of the present invention.

[0013] Reference is made to the accompanying drawings of the present embodiment to more fully elaborate the present invention. However, the present invention may also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, dimensions, or sizes of layers or regions in the drawings are enlarged for clarity. The same or similar reference numerals represent the same or similar components, and will not be repeated in the following paragraphs.

[0014] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of each embodiment in conjunction with the accompanying drawings. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0015] Unless otherwise clearly stated, any method described herein is not intended to be construed as requiring its steps to be performed in a specific order.

[0016] Figures 1A to 1L is a partial cross-sectional view of a partial manufacturing method of a substrate structure according to an embodiment of the present invention.

[0017] Please refer to Figure 1A , a substrate 110 is provided, where the substrate 110 includes a material with a heat-resistant temperature of 300 °C or higher to reduce the probability of problems such as delamination during subsequent annealing processes. In this way, it can be ensured that the annealing process will not have an obvious adverse effect on the substrate 110. Here, the heat-resistant temperature can be 1500 °C, and the substrate 110 can serve as the core layer of the substrate structure 100. The heat-resistant temperature is a technical term known to those skilled in the art and will not be elaborated herein.

[0018] For example, the material of the substrate 110 includes glass, ceramic, liquid crystal polymer (LCP), or a combination thereof. However, the present invention is not limited thereto, and other suitable heat-resistant inorganic compounds and / or organic compounds may also be used as the material of the substrate 110.

[0019] In some embodiments, the thickness 110T of the substrate 110 is between 0.05 millimeters (mm) and 10 mm. However, the present invention is not limited thereto, and the thickness 110T of the substrate 110 can be selected according to the actual design requirements.

[0020] In Figure 1A the substrate 110 may be formed with a plurality of through holes 111, where the through holes 111 penetrate the substrate 110, for example, from the upper surface 110a of the substrate 110 to the lower surface 110b of the substrate 110 in the direction of the thickness 110T. Further, the through holes 111 are formed by a drilling process or a similar process.

[0021] In some embodiments, the aperture diameter 111D of the through holes 111 is between 0.05 mm and 0.5 mm. However, the present invention is not limited thereto, and the aperture diameter 111D of the through holes 111 can be determined according to the actual design requirements.

[0022] In the present embodiment, neither the through holes 111, the upper surface 110a of the substrate 110, nor the lower surface 110b of the substrate 110 is formed with a seed layer composed of a metal material such as titanium, copper, palladium, or the like.

[0023] In some embodiments, when the material of the substrate 110 is glass, due to the low surface roughness of the glass (for example, Ra < 1 nanometer (nm)), it is difficult to deposit the seed layer thereon (whether it is sputtered titanium / copper formed by a dry process or nano-palladium formed by a wet process), resulting in an uneven deposition amount of the seed layer. In this way, the tensile force of the seed layer will be reduced (such as the tensile force of sputtered titanium / copper < 0.3 (kg / cm)), so it cannot effectively improve the adhesion strength between the subsequent vertical conductive connector and its adjacent components. Based on this, this embodiment can omit the formation of such a film layer, and still achieve the technical effect of improving the adhesion strength between the vertical conductive connector and its adjacent components without forming such a film layer. However, the present invention is not limited thereto.

[0024] Please refer to Figure 1B , the substrate 110 is bonded to the conductive layer 121. For example, the conductive layer 121 can be attached to the substrate 110 through the adhesive layer 130. Therefore, the adhesive layer 130 is located between the conductive layer 121 and the substrate 110, and the through holes 111 can expose a part of the adhesive layer 130.

[0025] In some embodiments, the thickness 121T of the conductive layer 121 ranges from 2 microns to 100 microns (such as 3 microns), so it can be regarded as a thin metal layer. At this thinness, defects (such as holes) are more likely to occur during use. Therefore, the conductive layer 121 can be further bonded to the carrier layer 122, where the thickness 122T of the carrier layer 122 ranges from 1 micron to 25 microns (such as 18 microns). Thus, the probability of defects occurring in the conductive layer 121 during the manufacturing process can be reduced by the carrier layer 122, but the present invention is not limited thereto. Here, the conductive layer 121 and the carrier layer 122 can be bonded together through a release layer (not shown) to reduce the difficulty of subsequently removing the carrier layer 122.

[0026] In some embodiments, the material of the conductive layer 121 includes copper or the like, the material of the carrier layer 122 includes copper or the like, and the adhesive layer 130 includes polyimide or the like, but the present invention is not limited thereto.

[0027] In some embodiments, in order to improve the adhesion between the adhesive layer 130, the conductive layer 121, and the carrier layer 122, optionally, a lamination process can be further used.

[0028] In some embodiments, the thickness 130T of the adhesive layer 130 ranges from 1 nanometer to 50 microns, but the present invention is not limited thereto. The thickness 130T of the adhesive layer 130 can be determined according to the actual design requirements.

[0029] Please refer to Figure 1C , remove the adhesive layer 130 at the bottom of the through hole 111 to expose the underlying conductive layer 121, where the removal method includes dry processes such as laser, plasma, etc. or wet processes such as de-smear, etc., and the present invention is not limited thereto.

[0030] Please refer to Figure 1D , perform an electro-plating process to form vertical conductive connectors 140 in the plurality of through holes 111 respectively. The electro-plating process can be such that after power-on through the conductive layer 121, a conductive material (such as copper) starts to form upward from the bottom of the through hole 111 until it fills the through hole 111 and is higher than the top surface of the substrate 110 (such as the upper surface 110a), that is, the top surface 140a of the formed vertical conductive connector 140 is higher than the top surface of the substrate 110 (such as the upper surface 110a). In this way, in addition to ensuring that the conductive material completely fills the internal space of the through hole 111, it can also ensure that the subsequent circuit formed on the substrate 110 does not recess into the substrate 110, and thus the product can have better electrical performance, but the present invention is not limited thereto. Here, the conductive material includes copper or the like.

[0031] In this embodiment, since no seed layer is formed in the through hole 111, the vertical conductive connector 140 is physically connected to the substrate 110. In other words, the vertical conductive connector 140 can directly contact the substrate 110.

[0032] In some embodiments, when forming a vertical conductive connector through a seed layer, a relatively large thickness (for example, a thickness greater than 60 micrometers (μm)) of metal needs to be plated to fill the through hole, and in this case, it is difficult for the substrate wiring to achieve fine lines with a line width / line pitch (L / S) of less than 16 / 16 micrometers. However, by the method of this embodiment, the aforementioned problems can be overcome, and it is easier to meet the requirements of fine lines.

[0033] Please refer to Figure 1E , after performing the electroplating process, for example, the carrier layer 122 is removed from the conductive layer 121 through a release layer to expose the bottom surface of the conductive layer 121. However, the present invention is not limited thereto, and the carrier layer 122 can also be removed by other suitable methods.

[0034] Please refer to Figure 1F , the conductive layer 121 is removed by stripping or reduction with a suitable etching solution to expose the bottom surface 140b of the vertical conductive connector 140, wherein the bottom surface 140b of the vertical conductive connector 140 can be coplanar with the bottom surface 130b of the adhesive layer 130.

[0035] Please refer to Figure 1G , the adhesive layer 130 is immersed in a suitable alkaline solution to remove the adhesive layer 130. In this way, the vertical conductive connector 140 protrudes from the lower surface 110b of the substrate 110. However, the present invention is not limited thereto, and the adhesive layer 130 can also be removed by other suitable methods.

[0036] Please refer to Figure 1H , perform an annealing process to cause a plurality of first atoms (not shown) in the vertical conductive connector 140 to diffuse toward the substrate 110 to form a bonding structure 141. Further, in this embodiment, by introducing the annealing process, atomic diffusion occurs in the first atoms of the vertical conductive connector 140 in the direction toward the substrate 110, that is, as Figure 1HAs shown in the enlarged part, the first atoms will move from the interface between the vertical conductive connector 140 and the substrate 110 into the gaps inside the substrate 110, and the first atoms will be arranged between the gaps to form a bonding structure 141 extending into the substrate 110. In this mechanism, the bonding structure 141 can have an irregular boundary, and multiple first atoms are inserted into the gaps of the material of the substrate 110 to enhance the adhesion strength between the vertical conductive connector 140 and the adjacent substrate 110, thereby effectively improving the product reliability. Here, the first atoms include copper atoms or other metal atoms

[0037] In some embodiments, the maximum extension distance of the bonding structure 141 is between 0.1 nanometer and 100 nanometers, but the present invention is not limited thereto. The extension distance of the bonding structure 141 depends on the process temperature and execution time of the annealing process

[0038] In some embodiments, the annealing process is carried out in nitrogen (N2) or other suitable ovens, its execution time is more than 30 minutes (for example, between 30 minutes and 90 minutes), and its process temperature is 300 °C or more (for example, between 300 °C and 600 °C) to enable the first atoms to diffuse out effectively, but the present invention is not limited thereto. The parameter settings of the annealing process can be determined according to the actual design requirements

[0039] Please refer to Figure 1I , and use a planarization process such as chemical mechanical polishing (CMP) or the like to remove the excess vertical conductive connectors 140 on the upper surface 110a and the lower surface 110b of the substrate 110. It should be noted that in an embodiment not shown, the foregoing planarization process may also be performed before the annealing process

[0040] Please refer to Figure 1J , and form a seed layer 150 on the substrate 110. For example, the seed layer 150 can completely cover and directly contact the upper surface 110a and the lower surface 110b of the substrate 110 and the top surface 140a and the bottom surface 140b of the vertical conductive connector 140. Here, the seed layer 150 includes a sputtered titanium / copper layer or a copper layer formed by an electroless plating process, but the present invention is not limited thereto

[0041] Please refer to Figure 1K , and form a circuit layer 160 on the seed layer 150. The circuit layer 160 can form a circuit pattern with multiple openings through a lithography process such as semi-additive process (SAP) or patterned electroplating, and the multiple openings expose the seed layer 150. For example, the circuit layer 160 is located on the seed layer 150 on both sides of the substrate 110. Here, the material of the circuit layer 160 includes copper or the like

[0042] Please refer to Figure 1L , and remove the part of the seed layer 150 exposed by the plurality of openings of the circuit layer 160 through a stripping process (such as using an appropriate etching solution) to complete the circuit fabrication.

[0043] After the above processes, the fabrication of the substrate structure 100 of this embodiment can be substantially completed. In this embodiment, the substrate structure 100 includes a substrate 110 and a vertical conductive connector 140 passing through the substrate 110, wherein the vertical conductive connector 140 has a bonding structure 141 extending in the direction of the substrate 110 (formed by an annealing process). In this way, the adhesion strength between it and the adjacent substrate 110 can be enhanced, and thus the product reliability can be effectively improved.

[0044] It must be noted here that the following embodiments follow the component numbers and some contents of the above embodiments, where the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference can be made to the foregoing embodiments, and the following embodiments will not be repeated.

[0045] Figures 2A to 2L is a partial cross-sectional view of a partial manufacturing method of a substrate structure according to another embodiment of the present invention.

[0046] Please refer to Figure 2A , similar to Figure 1A , the difference is that after forming the through hole 111, it further includes forming a buffer layer 270 on the substrate 110, wherein the buffer layer 270 is formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0047] In some embodiments, the material of the buffer layer 270 includes metal oxides (such as titanium oxide, zinc oxide, aluminum oxide, silicon oxide or the like), metals (such as titanium) or combinations thereof, but the present invention is not limited thereto.

[0048] In some embodiments, the buffer layer 270 can surround the outer surface of the substrate 110 so that no surface of the substrate 110 is exposed, but the present invention is not limited thereto.

[0049] In an embodiment not shown, the buffer layer can be a multi-layer structure, such as a titanium oxide layer can be formed first and then a titanium layer, but the present invention is not limited thereto.

[0050] Please refer toFigure 2B and Figure 2C , similar to Figure 1B and Figure 1C , the substrate 110 is joined to the conductive layer 121 through the adhesive layer 130, and the adhesive layer 130 at the bottom of the via hole 111 is removed to expose the underlying conductive layer 121. In this embodiment, the buffer layer 270 is in direct contact with the adhesive layer 130, while separating the substrate 110 from the adhesive layer 130.

[0051] Please refer to Figure 2D , similar to Figure 1D , an electroplating process is performed to respectively form vertical conductive connectors 140 in the plurality of via holes 111. The buffer layer 270 is disposed between the substrate 110 and the vertical conductive connectors 140 (such as in the direction perpendicular to the thickness), and the buffer layer 270 is in direct contact with the vertical conductive connectors 140, such that the vertical conductive connectors 140 are not physically connected to the substrate 110.

[0052] Please refer to Figure 2E 、 Figure 2F and Figure 2G , similar to Figure 1E 、 Figure 1F and Figure 1G , after the electroplating process is performed, the carrier layer 122, the conductive layer 121 and the adhesive layer 130 are sequentially removed. After the adhesive layer 130 is removed, the vertical conductive connectors 140 protrude from the bottom surface of the buffer layer 270.

[0053] Please refer to Figure 2H , similar to Figure 1H , an annealing process is performed to cause a plurality of first atoms in the vertical conductive connectors 140 to diffuse toward the substrate 110 to form a bonding structure 141. Further, the difference between this embodiment and the embodiment of Figure 1H is that since the buffer layer 270 is located between the vertical conductive connectors 140 and the substrate 110, after the annealing process is performed, the bonding structure 141 extends into the buffer layer 270 rather than the substrate 110, such that a plurality of first atoms are inserted into the gaps of the material of the buffer layer 270. In addition, a plurality of second atoms (not shown) in the buffer layer 270 diffuse toward the substrate 110 after the annealing process is performed to form another bonding structure 271, such that a plurality of second atoms are inserted into the gaps of the material of the substrate 110. In this way, the adhesion strength between the corresponding components can be further enhanced through the plurality of bonding structures 141, 271. Here, the second atoms include titanium or aluminum, but the present invention is not limited thereto.

[0054] For example, in this embodiment, by introducing the annealing process, both the first atoms of the vertical conductive connectors 140 and the second atoms in the buffer layer 270 exhibit an atomic diffusion phenomenon toward the substrate 110, that is, as Figure 2HAs shown in the enlarged part, the first atom will move from the interface between the vertical conductive connector 140 and the buffer layer 270 into the gap inside the buffer layer 270, and the second atom will move from the interface between the buffer layer 270 and the substrate 110 into the gap inside the substrate 110. Therefore, both the bonding structures 141 and 271 have irregular boundaries.

[0055] In some embodiments, the annealing process is carried out in nitrogen or other suitable ovens, with an execution time of more than 30 minutes (for example, between 30 minutes and 90 minutes), and a process temperature of more than 300 °C (for example, between 300 °C and 600 °C) to ensure that the first and second atoms diffuse out effectively.

[0056] In some embodiments, the maximum extension distance of the bonding structure 271 is between 0.1 nanometer and 100 nanometers, but the present invention is not limited thereto. The extension distance of the bonding structure 271 depends on the process temperature and execution time of the annealing process.

[0057] Please refer to Figure 2I , similar to Figure 1I , perform a planarization process to remove the excess vertical conductive connectors 140 on the buffer layer 270, so that the top surface 270a of the buffer layer 270 and the top surface 140a of the vertical conductive connectors 140 are coplanar, and the bottom surface 270b of the buffer layer 270 and the bottom surface 140b of the vertical conductive connectors 140 are coplanar.

[0058] Please refer to Figure 2J , Figure 2K and Figure 2L , similar to Figure 1J , Figure 1K and Figure 1L , form a seed layer 150 and a circuit layer 160 stacked in sequence on the substrate 110, and remove the part of the seed layer 150 exposed by the multiple openings of the circuit layer 160 through a lift-off process (such as using an appropriate etching solution) to complete the circuit fabrication. After the above processes, the fabrication of the substrate structure 200 of this embodiment is generally completed.

[0059] Figures 3A to 3E is a partial cross-sectional schematic diagram of a partial manufacturing method of a substrate structure according to another embodiment of the present invention. Specifically, Figures 3A to 3E shows the structure fabrication following the steps of Figure 1I .

[0060] Please refer to Figure 3A, after performing the annealing process, it further includes forming an insulating layer 380 on the substrate 110. The insulating layer 380 can be formed by a lamination process using ABF (Ajinomoto Build-up Film) material or a slit coating process using a photo imageable dielectric (PID) material, but the present invention is not limited thereto.

[0061] For example, the insulating layer 380 can entirely cover and directly contact the upper surface 110a and the lower surface 110b of the substrate 110, as well as the top surface 140a and the bottom surface 140b of the vertical conductive connector 140, but the present invention is not limited thereto.

[0062] Please refer to Figures 3B to 3E , first, as Figure 3B shown, a plurality of openings 380a are formed in the insulating layer 380 on both sides of the substrate 110 to expose the vertical conductive connector 140. Then, as Figures 3C to 3E shown, similar to Figures 1J to 1L , a seed layer 150 and a circuit layer 160 are sequentially stacked on the substrate 110, and the portion of the seed layer 150 exposed by the openings of the circuit layer 160 is removed by lift-off to complete the circuit fabrication. After the above processes, the fabrication of the substrate structure 300 of this embodiment is generally completed.

[0063] In some embodiments, it can further clean the bottom of the opening of the insulating layer 380, such as by a desmear process or a plasma process, to more surely expose the vertical conductive connector 140, but the present invention is not limited thereto.

[0064] In this embodiment, the circuit layer 160 formed on the insulating layer 380 can penetrate the insulating layer 380 and directly contact and be electrically connected to the vertical conductive connector 140. That is, the insulating layer 380 is located between the circuit layer 160 and the substrate 110, and the circuit layer 160 only directly contacts the vertical conductive connector 140, such that the circuit layer 160 does not directly contact the substrate 110.

[0065] Figures 4A to 4E is a partial cross-sectional view of a partial manufacturing method of a substrate structure according to another embodiment of the present invention. Specifically, Figures 4A to 4E shows the structure fabrication following the steps of Figure 2I .

[0066] Please refer to Figure 4A and Figure 4B , similar to Figure 3A and Figure 3B, after performing the annealing process, an insulating layer 380 is formed on the substrate 110. Then, a plurality of openings 380a are formed in the insulating layer 380 to expose the vertical conductive connectors 140, where the insulating layer 380 can be in direct contact with the buffer layer 270.

[0067] Please refer to Figures 4C to 4E , similar to Figures 3C to 3E , a seed layer 150 and a wiring layer 160 are sequentially stacked on the substrate 110, and the portion of the seed layer 150 exposed by the plurality of openings of the wiring layer 160 is removed through a lift-off process (such as using an appropriate etching solution) to complete the wiring fabrication. After the above processes, the fabrication of the substrate structure 400 of this embodiment can be substantially completed.

[0068] In summary, by introducing the annealing process, the atoms in the vertical conductive connectors diffuse to form a bonding structure extending in the direction of the substrate. In this way, the adhesion strength between it and adjacent components can be enhanced, and thus the product reliability can be effectively improved.

[0069] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A substrate structure, characterized in that: include: A substrate, wherein the substrate comprises a material having a heat-resistant temperature of 300° C. or more; as well as The vertical conductive connection penetrates through the substrate, wherein the vertical conductive connection has a bonding structure extending toward the substrate.

2. The substrate structure according to claim 1, characterized in that: The bond structure has irregular boundaries.

3. The substrate structure according to claim 1, characterized in that: The vertical conductive connection includes a plurality of first atoms, and the bonding structure is formed by the arrangement of the plurality of first atoms.

4. The substrate structure according to claim 1, characterized in that: The maximum extension distance of the bonding structure is between 0.1 nanometers and 100 nanometers.

5. The substrate structure according to claim 1, characterized in that: The bonding structure extends into the substrate.

6. The substrate structure according to claim 5, characterized in that: The vertical conductive connector is physically connected to the substrate.

7. The substrate structure according to claim 1, characterized in that: A buffer layer is also included, which is disposed between the substrate and the vertical conductive connection, wherein the bonding structure extends into the buffer layer.

8. The substrate structure according to claim 7, characterized in that: The vertical conductive connector is not physically connected to the substrate.

9. The substrate structure according to claim 7, characterized in that: The buffer layer has another bonding structure extending into the substrate.

10. The substrate structure according to claim 9, characterized in that: The vertical conductive connection includes a plurality of second atoms, and the another bonding structure is formed by the arrangement of the plurality of second atoms.

11. The substrate structure according to claim 1, characterized in that: It also includes a circuit layer and an insulating layer, wherein the insulating layer is located between the circuit layer and the substrate, and the circuit layer is directly in contact with and electrically connected to the vertical conductive connecting member only.

12. A method for manufacturing a substrate structure, characterized in that: include: Providing a substrate having a plurality of through holes and a conductive layer; bonding the substrate to the conductive layer; performing an electroplating process to form vertical conductive connections in the plurality of through holes; as well as An annealing process is performed to diffuse a plurality of first atoms in the vertical conductive connection toward the substrate to form a bonding structure.

13. The method for manufacturing a substrate structure according to claim 12, characterized in that: The annealing process is performed for more than 30 minutes.

14. The method for manufacturing a substrate structure according to claim 12, characterized in that: The process temperature of the annealing process is above 300° C.

15. The method for manufacturing a substrate structure according to claim 12, characterized in that: The step of forming a seed layer is not included before forming the vertical conductive connection.

16. The method for manufacturing a substrate structure according to claim 15, characterized in that: The plurality of first atoms are embedded in gaps in the material of the substrate.

17. The method for manufacturing a substrate structure according to claim 12, characterized in that: Before bonding the substrate to the conductive layer, the method further includes: A buffer layer is formed on the substrate, wherein a plurality of second atoms in the buffer layer diffuse toward the substrate after performing the annealing process to form another bonding structure.

18. The method for manufacturing a substrate structure according to claim 17, characterized in that: The plurality of first atoms are embedded in gaps of the material of the buffer layer, and the plurality of second atoms are embedded in gaps of the material of the substrate.

19. The method for manufacturing a substrate structure according to claim 12, characterized in that: After performing the annealing process, the method further includes: forming an insulating layer on the substrate; and A circuit layer is formed on the insulating layer, wherein the circuit layer penetrates the insulating layer and directly contacts and is electrically connected to the vertical conductive connecting member.

20. The method for manufacturing a substrate structure according to claim 12, characterized in that: Before bonding the substrate to the conductive layer, the method further includes: providing a carrier layer; and The conductive layer is bonded to the carrier layer.

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