Semiconductor package, power module, and method of manufacturing same

Abstract

The present application discloses a power module having a semiconductor package, wherein all interconnects are formed of direct copper (direct copper). Thus, the power module is suitable for use as a high efficiency power module. In addition, the direct copper interconnection also enhances the heat dissipation of the semiconductor package, so that the operation of the power module is more reliable, especially at high temperature. The power module also includes a substrate (e.g., a direct copper bond (DBC) substrate or a ceramic substrate) on which the semiconductor package is mounted; a plurality of external connection mechanisms coupled to the substrate for electrically leading out the power module; and the at least one signal lead is arranged on the substrate.

Description

Technical Field

[0001] This application relates to a semiconductor package, a power module, and a manufacturing method thereof. More specifically, this application relates to a power module of a semiconductor package with direct copper (Cu) interconnections. This application also relates to a panel-level method for manufacturing the semiconductor package and the power module. Background Art

[0002] Traditional power modules such as power converters use wire bonding to interconnect multiple components. However, they cannot meet the requirements of high power and high efficiency (including fast switching, high frequency, and high voltage and large current) and heat dissipation. At the same time, traditional power modules do not have sufficient reliability because wire bonding is easily damaged during long-term operation. Summary of the Invention

[0003] This application discloses a power module with a special semiconductor package. All interconnections in the special semiconductor package are direct copper (Cu) interconnections. Therefore, the power module is suitable for use as a high-efficiency power module. In addition, the direct copper (Cu) interconnections also enhance the heat dissipation of the semiconductor package, making the operation of the power module (especially at high temperatures) more reliable. The power module includes various forms of converters, such as an inverter for converting direct current (DC) to alternating current (AC), a rectifier for converting alternating current (AC) to direct current (DC), a chopper for converting direct current (DC) to direct current of different voltages, and a voltage regulator for converting alternating current (AC) to alternating current of different phases.

[0004] As a first aspect of this application, a semiconductor package for a power module is disclosed. The semiconductor package includes: at least one high-side semiconductor die having a high-side active surface and a high-side non-active surface; at least one low-side semiconductor die having a low-side active surface and a low-side non-active surface; a plurality of vertical structures surrounding the at least one high-side semiconductor die and at least one low-side semiconductor die, wherein each vertical structure has a front surface aligned with the high-side active surface and the low-side active surface, and a rear surface aligned with the high-side non-active surface and the low-side non-active surface; a molding layer for encapsulating the at least one high-side semiconductor die, at least one low-side semiconductor die, and the plurality of vertical structures; a front-side build-up layer coupled to the high-side active surface of the at least one high-side semiconductor die, the low-side active surface of the at least one low-side semiconductor die, and the front surface of the vertical structures; a back-side build-up layer coupled to the high-side non-active surface of the at least one high-side semiconductor die, the low-side non-active surface of the at least one low-side semiconductor die, and the rear surface of the vertical structures; and an external connection layer coupled to the back-side build-up layer.

[0005] As a second aspect of the present application, a power module is disclosed. The power module includes: a semiconductor package having at least one high-side semiconductor die and at least one low-side semiconductor die; a substrate (such as a direct copper bonding (DBC) substrate or a ceramic substrate) on which the semiconductor package is mounted, wherein functional circuits of the at least one low-side semiconductor die and the at least one high-side semiconductor die lead out from the substrate; an external connection mechanism coupled to the substrate for electrically leading out the power module; and at least one signal lead mounted on the substrate.

[0006] As a third aspect of the present application, a method of manufacturing a power module is disclosed. The method includes: forming a semiconductor package for the power module, wherein the semiconductor package includes at least one low-side semiconductor die and at least one high-side semiconductor die; mounting the semiconductor package onto a substrate (such as a direct copper bonding (DBC) substrate or a ceramic substrate), wherein functional circuits of the at least one low-side semiconductor die and the at least one high-side semiconductor die are led out to the substrate; coupling an external connection mechanism to the substrate; and mounting at least one signal lead onto the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings illustrate embodiments of the present application for explaining the principles of the disclosure of the present application. However, it should be understood that these drawings are for illustrative purposes only and do not limit the scope of the present application.

[0008] Figure 1 A flowchart of a panel-level method S10 for manufacturing a power module 100 having a semiconductor package 200 according to an exemplary embodiment of the present disclosure is shown.

[0009] Figure 2a and 2b Step S102 of the panel-level method S10 is shown.

[0010] Figures 3a to 3h Step S104 of the panel-level method S10 is shown.

[0011] Figure 4 Step S106 of the panel-level method S10 is shown.

[0012] Figures 5a to 5c Step S108 of the panel-level method S10 is shown.

[0013] Figures 6 to 8 An optional step S110 of the panel-level method S10 is shown.

[0014] Figure 9 and Figure 10 Step S112 of the panel-level method S10 is shown.

[0015] Figures 11 to 16 Shows step S114 of the panel-level method S10.

[0016] Figure 17 Shows step S116 of the panel-level method S10.

[0017] Figures 18a to 18d Shows the first embodiment of steps S118 and S120 of the panel-level method S10.

[0018] Figure 19a and 19b Shows embodiment 260 of the semiconductor package 200 obtained from the panel-level method S10.

[0019] Figure 20 Shows the second embodiment of steps S118 and S120 of the panel-level method S10.

[0020] Figures 21a to 21c Shows other embodiments 270, 280, and 290 of the semiconductor package 200 obtained from the panel-level method S10.

[0021] Figures 22a to 22d Shows other embodiments 300, 310, 320, and 330 of the semiconductor package 200 obtained from the panel-level method S10.

[0022] Figures 23a to 25b Shows step S122 of the panel-level method S10.

[0023] Figures 26a to 27a Shows an embodiment of step S124 of the panel-level method S10 and an embodiment 400 of the power module 100.

[0024] Figure 27b Shows the optional step S126 of performing the panel-level method S10 on embodiment 400 to form a corresponding another embodiment 410 of the power module 100.

[0025] Figure 28a and 28b Shows the optional step S128 of performing the panel-level method S10 on embodiment 400 to form a corresponding embodiment 420 of the power module 100.

[0026] Figure 29 Shows the optional step S126 of performing the panel-level method S10 on embodiment 420 to form a corresponding another embodiment 430 of the power module 100.

[0027] Figure 30a and 30bShows another optional step S130 of the panel-level method S10, thereby forming a corresponding embodiment 440 of the power module 100.

[0028] Figure 30c Shows an optional step S126 of the panel-level method S10 for the embodiment 440, thereby forming another corresponding embodiment 450 of the power module 100.

[0029] Figures 31a to 33b Shows other embodiments 460, 470, 480, 490, 500, and 510 of the power module 100.

[0030] Figure 34a and 34b Shows two other embodiments 340, 350 of the semiconductor package 200.

[0031] Figure 35a and 35b Shows another embodiment of step S124 of the panel-level method S10, using the embodiment 340 of the semiconductor package 200 to manufacture the embodiment 520 of the power module 100.

[0032] Figure 36a and 36b Shows other embodiments 530, 540 of the power module 100 with a liquid cooling system.

[0033] Reference numeral

[0034] 100 Power module, 102 First carrier, 1022 Upper surface of the carrier, 104 First heat release tape, 106 Second carrier, 1062 Upper surface of the carrier, 108 Second heat release tape, 110 Substrate, 1102 First conductive layer, 1104 Second conductive layer, 1106 Third conductive layer, 1108 Fourth conductive layer, 1110 Bottom surface, 1112 Alternating current (AC) conductive layer, 1114 Direct current (DC) conductive layer, 1116 Low-side wiring, 1118 High-side wiring, 112, 112’ External connection mechanism, 1122 AC copper clip, 1124 DC positive (DC+) copper clip, 1126 DC negative (DC-) copper clip, 114 First part, 116 Second part, 118 Third part, 120 First conductive joint, 122 Second conductive joint, 124 Third conductive joint, 130 First signal lead, 132 Upper surface of the lead, 134 Second signal lead, 138 Integral signal lead, 1382 Top, 1384 Bottom, 140 Module molding layer, 142 Fastener, 150 Heat sink, 160 First liquid cooling system, 162 Intermediate component, 164 Second liquid cooling system, 200 Semiconductor package, 202 Low-side semiconductor die, 2022 Low-side active surface, 2024 Low-side non-active surface, 2026 Low-side pre-through hole, 2028 Low-side filled through hole, 204 High-side semiconductor die, 2042 High-side active surface, 2044 High-side non-active surface, 2046 High-side pre-through hole, 2048 High-side filled through hole, 206 Copper pillar, 2062 Front surface, 2064 / 2064’ Rear surface / (new) rear surface, 2066 Top, 2072 First copper pillar, 2074 Second copper pillar, 2076 Third copper pillar, 2078 Fourth copper pillar, 208 Molding layer, 2082 First molding surface, 2084 Second molding surface, 2086a First top, 2086b Second top, 2092 Low-side gate current path, 2094 High-side gate current path, 210 Molding panel, 2102 (Molding panel) front surface, 2104 (Molding panel) rear surface, 212 Grinding device, 220 Backside build-up layer, 2204 (Backside build-up layer) upper surface, 222 Backside seed layer, 224 Backside redistribution layer (RDL) 2244 (Backside redistribution layer (RDL)) upper surface, 226 Backside dielectric layer, 2264 (Backside dielectric layer) upper surface, 2266 (Backside dielectric layer) top, 230 Front-side build-up layer, 232 First front-side seed layer, 234 First front-side redistribution layer (RDL), 236 First front-side dielectric layer, 2364 (First front-side dielectric layer) upper surface, 238 Groove, 240 Filled groove, 242 Second front-side seed layer, 244 Second front-side redistribution layer (RDL), 246 Second front-side dielectric layer, 2462 (Second front-side dielectric layer) top, 248 External connection layer, 2482 Low-side external connection layer, 2484 High-side external connection layer, 2486 First external connection layer, 2487 Second external connection layer,2488 The third external connection layer, 2489 The fourth external connection layer, 249 External connection dielectric layer, 250 Sub-panel, 252 Molded Interconnect Substrate (MIS) unit, 2522 Wiring layer, 2522a The first wiring layer, 2522b The second wiring layer, 2524 Insulating portion, 2526 MIS front surface, 2528 MIS rear surface, 254 Molded Via Substrate (MVS) unit, 2542 Conductive via, 2544 Insulating portion, 2546 MVS front surface, 2548 MVS rear surface, 256 Metal frame, 2562 Connection pad, 2564 Connection bar, 257 Metal unit, 2572 The first vacant space, 2574 The second vacant space, 258 Temporary support, 260 - 340 Embodiments of semiconductor packages, 400 - 540 Embodiments of power modules. Detailed description

[0035] Figure 1 A flowchart of a panel - level method S10 for manufacturing a power module 100 having a semiconductor package 200 according to an exemplary embodiment of the present disclosure is shown. The panel - level method S10 includes steps S102 to step S124, and also includes optional steps S126, step S128, and S130.

[0036] Figure 2a and Figure 2b Step S102 of the panel - level method S10 is shown, which is to provide a first carrier 102 and a possible first thermal release tape 104. Figure 2a A cross - sectional view of a part of the first carrier 102 and a part of the first thermal release tape 104 fixed on this part is shown. Figure 2b A top view of this part of the first carrier 102 is shown, which has a rectangular shape. Thus, the first carrier 102 has a plurality of such Figure 2b parts as shown. In one embodiment, the first carrier 102 has a square shape with dimensions of 700 millimeters (mm)×700 millimeters (mm), which is much larger than a conventional wafer with a diameter of 8 inches or 12 inches. Therefore, the panel - level method S10 has a higher productivity than the conventional wafer - level method. It should be understood that the first carrier 102 may also have other shapes, such as rectangular or circular. The first thermal release tape 104 can almost completely cover the carrier upper surface 1022 of the first carrier 102 to improve productivity.

[0037] Figures 3a to 3h Step S104 of the panel - level method S10 is shown, which is to bond a semiconductor die and a vertical structure to the first carrier 102 and the first thermal release tape 104. The first thermal release tape 104 has sufficient adhesiveness at room temperature to fix the semiconductor die and the vertical structure in place on the first carrier 102. Figure 3aA cross-sectional view is shown in which a plurality of low-side semiconductor dies 202 and a plurality of high-side semiconductor dies 204 are bonded to respective predetermined positions on a first carrier 102 and a first thermal release tape 104. The terms "low side" and "high side" refer to the higher-voltage side and the lower-voltage side, respectively. Thus, the low-side semiconductor dies 202 and the high-side semiconductor dies 204 will be electrically coupled to one end (input or output) of a lower voltage and the other end (input or output) of a higher voltage of a power module, respectively. The low-side semiconductor dies 202 and the high-side semiconductor dies 204 can be metal-oxide semiconductor field effect transistors (MOSFETs) made of silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). Specifically, the low-side semiconductor dies 202 and the high-side semiconductor dies 204 can be bonded in a face-down manner, i.e., the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204 are in contact with the upper surface 1022 of the carrier of the first thermal release tape 104 and the first carrier 102. The low-side semiconductor dies 202 and the high-side semiconductor dies 204 have low-side inactive surfaces 2024 and high-side inactive surfaces 2044, respectively, which are opposite to the low-side active surface 2022 and the high-side active surface 2042. The low-side semiconductor dies 202 and the high-side semiconductor dies 204 can be configured to have the same die thickness, such that the low-side active surface 2022 and the low-side inactive surface 2024 of the low-side semiconductor die 202 are coplanar with the high-side active surface 2042 and the high-side inactive surface 2044 of the high-side semiconductor die 204, respectively.

[0038] The low-side semiconductor dies 202 and the high-side semiconductor dies 204 each have a low-side pre-through hole 2026 and a high-side pre-through hole 2046 at the low-side active surface 2022 and the high-side active surface 2042, respectively. The low-side pre-through hole 2026 and the high-side pre-through hole 2046 can be filled with a conductive material such as copper (Cu) or a titanium / copper (Ti / Cu) composite material, and are respectively transformed into a low-side filled through hole 2028 of the low-side semiconductor die 202 and a high-side filled through hole 2048 of the high-side semiconductor die 204. Thus, the functional circuits of the low-side semiconductor dies 202 and the high-side semiconductor dies 204 can be led out from the contact pads at the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204, respectively, through the low-side filled through hole 2028 and the high-side filled through hole 2048.

[0039] The low-side semiconductor die 202 and the high-side semiconductor die 204 can be obtained by dicing a received low-side semiconductor wafer (not shown) and a received high-side semiconductor wafer (not shown) from a customer, respectively. The received low-side semiconductor wafer and the received high-side semiconductor wafer have functional circuits at their respective wafer active surfaces. They can be silicon (Si) wafers, silicon carbide (SiC) wafers, or gallium nitride (GaN) wafers; their wafer non-active surfaces are made of the same semiconductor material. Therefore, after dicing, the respective wafer active surfaces of the received low-side semiconductor wafer and the received high-side semiconductor wafer form a low-side active surface 2022 and a high-side active surface 2042, respectively, which have the functional circuits of the low-side semiconductor die 202 and the high-side semiconductor die 204; at the same time, the respective wafer non-active surfaces of the received low-side semiconductor wafer and the received high-side semiconductor wafer form a low-side non-active surface 2024 and a high-side non-active surface 2044, respectively. Additionally, the received low-side semiconductor wafer and the received high-side semiconductor wafer may each have a conductive layer on their wafer non-active surfaces. After dicing, the conductive layers remain at the low-side non-active surface 2024 and the high-side non-active surface 2044, respectively. The conductive layers will serve as external connection layers 248 in subsequent processes.

[0040] The vertical structure can take various forms. For example, the vertical structure can be first fabricated into individual sheets and then bonded to the first carrier 102 and the first thermal release film 104. Alternatively, the vertical structures can be bonded in a group, that is, multiple vertical structures are bonded to the first carrier 102 and the first thermal release film 104 as a whole in a single process. In Figure 3a the embodiment shown, the vertical structure can include a plurality of copper (Cu) pillars 206 bonded to the first carrier 102 and the first thermal release tape 104, which are first fabricated into individual sheets and then bonded around the low-side semiconductor die 202 and the high-side semiconductor die 204. The copper pillars 206 have a front surface 2062 aligned with the low-side active surface 2022 / high-side active surface 2042 and a rear surface 2064 aligned with the low-side non-active surface 2024 / high-side non-active surface 2044. Specifically, the front surface 2062 of the copper pillar 206 contacts the carrier upper surface 1022 of the first thermal release tape 104 and the first carrier 102. Therefore, the front surface 2062 of the copper pillar 206 is coplanar with the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204. At the same time, the copper pillar 206 has a pillar height (measured between the front surface 2062 and the rear surface 2064) greater than the die thickness of the low-side semiconductor die 202 and the high-side semiconductor die 204. In Figure 3aIn the illustrated embodiment, for each semiconductor package 200, the copper pillars 206 include two first copper pillars 2072 located on the low side, and one second copper pillar 2074 located between the two first copper pillars 2072, which coincide in a direction perpendicular to Figure 3a the illustrated direction. Similarly, the copper pillars 206 also include two third copper pillars 2076 located on the high side, and one fourth copper pillar 2078 located between the two third copper pillars 2076, which coincide in a direction perpendicular to Figure 3a the illustrated direction.

[0041] In another embodiment as Figure 3b illustrated, the vertical structure may include a plurality of Molded Interconnect Substrates (MIS) units 252. The MIS units 252 are first fabricated as separate sheets and then bonded around the low-side semiconductor die 202 and the high-side semiconductor die 204. Figure 3b An enlarged view of the MIS unit 252 is shown in the upper left corner of. Among them, the MIS unit 252 further includes a plurality of interconnected wiring layers 2522 for electrical conduction; and an insulating portion 2524 for insulating the wiring layers 2522 within the MIS unit 252. The wiring layer 2522 can be made of any conductive material, such as copper. Compared with the copper pillars 206, the MIS unit 252 consumes less copper, so the weight of the semiconductor package 200 can be reduced. Similarly, the MIS unit 252 has an MIS front surface 2526, which is coplanar with the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204. The MIS unit 252 has an MIS height (measured between the MIS front surface 2526 and the MIS back surface 2528 of the MIS unit 252), which is greater than the die thickness of the low-side semiconductor die 202 and the high-side semiconductor die 204. Figure 3b The enlarged view of also shows that the wiring layers 2522 of the MIS unit 252 have a first wiring layer 2522a and a second wiring layer 2522b at the MIS front surface 2526 and the MIS back surface 2528, respectively. In particular, the first wiring layer 2522a and the second wiring layer 2522b are exposed from the insulating portion 2524 of the MIS unit 252.

[0042] In another embodiment as Figure 3c illustrated, the vertical structure may include a plurality of Molded Via Substrate (MVS) units 254. The MVS units 254 are first fabricated as separate sheets and then bonded around the low-side semiconductor die 202 and the high-side semiconductor die 204. Figure 3cAn enlarged view of the MVS unit 254 is shown in the upper left corner. Among them, the MVS unit 254 further includes a plurality of conductive vias 2542 for electrical conduction; and an insulating portion 2544 for insulating the conductive vias 2542 within the MVS unit 254. The conductive vias 2542 can be made of any conductive material, such as copper (Cu). Similar to the MIS unit 252, the MVS unit 254 consumes less copper, thus reducing the weight of the semiconductor package 200. The figure also shows that the MVS unit 254 has an MVS front surface 2546, which is coplanar with the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204. The MVS unit 254 has an MVS height (measured between the MVS front surface 2546 and the MVS back surface 2548 of the MVS unit 254), which is greater than the die thickness of the low-side semiconductor die 202 and the high-side semiconductor die 204. The MIS unit 252 and the MVS unit 254 have the same function as the copper pillar 206. For the sake of simplicity of description, the subsequent processes will only be described using the copper pillar 206. However, it should be understood that the subsequent processes are also applicable to the MIS unit 252 and the MVS unit 254.

[0043] As Figures 3d to 3g shown in another embodiment, in this vertical structure, it may include a metal frame 256, which is bonded in a group manner. Figure 3d And Figure 3e show a cross-sectional view and a top view respectively. The metal frame 256 includes an array of metal units 257, as Figure 3d And Figure 3e shown by the dashed rectangles in, which are 2 metal units 257. The metal frame 256 can be an existing lead frame in the industry, or can be formed by etching or mechanically stamping a metal sheet according to actual needs. The metal sheet to be patterned can be made of a single metal or an alloy such as copper. The surface of the metal sheet can be partially or completely coated with a second metal such as nickel and / or gold to protect the metal sheet from environmental erosion such as oxidation. In some embodiments, the thickness of the metal sheet is not less than the die thickness of the semiconductor dies 202 and 204. As Figure 3e shown, the metal sheet is patterned to include 2 identical metal units 257, and each metal unit 257 has the same rectangular outer contour. However, this design is only exemplary, and the number of metal units 257 is not limited to 2 and can be set according to actual needs. The shape of the metal unit 257 can be rectangular or other shapes.

[0044] The metal frame 256 includes a plurality of connection pads 2562, which are arranged inside the outer contour edge of the metal frame 256, or can also be arranged at other positions according to actual needs. The connection pads 2562 are connected by connection bars 2564, and the connection bars 2564 are formed by the metal that is not etched off the metal sheet. When patterning the metal sheet, the connection bars 2564 are reserved to ensure that some features such as the connection pads 2562 formed by patterning the metal sheet are connected to the outer contour edge of the metal frame 256, so as to ensure that the patterned features on the metal frame 256 will not be deformed or even fall off during the transfer process of the metal frame 256. Preferably, first, the metal part is fixed on the temporary support 258 for patterning. After the patterning is completed, the metal frame 256 is transferred to the first carrier 102 and the first thermal release tape 104 through the temporary support 258. However, it should be understood that the connection pads 2562 can also be individually bonded to the temporary support 258; however, it can be understood that the connection pads 2562 can be individually joined to the temporary support 258, and there is no need to retain the connection bars 2562 during the etching or mechanical stamping of the metal part.

[0045] The metal frame 256 includes a plurality of vacant positions, including a first vacant position 2572 and a second vacant position 2574, for accommodating the high-side semiconductor die 204 and the low-side semiconductor die 202 respectively in subsequent processes (as Figure 3g shown). Then, Figure 3f Fig. shows a cross-sectional view in which the connection bars 2564 are removed along the cutting line on the temporary support 258, so that the connection pads 2562 are separated individually but fixed on the temporary support 258 and remain stationary.

[0046] Figure 3g Fig. shows a cross-sectional view in which the metal unit 257 on the temporary support 258 is flipped and faces the first carrier 102 and the first thermal release tape 104. Specifically, the metal unit 257 is precisely positioned relative to the first carrier 102 and the first thermal release tape 104, so that the first vacant position 2572 and the second vacant position 2574 of the metal unit 257 are aligned with the high-side semiconductor die 204 and the low-side semiconductor die 202 to accommodate them. Although Figure 3g only one metal unit 257 is shown in Fig., it should be understood that all the metal units 257 on the temporary support 258 are flipped as a whole and bonded to the first carrier 102 and the first thermal release tape 104.

[0047] Figure 3hA top view is shown, with the low-side semiconductor die 202 and the high-side semiconductor die 204 arranged according to the design of the semiconductor package 200 (as shown by the dashed rectangle). In one embodiment, the semiconductor package 200 has a set of 8 low-side semiconductor dies 202 on the left side (low side) of the figure and another set of 8 high-side semiconductor dies 204 on the right side (high side) of the figure. It should be understood that the design of the semiconductor package 200 can be changed to have other numbers of low-side semiconductor dies 202 and / or high-side semiconductor dies 204. This portion of the first carrier 102 and the corresponding first thermal release tape 104 as shown have 12 semiconductor packages 200, arranged in a matrix of 3 rows and 4 columns. It should be understood that more semiconductor packages 200 (e.g., hundreds or even thousands) can be bonded to the entire first carrier 102 and the corresponding first thermal release tape 104 while performing subsequent processes to improve productivity.

[0048] Figure 4 The step S106 of the panel-level method S10 is shown, that is, forming a molding layer 208 for encapsulating the low-side semiconductor die 202, the high-side semiconductor die 204, and the copper pillar 206 to form a molded panel 210. The low-side non-active surface 2024 of the low-side semiconductor die 202, the high-side non-active surface 2044 of the high-side semiconductor die 204, and the rear surface 2064 of the copper pillar 206 are completely encapsulated in the molding layer 208; while the low-side active surface 2022 of the low-side semiconductor die 202, the high-side active surface 2042 of the high-side semiconductor die 204, and the front surface 2062 of the copper pillar 206 are not encapsulated because they are in contact with the first thermal release tape 104 and the carrier upper surface 1022 of the first carrier 102. Specifically, the molding layer 208 has a first molding surface 2082 that contacts the first thermal release tape 104 and the carrier upper surface 1022 of the first carrier 102. Therefore, the first molding surface 2082 is coplanar with the low-side active surface 2022 of the low-side semiconductor die 202, the high-side active surface 2042 of the high-side semiconductor die 204, and the front surface 2062 of the copper pillar 206. The molding layer 208 can be formed from any molding compound by any suitable method, for example, formed by compression molding using Sumitomo G730.

[0049] Figures 5a to 5c The step S108 of the panel-level method S10 is shown, that is, thinning the molding layer 208 to the required thickness of the molded panel 210. In one embodiment, step S108 can be divided into two sub-steps for implementation. Figure 5a A cross-sectional view of the first sub-step is shown, removing its first top 2086a from the molding layer 208 by a grinding device 212 (as Figure 5aas shown by the dashed rectangle in [Fig.]. In the first sub-step, the rear surface 2064 of the copper pillar 206 can be retained and exposed from the molding layer 208; while the low-side inactive surface 2024 of the low-side semiconductor die 202 and the high-side inactive surface 2044 of the high-side semiconductor die 204 remain encapsulated. The first sub-step can be performed in a rapid manner to improve productivity. Then, Figure 5b shows a cross-sectional view of the second sub-step, that is, further removing its second top 2086b from the molding layer 208 (as Figure 5b shown by the dashed rectangle in [Fig.]. Thus, after the second sub-step, the molding layer 208 has a second molding surface 2084. Specifically, the low-side inactive surface 2024 of the low-side semiconductor die 202 and the high-side inactive surface 2044 of the high-side semiconductor die 204 are exposed from the second molding surface 2084 of the molding layer 208. Correspondingly, in the second sub-step, a top 2066 of the copper pillar 206 (as Figure 5a shown by the dashed square in [Fig.]) is also removed by the grinding device 212, thereby forming a new rear surface 2064' and exposing it from the second molding surface 2084 of the molding layer 208. The second sub-step is performed slower than the first sub-step to avoid damaging the low-side inactive surface 2024 of the low-side semiconductor die 202 and the high-side inactive surface 2044 of the high-side semiconductor die 204. The second sub-step is also referred to as "lapping" of the molding layer 208. Preferably, to improve productivity, the thickness of the second top 2086b is less than the thickness of the first top 2086a. Figure 5c shows a top view of a part of the molding panel 210, where the low-side inactive surface 2024 of the low-side semiconductor die 202, the high-side inactive surface 2044 of the high-side semiconductor die 204, and the new rear surface 2064' of the copper pillar 206 are exposed from the second molding surface 2084 of the molding layer 208.

[0050] Figures 6 to 8 shows step S110 of the panel-level method S10, that is, forming a backside build-up layer 220 at the rear surface 2104 of the molding panel 210. The rear surface 2104 includes the low-side inactive surface 2024 of the low-side semiconductor die 202, the high-side inactive surface 2044 of the high-side semiconductor die 204, the new rear surface 2064' of the copper pillar 206, and the second molding surface 2084 of the molding layer 208. Figure 6 shows a cross-sectional view of forming a backside seed layer 222 on the rear surface 2104 of the molding panel 210. The backside seed layer 222 is electrically coupled to the copper pillar 206 at the new rear surface 2064'. The backside seed layer 222 can be formed of any conductive material by any suitable method. In one embodiment, the backside seed layer 222 is formed by sputtering a titanium / copper (Ti / Cu) composite material. Then, Figure 7A cross-sectional view is shown in which a backside redistribution layer (RDL) 224 is formed on the backside seed layer 222. The backside RDL 224 can be formed of any conductive material by any suitable method. In one embodiment, the backside RDL 224 is formed of copper (Cu) by electroplating. The backside RDL 224 can also be patterned by any suitable method (e.g., photolithography). Thus, the copper pillars 206 are electrically coupled to the backside RDL 224 for current / signals to pass through. Subsequently, Figure 8 A cross-sectional view is shown in which a backside dielectric layer 226 is formed to encapsulate the backside RDL 224. The backside dielectric layer 226 can be formed of any dielectric material, such as a molding compound, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), or other materials having similar insulating and structural properties. Then, a top portion 2266 of the backside dielectric layer 226 (as shown by the dashed rectangle in Figure 8 ) is removed by a grinding device 212 in a grinding process to expose the backside RDL 224 from the backside dielectric layer 226. Thus, the backside build-up layer 220 includes the backside RDL 224 and the backside dielectric layer 226. Preferably, the grinding process can also make the upper surface 2204 of the backside build-up layer 220 have a substantially flat configuration, which is conducive to subsequent processes in step S112. The upper surface 2204 includes the upper surface 2244 of the backside RDL 224 and the upper surface 2264 of the backside dielectric layer 226.

[0051] Figure 9 and Figure 10 Step S112 of the panel-level method S10 is shown, that is, the molded panel 210 having the backside build-up layer 220 is transferred to the second carrier 106. Figure 9 A cross-sectional view of the molded panel 210 having the backside build-up layer 220 is shown. Since the first thermal release tape 104 loses its adhesiveness at high temperatures, the backside build-up layer 220 can be separated from the first carrier 102 at high temperatures. Thus, the front surface 2102 of the molded panel 210 is exposed from the first carrier 102 and the first thermal release tape 104. The front surface 2102 of the molded panel 210 includes the low-side active surface 2022 of the low-side semiconductor die 202, the high-side active surface 2042 of the high-side semiconductor die 204, the front surface 2062 of the copper pillars 206, and the first molded surface 2082 of the molding layer 208. Subsequently, Figure 10A cross-sectional view is shown in which the molded panel 210 having the backside build layer 220 is flipped and mounted onto the second carrier 106 and the second thermal release tape 108. As described above, the molded panel 210 has a substantially flat configuration, so that the molded panel 210 can be mounted on the second carrier 106 and the second thermal release tape 108 quite stably. At the same time, the second thermal release tape 108 has sufficient adhesiveness at room temperature to fix the molded panel 210 having the backside build layer 220 at an appropriate position on the carrier upper surface 1062 of the second carrier 106. The low-side pre-via holes 2026 of the low-side semiconductor die 202, the high-side pre-via holes 2046 of the high-side semiconductor die 204, and the front surface 2062 of the copper pillar 206 are exposed from the first molding surface 2082 of the molding layer 208.

[0052] Figures 11 to 16 Step S114 of the panel-level method S10 is shown, i.e., forming the front-side build layer 230 on the front surface 2102 of the molded panel 210. Figure 11 A cross-sectional view is shown in which, following the contours of the low-side pre-via holes 2026 of the low-side semiconductor die 202, the high-side pre-via holes 2046 of the high-side semiconductor die 204, the front surface 2062 of the copper pillar 206, and the first molding surface 2082 of the molding layer 208, the first front-side seed layer 232 is formed conformally. The first front-side seed layer 232 can be made of any conductive material by any suitable method. In one embodiment, the first front-side seed layer 232 is made of a titanium / copper (Ti / Cu) composite material by sputtering. Thus, the first front-side seed layer 232 is electrically coupled to the front surface 2062 of the copper pillar 206. After forming the first front-side seed layer 232, a Die Location Check (DLC) process can be performed to check whether the low-side semiconductor die 202 and the high-side semiconductor die 204 are bonded to their predetermined positions. If not, the DLC process will collect the actual positions of the low-side semiconductor die 202 and the high-side semiconductor die 204 in the molded panel 210.

[0053] Figure 12A cross-sectional view is shown. According to the actual positions of the low-side semiconductor die 202 and the high-side semiconductor die 204, the low-side pre-vias 2026 of the low-side semiconductor die 202 and the high-side pre-vias 2046 of the high-side semiconductor die 204 are filled with a conductive material and are respectively transformed into low-side filled vias 2028 and high-side filled vias 2048. Then, a first front-side redistribution layer (RDL) 234 is formed on the front surface 2102 of the molding panel 210. The first front-side RDL 234 can be made of any conductive material such as metal by any suitable method. Preferably, the first front-side RDL 234 is made of copper (Cu) by electroplating. Thus, the first front-side RDL 234 is electrically coupled to the low-side filled vias 2028 of the low-side semiconductor die 202, the high-side filled vias 2048 of the high-side semiconductor die 204, and the front surface 2062 of the copper pillar 206. Thus, the functional circuits of the low-side semiconductor die 202 and the high-side semiconductor die 204 are led out from the contact pads at the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204, respectively, through the first front-side RDL 234 and the copper pillar 206 to the back-side RDL 224 of the back-side build-up layer 220. Alternatively, before bonding the low-side semiconductor die 202 and the high-side semiconductor die 204 to the first carrier 102 and the first thermal release tape 104, the low-side pre-vias 2026 of the low-side semiconductor die 202 and the high-side pre-vias 2046 of the high-side semiconductor die 204 can be filled. Thus, the filling of the low-side pre-vias 2026 of the low-side semiconductor die 202 and the high-side pre-vias 2046 of the high-side semiconductor die 204 can be skipped here. Figures 3a to 3d Before bonding the low-side semiconductor die 202 and the high-side semiconductor die 204 to the first carrier 102 and the first thermal release tape 104, the low-side pre-vias 2026 of the low-side semiconductor die 202 and the high-side pre-vias 2046 of the high-side semiconductor die 204 can be filled. Thus, the filling of the low-side pre-vias 2026 of the low-side semiconductor die 202 and the high-side pre-vias 2046 of the high-side semiconductor die 204 can be skipped here.

[0054] Figure 13 A cross-sectional view is shown. A first front-side dielectric layer 236 is formed to encapsulate the first front-side RDL 234. The first front-side dielectric layer 236 can be made of any dielectric material, such as a molding compound, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), or other materials with similar insulating and structural properties. The first front-side dielectric layer 236 can be formed by any suitable method, such as the compression molding process of Sumitomo G730. Preferably, the first front-side dielectric layer 236 is formed by a thin-film lamination process to control the first front-side dielectric layer 236 at a specific first thickness, such as 100 micrometers (μm). Before forming the first front-side dielectric layer 236, the first front-side seed layer 232 can be removed by any suitable method, such as chemical etching, to ensure electrical insulation between the first front-side RDL 234. Thus, a front-side build-up layer 230 including the first front-side RDL 234 and the first front-side dielectric layer 236 is formed.

[0055] Figure 14A cross-sectional view is shown in which a plurality of grooves 238 are formed in the first front-side dielectric layer 236. The grooves 238 can be formed by any suitable panel-level method, such as laser drilling, photolithography, photoimageable, etc., according to the design of the semiconductor package 200. For photolithography or photoimageable techniques, the first front-side dielectric layer 236 can be made of a solder mask material or a photoimageable dielectric material for forming the grooves 238 in the first front-side dielectric layer 236. The solder mask material can include resins (such as epoxy resin, polyurethane, acrylic), hardeners, fillers, dyes, and ultraviolet reactive substances, etc. Preferably, the solder mask material includes TAIYO PSR-4000 series materials. Thus, a portion of the first front-side RDL 234 is exposed from the first front-side dielectric layer 236 through the grooves 238. Then, the second front-side seed layer 242 is conformally formed by following the contours of the grooves 238 and the upper surface 2364 of the first front-side dielectric layer 236. The second front-side seed layer 242 can be formed of any conductive material by any suitable method. In one embodiment, the second front-side seed layer 242 is formed by sputtering a titanium / copper (Ti / Cu) composite material. Thus, the second front-side seed layer 242 is electrically coupled to the first front-side RDL 234. Figure 15 A cross-sectional view is shown in which the grooves 238 are filled by electroplating or other methods using conductive materials such as copper (Cu) or titanium / copper (Ti / Cu) composites, and are accordingly transformed into filled grooves 240. Then, a second front-side redistribution layer (RDL) 244 is formed on the filled grooves 240 and the second front-side seed layer 242. The second front-side RDL 244 can be formed of any conductive material such as metal by any suitable method. Preferably, the second front-side RDL 244 is formed by electroplating copper (Cu). Thus, the second front-side RDL 244 is electrically coupled to the first front-side RDL 234 through the filled grooves 240.

[0056] Figure 16A cross-sectional view is shown, forming a second front-side dielectric layer 246 for encapsulating the second front-side RDL 244. The second front-side dielectric layer 246 can be made of any dielectric material, such as a molding compound, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), or other materials with similar insulating and structural properties. The second front-side dielectric layer 246 can be formed by any suitable method, such as a compression molding process or a thin film lamination process. Subsequently, a grinding process can be performed on the second front-side dielectric layer 246 by a grinding device 212 to remove the top 2462 of the second front-side dielectric layer 246, thereby reducing the second front-side dielectric layer 246 to a specific second thickness according to the design of the semiconductor package 200. Thus, the front-side build-up layer 230 shown herein has a first layer including the first front-side RDL 234 and the first front-side dielectric layer 236; a second layer including the second front-side RDL 244 and the second front-side dielectric layer 246; and a fill groove 240 for electrically coupling the first layer and the second layer. It can be understood that the front-side build-up layer 230 can also include more other layers that are the same or similar to the first layer or the second layer, and more other fill grooves that are the same or similar to the fill groove 240 for electrically coupling the more other layers. Before forming the second front-side dielectric layer 246, the second front-side seed layer 242 is removed by any suitable method (such as chemical etching) to ensure electrical insulation between the second front-side RDLs 244.

[0057] Figure 17 The step S116 of the panel-level method S10 is shown, that is, since the second thermal release tape 108 loses its adhesiveness at a higher temperature, the molded panel 210 having a back-side build-up layer 220 and a front-side build-up layer 230 (such as including the first layer and the second layer as described above) can be separated from the second carrier 106 and the second thermal release tape 108. Thus, the back-side build-up layer 220 is exposed from the second carrier 106 and the second thermal release tape 108.

[0058] Figures 18a to 18d A first embodiment of steps S118 and S120 of the panel-level method S10 is shown. Step S118 is optional and thus can be skipped. For example, as Figures 22a to 22d and Figure 34b shown in the semiconductor package 200, where the external connection layer 248 is directly formed on the rear surface 2104 of the molded panel 210. Figure 18a A cross-sectional view is shown, cutting the molded panel 210 having a back-side build-up layer 220 and a front-side build-up layer 230 (such as including the first layer and the second layer as described above) into a plurality of sub-panels 250 along a saw line, and the size of the sub-panels 250 is smaller than that of the molded panel 210. In one embodiment, the size of the sub-panels 250 is 212 millimeters (mm) × 216 millimeters (mm). Figure 18bA top view is shown. The sub-panel 250 has six semiconductor packages 200 arranged in a 2-row by 3-column matrix. It should be understood that the sub-panel 250 may also have other numbers and arrangements of semiconductor packages 200. Then, Figure 18c A cross-sectional view of the sub-panel 250 is shown. At the scale of the sub-panel 250, an external connection layer 248 is formed on the backside RDL 224 exposed at the backside dielectric layer 226 of the build-up layer 220 from the backside. The external connection layer 248 can be formed of any conductive material such as metal by any suitable method to form a surface finish for providing a flat surface for input / output (I / O). The surface finish can be made of a single layer of metal such as tin or a single layer metal composite such as nickel / gold. Alternatively, the surface finish can also be made of multiple layers. In some embodiments, the surface finish is made of electroless nickel immersion gold (ENIG), which has a two-layer metal surface coating, where the first nickel layer can be formed using an electroless chemical reaction; then a very thin gold layer is plated on top of the nickel layer. In other embodiments, the surface finish can be made of electroless nickel electroless palladium immersion gold (ENEPIG), which is formed by depositing electroless nickel, subsequently depositing electroless palladium, and finally immersion gold flash. Preferably, the external connection layer 248 is formed by electroplating silver (Ag) to form the surface finish. The surface finish is chemically compatible with the I / O to improve the stability of the connection. The thickness of the surface finish can be in the range of 1 micrometer (μm) to 10 micrometers (μm), preferably in the range of 1 micrometer (μm) to 5 micrometers (μm), or more preferably in the range of 1 micrometer (μm) to 3 micrometers (μm). Finally, Figure 18d A cross-sectional view is shown. According to the design of the semiconductor package 200, the sub-panel 250 having the external connection layer 248 is further divided into individual semiconductor packages 200 along the saw lines.

[0059] Figure 19a and 19b An embodiment 260 of the semiconductor package 200 obtained from the panel-level method S10 is shown. Figure 19aA cross-sectional view of Example 260 is shown, in which all the interconnections in the semiconductor package 200 are formed of direct copper, i.e., the interconnections between the contact pads and the low-side filled vias 2028 of the low-side semiconductor die 202 and the high-side filled vias 2048 of the high-side semiconductor die 204, the interconnections between the low-side filled vias 2028 and the high-side filled vias 2048 and the first front-side RDL 234 of the front-side build-up layer 230 respectively, the interconnection between the first front-side RDL 234 of the front-side build-up layer 230 and the copper pillar 206, and the interconnection between the copper pillar 206 and the back-side RDL 224 of the back-side build-up layer 220. The direct copper also includes the interconnection between the first front-side RDL 234 and the second front-side RDL 244 through the filled groove 240 in the front-side build-up layer 230. Therefore, the functional circuits of the low-side semiconductor die 202 and the high-side semiconductor die 204 are led out from the contact pads at the low-side active surface 2022 and the high-side active surface 2042 to the back-side RDL 224 of the back-side build-up layer 220 located at the low-side inactive surface 2024 of the low-side semiconductor die 202 and the high-side inactive surface 2044 of the high-side semiconductor die 204 respectively; and are further led out to external devices through the back-side RDL 224 of the back-side build-up layer 220 and the external connection layer 248, such as Figure 23a and 23b the substrate 110 shown (such as a Direct Bonded Copper (DBC) substrate or a ceramic substrate)) or a PCB (not shown). The direct copper interconnections have the advantages of fast switching, high frequency, and being able to withstand high voltage and large current. Therefore, the semiconductor package 200 is suitable for high-efficiency power modules. In addition, the direct copper interconnections also enhance the heat dissipation of the semiconductor package 200, making the operation of the power module 100 more reliable, especially at high temperatures.

[0060] Figure 19b A top view of Example 260 is shown. The semiconductor package 200 has a package size of 37 millimeters (mm) × 23 millimeters (mm), in which 8 low-side semiconductor dies 202 are arranged in a matrix of 2 columns and 4 rows, located on the right side (low side) in the figure; 8 high-side semiconductor dies 204 are also arranged in a matrix of 2 columns and 4 rows, located on the left side (high side) in the figure. Figure 19a The cross-sectional view in Figure 19bIt is drawn along the cross-sectional line AA in []. It should be understood that the semiconductor package 200 may also have other arrangements of 8 low-side semiconductor dies 202 and 8 high-side semiconductor dies 204. It should also be understood that the semiconductor package 200 may also have other numbers of low-side semiconductor dies 202 and high-side semiconductor dies 204. The layout of the semiconductor package 200 used as a metal-oxide-semiconductor field-effect transistor (MOSFET) is also shown here. Among them, the copper pillar 206 has two first copper pillars 2072 and one second copper pillar 2074, which are used as two low-side sources and one low-side gate of the low-side semiconductor die 202. The copper pillar 206 also has two third copper pillars 2076 and one fourth copper pillar 2078, which are used as two high-side sources and one high-side gate of the high-side semiconductor die 204. At the same time, the external connection layer 248 has a low-side external connection layer 2482 covering the low-side inactive surface 2024 of the low-side semiconductor die 202, and a high-side external connection layer 2484 covering the high-side inactive surface 2044 of the high-side semiconductor die 204, which are used as the low-side drain and the high-side drain respectively. The external connection layer 248 also has a first external connection layer 2486 and a second external connection layer 2487, which are electrically connected to the two first copper pillars 2072 and one second copper pillar 2074 of the copper pillar 206 respectively. The external connection layer 248 also has a third external connection layer 2488 and a fourth external connection layer 2489, which are electrically connected to the two third copper pillars 2076 and one fourth copper pillar 2078 of the copper pillar 206 respectively. In addition, Figure 19b It is also shown that the semiconductor package 200 has a low-side gate current path 2092 of the same length between all the low-side semiconductor dies 202 and the second copper pillar 2074 serving as the low-side gate; and a high-side gate current path 2094 of another length between all the high-side semiconductor dies 204 and the fourth copper pillar 2078 serving as the high-side gate. Therefore, the semiconductor package 200 can be precisely controlled simultaneously, that is, turned to the "ON" state or the "OFF" state simultaneously. The lengths of the low-side gate current path 2092 and the high-side gate current path 2094 may be the same or different. It should be understood that the semiconductor package 200 may also have other layouts for the low-side source, low-side gate, and low-side drain, as well as other layouts for the high-side source, high-side gate, and high-side drain. Changes in the layout of the semiconductor package 200 are also within the scope of the present disclosure.

[0061] Figure 20Shows a second embodiment of steps S118 and S120 of the panel-level method S10. Compared with the above-described first embodiment (on the scale of the sub-panel 250), the molded panel 210 is not divided into sub-panels 250 here. Instead, forming the external connection layer 248 on the backside RDL 224 exposed at the backside dielectric layer 226 of the backside build-up layer 220 is performed on the scale of the molded panel 210. Then, according to the design of the semiconductor package 200, the molded panel 210 (with the backside build-up layer 220, the front-side build-up layer 230, and the external connection layer 248) is directly cut into individual semiconductor packages 200 along the saw lines.

[0062] Figures 21a to 21c Shows other embodiments 270, 280, 290 of the semiconductor package 200 obtained from the panel-level method S10. Similar to embodiment 260, all embodiments 270, 280, and 290 have a backside build-up layer 220 and a front-side build-up layer 230. Figure 21a Shows a cross-sectional view of embodiment 270. Compared with embodiment 260, the front-side build-up layer 230 of embodiment 270 has only the first layer and does not have the second layer as described above. At the same time, it should be understood that other embodiments with a front-side build-up layer 230 having 3 layers, 4 layers, or more layers are also within the scope of the present disclosure. Figure 21b Shows a cross-sectional view of embodiment 280. Compared with embodiment 260, the front-side build-up layer 230 of embodiment 280 does not have the second front-side dielectric layer 246. Therefore, the second front-side RDL 244 is not encapsulated. Figure 21c Shows a cross-sectional view of embodiment 290. Compared with embodiment 260, embodiment 290 has an external connection dielectric layer 249 for encapsulating the external connection layer 248; at the same time, the front-side build-up layer 230 does not have its second layer, so the filling groove 240 is exposed from the first front-side dielectric layer 236.

[0063] Figures 22a to 22d Shows other embodiments 300, 310, 320, and 330 of the semiconductor package 200 obtained from the panel-level method S10. Compared with embodiment 260, embodiments 300, 310, 320, and 330 do not have a backside build-up layer 220; correspondingly, the external connection layer 248 is directly formed on the rear surface 2104 of the molded panel 210. Figure 22aA cross-sectional view of Embodiment 300 is shown. Compared with Embodiment 260, in Embodiment 300, the low-side external connection layer 2482 is in contact with the low-side non-active surface 2024 of the low-side semiconductor die 202; the high-side external connection layer 2484 is in contact with the high-side non-active surface 2044 of the high-side semiconductor die 204; the first external connection layer 2486 is in contact with the first copper pillar 2072, the second external connection layer 2487 is in contact with the second copper pillar 2074, the third external connection layer 2488 is in contact with the third copper pillar 2076, and the fourth external connection layer 2489 is in contact with the fourth copper pillar 2078. Alternatively, if (as described above) the received low-side semiconductor wafer and the received high-side semiconductor wafer each have the conductive layer on their non-active wafer surfaces. That is, the process of forming the external connection layer 248 can be skipped because the conductive layers on the received low-side semiconductor wafer and the received high-side semiconductor wafer will be retained and used as the external connection layer 248 described above. Figure 22b A cross-sectional view of Embodiment 310 is shown. Compared with Embodiment 300, in Embodiment 310, the front-side build layer 230 does not have the second front-side dielectric layer 246; thus, the second front-side RDL 244 is exposed. Figure 22c A cross-sectional view of Embodiment 320 is shown. Compared with Embodiment 310, in Embodiment 320, the front-side build layer 230 does not have the second layer; thus, the fill groove 240 is exposed from the first front-side dielectric layer 236. Figure 22d A cross-sectional view of Embodiment 330 is shown. Compared with Embodiment 320, Embodiment 330 further has an external connection dielectric layer 249 encapsulating the external connection layer 248; and the fill groove 240 is also exposed from the first front-side dielectric layer 236.

[0064] Figures 23a to 25b Step S122 of the panel-level method S10 is shown, that is, preparing a substrate 110 (such as a direct copper bonding (DBC) substrate or a ceramic substrate) having an external connection mechanism 112. The substrate 110 can be made of any insulating material, such as ceramic materials, alumina (Al2O3), silicon nitride (Si3N4)), aluminum nitride (AlN), or HPS (doped with about 9% ZrO2 or zirconia toughened alumina (ZTA)). Figure 23aA cross-sectional view of the substrate 110 is shown. The substrate 110 has (from left to right in sequence) an alternating current (AC) conductive layer 1112, a first conductive layer 1102, a second conductive layer 1104, a third conductive layer 1106, a fourth conductive layer 1108, and a direct current (DC) conductive layer 1114, which are separated from each other. The conductive layers 1112, 1102, 1104, 1106, 1108, 1114 can be made of any conductive material, such as metal, and are made into a surface finish by any suitable method for providing a flat surface for input / output (I / O). The surface finish can be made of a single-layer metal such as tin or a single-layer metal composite material such as nickel / gold. Alternatively, the surface finish can also be made of multiple layers. In some embodiments, the surface finish is made of electroless nickel immersion gold (ENIG), which has a two-layer metal surface coating, where the first nickel layer can be formed by an electroless chemical reaction; then a very thin gold layer is plated on the nickel layer. In other embodiments, the surface finish can be made of electroless nickel electroless palladium immersion gold (ENEPIG), which is formed by depositing electroless nickel, then depositing electroless palladium, and finally immersion gold flash. Preferably, the conductive layers 1112, 1102, 1104, 1106, 1108, 1114 are formed by electroplating with silver (Ag) to form a surface finish. The surface finish is chemically compatible with I / O to improve the stability of the connection. The thickness of the surface finish can be in the range of 1 micrometer (μm) to 10 micrometers (μm), preferably in the range of 1 micrometer (1μm) to 5 micrometers (5μm), or more preferably in the range of 1 micrometer (μm) to 3 micrometers (μm). Figure 23b shows a top view of the substrate 110 as described in Figure 23a In one embodiment, for a semiconductor package 200 with a package size of 37 millimeters (mm) × 23 millimeters (mm), correspondingly, the substrate 110 can have a substrate size of 57 millimeters (mm) × 42 millimeters (mm). The substrate 110 has a substrate thickness that can make the substrate 110 rigid enough to carry the semiconductor package 200. In one embodiment, the substrate thickness of the substrate 110 can be about 3 millimeters (mm). It can be understood that the substrate size and substrate thickness can vary according to the design of the power module 100; all variations are within the scope of the present disclosure. Figure 23b It is further shown that the substrate 110 has a low-side wiring 1116 and a high-side wiring 1118 that are electrically coupled to the first conductive layer 1102 and the fourth conductive layer 1108, respectively.

[0065] In one embodiment, Figure 24a A top view of the external connection mechanism 112 is shown, which includes an alternating current (AC) copper clip 1122 located on the left side (high side) of the figure; and two direct current positive (DC+) copper clips 1124 and one direct current negative (DC-) copper clip 1126 located on the right side (low side) of the figure. Figure 24b A cross-sectional view of the external connection mechanism 112 taken along Figure 24a section line AA in. The copper clips 1122, 1124, 1126 have the same or similar structures, where the first part 114 has a substantially flat configuration, the third part 118 has another substantially flat configuration, and the second part 116 has a Z-shaped configuration. The second part 116 firmly connects the first part 114 and the third part 118 to make the external connection mechanism 112 an integral structure.

[0066] Figure 25a and Figure 25b The top view and cross-sectional view are respectively shown. By coupling the AC copper clip 1122 to the AC conductive layer 1112 and coupling the DC+ copper clip 1124 and the DC- copper clip 1126 to the DC conductive layers 1114 respectively, the external connection mechanism 112 can be coupled to the substrate 110. Specifically, the coupling must create a first conductive joint 120 between the substrate 110 and the external connection mechanism 112. The coupling can be performed by any suitable method, including conductive adhesives (such as epoxy-silver pastes). Preferably, the coupling is performed by silver sintering, which uses silver (Ag) particles and high-temperature sintering to make the first conductive joint 120 between the substrate 110 and the external connection mechanism 112 conductive and strong and reliable.

[0067] Therefore, the power module 100 can be used as an inverter for converting DC to AC. The DC+ copper clip 1124 and the DC- copper clip 1126 can serve as input terminals and are electrically connected to the positive and negative poles of a direct current (DC) power source (such as a battery or other electricity storage device) respectively. At the same time, the AC copper clip 1122 serves as an output terminal and is electrically connected to an alternating current (AC) electrical appliance (such as a motor). The function of the inverter is realized by the semiconductor package 200, where the input terminal is configured to electrically couple the DC power source to the low-side semiconductor die 202; the output terminal is configured to electrically couple the high-side semiconductor die 204 to the AC electrical appliance. Therefore, the power module 100 converts the low-voltage direct current from the DC power source into high-voltage alternating current for use by the AC electrical appliance.

[0068] Alternatively, the power module 100 can also be used as a rectifier to convert AC to DC. The AC copper clip 1122 serves as the input terminal and is electrically connected to an AC power source (such as a household power grid); at the same time, the DC+ copper clip 1124 and the DC- copper clip 1126 serve as the output terminals and are respectively electrically connected to the positive and negative electrodes of a DC energy storage device or a battery. Therefore, the high-voltage alternating current of the AC power source is converted into low-voltage direct current by the power module 100 and supplied to the DC energy storage device. It can be understood that only one embodiment of the power module 100 is shown in FIG. 25, and other designs of the power module 100 are also included within the scope of the present disclosure.

[0069] Figures 26a to 27a An embodiment of step S124 of the panel-level method S10 and an embodiment 400 of the power module 100 are shown. Figure 26a and Figure 26bA sectional view and a top view are respectively shown. The semiconductor package 200 is mounted and coupled to the substrate 110 by coupling the first and second external connection layers 2486, 2487 to the fourth conductive layer 1108, coupling the low-side external connection layer 2482 to the third conductive layer 1106, coupling the high-side external connection layer 2484 to the second conductive layer 1104, and coupling the third and fourth external connection layers 2488, 2489 to the fourth conductive layer 1108. Similarly, the coupling must form a second conductive joint 122 between the substrate 110 and the semiconductor package 200. The coupling can be performed by any suitable method, including conductive adhesives (such as epoxy-silver pastes). Preferably, the coupling is performed by the above-mentioned silver sintering. Since all of the low-side external connection layer 2482, high-side external connection layer 2484, first and second external connection layers 2486, 2487, third and fourth external connection layers 2488, 2489, first conductive layer 1102, second conductive layer 1104, third conductive layer 1106, fourth conductive layer 1108, and second conductive joint 122 are formed of conductive materials, the functional circuits of the low-side semiconductor die 202 and the high-side semiconductor die 204 will be led out from the low-side external connection layer 2482 and the high-side external connection layer 2484 of the semiconductor package 200 to the second conductive layer 1104 and the third conductive layer 1106 of the substrate 110 respectively through the second conductive joint 122. In this embodiment, 260 is shown as the semiconductor package 200, but it should be understood that the above-mentioned other embodiments can also be mounted and coupled to the substrate 110 as the semiconductor package 200. In addition, since the second conductive layer 1104 and the third conductive layer 1106 of the substrate 110, and the low-side external connection layer 2482 and the high-side external connection layer 2484 of the external connection layer 248 form the surface finish as described above, all of them have very flat surfaces, which will make the second conductive joint 122 more firm and reliable, especially when it is formed of the same conductive material (preferably silver plating).

[0070] Figure 27aA cross-sectional view is shown where an integral signal lead 138 is mounted and coupled to a substrate 110. Such coupling must create a third conductive joint 124 between the substrate 110 and the integral signal lead 138. Specifically, the integral signal lead 138 has a lead height that is greater than the package thickness of the semiconductor package 200. The integral signal lead 138 can be made of any conductive material such as metal. Preferably, the integral signal lead 138 is made of copper (Cu) and is referred to as a copper pin. The integral signal lead 138 is electrically coupled to a gate driver (not shown) that controls the performance of the power module 100, such as the switching between the "ON" state and the "OFF" state of a power inverter. It should be understood that the integral signal lead 138 can be installed before the semiconductor package 200 is mounted onto the substrate 110. Thus, an embodiment 400 of the power module 100 as shown in Figure 27a is formed, which can be suitable for various power modules 100, such as a half-bridge inverter.

[0071] Figure 27b An alternative step S126 of the panel-level method S10 and another embodiment 410 of the power module 100 are shown, where a heat dissipation device is attached to the substrate 110 in the embodiment 400 to form another embodiment 410 of the power module 100. Figure 27b A cross-sectional view is shown where a heat sink 150 is used as an embodiment of the heat dissipation device, attached to the bottom surface 1110 of the substrate 110 for more effectively dissipating the heat generated by the semiconductor package 200.

[0072] Figure 28a and 28b An alternative step S128 of the panel-level method S10 and an embodiment 420 of the power module 100 are shown. Following steps S124 and Figure 27a the embodiment 400 as shown, i.e., after the integral signal lead 138 and the semiconductor package 200 are mounted on the substrate 110, Figure 28a A cross-sectional view is shown where a module molding layer 140 is formed to encapsulate the substrate 110, the integral signal lead 138, the semiconductor package 200, and a portion of the external connection mechanism 112 coupled to the substrate 110. The module molding layer 140 can be formed from an insulating material by any suitable method, such as a molding material. Then, a grinding process is performed on the module molding layer 140 by a grinding device 212 to expose a top 1382 of the integral signal lead 138 from the module molding layer 140, while a bottom 1384 of the integral signal lead 138 remains encapsulated in the module molding layer 140. Here, Figure 28b a cross-sectional view is shown where the embodiment 420 is formed after the alternative step S128 is performed.

[0073] Figure 29An alternative step S126 of the panel - level method S10 for Example 420 is shown, thereby forming another Example 430 of the power module 100. As above, the heat - dissipating device (such as the heat sink 150) is attached to the substrate 110 to enhance the dissipation of heat generated from the semiconductor package 200. Figure 29 A cross - sectional view of Example 430 is shown.

[0074] Figure 30a and 30b Another alternative step S130 of the panel - level method S10 and Example 440 of the power module 100 are shown. Different from the integral signal lead 138, Figure 30a A cross - sectional view is shown where a plurality of first signal leads 130 are mounted and coupled to the power module 100 and are located around the semiconductor package 200. The first signal leads 130 can be formed of any electrical material, such as metal. Preferably, the first signal leads 130 are formed of copper (Cu). Similarly, a third conductive joint 124 must be formed between the substrate 110 and the first signal leads 130. Specifically, the first signal leads 130 have another lead height that is greater than the package thickness of the semiconductor package 200. After forming the module molding layer 140, a grinding process is performed on the module molding layer 140 by a grinding device 212 such that the upper surface 132 of the leads of the first signal leads 130 is exposed from the module molding layer 140.

[0075] Figure 30b A cross - sectional view is shown where a plurality of second signal leads 134 can be respectively coupled to the plurality of first signal leads 130 by any suitable method, such as using fasteners 142 to mechanically couple the first signal leads 130 and the second signal leads 134. For example, the first signal leads 130 and the second signal leads 134 respectively have internal and external threads that cooperate with each other so that the first signal leads 130 and the second signal leads 134 can be mechanically fixed together. The first signal leads 130 and the second signal leads 134 can be made of any conductive material, such as metal. Preferably, the first signal leads 130 and the second signal leads 134 are made of copper (Cu); accordingly, their combination is called copper pins. The first signal leads 130 and the second signal leads 134 are electrically coupled to a gate driver (not shown), and the gate driver controls the performance of the power module 100, such as the switching between the "ON" state and the "OFF" state of a power inverter. Here, the power module 100 of Example 440 as Figure 30b shown is formed.

[0076] Figure 30cAn alternative step S126 of the panel-level method S10 for Example 440 is shown, resulting in another Example 450 of the power module 100. As above, the heat dissipation device (e.g., the heat sink 150) is attached to the substrate 110 to enhance the dissipation of heat generated from the semiconductor package 200. Figure 30c A cross-sectional view of Example 450 is shown. For Examples 400 to 450 of the power module 100 as described above, the semiconductor package 200 is mounted in a face-up manner, i.e., the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204 face away from the substrate 110. Therefore, the external connection layer 248 at the backside build-up layer 220 must be exposed to contact the substrate 110. In Examples 290 and 330, since the external connection layer 248 is completely encapsulated in the external connection dielectric layer 249, the semiconductor package 200 cannot be mounted in the face-up manner.

[0077] Different from the face-up manner, the semiconductor package 200 can also be mounted in a face-down manner, i.e., the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204 face the substrate 110. Figures 31a to 33b Other Examples 460, 470, 480, 490, 500, and 510 of the power module 100 are shown, in which Example 290 of the semiconductor package 200 is mounted in the face-up manner. Compared with the face-up manner, the face-down manner directly contacts the semiconductor package 200 with the substrate 110, enhancing the heat dissipation from the semiconductor package 200 to the substrate 110 because most of the heat is generated by the functional circuits of the semiconductor dies (e.g., the low-side semiconductor die 202 and the high-side semiconductor die 204). It should be understood that Example 330 of the semiconductor package 200 can also be mounted in the face-up manner.

[0078] Figure 31a A cross-sectional view of Example 460 is shown, which corresponds to Example 400, except that Example 290 of the semiconductor package 200 is mounted in a face-down manner. Figure 31b A cross-sectional view of Example 470 is shown, which corresponds to Example 410, where the heat sink 150 is attached to the substrate 110.

[0079] Figure 32a A cross-sectional view of Example 480 is shown, which corresponds to Example 420, except that Example 290 of the semiconductor package 200 is mounted in a face-down manner. Figure 32b A cross-sectional view of Example 490 is shown, which corresponds to Example 430, where the heat sink 150 is attached to the substrate 110.

[0080] Figure 33aA cross-sectional view of Example 500 is shown, which corresponds to Example 440, except that the embodiment 290 of the semiconductor package 200 is mounted in a face-down manner. Figure 33b A cross-sectional view of Example 510 is shown, which corresponds to Example 450, in which the heat sink 150 is attached to the substrate 110. It should be understood that although not shown, other embodiments of the power module 100 are also within the scope of the present disclosure, that is, by mounting other embodiments of the semiconductor package 200 onto the substrate 110, such as embodiments 280, 310, and 320 (which can also be mounted in the above-mentioned face-up configuration).

[0081] Figure 34a and 34b Two additional embodiments 340, 350 of the semiconductor package 200 are shown. Starting from a molded panel 210 (having a backside build-up layer 220 and a frontside build-up layer 230) as shown in Figure 13 (the difference being that the backside RDL 224 is completely encapsulated within the backside dielectric layer 226), if the first frontside dielectric layer 236 is composed of a solder mask or a photoimageable dielectric material, then the first thickness of this first frontside dielectric layer 236 is much smaller than that described above (for example, 100 micrometers (μm)). In some embodiments, the first thickness is about 10 micrometers (μm), as shown in Figure 34a Then, a groove 238 is formed by photolithography or photoimageable technology as shown in Figure 14 to expose the first frontside RDL from the first frontside dielectric layer 236. Thus, the groove 238 has a depth that is substantially equal to the first thickness of the first frontside dielectric layer 236, for example, about 10 micrometers (μm). As described above, in subsequent processes, including step S116, after separating the molded panel 210 from the second carrier 106 and the second thermal release film 108; and step S120, dividing the molded panel 210 into the embodiment 340 of the semiconductor package 200, the groove 238 remains unfilled. Figure 34a A cross-sectional view of the resulting embodiment 340 is shown, in which the groove 238 remains unfilled. Similarly, for the embodiment 350, the groove 238 also remains unfilled in the said subsequent process. The embodiment 350 is different from the embodiment 340 in that it does not have a backside build-up layer 220, and thus, the external connection layer 248 is directly formed on the back surface 2104 of the molded panel 210. Figure 34b A cross-sectional view of the resulting embodiment 350 is shown, in which the groove 238 remains unfilled.

[0082] Figure 35aand 35b shows another embodiment of step S124 of the panel-level method S10, using embodiment 340 of semiconductor package 200 to manufacture embodiment 520 of power module 100. Figure 35a Shows a cross-sectional view, where embodiment 340 is mounted and coupled to substrate 110 in a face-down manner, and the groove 238 is not filled. Figure 35b Shows a cross-sectional view. During the formation of the second conductive joint 122 between substrate 110 and embodiment 340 of semiconductor package 200, the conductive adhesive (such as epoxy-silver pastes) enters and fills the groove 238 along with silver sintering. Specifically, the conductive adhesive (such as epoxy-silver pastes) has an adhesive thickness greater than the depth of the groove 238. For example, when the first thickness of the first front-side dielectric layer 236 is less than or about 10 micrometers (μm), the adhesive thickness of the conductive adhesive can be in the range of 10 to 20 micrometers (μm), or preferably about 14 micrometers (μm). Thus, in embodiment 340 of semiconductor package 200, the filled groove 240 is electrically coupled to the first front-side RDL 234 of the front-side build layer 230. Instead of the above-mentioned conductive adhesive (such as epoxy-silver pastes) and silver sintering process, solder materials (such as solder balls) can also be used here through a solder reflowing process to fill the groove 238. Similarly, the solder has a solder thickness greater than the depth of the groove 238. For example, when the first thickness of the first front-side dielectric layer 236 is less than or about 10 micrometers (μm), the solder thickness can be in the range of 10 to 20 micrometers (μm), or preferably about 14 micrometers (μm). Similar to the description of embodiment 340 of semiconductor package 200 above, the solder also enters and fills the groove 238 during the solder reflow process. It should be understood that embodiment 350 in which the groove 238 remains unfilled can also be mounted in a face-down manner, and then the groove 238 is filled during the formation of the second conductive joint 122.

[0083] Figure 36a and 36b shows other embodiments 530, 540 of power module 100, which have a liquid cooling system as another embodiment of the heat dissipation device. Figure 36a Shows a cross-sectional view of embodiment 530 of power module 100, where the semiconductor package 200 is mounted to the substrate 110 in a face-up manner, and the first liquid cooling system 160 is directly or indirectly (such as through an intermediate component 162, such as a heat dissipation metal layer) Figure 36aAs shown), it is attached to the module molding layer 140. At the same time, the second liquid cooling system 164 can also be attached to the bottom surface 1110 of the substrate 110 to replace the heat sink 150, thereby effectively dissipating the heat generated by the semiconductor package 200. Figure 36b A cross-sectional view is shown, and the semiconductor package 200 is mounted on the substrate 110 in a face-down manner. Similarly, the first liquid cooling system 160 is directly or indirectly (such as Figure 36b As shown) attached to the external connection dielectric layer 249. At the same time, the second liquid cooling system 164 can also be attached to the bottom surface 1110 of the substrate 110. The first liquid cooling system 160 and the second liquid cooling system 164 can be of the liquid-to-liquid type, closed-loop dry system type, closed-loop dry system with trim cooling type, open-loop evaporative system type, closed-loop evaporative system type, chilled water system type, or any combination thereof. However, it should be understood that the heat sink 150 can still be retained on the bottom surface 1110 of the substrate 110, and the first liquid cooling system 160 is attached to the module molding layer 140 (such as Figure 36a ) or the external connection dielectric layer 249 of the semiconductor package 200 ( Figure 36b ).

[0084] Without departing from the spirit or essential characteristics of the present disclosure, the present disclosure can be implemented in other specific forms. Therefore, the foregoing embodiments are considered illustrative in all respects and not restrictive of the present disclosure. Accordingly, the scope of the present disclosure is defined by the appended claims rather than the foregoing description, and all variations within the meaning and scope of the claims are included in the present disclosure. In this application, unless otherwise specified, the terms "comprising", "including" and their grammatical variants are intended to express "open" or "inclusive" language, such that they include the recited elements but also permit the inclusion of additional, non-specified elements.

[0085] This patent application claims the priority of Singapore Application No. 10202303517V, with an application date of December 14, 2023, and the entire disclosure thereof is incorporated herein by reference.

Claims

1. A semiconductor package for a power module, comprising: at least one high-side semiconductor die having a high-side active surface and a high-side inactive surface; at least one low-side semiconductor die having a low-side active surface and a low-side inactive surface; a plurality of vertical structures surrounding the at least one high-side semiconductor die and the at least one low-side semiconductor die, wherein each vertical structure has a front surface aligned with the high-side active surface and the low-side active surface, and a back surface aligned with the high-side inactive surface and the low-side inactive surface; a molding layer for encapsulating the at least one high-side semiconductor die and the at least one low-side semiconductor die, and the plurality of vertical structures; a front-side build-up layer coupled to the high-side active surface of the at least one high-side semiconductor die and the low-side active surface of the at least one low-side semiconductor die, and to the front surface of the vertical structure; a backside build-up layer coupled to the high-side inactive surface of the at least one high-side semiconductor die and the low-side inactive surface of the at least one low-side semiconductor die, and to the rear surface of the vertical structure; and An external connection layer is coupled to the backside build-up layer.

2. The semiconductor package of claim 1, wherein the vertical structure comprises a plurality of copper pillars, a plurality of molded interconnect substrate units, a plurality of molded through-hole substrate units, or any combination thereof.

3. The semiconductor package according to claim 1, wherein The high-side active surface of the high-side semiconductor die, the low-side active surface of the low-side semiconductor die, and the front surface of the vertical structure are exposed from the first molding surface of the molding layer; and The high-side inactive surface of the high-side semiconductor die, the low-side inactive surface of the low-side semiconductor die, and the rear surface of the vertical structure are exposed from the second molding material surface of the molding layer.

4. The semiconductor package according to claim 1, wherein the front side building layer further comprises a front-side redistribution layer electrically coupled to the high-side active surface of the high-side semiconductor die, the low-side active surface of the low-side semiconductor die, and the front surface of the vertical structure; and A front-side dielectric layer is used to encapsulate the front-side redistribution layer.

5. The semiconductor package according to claim 1, wherein the backside build-up layer further comprises: a backside redistribution layer electrically coupled to the rear surface of the vertical structure; and A backside dielectric layer is used to encapsulate the backside redistribution layer.

6. The semiconductor package according to claim 1, wherein The at least one high-side semiconductor die includes eight silicon carbide high-side metal oxide semiconductor field effect transistors electrically coupled to a high-side gate; and The at least one low-side semiconductor die includes eight silicon carbide low-side metal oxide semiconductor field effect transistors electrically coupled to a low-side gate.

7. The semiconductor package according to claim 6, wherein the external connection layer comprises a low-side external connection layer in contact with an inactive surface of the at least one low-side semiconductor die and serving as a low-side drain; a high-side external connection layer in contact with the inactive phase surface of the at least one high-side semiconductor die and serving as a high-side drain; a first external connection layer, contacting the plurality of first copper pillars and serving as a low-side source; a second external connection layer, contacting a second copper pillar, and serving as a low-side gate; a third external connection layer, contacting with a plurality of third copper pillars and serving as a high-side source; and A fourth external connection layer, contacting a fourth copper pillar, is used as a high-side gate.

8. A power module, comprising: A semiconductor package having at least one high-side semiconductor die and at least one low-side semiconductor die; a substrate on which the semiconductor package is mounted, wherein functional circuits of the at least one low-side semiconductor die and the at least one high-side semiconductor die are led out of the substrate; an external connection mechanism coupled to the substrate for electrically leading out the power module; and At least one signal lead is mounted on the substrate.

9. The power module according to claim 8, wherein The at least one signal lead includes an integrated signal lead, or a combination of a first signal lead and a second signal lead.

10. The power module according to claim 9, further comprising: A module molding layer is used to encapsulate the semiconductor package and the at least one signal lead, wherein a portion of the at least one signal lead is exposed from the module molding layer.

11. The power module according to claim 8, wherein The external connection mechanism includes a DC positive copper clip, a DC negative copper clip and an AC copper clip.

12. The power module according to claim 8, further comprising The semiconductor package according to claim 1, which is mounted in a face-up configuration or a face-down configuration.

13. The power module according to claim 8, further comprising: A heat sink is coupled to the substrate.

14. A method for manufacturing a power module, comprising: forming a semiconductor package for the power module, wherein the semiconductor package includes at least one low-side semiconductor die and at least one high-side semiconductor die; mounting the semiconductor package on a substrate, wherein functional circuits of the at least one low-side semiconductor die and the at least one high-side semiconductor die are led out to the substrate; coupling an external connection mechanism to the substrate; and At least one signal lead is mounted on the substrate.

15. The method of claim 14, wherein forming the semiconductor package further comprises: bonding the at least one high-side semiconductor die and the at least one low-side semiconductor die to a first carrier; bonding a plurality of vertical structures to the first carrier; forming a molding layer for encapsulating the at least one high-side semiconductor die, the at least one low-side semiconductor die, and the plurality of vertical structures to form a molding panel; forming a front-side build-up layer coupled to the at least one high-side semiconductor die, the at least one low-side semiconductor die, and the vertical structure; forming a backside build-up layer coupled to the at least one high-side semiconductor die, the at least one low-side semiconductor die, and the vertical structure; forming an external connection layer coupled to the backside build-up layer; and The molded panel, the front-side build-up layer, the back-side build-up layer, and the external connection layer are separated into the individual semiconductor packages.

16. The method according to claim 15, further comprising: The pre-vias of the at least one high-side semiconductor die and the at least one low-side semiconductor die are filled respectively to form filled vias coupled to the front-side build-up layer.

17. The method according to claim 15, further comprising: Before forming the external connection layer, dividing the molded panel, the front side building layer and the back side building layer into a plurality of sub-panels; and After forming the external connection layer, the sub-panel is divided into the individual semiconductor packages.

18. The method according to claim 15, further comprising removing a first top portion of the molding layer to expose a rear surface of the vertical structure; and The second top portion of the molding layer is removed to expose the inactive surfaces of the at least one high-side semiconductor die and the at least one low-side semiconductor die.

19. The method according to claim 14, further comprising: A module molding layer is formed to encapsulate the semiconductor package and a portion of the at least one signal lead.

20. The method of claim 14, further comprising: A heat sink is connected to the substrate.

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