Vertical power semiconductor device and manufacturing method thereof

Abstract

The invention relates to a vertical power semiconductor device and a manufacturing method thereof. The device comprises: a substrate having two surfaces opposite to each other; the first gate structure and the second gate structure are arranged on the first surface of the substrate and are adjacent to each other; the first dielectric layer covers the first gate structure, the second gate structure and the first surface of the substrate, and the first dielectric layer is provided with a first opening between the first gate structure and the second gate structure; the current expansion layer is located at the bottom of the first opening between the first gate structure and the second gate structure, the current expansion layer has a first width, and the first width is approximately the same as the width of the bottom of the first opening; the conductive plug is located between the first gate structure and the second gate structure and makes contact with the current expansion layer, the bottom of the conductive plug has a second width, and the second width is smaller than the first width; the source electrode layer is located on the first surface of the substrate and electrically connected with the conductive plug; and a drain electrode layer on the second surface of the substrate.

Description

Technical Field

[0001] The present invention relates to a vertical power semiconductor device and a manufacturing method thereof. More specifically, it relates to a vertical power semiconductor device having a current spreading layer and a manufacturing method thereof. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth in the past few decades. Technological advancements in semiconductor materials and design have resulted in increasingly compact and complex circuits. Since the technologies related to processing and manufacturing have also undergone technological advancements, the progress of new materials and designs has become possible. During the development of semiconductors, as the minimum component size that can be manufactured decreases, the number of interconnected devices per unit area increases, and the allowable contact area between conductive elements in the current conduction path is limited, resulting in an increase in the device resistance value or a decrease in the reliability of the product. Summary of the Invention

[0003] Embodiments of the present disclosure relate to a vertical power semiconductor device. The vertical power semiconductor device includes: a substrate having a first surface and a second surface opposite to each other; a first gate structure located on the first surface of the substrate; a second gate structure located on the first surface of the substrate and adjacent to the first gate structure; a first dielectric layer covering the first gate structure, the second gate structure, and the first surface of the substrate, wherein the first dielectric layer has a first opening between the first gate structure and the second gate structure; a current spreading layer located at the bottom of the first opening between the first gate structure and the second gate structure, wherein the current spreading layer has a first width, and the first width is approximately the same as the width of the bottom of the first opening; a conductive plug located between the first gate structure and the second gate structure and contacting the current spreading layer, wherein the bottom of the conductive plug has a second width, and the second width is less than the first width of the current spreading layer; a source electrode layer located on the first surface of the substrate and electrically connected to the conductive plug; and a drain electrode layer located on the second surface of the substrate.

[0004] Embodiments of the present disclosure relate to a method for manufacturing a vertical power semiconductor device. The method includes: forming a first gate structure and a second gate structure adjacent to each other on a substrate; forming a first dielectric layer covering the first gate structure, the second gate structure, and the substrate; performing a first patterning process on the first dielectric layer to form a first opening between the first gate structure and the second gate structure, exposing a portion of the substrate; forming a metal layer on the first dielectric layer, covering the exposed portion of the substrate; performing a first annealing process on the metal layer to form a metal silicide layer; performing a second annealing process on the metal silicide layer to form a current spreading layer, wherein the temperature of the first annealing process is less than the temperature of the second annealing process, and the resistance value of the current spreading layer is less than the resistance value of the metal silicide layer; and forming a conductive plug on the current spreading layer, wherein the width of the bottom of the conductive plug is less than the width of the current spreading layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of certain embodiments of the present disclosure are best understood when read in conjunction with the following detailed description with reference to the drawings. It should be noted that the various structures are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0006] Figure 1A Shown is a top view of a semiconductor structure according to some embodiments of the present case;

[0007] Figure 1B Shown is a top perspective view of doped regions 113, 115 of a vertical power semiconductor structure according to some embodiments of the present case;

[0008] Figure 2 Shown is a cross-sectional view of the semiconductor structure of FIG. 1 taken along the tangent A-A' according to some embodiments of the present case;

[0009] Figure 3 Shown is a cross-sectional view of the semiconductor structure of FIG. 1 taken along the tangent B-B' according to some embodiments of the present case;

[0010] Figure 4 Shown is according to some embodiments of the present case Figure 3 partial enlarged view;

[0011] Figure 5 Shown is a flowchart of a manufacturing method according to some embodiments of the present case;

[0012] Figure 6 and 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 show one or more stages in a method of manufacturing a semiconductor structure according to certain embodiments of the present case;

[0013] Figure 22 , 23 , 24 show partial cross-sectional views according to different embodiments of the present case; and

[0014] Figure 25 , 26 shows a cross-sectional view of a semiconductor structure according to different embodiments of the present case.

[0015] The same or similar components are denoted by the same reference numerals in the drawings and the detailed description. From the following detailed description in conjunction with the accompanying drawings, several embodiments of the present disclosure will be immediately understood. Detailed Description of Embodiments

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be restrictive. In the present disclosure, a reference to forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0017] Embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are illustrative only and do not limit the scope of the present disclosure.

[0018] Figure 1A , Figure 1B , Figure 2 , Figure 3 is a schematic structural diagram of a vertical power semiconductor structure 1 according to certain embodiments of the present case, where Figure 1A shows a partial top view of the vertical power semiconductor structure 1, Figure 1B shows a top perspective view of the doped regions 113, 115 of the vertical power semiconductor structure 1, Figure 2 shows a cross-sectional view of a portion of the vertical power semiconductor structure 1 along the tangent line A-A' in FIG. 1 (denoted by reference numeral 1A), Figure 3Shown is a cross-sectional view of a vertical power semiconductor structure 1 (designated 1B) along the B-B' tangent in FIG. 1. At least some of these figures have been simplified for a better understanding of aspects of the present disclosure.

[0019] Referring Figure 1A 、 1B 、2、 Figure 3 , the vertical power semiconductor structure 1 can be of different types or manufactured by different technologies. For example, the vertical power semiconductor structure 1 can include a power metal-oxide-semiconductor field-effect transistor (MOSFET), a double-diffused MOSFET (DMOSFET), an insulated-gate bipolar transistor (IGBT), a junction gate field-effect transistor (JFET). Specifically, the vertical power semiconductor device has a vertical current conduction path. For example, the current of the vertical power semiconductor structure 1 can flow in a direction orthogonal to the active surface of the vertical power semiconductor structure 1. For example, the current of the vertical power semiconductor structure 1 can conduct vertically through the vertical power semiconductor structure 1. It should be noted that the vertical power semiconductor structure 1 in FIG. 1 includes a substrate 11 made of a silicon carbide material and a gate structure 13 formed on the substrate 11 for illustrative purposes only and is not intended to limit the application of the present case.

[0020] In some embodiments, the vertical power semiconductor structure 1 includes a substrate 11, a gate structure 13 located on the substrate 11, at least one dielectric layer (such as 21, 22, 23) covering the gate structure 13, a current spreading layer 31 in an opening of the dielectric layer 21 between the gate structures, and a conductive plug 37 located on the current spreading layer 31, wherein the width of the conductive plug 37 is smaller than the width of the current spreading layer 31.

[0021] The substrate 11 has a surface 11A and a surface 11B opposite to the surface 11A. In some embodiments, the surface 11A and the surface 11B can be horizontal planes. For ease of description, the direction orthogonal to the surface 11A and the surface 11B is defined as the vertical direction, and the direction orthogonal to the vertical direction (such as the Z direction) is defined as the horizontal direction (such as the X direction, the Y direction), and the surface 11A of the substrate 11 is defined as the top surface of the substrate 11, and the surface 11B of the substrate 11 is defined as the bottom surface of the substrate 11. In some embodiments, the surface 11A can be the active surface of the semiconductor material layer 11.

[0022] The substrate 11 may include, for example, single-crystalline silicon material, epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials, which may be N-type or P-type. The substrate 11 includes a p-type doped region and an n-type doped region that can be configured for n-type transistors and can be configured as p-type transistors. The n-type doped region is doped with an n-type dopant, such as phosphorus, arsenic, other n-type doping ions, or a combination thereof. The p-type doped region is doped with p-type doping ions, such as boron, indium, other p-type doping ions, or a combination thereof. The n-type or p-type doped region can be formed by performing an ion implantation process, a diffusion process, and / or other suitable doping processes. In some embodiments, the substrate 11 has a lightly doped region 111 of the first type adjacent to the surface 11B. For the convenience of description, the first type is taken as an example of N-type hereinafter, but the present disclosure is not limited thereto. The substrate 11 of N-type (the first type) or P-type (the second type) can be adjusted according to the conductivity type of the vertical power semiconductor structure 1.

[0023] In addition to the lightly doped region 111, the vertical power semiconductor structure 1 further has a plurality of doped regions 112, 113, 114, 115, 116.

[0024] The doped region 112 has the same conductivity type as the lightly doped region 111, such as N-type. In some embodiments, the doped region 112 has a higher first conductivity type ion doping concentration than the doped region 111. The doped regions 111 and 112 together serve as the substrate doped region, and the doped regions 111 and 112 have a concentration gradient that helps to reduce the forward voltage (VF) and the resistance value, but the present disclosure is not limited thereto. In some embodiments, the doped region 112 is located on the side of the lightly doped region 111 adjacent to the surface 11A. In some embodiments, the doped region 112 is located above the lightly doped region 111 along the Z direction. In some embodiments, the doped region 112 is adjacent to the surface 11A of the substrate 11. In other embodiments, the substrate doped region of the substrate 11 does not have a concentration gradient. In other words, the doped regions 111 and 112 in the drawings can be combined into a single first conductivity type doped region with a uniform concentration.

[0025] The doped region 113 serves as the body doped region of the vertical power semiconductor structure 1 (collectively referred to as the body doped region 113 hereinafter) and is located in the substrate 11 between the gate structures 13. The body doped region 113 extends from the surface 11A towards the surface 11B. In some embodiments, the body doped region 113 is adjacent to the surface 11A. The depth of the body doped region 113 along the Z direction from the surface 11A is greater than or equal to the depth of the doped region 112. In some embodiments, as Figure 2 、 3The vertical power semiconductor structure 1 shown has a body doping region 113 with a depth along the Z direction from the surface 11A greater than that of the doping region 112 to ensure that the depth of the body doping region 113 is not less than that of the doping region 112. The body doping region 113 is at least located between adjacent gate structures 13. In some embodiments, the portion of the gate structure 13 adjacent to the body doping region 113 covers the body doping region 113.

[0026] The doping region 114 serves as the source of the vertical power semiconductor structure 1 (collectively referred to as the source doping region 114 hereinafter), is located in the body doping region 113 and is adjacent to the surface 11A of the substrate 11. In some embodiments, the source doping region 114 abuts the surface 11A of the substrate 11. The depth of the source doping region 114 from the surface 11A of the substrate 11 to the surface 11B is less than that of the body doping region 113 and has a conductivity type different from that of the body doping region 113, for example, it is N-type. In some embodiments, the doping concentration of the first-type doping ions in the source doping region 114 is greater than that of the second-type doping ions in the body doping region 113. In some embodiments, as shown in FIG. 1, the vertical power semiconductor structure 1 has a plurality of source doping regions 114 extending in the Y direction, and the plurality of source doping regions 114 are parallel to each other.

[0027] The vertical power semiconductor structure 1 may further include a heavily doped region 115 located in the substrate 11 between the gate structures 13. In some embodiments, the heavily doped region 115 is separated from the gate structure 13 along the Z direction, as Figure 2 , 3 shown. In other words, the heavily doped region 115 is not covered by the gate structure 13, as shown in FIG. 1. In some embodiments, a part of the heavily doped region 115 abuts a part of the surface 11A of the substrate 11. In some embodiments, the depth of the heavily doped region 115 from the surface 11A along the Z direction to the surface 11B is less than that of the body doping region 113 and greater than that of the source doping region 114. The heavily doped region 115 has the same conductivity type as the body doping region 113, for example, P-type. The doping concentration of the second conductivity type ions in the heavily doped region 115 is greater than that of the second conductivity type ions in the body doping region 113.

[0028] The bottom of the heavily doped region 115 is in contact with the bulk doped region 113 of the second conductivity type and the lightly doped region 111 of the first conductivity type simultaneously, and the heavily doped region 115 is in contact with the source doped region 114, electrically connecting the bulk doped region 113 and the source doped region 114, thereby avoiding a voltage difference between the emitter and the base of a parasitic bipolar junction transistor (BJT for short), and further avoiding the activation of the parasitic BJT. In addition, the heavily doped region 115 can also achieve the same effect as the bulk doped region 113, so it does not affect the effect of the vertical power semiconductor structure 1 and can further avoid the activation of parasitic elements. In some embodiments, the heavily doped region 115 is connected to two adjacent and separated bulk doped regions 113, such as Figure 3 the cross-sectional structure shown.

[0029] The number, pattern, coverage, depth, etc. of the heavily doped regions 115 can be adjusted according to different embodiments. In some embodiments, the coverage of the heavily doped regions 115 falls within the source doped regions 114, as shown in the top view of FIG. 1. The vertical power semiconductor structure 1 can have multiple heavily doped regions 115. In some embodiments, there are multiple heavily doped regions 115 arranged in the Y direction and separated from each other in each source doped region 114. In some embodiments, each heavily doped region 115 has a configuration extending in the Y direction, but the present disclosure is not limited thereto. In some embodiments, as shown in FIGS. 1 and 2, the width of the heavily doped region 115 in the X direction is smaller than the width of the source doped region 114. In some embodiments, as shown in FIGS. 1 and 2, the width of the heavily doped region 115 in the X direction is larger than the width of the metal silicide 31.

[0030] The vertical power semiconductor structure 1 has a plurality of adjacent and separated gate structures 13. The gate structures 13 are disposed on the surface 11A of the substrate 11. In some embodiments, as shown in the top view of FIG. 1, the plurality of gate structures 13 extend in the Y direction and are parallel to each other. The gate structure 13 may include, for example, a gate electrode layer, a gate dielectric layer located between the gate electrode layer and the surface 11A of the substrate 11, sidewall spacers, etc., which may vary according to different processes and manufacturing methods, and the gate structure 13 will not be described in detail herein. In some embodiments, the portion of the gate structure 13 adjacent to the body doping region 113 covers a part of the body doping region 113 in the Z direction. In some embodiments, the source doping region 114 extends between adjacent gate structures 13, and opposite sides of the source doping region 114 overlap respectively under adjacent two gate structures 13. In some embodiments, the portion of the gate structure 13 adjacent to the source doping region 114 covers a part of the source doping region 114 in the Z direction. In some embodiments, the overlapping range of the gate structure 13 and the body doping region 113 in the X direction is greater than the overlapping range of the gate structure 13 and the source doping region 114.

[0031] The vertical power semiconductor structure 1 may further include a heavily doped region 116 in a part of the substrate 11 located between the gate structures 13 and covered by the current spreading layer 31. In some embodiments, the heavily doped region 116 is adjacent to the bottom of the current spreading layer 31. In some embodiments, the depth of the heavily doped region 116 from the surface 11A in the Z direction towards the surface 11B is less than the depth of the source doping region 114. The heavily doped region 115 has the same conductivity type as the source doping region 114, for example, N-type. In some embodiments, the doping concentration of the first conductivity type ions in the heavily doped region 116 is greater than the doping concentration of the first conductivity type ions in the source doping region 114. In some embodiments, the heavily doped region 116 is aligned with the metal silicide 31.

[0032] As shown in FIG. 1, the vertical power semiconductor structure 1 may have a plurality of heavily doped regions 116 extending in the Y direction, and the plurality of heavily doped regions 116 are parallel to each other. The number of the heavily doped regions 116 corresponds to the number of the source doping regions 114. In some embodiments, the heavily doped regions 116 fall within the source doping regions 114, as shown in the top view of FIG. 1. In some embodiments, as shown in FIGS. 1 and 3, the width of the heavily doped region 116 in the X direction is greater than the width of the metal silicide 31 and less than the width of the source doping region 114. In some embodiments, as shown in FIGS. 1 and 2, the width of the heavily doped region 116 in the X direction is less than the width of the heavily doped region 115.

[0033] The depth of the heavily doped region 116 can be adjusted according to different embodiments and manufacturing processes. In some embodiments, the portion of the substrate 11 covered by the heavily doped region 116 is converted into a portion of the current spreading layer 31 through a silicidation process, so the heavily doped region 116 below the current spreading layer 31 cannot be seen in the product. In some embodiments, the current spreading layer 31 contacts the source doped region 114.

[0034] The vertical power semiconductor structure 1 may further include a dielectric layer 12 located on the surface 11A of the substrate 11. The dielectric layer 12 covers the surface 11A of the substrate 11 and extends along the surface 11A. According to different manufacturing methods, the thickness of the dielectric layer 12 on the surface 11A may be uniform or uneven. In some embodiments, as shown in FIG. Figure 2 , 3 In the cross-sectional structures 1A and 1B shown, the portion of the dielectric layer 12 contacting the source doping region 114 has a thicker thickness. In some embodiments, the dielectric layer 12 is formed by an oxidation process, and different portions of the substrate 11 with different doping concentrations have different oxidation rates, so the thickness of the dielectric layer 12 on the surface 11A is uneven. In some embodiments, the dielectric layer 21 serves as a gate dielectric layer of the gate structure 13, and the gate structure 13 does not need to include an additional gate dielectric layer. In some embodiments, the thickness of the dielectric layer 21 is between 50 angstroms and 100 angstroms. To allow the metal silicide 31 to contact the substrate 11 , the dielectric layer 12 has an opening between adjacent gate structures 13 .

[0035] The vertical power semiconductor structure 1 further includes a dielectric layer 21, which covers the gate structure 13 and a portion of the surface 11A of the substrate 11. In order for the metal silicide 31 to electrically connect to the source doping region 114, the dielectric layer 21 has an opening between adjacent gate structures 13. In some embodiments, the dielectric layer 12 further extends between the surface 11A of the substrate 11 and the dielectric layer 21. In some embodiments, the opening of the dielectric layer 21 is flush with the opening of the dielectric layer 12 (for convenience of description, collectively referred to as opening 41 below). In some embodiments, the sidewalls of the dielectric layer 21 are aligned with the sidewalls of the dielectric layer 12. In some embodiments, the sidewalls of the dielectric layer 21 and the sidewalls of the dielectric layer 12 are continuous sidewalls. The material of the dielectric layer 21 may include a high dielectric constant material, a low dielectric constant material, etc., such as silicon oxide (SiO2), silicon nitride (Si3N4 or Si x N y ), silicon oxynitride (SiO x N y ) and other materials.

[0036] The current spreading layer 31 is located at the bottom of the opening 41 between adjacent gate structures 13. The current spreading layer 31 has a width W31, and the width W31 is approximately the same as the width W412 of the bottom of the opening 41. In other words, the current spreading layer 31 covers the entire bottom of the opening 41. In some embodiments, the endpoints of the current spreading layer 31 formed via a thermal annealing process extend under the dielectric layer 12, so the width W31 of the current spreading layer 31 is greater than the width W412 of the bottom of the opening 41. In some embodiments, the difference between the width W31 and the width W412 is very small and negligible. In some embodiments, the substrate 11 located in the opening 41 is entirely covered by the current spreading layer 31. In some embodiments, the width W31 of the current spreading layer 31 is between 0.1 micrometer and 2 micrometers. The vertical power semiconductor structure 1 may include a plurality of current spreading layers 31, and the number of current spreading layers 31 corresponds to the number of source doping regions 114. In some embodiments, as shown in FIG. 1, the current spreading layers 31 extend in the Y direction, and the plurality of current spreading layers 31 are separated from each other and parallel. Additionally, since the heavily doped region 116 is aligned with the current spreading layer 31 in the Z direction, the pattern of the current spreading layer 31 shown in FIG. 1 can simultaneously represent the pattern of the heavily doped region 116. In some embodiments, the opposite two endpoints of the current spreading layer 31 contact the sidewalls of the dielectric layer 12.

[0037] The current spreading layer 31 can be a single layer or a multi-layer structure. In some embodiments, the current spreading layer 31 includes one or more of the following materials: nickel (Ni), cobalt (Co), titanium (Ti), nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), titanium silicide (Ti x Si y ), nickel silicide (Ni x Si y ), titanium nitride (TiN), tantalum nitride (TaN). In some embodiments, the thickness of the current spreading layer 31 is between 5 nanometers (nm) and 300 nanometers. In embodiments where the current spreading layer 31 is a multi-layer structure, the thickness of a single layer in the current spreading layer 31 is between 5 nanometers and 300 nanometers.

[0038] The vertical power semiconductor structure 1 further includes at least two dielectric layers 22 and 23 covering the dielectric layer 21. The vertical power semiconductor structure 1 has dielectric layers 22 and 23 stacked in sequence along the Z direction on the dielectric layer 21, but the present disclosure is not limited thereto. In other embodiments, the vertical power semiconductor structure may only include the dielectric layer 22 or have other dielectric layers stacked on the dielectric layer 23. Taking the vertical power semiconductor structure 1 as an example, the dielectric layer 22 covers the dielectric layer 21, and a part of the dielectric layer 22 fills the opening 41. In some embodiments, the dielectric layer 22 contacts a part of the metal silicide 31. In some embodiments, the dielectric layer 22 covers the gate structure 13. In some embodiments, the dielectric layer 23 covers the dielectric layer 22 and has a top surface flatter than the top surface of the dielectric layer 22. The dielectric layers 22 and 23 may be the same or different dielectric materials. The materials of the dielectric layers 22 and 23 may include high-k materials, low-k materials, etc., such as silicon oxide (SiO2), silicon nitride (Si3N4 or Si x N y ), silicon oxynitride (SiO x N y ) and other materials. In some embodiments, the thickness of the dielectric layer 22 is between 500 angstroms and 20,000 angstroms. In some embodiments, the thickness of the dielectric layer 23 is between 500 angstroms and 20,000 angstroms, where the thickness of the dielectric layer 23 can be determined according to the depth and specifications of the conductive plug 37. In some embodiments, the dielectric layers 22 and 23 together have an opening 43 to accommodate the conductive plug 37.

[0039] The conductive plug 37 includes a part of the barrier layer surrounded by the dielectric layers 21, 22, and 23, and a metal layer 33 surrounded by the barrier layer 32. In some embodiments, the barrier layer 32 surrounds the metal layer 33 and further covers the top surface of the dielectric layer 23. The metal layer 33 may include one or more metal materials, such as tungsten (W), aluminum (Al), copper (Cu), aluminum copper (Al x Cu y)), its alloy, or a combination thereof. The barrier layer 32 may include one or more metal materials, such as nickel, cobalt, titanium, titanium nitride, tantalum nitride, its alloy, or a combination thereof. The barrier layer 32 includes a first portion 321 surrounding the sidewalls and bottom of the metal layer 33, a second portion 322 located above the metal layer 33, and a third portion 323 located above the dielectric layer 23. Since the third portion 323 covering the top surface of the dielectric layer 23 does not have the configuration of a plug, for convenience of description, and the conductive plug 37 in this document does not include the barrier layer 32 of the third portion 323 on the top surface of the dielectric layer 23. In some embodiments, the conductive plug 37 includes the first portion 321, the second portion 322, and the metal layer 33. In some embodiments, the conductive plug 37 is located between adjacent gate structures 13 and contacts the current spreading layer 31. In some embodiments, the conductive plug 37 is surrounded by the dielectric layers 22 and 23 and separated from the dielectric layer 21. In some embodiments, the conductive plug 37 is separated by the dielectric layer 22 and the dielectric layer 21. The first portion 321, the second portion 322, and the third portion 323 of the barrier layer 32 may be formed via a single or multiple deposition steps. It should be noted that, according to different manufacturing methods, the barrier layer 32 may not include the second portion 322 or / and the third portion 323. For example Figure 25 As shown in the vertical power semiconductor structure 2, in some embodiments, the barrier layer 32 does not have the second portion 322, and the source electrode layer 35 contacts the metal layer 33. In some embodiments, the thickness of the first portion 321 of the barrier layer 32 in the conductive plug 37 ranges between 50 angstroms and 5000 angstroms. In some embodiments, the thickness of the second portion 322 of the barrier layer 32 in the conductive plug 37 ranges between 50 angstroms and 5000 angstroms. In embodiments having the second portion 322, the thickness of the third portion 323 of the barrier layer 32 is approximately equal to the thickness of the second portion 322. In embodiments without the second portion 322, the thickness of the third portion 323 of the barrier layer 32 is approximately equal to the thickness of the first portion 321.

[0040] The vertical power semiconductor structure 1 may include a plurality of conductive plugs 37, and the number of conductive plugs 37 corresponds to the number of current spreading layers 31. In some embodiments, as shown in FIG. 1, the conductive plugs 37 extend in the Y direction, and the plurality of conductive plugs 37 are separated from each other and parallel. In some embodiments, as Figure 2 , 3 shown, the relatively two end points where the conductive plugs 37 are arranged in the X direction contact the dielectric layer 12.

[0041] Figure 4 is made according to some embodiments of the present disclosure, Figure 3 is an enlarged view of the cross-sectional structure 1B of the part in the dashed box. In some embodiments, the conductive plug 37 may contact and stop at the top of the current spreading layer 31, asFigure 2 , 3 as shown. In some embodiments, the conductive plug 37 can extend into the current spreading layer 31, as Figure 4 shown, which can increase the contact area between the conductive plug 37 and the current spreading layer 31 to facilitate reducing the resistance and reducing the current crowding effect (CCE). In some embodiments, the bottom surface of the conductive plug 37 (i.e., the bottom surface of the first portion 321 of the barrier layer 32) is lower than the surface 11A of the substrate 11. In some embodiments, the bottom surface of the conductive plug 37 is located between the surface 11A and the surface 11B of the substrate 11 in the Z direction, and the distance D42 from the bottom surface of the conductive plug 37 to the surface 11A in the Z direction is between 0.01 micrometer and 0.5 micrometers. The sidewall of the conductive plug 37 can be vertical, inclined, or arcuate. In some embodiments, the angle θ1 between the conductive plug 37 and the top surface of the current spreading layer 31 ranges between 45 degrees and 90 degrees.

[0042] The bottom of the conductive plug 37 has a width W43 that is smaller than the width W31 of the current spreading layer 31. The current spreading layer 31 has approximately the same width as the bottom of the opening 41, and the conductive plug 37 is separated from the dielectric layer 21 via the dielectric layer 22. Therefore, the conductive plug 37 is approximately disposed at the middle position of the current spreading layer 31 in the X direction. In some embodiments, the current spreading layer 31 has a first portion 311 and a second portion 312 located on opposite sides of the conductive plug 37 in the X direction. The first portion 311 and the first portion 311 of the current spreading layer 31 extend from opposite sidewalls of the conductive plug 37 to opposite sidewalls of the opening 41 (or the sidewalls of the dielectric layer 21), respectively. In some embodiments, the width W311 of the first portion 311 in the X direction (i.e., the distance from the sidewall of the conductive plug 37 to the sidewall of the dielectric layer 21) is approximately the same as the width W312 of the second portion 312 in the X direction (i.e., the distance from the other sidewall of the conductive plug 37 to the sidewall of the dielectric layer 21). In other words, the width W311 of the first portion 311 or the width W312 of the second portion 312 is approximately equal to half of the difference between the width W31 of the current spreading layer 31 and the width W43 of the bottom of the conductive plug 37 (i.e., (W31 - W43) / 2). In some embodiments, the width W311 of the first portion 311 or the width W312 of the second portion 312 is between 0.1 micrometer and 1 micrometer. In some embodiments, the ratio of the width W311 of the first portion 311 to the width W43 of the bottom of the conductive plug 37 (i.e., W311 / W43) is between 0.1 and 10. Similarly, in some embodiments, the ratio of the width W312 of the second portion 312 to the width W43 of the bottom of the conductive plug 37 (i.e., W312 / W43) is between 0.1 and 10.

[0043] The vertical power semiconductor structure 1 further includes a source electrode layer 35 and a drain electrode layer 36, which are located on opposite sides of the substrate 11. The source electrode layer 35 is located above the surface 11A of the substrate 11 and is electrically connected to the conductive plug 37. The drain electrode layer 36 is located above the surface 11B of the substrate 11. In some embodiments, the drain electrode layer 36 contacts the surface 11B of the substrate 11. The source electrode layer 35 and the drain electrode layer 36 may include the same or different metal materials, such as aluminum, copper, aluminum-copper, their alloys, or combinations thereof. According to the specifications of different products, the metal layer 33 and the source electrode layer 35 may be the same or different metal materials. In embodiments where the size of the opening 43 is small, the metal layer 33 may be selected to use, for example, tungsten or other metals with better hole-filling ability, while the source electrode layer 35, without considering the hole-filling ability, may be selected to use metals such as aluminum, copper, aluminum-copper, etc. In embodiments where the size of the opening 43 is large, the metal layer 33 and the source electrode layer 35 may be made of the same material, or even the metal layer 33 and the source electrode layer 35 may be formed simultaneously in a single step. In embodiments where the metal layer 33 and the source electrode layer 35 are formed simultaneously in a single step, the metal layer 33 and the source electrode layer 35 are an integrally formed structure, so the barrier layer 32 does not include the second part 322. For example Figure 26 As shown in the vertical power semiconductor structure 3, in some embodiments, the barrier layer 32 does not have the second part 322, and the source electrode layer 35 and the metal layer 33 have the same metal material. In some embodiments, the thickness of the source electrode layer 35 located on the dielectric layer 23 is between 1 micron and 10 microns.

[0044] In the formation of plug trenches in existing vertical power semiconductor devices, metal silicide is first formed at the bottom of the trench and then metal plugs are formed in the trench to achieve the effect of reducing the interface resistance value. However, with the progress of technology, in the current situation of product size miniaturization, existing vertical power semiconductor devices not only face the dilemma of being unable to further reduce the interface resistance value and the resistance value of vertical power semiconductor devices, but also, in the structure where the metal silicide is aligned with the metal plug, a current crowding effect is likely to occur at the bottom end point of the plug trench (that is, the bottom end point of the metal plug and the metal silicide), resulting in a decrease in the reliability of vertical power semiconductor devices.

[0045] The vertical power semiconductor structure (1) provided by the present disclosure has a vertical current conduction path. The current conducts from the source electrode layer 35 along the conductive plug 37, the current spreading layer 31, and the channel (the substrate 11 under the gate structure 13) to the drain electrode layer 36. The current spreading layer 31 is located between the conductive plug and the substrate 11, which can help reduce the interface barrier height and is beneficial to reducing the resistance value of the vertical power semiconductor structure 1. Compared with the existing metal silicide, the current spreading layer 31 has a first part 311 and a second part 312 extending from the bottom of the conductive plug 37 towards the gate structure 13. It can provide a current conduction path extending outside the conductive plug 37 and having a lower resistance value than the substrate 11 while reducing the interface resistance value without modifying the specifications of the conductive plug 37, thereby improving the resistance value and reliability issues of the vertical power semiconductor structure.

[0046] Furthermore, in recent years, silicon carbide materials have been introduced as the substrate of power semiconductor devices. The manufacturing methods of traditional metal silicide structures cannot be well integrated with silicon carbide substrates. The metal silicide structures manufactured according to traditional methods will have problems such as holes and carbon precipitation, resulting in instability of the resistance value and reducing the reliability of the product. The present disclosure provides an exemplary manufacturing method 700 associated with forming the vertical power semiconductor structure 1, including multi-stage annealing processes, multi-layer composite metal materials, etc. to form the current spreading layer 31 and improve the problems of holes and carbon precipitation. The manufacturing method 700 of the present disclosure can be well integrated with silicon carbide substrates.

[0047] Figure 5 is a flowchart of an exemplary manufacturing method 700 associated with forming the vertical power semiconductor structure 1. The manufacturing method 700 includes multiple steps (such as steps 701, 702, 703, 704, 705, 706, and 707). In some embodiments, different dielectric layers are used to define the current spreading layer 31 and the conductive plug 37, so that the width W31 of the current spreading layer 31 is greater than the width W43 of the bottom of the conductive plug 37 to achieve the above-mentioned extended low-resistance current conduction path. In some embodiments, multi-stage annealing processes and multi-layer composite metal materials are used to form the current spreading layer 31 to achieve the effects of improving hole formation and avoiding carbon precipitation.

[0048] Figures 6 to 22 Shown is one or more stages in the manufacturing method 700 of the vertical power semiconductor structure 1 according to certain embodiments of the present case. It should be noted that Figures 6 to 22Shown is a cross-sectional structure corresponding to the A-A' tangent in FIG. 1 at different stages in manufacturing method 700 as an exemplary embodiment, but the present disclosure is not limited thereto. At least some of these figures have been simplified to better understand aspects of the present disclosure. It should be noted that manufacturing method 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0049] Referring Figure 6 , corresponding to step 701 of manufacturing method 700, manufacturing method 700 includes: forming a plurality of gate structures 13 on the surface 11A of substrate 11. The plurality of doped regions 111, 112, 113, 114, and 115 in substrate 11 may be formed via multiple ion implantation processes in combination with photoresist layers or mask layers having different patterns to form doped regions 111, 112, 113, 114, and 115 having different depths, concentrations, coverage ranges, and conductivity types. Before forming the gate structures 13, manufacturing method 700 may further include: forming dielectric layer 12 on the surface 11A of substrate 11. In some embodiments, the formation of gate structures 13 includes performing one or more etching processes on the material layers for forming the gate structures 13 (such as the gate electrode layer, sidewall spacers, etc. described above) to define the positions and configurations of the gate structures 13. In some embodiments, the above etching process does not remove dielectric layer 12. In some embodiments, after step 701, dielectric layer 12 covers the surface 11A of the portion of substrate 11 located outside the gate structures 13.

[0050] Referring Figure 7 , corresponding to step 702 of manufacturing method 700, manufacturing method 700 includes: forming dielectric layer 21 on the gate structures 13 to cover the gate structures 13 and substrate 11. In some embodiments, after step 701, a deposition process is performed on the surface 11A of substrate 11 to form dielectric layer 21 that covers the plurality of gate structures 13 and dielectric layer 12. In some embodiments, the profile of dielectric layer 21 corresponds to the profiles of the gate structures 13 and dielectric layer 12. In some embodiments, dielectric layer 21 conformally covers the gate structures 13 and dielectric layer 12.

[0051] Referring Figure 8, corresponding to step 703 of manufacturing method 700, manufacturing method 700 includes: performing a first patterning process on dielectric layers 12 and 21 to form an opening 41 between adjacent gate structures 13, wherein the opening 41 exposes the surface 11A of a portion of the substrate 11. In some embodiments, before performing the first patterning process, a mask layer (not shown in the figure) defined by a photomask 61 is formed on the dielectric layer 21. In some embodiments, the dielectric layers 12 and 21 have a low etch selectivity for the etchant used in the first patterning process, so the dielectric layers 12 and 21 can be removed in the same etching step to form the opening 41. In some embodiments, if the dielectric layers 12 and 21 have a high etch selectivity for a single etchant in the first patterning process, the same mask layer can be used as a mask to etch the dielectric layers 12 and 21 separately to form the opening 41. In some embodiments, the sidewalls of the opening 41 are jointly defined by the patterned dielectric layers 12 and 21. The sidewalls of the opening 41 can be vertical, inclined, or arcuate. However, since they are defined by the same photomask 61 and mask layer, the sidewalls of the opening 41 are continuous or smooth sidewalls, and no stepped drop is formed at the junction of the dielectric layers 12 and 21. In some embodiments, the width W411 of the top of the opening 41 is greater than the width W412 of the bottom of the opening 41. In some embodiments, the width 411 of the top of the opening 41 and the width 412 of the bottom of the opening 41 are approximately the same.

[0052] The purpose of retaining the dielectric layer 12 until it is removed together with the dielectric layer 21 is to minimize the exposure of the substrate 11 to other etching or cleaning steps. According to different embodiments, after etching the gate electrode layer of the gate structure 13, a spacer material layer can be formed to cover the gate electrode layer, and then the spacer material layer is etched to form sidewall spacers. Assuming that the dielectric layer 12 is removed simultaneously when etching the gate electrode layer or the spacer material layer, the substrate 11 will be exposed during the etching of the spacer material layer or the subsequent cleaning step, resulting in damage to the surface 11A (especially the part adjacent to the source doping region 114). By removing the dielectric layer 12 in the step of etching the dielectric layer 21 in the present disclosure, the chance of damage to the surface 11A of the substrate 11 can be reduced.

[0053] The surface 11A exposed by the opening 41 will define the position of the current spreading layer 31 formed later. Figures 9 to 14 Shown are schematic diagrams of multiple stages of forming the current spreading layer 31. In order to make the current spreading layer 31 have a low resistance value and good current conduction effect, the formation of the current spreading layer 31 can include multiple ion implantation steps and multiple thermal annealing steps at different temperatures.

[0054] Referring to Figure 9, before step 704, the manufacturing method 700 may further include: performing an ion implant process S1 on the substrate 11 of the portion exposed by the opening 41 to form a heavily doped region 116. The purpose of forming the heavily doped region 116 is to reduce the barrier height between the metal material and the substrate 11. Especially when the material of the substrate 11 is silicon carbide, after silicon carbide forms a bond with the implanted ions and then forms defects, the energy barrier and contact resistance can be reduced through the principle of Trap-assisted Tunneling. Therefore, the ions used in the ion implant process S1 have a first conductivity type, and the heavily doped region 116 is a shallowly doped region with a high doping concentration and the same conductivity type as the source doping region 114. In some embodiments, the doping concentration of the heavily doped region 116 is greater than that of the source doping region 114. In some embodiments, the temperature range of the ion implant process S1 is between 15 degrees C and 100 degrees C. In some embodiments, the energy range of the ion implant process S1 is between 15 keV (kilo-electron volts) and 80 keV. In some embodiments, the ion dose range of the ion implant process S1 is between 5E13 cm -2 (per square centimeter) and 5E16 cm -2 .

[0055] Referring to Figure 10 , before or after the ion implant process S1 and before step 704, the manufacturing method 700 may further include: performing an ion bombard process S2 on the exposed substrate 11 to increase the surface roughness (reduce the grain size) of the exposed portion of the substrate 11. In order to effectively increase the surface roughness of the substrate 11 without significantly changing the doping region concentration in the substrate 11, the ion bombard process S2 uses inert gas ions. In some embodiments, the ions used in the ion bombard process S2 have a larger size or weight compared to the ions used in the ion implant process S1. The ion implant process S1 may increase the surface roughness of the substrate 11, but its main purpose is to form defects, while the ion bombard process S2 can ensure that the surface 11A of the exposed substrate 11 has a larger surface roughness, so as to increase the surface contact area and reaction rate, which is helpful for the formation of the subsequent current spreading layer 31. In some embodiments, the ion bombard process S2 is performed after the ion implant process S1, which can well control the depth of ion implantation and reduce or avoid the probability of unstable ion implantation depth. In addition, as described above, defects in silicon carbide help to reduce the energy barrier and contact resistance, and the ion bombard process S2 is beneficial to increasing the number of defects, thereby enhancing the effect of trap-assisted tunneling.

[0056] Referring to Figure 11, corresponding to step 704 of manufacturing method 700, manufacturing method 700 includes: forming a metal layer 315 on the first dielectric layer, covering at least the substrate 11 exposed by the opening 41. The metal layer 315 is a single-layer or multi-layer metal material layer formed by a deposition process. In some embodiments, when the material of the substrate 11 is silicon carbide, the metal layer 315 is a composite material formed by sequentially depositing and stacking multi-layers of different metal materials. The metal layer 315 will be transformed into a metal silicide via a thermal annealing process in subsequent steps, and the metal silicide formed from the metal layer 315 with a composite material has fewer pores compared to the metal layer 315 made of a single metal material, and there will be no problem of carbon precipitation.

[0057] Referring to Figure 12 , before step 705, manufacturing method 700 may further include: performing an ion implantation process S3 on the metal layer 315. In the ion implantation process S3, ions of the same semiconductor material as that of the substrate 11 can be used to implant the metal layer 315. In some embodiments, the ion implantation process S3 uses at least one of the elements from group III to V. In the ion implantation process S3, gas ions that do not affect the conductivity type of the substrate 11 can also be used to implant the metal layer 315. In some embodiments, the ion implantation process S3 uses inert gas ions to implant the metal layer 315. In embodiments where silicon carbide is used as the substrate 11, as described above, during the formation of the metal silicide, carbon ions in the silicon carbide will precipitate, affecting the resistance value and reliability of the subsequently formed metal silicide. The ion implantation process S3 can reduce the grain size of the metal layer 315, which is beneficial to the formation of the metal silicide. Therefore, the ion implantation process S3 is also called a nucleation assisting implant process. Additionally, research by the inventors shows that the ion implantation process S3 can further improve the problem of carbon precipitation.

[0058] Referring to Figure 12 , corresponding to step 705 of manufacturing method 700, manufacturing method 700 includes: performing a first annealing process S4 on the metal layer 315 to form a metal silicide layer 316. In some embodiments, the temperature range of the first annealing process S4 is between 550 °C and 800 °C. The temperature of the first annealing process S4 is sufficient to cause the metal layer 316 to react with the substrate 11, so that a part of the metal layer 315 in contact with the substrate 11 and a part of the substrate 11 in contact with the metal layer 315 form the metal silicide layer 316. In some embodiments, a part of the substrate 11 located in the heavily doped region 116 reacts to form the metal silicide layer 316. In other embodiments, all of the substrate 11 located in the heavily doped region 116 reacts to form the metal silicide layer 316.

[0059] Referring to Figure 13, after step 705, fabrication method 700 may further include: removing the metal layer 315 other than the metal silicide 316. The portion of the metal layer 315 covering the dielectric layer 21 is not formed into a metal silicide because it is separated from the substrate 11. In some embodiments, an etching process is used to remove the unreacted metal layer 315.

[0060] Referring to Figure 14 , corresponding to step 706 of fabrication method 700, fabrication method 700 includes: performing a second annealing process S5 on the metal silicide layer 316 to form a current spreading layer 31. The temperature of the second annealing process S5 is higher than that of the first annealing process S4 by a small amount. In some embodiments, the temperature of the second annealing process S5 ranges from 700 °C to 1000 °C. The purpose of the second annealing process S5 is to adjust the phase of the metal silicide. Although the temperature of the first annealing process S4 is sufficient to form the metal silicide, the phase of the formed metal silicide layer 316 has a relatively high resistance value. The second annealing process S5 has a higher temperature, which is sufficient to adjust the phase of the metal silicide to a phase with a low resistance value. In some embodiments, the resistance value of the current spreading layer 31 is less than that of the metal silicide 316. In some embodiments, the time range of the second annealing process S5 is from 30 seconds to 90 seconds.

[0061] Existing procedures for forming metal silicides include a single high-temperature thermal annealing process (for example, the temperature generally ranges from 950 °C to 1150 °C, and the total duration is greater than 90 seconds), which directly forms a metal silicide with a low-resistance phase. Compared with the two-stage thermal annealing process of the present disclosure, the existing procedures have a higher thermal budget, which also results in a longer time for the substrate 11 to be in a high-temperature environment. Since the silicon carbide substrate is less suitable for high-temperature processes compared to the silicon crystal substrate, the existing metal silicide formation procedures are not conducive to the application of the silicon carbide substrate, restricting the choice of substrate materials. Furthermore, the two-stage thermal annealing process of the present disclosure has a lower thermal budget compared to the existing single high-temperature thermal annealing process. When the thermal budget of the annealing process (especially the thermal budget of the high-temperature annealing process) is higher, the metal silicide is more likely to grow along the surface of the substrate. Therefore, a higher thermal budget is more likely to cause leakage current. Taking Figure 13 the structure as an example, if the existing single high-temperature thermal annealing process is used instead of the two-stage thermal annealing process of the present disclosure, the metal silicide may not only form at the position of the metal silicide layer 316 in Figure 13 , but may also further grow along the surface 11A of the substrate 11 and extend in the direction of the gate structure 13, resulting in an increased probability of leakage current. The present disclosure has a lower thermal budget compared to the existing single high-temperature thermal annealing process, so the occurrence of leakage current can be avoided. In addition, the thermal budget is also one of the factors for carbon precipitation. The present disclosure has a lower thermal budget compared to the existing thermal annealing process, so the problem of carbon precipitation can be further avoided.

[0062] Referring to Figure 16 , after step 706, manufacturing method 700 further includes: forming at least one dielectric layer (such as 22, 23) to cover the current spreading layer 31 and the dielectric layer 21. The dielectric layer 22 fills Figure 8 the opening 41 shown. In some embodiments, the dielectric layer 22 contacts the upper surface of the current spreading layer 31. In some embodiments, the dielectric layer 23 covers the top surface of the dielectric layer 22. In some embodiments, the dielectric layer 23 is located above and separated from the opening 41. The dielectric layer 23 can be optional, or to provide a flatter surface for subsequent operations, other dielectric layers can be selectively formed on the dielectric layer 23. In some embodiments, the top surface of the dielectric layer 23 is flatter than the top surface of the dielectric layer 22.

[0063] Referring to Figure 17 and 18 , after step 706, manufacturing method 700 further includes: performing a second patterning process on at least one dielectric layer (such as 22, 23) to form an opening 43 between adjacent gate structures 13, exposing a portion of the current spreading layer 31. The opening 43 will define the position of the conductive plug 37 to be formed later. To ensure that the conductive plug 37 is entirely located on the current spreading layer 31, the width W432 of the bottom of the opening 43 should be less than Figure 8 the width W412 of the bottom of the opening 41 in Figure 8 . Details of the second patterning process can refer to the relevant description paragraphs in the foregoing

[0064] As Figure 17As shown, in some embodiments, the second patterning process uses a photomask 62 different from the first patterning process to define the opening 43. In some embodiments, the width W431 at the top of the opening 43 is greater than the width W432 at the bottom of the opening 41. In some embodiments, the width W431 at the top of the opening 43 is less than the width W411 at the top of the opening 41, and the width W432 at the bottom of the opening 43 is less than the width W412 at the bottom of the opening 41. The second patterning process may include a dry etching process. Without special adjustment of the etching angle (such as an angled etching process), generally, the maximum width of the opening 43 occurs at the top of the opening 43, that is, the width W431. In some embodiments, the sidewalls of the opening 43 are vertical sidewalls. In some embodiments, the opening 43 has a configuration with a wider top and a narrower bottom. Using a photomask 62 different from the photomask 61 of the first patterning process can ensure that the width W432 at the bottom of the opening 43 is less than the width W412 at the bottom of the opening 41. In some embodiments, the opening 43 is within the coverage of the opening 41.

[0065] As Figure 18 shown, in some embodiments, the second patterning process uses the same photomask 61 as the first patterning process to define the opening 43. In some embodiments, the opening 43 has a configuration with a wider top and a narrower bottom, and the top of the opening 43 is aligned with the top of the opening 41 in the vertical direction. As described above, the configuration of the opening 43 can be adjusted and controlled via an etching process. In Figure 16 the embodiments shown, as long as the opening 43 has a configuration with a wider top and a narrower bottom, and the inclination angle of the sidewalls of the opening 43, even if the same photomask 61 is used, it is also possible to ensure that the width W432 at the bottom of the opening 43 is less than the width W412 at the bottom of the opening 41. In Figure 17 the embodiments shown, although an additional photomask 62 needs to be used, the selectivity of the etching process is higher and the operating window is larger. In Figure 17 the embodiments shown, the same photomask 61 can be used in multiple stages, reducing the manufacturing cost, but the accuracy requirements for the etching process are higher.

[0066] Over-etching commonly occurs in the etching process. Generally speaking, over-etching is an undesirable result in the etching process and can be controlled or improved by adjusting parameters or the etching selectivity ratio. However, in some embodiments of the present disclosure, the over-etching of the etching process for forming the opening 43 can increase the contact area between the subsequently formed conductive plug 37 and the current spreading layer 31, which is beneficial to current conduction and reducing the resistance value. In some embodiments, the manufacturing method 700 may further include: performing an over-etching process on the exposed portion of the current spreading layer 31 such that the bottom of the opening 43 is located in the current spreading layer 31. In some embodiments, the manufacturing method 700 may further include: etching the dielectric layers 22 and 23, setting the etching end point of the etching process at the current spreading layer 31, and continuing the etching process for a preset number of seconds after detecting the etching end point signal to control the depth at which the bottom of the opening 43 is located in the current spreading layer 31. In some embodiments, the distance between the bottom of the opening 43 and the surface 11A of the substrate 11 (i.e., Figure 4 shown as D42) is between 0.01 micrometers and 0.5 micrometers. The opening 43 stops at and does not penetrate the current spreading layer 31. In some embodiments, the depth of the opening 43 from the surface 11A of the substrate 11 towards the surface 11B (i.e., Figure 4 shown as D42) is less than the depth of the current spreading layer 31.

[0067] Figures 19 to 20 Shown is a schematic diagram of multiple stages for forming the conductive plug 37 (corresponding to step 706). In some embodiments, the conductive plug 37 may include multiple conductive materials, and the manufacturing method is as Figures 19 to 21 shown.

[0068] Referring to Figure 19 , the manufacturing method 700 may further include: forming a barrier layer 32 lining the opening 43, and forming a metal layer 33 in the opening 43. In some embodiments, a first process is performed to form the barrier layer 32, where the first process may include sputtering, electroplating, deposition, or other suitable processes. In some embodiments, a first portion 321 of the barrier layer 32 formed by the first process lines the opening 43, and a third portion 323 covers the top surface of the dielectric layer 23. In some embodiments, the metal layer 33 is deposited. The metal layer 33 may be a whole layer covering above the surface 11A of the substrate 11. In some embodiments, the metal layer 33 fills the opening 43 and further covers the barrier layer 32 located above the dielectric layer 23.

[0069] Referring to Figure 20, the manufacturing method 700 may further include: removing the metal layer 33 located above the barrier layer 32, and selectively forming a second portion 322 of the barrier layer 32 to cover the metal layer 33. The metal layer 33 can be removed by an etch-back process or a polishing process (such as chemical mechanical polishing, CMP), etc. In some embodiments, an etch-back process is performed on the metal layer 33 to remove the metal layer 33 located above the barrier layer 32, where the etch endpoint of the etch-back process stops at the barrier layer 32. In the above embodiments, an additional deposition process may not be performed to form the second portion 322 of the barrier layer 32 (e.g., Figure 25 as shown). In some embodiments, an etch-back process is performed on the metal layer 33 and the barrier layer 32 to remove the metal layer 33 and the third portion 323 of the barrier layer 32 located above the dielectric layer 23, where the etch endpoint of the etch-back process stops at the dielectric layer 23. In the above embodiments, a deposition process can be performed to form the second portion 322 of the barrier layer 32, and since the deposition process will simultaneously form the barrier layer 32 on the top surface of the dielectric layer 23, a new third portion 323 of the barrier layer 32 can be simultaneously formed while forming the second portion 322 of the barrier layer 32 (e.g., Figure 20 as shown). In some embodiments, the thickness of the third portion 323 of the barrier layer 32 is approximately equal to the thickness of the second portion 322. The first portion 321, the second portion 322 of the barrier layer 32, and the metal layer 33 together define the conductive plug 37.

[0070] Referring to Figure 21 , after forming the conductive plug 37, the manufacturing method 700 further includes: forming a source electrode layer 35 on the conductive plug 37, and forming a drain electrode layer 36 on a side of the substrate 11 opposite to the source electrode layer 35. In some embodiments, the source electrode layer 35 contacts the second portion 322 and the third portion 323 of the barrier layer 32. In some embodiments, the drain electrode layer 36 contacts the surface 11B of the substrate 11. The source electrode layer 35 and / or the drain electrode layer 36 can be formed by electroplating, sputtering, deposition, etc. or other suitable processes.

[0071] It should be noted that, as described above, when the size of the opening 43 is large, there are more choices of metal materials that can be filled into the opening 43, and the source electrode layer 35 and the metal layer 33 can choose the same metal material. In some embodiments, Figure 21 the steps can be directly applied after forming the barrier layer 32 in Figure 19 to form a vertical power semiconductor structure 3 as shown in Figure 26 .

[0072] Figures 22 to 24The conductive plugs 37 of different configurations are drawn according to different embodiments of the present disclosure. Based on the embodiment without the dielectric layer 23 and the barrier layer 32 in the second part 322, various different configurations of the conductive plugs 37 formed according to different etching processes are shown. As an exemplary illustration, the current spreading layer 31 of the present disclosure can be applied to the conductive plugs 37 of different configurations.

[0073] The sidewall of the conductive plug 37 can be arc-shaped, as Figure 22 shown. The sidewall of the conductive plug 37 contacts the dielectric layer 22. In other words, the configuration of the sidewall of the conductive plug 37 is consistent with the configuration of the sidewall of the dielectric layer 22. In some embodiments, the angle θ2 between the bottom of the sidewall of the conductive plug 37 and the current spreading layer 31 ranges from 45 degrees to 90 degrees.

[0074] The conductive plug 37 can have a dual damascene configuration, as Figure 23 、 24 shown. The conductive plug 37 has a lower part in contact with the current spreading layer 31 and an upper part located above the lower part, where the lower part has a smaller width W1 and the upper part has a larger width W2. And according to different manufacturing methods, the corner of the upper part adjacent to the lower part can be a right-angle profile approximately 90 degrees (as Figure 23 shown) or a rounded-corner profile (as Figure 24 shown).

[0075] In summary, the current spreading layer 31 of the present disclosure can provide an additional current conduction path without changing the specifications of the conductive plug 37, which is beneficial to the trend of product miniaturization. Furthermore, the present disclosure further explores the application of the current spreading layer 31 to a silicon carbide substrate. According to the manufacturing method taught above, the current spreading layer 31 can be well integrated with the silicon carbide substrate to achieve the effect of a low resistance value.

[0076] In this document, spatial relative terms such as "below", "beneath", "lower", "above", "upper", "left", "right", etc. may be used for convenience of description to describe the relationship of one component or feature to another or other components or features as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as "connected to" or "coupled to" another component, it can be directly connected to or coupled to the other component, or there may be intermediate components.

[0077] As used herein, the terms "about," "substantially," "essentially," and "approximately" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs nearly. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges herein may be expressed as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified. The term "substantially coplanar" may refer to a positional difference between two surfaces located along the same plane that is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm of being located along the same plane. When a numerical value or characteristic is referred to as being "substantially" the same, the term may refer to a value that is within ±10%, ±5%, ±1%, or ±0.5% of the average of the value.

[0078] The foregoing outlines the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure can be readily used as a basis for designing or modifying other processes and structures in order to facilitate the implementation of the same or similar purposes and / or achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A vertical power semiconductor device, characterized in that, Comprising: A substrate having a first surface and a second surface opposite to each other; A first gate structure located on the first surface of the substrate; A second gate structure located on the first surface of the substrate and adjacent to the first gate structure; A first dielectric layer covering the first gate structure, the second gate structure and the first surface of the substrate, wherein the first dielectric layer has a first opening between the first gate structure and the second gate structure; A current spreading layer located at the bottom of the first opening between the first gate structure and the second gate structure, wherein the current spreading layer has a first width, and the first width is approximately the same as the width of the bottom of the first opening; A conductive plug located between the first gate structure and the second gate structure and contacting the current spreading layer, wherein the bottom of the conductive plug has a second width, and the second width is smaller than the first width of the current spreading layer; A source electrode layer located on the first surface of the substrate and electrically connected to the conductive plug; And A drain electrode layer located on the second surface of the substrate.

2. The vertical power semiconductor device according to claim 1, wherein the first width of the current spreading layer is between 0.1 micrometer and 2 micrometers.

3. The vertical power semiconductor device according to claim 2, wherein a part of the current spreading layer extends from the conductive plug to the first dielectric layer, the part of the current spreading layer has a third width, and the ratio of the third width to the second width of the bottom of the conductive plug is between 0.1 and 10.

4. The vertical power semiconductor device according to claim 3, wherein the third width is between 0.1 micrometer and 1 micrometer.

5. The vertical power semiconductor device according to claim 1, wherein the thickness of the first dielectric layer is between 50 angstroms and 5000 angstroms.

6. The vertical power semiconductor device according to claim 1, further comprising: A second dielectric layer covering the first dielectric layer and surrounding the conductive plug, wherein a part of the second dielectric layer fills the first opening, and the conductive plug is separated by the second dielectric layer and the first dielectric layer.

7. The vertical power semiconductor device according to claim 1, wherein the substrate comprises: A source doping region adjacent to the first surface and extending between the first gate structure and the second gate structure, wherein opposite sides of the source doping region respectively overlap below the first gate structure and the second gate structure; and A first heavily doped region overlapping below the current spreading layer and adjacent to the current spreading layer, wherein the heavily doped region has the same conductivity type as the source doping region, and the doping concentration of the heavily doped region is greater than the doping concentration of the source doping region.

8. The vertical power semiconductor device according to claim 7, wherein the depth of the first heavily doped region is less than the depth of the source doped region.

9. The vertical power semiconductor device according to claim 7, wherein the substrate further comprises: A second heavily doped region adjacent to the first surface and extending between the first gate structure and the second gate structure, wherein the second heavily doped region has a different conductivity type from the source doping region, the second heavily doped region is not covered by the first gate structure and the second gate structure, and the depth of the second heavily doped region is greater than the depth of the source doping region.

10. The vertical power semiconductor device according to claim 9, wherein a part of the first heavily doped region is located in the source doped region and a part of the first heavily doped region is located in the second heavily doped region.

11. The vertical power semiconductor device according to claim 9, further comprising: A third dielectric layer located on the first surface of the substrate, the third dielectric layer being located between the gate structure and the substrate and further extending between the first dielectric layer and the first surface of the substrate, wherein the sidewall of the third dielectric layer is flush with the sidewall of the first opening, and the current spreading layer contacts the sidewall of the third dielectric layer.

12. A manufacturing method of a vertical power semiconductor device, characterized in that, Comprising: Forming a first gate structure and a second gate structure adjacent to each other on a substrate; Forming a first dielectric layer covering the first gate structure, the second gate structure and the substrate; Performing a first patterning process on the first dielectric layer to form a first opening between the first gate structure and the second gate structure, exposing a part of the substrate; Form a metal layer on the first dielectric layer to cover the exposed portion of the substrate; Perform a first annealing process on the metal layer to form a metal silicide layer; Perform a second annealing process on the metal silicide layer to form a current spreading layer, wherein the temperature of the first annealing process is less than the temperature of the second annealing process, and the resistance value of the current spreading layer is less than the resistance value of the metal silicide layer; And Form a conductive plug on the current spreading layer, wherein the width of the bottom of the conductive plug is less than the width of the current spreading layer.

13. The manufacturing method according to claim 12, further comprising: Before forming the metal layer, perform an ion implantation process on the exposed portion of the substrate to form a heavily doped region, wherein the heavily doped region has the same conductivity type as the source doping region of the substrate, and the doping concentration of the heavily doped region is greater than the doping concentration of the source doping region.

14. The manufacturing method according to claim 12, further comprising: Before forming the metal layer, perform an ion bombardment process on the exposed portion of the substrate to increase the surface roughness of the exposed portion of the substrate, wherein the ion bombardment process uses inert gas ions.

15. The manufacturing method according to claim 12, further comprising: Before performing the first annealing process, perform an ion implantation process on the metal layer to implant at least one of group III elements, group V elements, and inert gas ions into the metal layer.

16. The manufacturing method according to claim 12, further comprising: After the first annealing process, remove the portion of the metal layer that has not formed the metal silicide.

17. The manufacturing method according to claim 12, further comprising: Form a second dielectric layer to cover the current spreading layer and the first dielectric layer; And Perform a second patterning process on the second dielectric layer to form a second opening between the first gate structure and the second gate structure, exposing a portion of the current spreading layer, wherein the width of the bottom of the second opening is less than the width of the bottom of the first opening.

18. The manufacturing method according to claim 17, wherein the second patterning process comprises: Perform an etching process on the second dielectric layer to remove a portion of the second dielectric layer to expose the portion of the current spreading layer; And Perform an over-etching process on the portion of the current spreading layer, wherein the bottom of the second opening is located in the current spreading layer.

19. The manufacturing method according to claim 18, wherein the distance from the bottom of the second opening to the top surface of the substrate is between 0.01 micrometer and 0.5 micrometers.

20. The manufacturing method according to claim 17, wherein the first patterning process and the second patterning process use the same photomask.

21. The manufacturing method according to claim 12, wherein the material of the conductive plug includes tungsten, and the manufacturing method further comprises: Form a source electrode layer on the conductive plug; And Form a drain electrode layer on a side of the substrate opposite to the source electrode layer.

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