PCS energy storage converter carrier synchronization method and device

Abstract

The invention discloses a PCS energy storage converter carrier synchronization method and device, and the method comprises the steps: generating a synchronous output signal through a pulse width modulation module of a centralized control processor and an independent core processor through a zero-crossing position of a carrier count value, and configuring a capturing module of a centralized control module, and the synchronous signal is enabled to be in phase synchronization with the carrier count value of the pulse width modulation module, and the synchronous signal is routed to a general input / output pin through a crossbar switch module to generate a carrier synchronous signal which is output outwards. According to the main technical scheme and effects, carrier synchronization of a plurality of PCS (power conversion system) converters can be realized, and phase consistency of carrier signals among a plurality of PCS units running in parallel is ensured. The high-precision synchronization effectively eliminates the problems of ring current and power imbalance caused by asynchronous carrier waves, and ensures the efficient operation of the energy storage system.

Description

Technical Field

[0001] The present invention relates to the field of converters, and in particular, to a carrier synchronization method and device for a PCS energy storage converter. Background Art

[0002] As a two-way power conversion device between a battery system and a power grid system, a power conversion system (PCS) is widely used in scenarios such as energy storage power stations, string-type, centralized large-scale energy storage, industrial and commercial, and household energy storage for power conversion. In the context of achieving the goals of carbon peak and carbon neutrality, with the technological maturity of new energy storage directions such as wind and solar power generation under clean energy, higher requirements are also put forward for the reliability and flexibility of power electronic power conversion systems.

[0003] In an energy storage system with a large power demand, under the existing cost and technical capabilities, multiple PCSs are used in parallel operation in the system to meet the total conversion power demand of the system. When multiple PCSs operate independently in parallel, there are problems of large circulating currents and power imbalance among multiple PCS modules, resulting in reduced efficiency, system instability, and high thermal resistance of the energy storage system. The existing technical solutions have the following defects:

[0004] (1) Based on digital phase-locked loop technology, the industrial frequency grid voltage is phase-detected and tracked to achieve the industrial frequency synchronization adjustment of the output voltage and current of each independent PCS to the grid phase. Each PCS is greatly affected by the grid phase and frequency, and its own sampling accuracy will also affect the tracking phase accuracy of the phase-locked loop to the grid, resulting in poor consistency in fast dynamic response power tracking and poor stability under weak grids;

[0005] (2) A corresponding circulating current suppression circuit is added to the AC side of each PCS. Based on each independent PCS, through a matching algorithm, the phase and amplitude of the output voltage and current are tracked and adjusted to achieve the purpose of reducing the circulating current, which will incur additional hardware cost overhead;

[0006] (3) An active-slave mode is adopted. The host generates a synchronization signal output at a specific position based on its control module pulse width modulator (ePWM), and all other slaves receive the synchronization signal to achieve the synchronization of the control carrier. This mode has high time accuracy, but it is difficult to suppress interference problems. When the synchronization output signal is abnormal, the pulse width modulators (ePWM) of all slaves will have abnormal modulation duty cycles, which has a great impact on the control of each slave. Summary of the Invention

[0007] Object of the Invention: The object of the present invention is to solve the defect of poor consistency of different energy storage converters in the prior art, and to provide a carrier synchronization method and device for a PCS energy storage converter.

[0008] Technical Solution:

[0009] In a first aspect, the present application proposes a PCS energy storage converter carrier synchronization method, including the steps of:

[0010] Step 1: Generate a synchronous output signal through the pulse width modulation modules of the centralized control processor and the independent core processor at the zero-crossing position of the carrier count value;

[0011] Step 2: Configure the capture module of the centralized control module to be phase-synchronized with the carrier count value of the pulse width modulation module, and generate an externally output carrier synchronization signal through the cross-switch module via the general-purpose input / output pins;

[0012] Step 3: In each independent core processor, capture the carrier synchronization signal through the input / output pins, and use its capture module to perform timestamp capture on the rising edge or falling edge of the carrier synchronization signal;

[0013] Step 4: Dynamically adjust the carrier count value of the pulse width modulation module of the independent core processor according to the captured timestamp data, so that the phase of the carrier synchronization signal of the core processor is synchronized with the carrier phase of the centralized control processor, thereby achieving converter carrier synchronization.

[0014] Preferably, step 1 includes:

[0015] The pulse width modulation module generates a synchronous output signal at the zero-crossing position of the carrier count value in an increasing and decreasing counting manner.

[0016] Preferably, step 2 includes:

[0017] Enable synchronous input enable through the auxiliary pulse width modulation function of the centralized control module, and select the synchronous input source of the auxiliary pulse width modulation module as the synchronous output signal.

[0018] Preferably, step 3 includes:

[0019] Configure the capture module of the independent core processor, enable its capture function, enable synchronous input enable, and configure the capture of the rising edge or falling edge of the externally incoming carrier synchronization signal based on absolute time in the capture mode to achieve tracking of the relative time position of the synchronously incoming carrier synchronization signal.

[0020] Preferably, step 3 includes: The independent core processor obtains the carrier synchronization signal, through the first rising edge event in the carrier synchronization signal, the second falling edge event after the first rising edge event, and the third rising edge event after the second falling edge event.

[0021] Preferably, step 3 further includes:

[0022] Obtain CAP1, CAP2, and CAP3 through the first rising edge event in the carrier synchronization signal, the second falling edge event after the first rising edge event, and the third rising edge event after the second falling edge event;

[0023] Among them, CAP1 represents the time stay value between the carrier counter of the core processor counting from zero to the captured first rising edge;

[0024] CAP2 represents the time stay value between the first rising edge and the second falling edge;

[0025] CAP3 represents the time stay value between the second falling edge and the third rising edge.

[0026] Preferably, judging the validity of CAP1 includes:

[0027] Filter CAP1 after removing the upper and lower limit ranges, and obtain the confirmation flag flg1 after the filtering is completed;

[0028] Form a complete carrier synchronization signal period through CAP2 and CAP3;

[0029] Obtain the frequency and duty cycle of the carrier synchronization signal through the complete carrier synchronization signal period;

[0030] Compare the calculated frequency and duty cycle of the carrier synchronization signal with the preset frequency and duty cycle of the carrier synchronization signal of the centralized control processor to obtain the frequency reference deviation and the duty cycle reference deviation;

[0031] Judge that when the frequency reference deviation and the duty cycle reference deviation are within the preset range, obtain the valid flag flg2;

[0032] When obtaining flg1 and flg2, it is determined that the CAP1 value is valid.

[0033] Preferably, the said step 4 includes:

[0034] The captured rising edge and falling edge timestamp data are used to adjust the carrier counter in the core processor. The adjusted carrier counter value drives the drive pulse of the independent core processor, and at the position where the carrier count crosses zero, a synchronous output signal associated with the capture module is output;

[0035] During the process of adjusting the carrier counter in the core processor, synchronously update the synchronous output signal in the independent core processor.

[0036] Preferably, step 4 includes:

[0037] Adjust the carrier period value by periodic compensation algorithm until the phase error of the carrier synchronization signals of all parallel independent core processors converges within a preset deviation range, where:

[0038] When the absolute time value of the captured valid CAP1 is less than half of the control carrier period and greater than a specific deviation value, reduce the pulse width modulation period value in the core processor to adjust the carrier synchronization signal;

[0039] When the absolute time value of the captured valid CAP1 is greater than half of the control carrier period and less than the carrier maximum threshold, increase the pulse width modulation period value, where the maximum threshold is the difference between the pulse width modulation period and the specific deviation value;

[0040] When the time value of the captured CAP1 is close to zero, restore the pulse width modulation period value to the standard set pulse width modulation period, thereby achieving carrier synchronization.

[0041] Second part, the present application also proposes a PCS energy storage converter carrier synchronization device, including the method described in the above embodiment, including:

[0042] A centralized control processor, multiple independent core processors;

[0043] The centralized control processor is electrically connected to the multiple independent core processors through links respectively;

[0044] Among them, the centralized control processor and the independent core processor respectively include a cross-switch module, a capture module, a pulse width modulation module, and the independent core processor also includes a converter;

[0045] The cross-switch module, the capture module, and the pulse width modulation module are electrically connected in sequence, and the converter.

[0046] Beneficial effects: This solution can achieve carrier synchronization of multiple PCS (Power Conversion System) converters, ensuring the phase consistency of carrier signals among multiple PCS units operating in parallel. This high-precision synchronization effectively eliminates the circulating current and power imbalance problems caused by carrier asynchronization, ensuring the efficient operation of the energy storage system;

[0047] This synchronization method does not rely on additional hardware circuits (such as circulating current suppression circuits, etc.), and completely realizes synchronization through software configuration and existing hardware resources (such as ePWM module, eCAP module, GPIO, etc.). This reduces the hardware cost of the system and simplifies the system design;

[0048] Through periodic compensation, the system can detect and adjust the phase deviation of the carrier synchronization signal in real time. By dynamically adjusting the ePWM period value, it can flexibly cope with different system states and load changes, ensuring that the carrier synchronization signal accurately tracks and converges within the preset deviation range. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the method framework provided by the present invention;

[0050] Figure 2 It is a diagram of the output signal of the centralized control processor of the present invention;

[0051] Figure 3 It is a diagram of the output signal of the core processor of the present invention;

[0052] Figure 4 It is a diagram of the output of the control processor and the output signal of the core processor of the present invention and a schematic diagram of signal reception;

[0053] Figure 5 It is a schematic diagram of the training process of the distortion parameter prediction model provided by the present invention;

[0054] Figure 6 It is a schematic diagram of the flow structure for judging the effectiveness of CAP1 in this application;

[0055] Figure 7 It is a block diagram of the carrier synchronization test diagram structure of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] To make the technical solutions of the present invention clearer, the following further describes the present invention in detail with specific embodiments in conjunction with the accompanying drawings.

[0057] Embodiment 1

[0058] To make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should have the ordinary meaning understood by those of ordinary skill in the art in the field to which the present invention belongs. The words such as "including" used herein mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0059] Regarding the problems existing in the prior art, as Figures 1-5 shown, a carrier synchronization method for a PCS energy storage converter includes the steps:

[0060] Step 1: The pulse width modulation modules (ePWM modules) of the centralized control processor and the independent core processors generate synchronous output signals (Syscon generated by the centralized control processor and SysconN generated by the independent core processor) at the zero-crossing positions through the carrier count values (Epwm_TBCtr generated by the centralized control processor and Epwm_TBCtrN generated by the independent core processor). The pulse width modulation modules (ePWM modules) of the centralized control processor and the independent core processors respectively generate carrier count values (Epwm_TBCtr and Epwm_TBCtrN), and generate synchronous output signals through the zero-crossing positions of these carrier count values. The centralized control processor generates Syscon, and the independent core processor generates SysconN. In this way, the carrier signals of the centralized controller and each independent core processor are synchronized with each other, laying a foundation for subsequent carrier synchronization;

[0061] Step 2: Configure the capture module (eCAP_APWM module) of the centralized control module to be phase-synchronized with the carrier count value of the pulse width modulation module, and route the synchronous signal to the general-purpose input / output pin (GPIO) through the cross-switch (X-BAR cross-switch module) module to generate an externally output carrier synchronization signal (APWM). The eCAP_APWM module ensures that the signal is in phase with the carrier count value by capturing the zero-crossing signal (i.e., the synchronous signal) of the carrier count value from the ePWM module. The cross-switch (X-BAR module) is used to transfer the synchronous signal to external devices, and generate the carrier synchronization signal APWM through the GPIO port. In this way, the carrier synchronization signal APWM can be transferred to each independent core processor. For the centralized control module, the carrier counter EcapCtr of the eCAP module and the carrier count value Epwm_TBCtr of the ePWM are phase-synchronized. For the core processor, the carrier counter EcapCtrN of the eCAP module and the carrier count value Epwm_TBCtrN of the ePWM are phase-synchronized. In some preferred embodiments, a corresponding comparison value is configured in the APWM. Cmp represents the carrier comparison value, which is an initially set fixed value. When the EcapCtr carrier count is greater than the Cmp value, the APWM synchronous output signal is set low; when the EcapCtr carrier count value is less than the Cmp value, the APWM synchronous output signal is set high;

[0062] Step 3, in each independent core processor, the carrier synchronization signal (Cap, APWM sent by the centralized control module, becomes Cap after being received by the core processor) is captured through the input / output pin, and the rising edge or falling edge of the carrier synchronization signal is timestamped by its capture module. By capturing the rising edge or falling edge of the APWM synchronization signal, the phase information of the synchronization signal can be accurately recorded, providing necessary data for subsequent phase adjustment and compensation;

[0063] Step 4: According to the captured timestamp data, dynamically adjust the carrier count value of the pulse width modulation module of the independent core processor so that the carrier synchronization signal phase of the core processor is synchronized with the carrier phase of the centralized control processor to achieve converter carrier synchronization. By analyzing the timestamp data, the core processor adjusts the carrier count value of its ePWM module so that the phase of the carrier synchronization signal it generates is completely synchronized with the carrier signal phase of the centralized control processor. This adjustment ensures that multiple PCS converters can be accurately synchronized when running in parallel, avoiding circulating current and power imbalance problems caused by different carrier phases.

[0064] In some preferred embodiments, step 1 comprises:

[0065] The pulse width modulation module generates a synchronous output signal at the zero crossing position of the carrier count value according to the increase and decrease counting method. The value of the carrier counter (such as Epwm_TBCtr or Epwm_TBCtrN) determines the frequency and phase of the pulse by increasing and decreasing the count. Increase count: At the beginning of each cycle, the value of the carrier counter increases from 0 until it reaches the predetermined maximum value, at which time an event is triggered, such as the rising edge of the pulse or the generation of a synchronization signal. Decrease count: When the carrier counter reaches the maximum value, the counter will decrease according to the set conditions and restart counting, thereby completing a complete PWM cycle.

[0066] In some preferred embodiments, Figure 2 , Figure 3 As shown, the step 2 includes:

[0067] Through the auxiliary pulse width modulator (APWM) function of the centralized control module, the synchronization input enable is enabled, and the synchronization input source of the auxiliary pulse width modulator is selected as the synchronization output signal. Configure the enhanced capture module (eCAP_APWM module) of the centralized control processor, enable its auxiliary pulse width modulator (APWM) function, enable the synchronization input enable, and select the synchronization input source of APWM as the ePWM synchronization output signal Syscon in the above steps. On this basis, the phase synchronization of the carrier counter EcapCtr of the eCAP module and the carrier count value Epwm_TBCtr of the ePWM is realized.

[0068] In some preferred embodiments, such as Figure 4 and Figure 5 , step 3 includes:

[0069] Configure the capture module (eCAP capture module) of the independent core processor, enable its capture function, enable the synchronous input enable, and configure the capture of the rising or falling edge of the externally incoming carrier synchronization signal based on the absolute time in the capture mode, so as to realize the tracking of the relative time position of the synchronous incoming carrier synchronization signal.

[0070] In some preferred embodiments, step 3 includes: The independent core processor acquires the carrier synchronization signal through the first rising edge event (CEV1) in the carrier synchronization signal, the second falling edge event (CEV2) after the first rising edge event, and the third rising edge event (CEV3) after the second falling edge event.

[0071] In some preferred embodiments, step 3 further includes:

[0072] Obtain CAP1, CAP2, and CAP3 through the first rising edge event (CEV1) in the carrier synchronization signal, the second falling edge event (CEV2) after the first rising edge event, and the third rising edge event (CEV3) after the second falling edge event (CEV2);

[0073] Among them, CAP1 represents the time stay value between the carrier counter count of the core processor from zero to the captured first rising edge;

[0074] CAP2 represents the time stay value between the first rising edge and the second falling edge;

[0075] CAP3 represents the time stay value between the second falling edge and the third rising edge.

[0076] In some preferred embodiments, such as Figure 6 , to meet the effective and accurate tracking of the synchronization signal, each PCS module needs to perform fault tolerance, filtering, and carrier adjustment on the captured synchronization signal. Since the synchronization signal has a fixed frequency and duty cycle in the centralized control processor, therefore, during the capture process, the PCS module can screen the rationality of the signal based on the frequency and duty cycle information of the captured synchronization input signal, and enter the next step after processing effectively. The core processor to which the PCS belongs needs to be adjusted through the following steps, including judging the validity of CAP1:

[0077] After removing the values of CAP1 outside the upper and lower limit ranges, filtering is performed. After the filtering is completed, the confirmation flag flg1 is obtained. CAP1 records the timestamp from the first rising edge of the synchronization signal to the capture module counter. To ensure the validity of the signal, the value of CAP1 needs to be compared with the preset upper and lower limit ranges. If the value of CAP1 exceeds this range, it will be removed. After removing the invalid CAP1 values, the remaining CAP1 values will be filtered to remove some random noise or errors to ensure the accuracy of the synchronization signal. The filtered CAP1 values will be used to generate the flag flg1, which indicates whether the CAP1 values are valid;

[0078] The complete carrier synchronization signal period is formed by CAP1, CAP2, and CAP3. Through these timestamps (CAP1, CAP2, CAP3), the system can accurately capture the entire period of the carrier synchronization signal. This is a complete synchronization signal waveform, including the rising edge, falling edge of the signal, and the corresponding time intervals;

[0079] The frequency and duty cycle ratio of the carrier synchronization signal are obtained through the complete carrier synchronization signal period. Frequency: Through the timestamp data of CAP1, CAP2, and CAP3, the system can calculate the entire period of the carrier synchronization signal, and then calculate the frequency of the carrier synchronization signal according to the existing formula;

[0080] Duty cycle ratio: The duty cycle ratio represents the ratio of the duration of the high level of the carrier signal in one period to the total period. According to the time difference between CAP1 and CAP2 and the time of the complete period, the duty cycle ratio can be calculated;

[0081] The calculated frequency and duty cycle ratio of the carrier synchronization signal are compared with the preset frequency and duty cycle ratio of the carrier synchronization signal by the centralized control processor to obtain the frequency reference deviation and the duty cycle ratio reference deviation;

[0082] When it is judged that the frequency reference deviation and the duty cycle ratio reference deviation are within the preset range, the valid flag flg2 is obtained. The system will judge whether the reference deviations of the frequency and the duty cycle ratio meet the requirements according to the preset tolerance range (for example, ±0.5%). If the deviations of the frequency and the duty cycle ratio are both within the preset range, the flag flg2 is valid;

[0083] When flg1 and flg2 are obtained, it is determined that the CAP1 value is valid. When both flg1 and flg2 are valid, it means that the synchronization process of the entire carrier synchronization signal period is valid, and the CAP1 value can be considered valid, and the system can continue with the subsequent synchronization adjustment.

[0084] In some preferred embodiments, such as Figure 5 , the step 4 includes:

[0085] The captured rising and falling edge timestamp data is used to adjust the carrier counter in the core processor. The adjusted carrier counter value drives the drive pulse of the independent core processor, and at the position where the carrier count crosses zero, a synchronous output signal associated with the capture module is output;

[0086] During the process of adjusting the carrier counter in the core processor, the synchronous output signal in the independent core processor is updated synchronously, the absolute timestamp data of the corresponding rising and falling edges is obtained, and after signal processing, the state of Epwm_TBCtrN in the core processor is adjusted to the Epwm_TBCtrN1 state. Epwm_TBCtrN1 is used for the drive adjustment of the drive pulse of the PCS (the drive pulse adjustment of the PCS is based on the carrier of the ePWM module of each core board. The ePWM generates a square wave signal to act on the drive gate of the switch tube of the PCS such as IGBT or MOSFET to realize the switching action of the IGBT to realize the required voltage and current regulation conversion). At the same time, Epwm_TBCtrN1 outputs the synchronous signal SysconN associated with the eCAP inside the core processor at the position where the carrier count crosses zero;

[0087] During the process of adjusting Epwm_TBCtrN to Epwm_TBCtrN1, it will also synchronously affect SysconN to follow and adjust to the SysconN1 position. Through such dynamic continuous adjustment, the synchronization of the central control processor Epwm_TBCtr and the core processor Epwm_TBCtrN can be achieved. All other parallel PCS converters are based on this scheme to achieve single synchronous tracking of the central control processor, and finally achieve the carrier synchronization of all parallel PCS converters.

[0088] In some preferred embodiments, step 4 includes:

[0089] The carrier period value is adjusted by increasing or decreasing through a periodic compensation algorithm until the phase error of the carrier synchronization signals of all parallel independent core processors converges within a preset deviation range, where:

[0090] When the absolute time value of the valid CAP1 captured is less than half of the control carrier period (PRD) and greater than a specific deviation value (DefValue), the ePWM pulse width modulation period value in the core processor is reduced to adjust the carrier synchronization signal. For example, if the absolute time value of the valid CAP1 captured is less than half of the control carrier period (PRD / 2) but greater than a specific deviation value (DefValue), at this time, the captured timestamp is close to the starting part of the synchronization signal, which means that the phase of the carrier signal has a certain offset. To compensate for this offset, the value of the ePWM pulse width modulation period is reduced, that is, the period is decreased, which can be adjusted by reducing a fixed value Value1; the purpose of reducing the ePWM period value is to adjust the phase of the signal so that the synchronization signal reaches the target phase position in advance;

[0091] When the absolute time value of the valid CAP1 captured is greater than half of the control carrier period (PRD) and less than the carrier maximum threshold, the pulse width modulation period value is increased, such as increasing Value2. Among them, the maximum threshold is the difference between the pulse width modulation period ePWM and the specific deviation value DefValue. If the absolute time value of the valid CAP1 captured is greater than half of the control carrier period (PRD / 2) but less than the carrier maximum threshold (ePWM period - DefValue), at this time, the captured timestamp is already close to the second half of the synchronization signal period. Therefore, to adjust the phase, the value of the ePWM pulse width modulation period is increased, which can be achieved by increasing a fixed value Value2. The purpose of increasing the ePWM period value is to adjust the phase of the signal so that the synchronization signal reaches the target phase position with a delay;

[0092] When the time value of the captured CAP1 is close to zero, the pulse width modulation period value is restored to the standard set pulse width modulation period, thereby achieving carrier synchronization. When the time value of the captured CAP1 is close to zero, it means that the captured synchronization signal is already very close to the start or end of the period. The system needs to be restored to the standard set pulse width modulation period. At this time, the system will restore the ePWM pulse width modulation period value to its standard set value, that is, restore to the initial PWM period. Restoring the standard period means that no additional adjustment is required and the system has been synchronized to the predetermined signal period;

[0093] Through the above adjustment, the PCS module can achieve high-frequency stable carrier synchronization tracking of the centralized control processor as follows Figure 7 As shown in the actual test diagram, CH1 is the APWM synchronous output signal generated by the centralized control processor, CH2 is the ePWM synchronous signal of the centralized control processor, CH3 is the rising edge position signal of the core processor, and CH4 is the ePWM synchronous signal of the core processor

[0094] In some embodiments, the present application proposes a PCS energy storage converter carrier synchronization device, including the method described in the above embodiments, including:

[0095] A centralized control processor and multiple independent core processors;

[0096] The centralized control processor is electrically connected to the multiple independent core processors through links respectively;

[0097] Among them, the centralized control processor and the independent core processor respectively include a cross-switch module, a capture module, and a pulse width modulation module. The independent core processor also includes a converter;

[0098] The cross-switch module, the capture module, and the pulse width modulation module are electrically connected in sequence, and the converter is electrically connected to the pulse width modulation module of the independent core processing module.

[0099] As described above, it is only the specific implementation manner of the embodiments of the present invention, but the protection scope of the embodiments of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of the present invention should be covered by the protection scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be subject to the protection scope of the claims.

Claims

1. A PCS energy storage converter carrier synchronization method, characterized in that: Includes steps: Step 1, generating a synchronous output signal through the pulse width modulation module of the centralized control processor and the independent core processor through the zero crossing position of the carrier count value; Step 2: configuring the capture module of the centralized control module to synchronize its phase with the carrier count value of the pulse width modulation module, and generating a carrier synchronization signal for external output through a general input / output pin in the cross switch module; Step 3: In each independent core processor, the carrier synchronization signal is captured through the input / output pin, and the rising edge or falling edge of the carrier synchronization signal is time-stamped and captured by the capture module; Step 4: dynamically adjust the carrier count value of the pulse width modulation module of the independent core processor according to the captured timestamp data, so that the carrier synchronization signal phase of the core processor is synchronized with the carrier phase of the centralized control processor to achieve converter carrier synchronization.

2. The method according to claim 1, characterized in that The step 1 comprises: The pulse width modulation module generates a synchronous output signal at the zero-crossing position of the carrier count value in an up-down counting manner.

3. The method according to claim 1, characterized in that The step 2 comprises: Through the auxiliary pulse width modulator function of the centralized control module, the synchronization input enable is enabled and the synchronization input source of the auxiliary pulse width modulator is selected as the synchronization output signal.

4. The method according to claim 1, characterized in that: The step 3 comprises: Configure the capture module of the independent core processor, enable its capture function, enable the synchronization input enable, and capture the rising edge or falling edge of the external incoming carrier synchronization signal based on the absolute time configuration in the capture mode to achieve tracking of the relative time position of the synchronous incoming carrier synchronization signal.

5. The method according to claim 1, characterized in that: The step 3 includes: the independent core processor obtains the carrier synchronization signal through the first rising edge event in the carrier synchronization signal, the second falling edge event after the first rising edge event, and the third rising edge event after the second falling edge event.

6. The method according to claim 5, characterized in that Step 3 also includes: CAP1, CAP2, and CAP3 are obtained through the first rising edge event, the second falling edge event after the first rising edge event, and the third rising edge event after the second falling edge event in the carrier synchronization signal; Among them, CAP1 represents the time dwell value between the carrier counter count of the core processor from zero to the first rising edge captured; CAP2 represents the time dwell value from the first rising edge to the second falling edge; CAP3 represents the time dwell value from the second falling edge to the third rising edge.

7. The method according to claim 6, characterized in that Determine the effectiveness of CAP1, including: CAP1 is filtered after removing the values ​​outside the upper and lower limits, and a confirmation flag flg1 is obtained after the filtering is completed; CAP2 and CAP3 form a complete carrier synchronization signal cycle; The frequency and duty cycle of the carrier synchronization signal are obtained through a complete carrier synchronization signal cycle; Comparing the calculated frequency and duty cycle value of the carrier synchronization signal with the frequency and duty cycle value of the carrier synchronization signal preset by the centralized control processor to obtain a frequency reference deviation and a duty cycle value reference deviation; When the frequency reference deviation and the duty cycle value reference deviation are within a preset range, a valid flag flg2 is obtained; When flg1 and flg2 are obtained, the CAP1 value is determined to be valid.

8. The method according to claim 1, characterized in that: The step 4 comprises: The captured rising and falling edge timestamp data are used to adjust the carrier counter in the core processor, and the adjusted carrier count value drives the drive pulse of the independent core processor, and outputs the synchronous output signal associated with the capture module at the carrier count zero crossing position; During the adjustment of the carrier counter in the core processor, the synchronization output signal in the independent core processor is synchronously updated.

9. The method according to claim 1, characterized in that: Step 4 includes: The carrier period value is increased or decreased by a periodic compensation algorithm until the phase error of the carrier synchronization signal of all parallel independent core processors converges within a preset deviation range, where: When the absolute time value of the captured valid CAP1 is less than half of the control carrier cycle and greater than a specific deviation value, the pulse width modulation cycle value in the core processor is reduced to adjust the carrier synchronization signal; When the absolute time value of the captured valid CAP1 is greater than half of the control carrier cycle and less than the carrier maximum threshold, the pulse width modulation cycle value is increased, wherein the maximum threshold is the difference between the pulse width modulation cycle and the specific deviation value; When the captured time value of CAP1 is close to zero, the pulse width modulation period value is restored to the pulse width modulation period set by the standard, thereby achieving carrier synchronization.

10. A PCS energy storage converter carrier synchronization device, comprising the method according to any one of claims 1 to 9, characterized in that: include: Centralized control processor, multiple independent core processors; The centralized control processor is electrically connected to the multiple independent core processors through links; The centralized control processor and the independent core processor respectively include a cross switch module, a capture module, and a pulse width modulation module, and the independent core processor also includes a converter; The cross switch module, the capture module, and the pulse width modulation module are electrically connected in sequence, and the converter is electrically connected to the pulse width modulation module of the independent core processing module.

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