LLC four-path interleaved parallel circuit structure and control method

Abstract

The invention relates to a wide-power-range four-path interlaced LLC control method, which comprises the following steps of: sampling a circulating current, processing to obtain a loop output pointer, inquiring a switching frequency and a full-bridge phase shift according to the pointer, and generating four paths of complementary phase-shift PWM switching signals. Wherein the four paths of PWM shift signals act on four paths of switch tubes of the four paths of full bridges Q1, Q2, Q3 and Q4 respectively. According to the invention, the query mechanism is optimized according to the LLC gain change rate, so that the static adjustment of the LLC in the full range is simpler. According to the invention, the purpose of stabilizing the input current is achieved through series double-loop control and output current control, and the compatibility of a rectification circuit soft switch and a full-bridge change soft switch under different gains and loads of LLC working is achieved through a pointer query mode. The function of full-range four-path parallel current sharing is achieved through pointers and phase shifting. Through four branches and feedback, the converter works in the maximum demand state of the converter in real time.

Description

Technical Field

[0001] The present invention relates to the technical field of digital switching power supplies, and particularly to an LLC four-way interleaved parallel circuit structure and a control method therefor. Background Art

[0002] LLC resonant converters are widely used due to advantages such as high power density and easy implementation of soft switching. In high-power applications, a single LLC branch requires large inductors, capacitors, and transformers, while parallel LLC branches can solve this problem. Since the fuel cell stack has requirements for waveform quality, interleaved control can effectively reduce circuit ripple. The current four-way interleaved parallel LLC control methods have the following defects: First, if a single path fails during application, the other branches cannot operate; second, the voltage gain of the LLC resonant converter is relatively sensitive to the parameters of the resonant devices. In practical applications, due to factors such as manufacturing processes and natural environments, it is difficult to keep the parameters of the resonant devices of each module consistent, which in turn leads to differences in the output load currents of each parallel branch, seriously affecting the reliability and lifespan of the LLC resonant converter. In the prior art, current sharing is achieved through phase-shift control of the main LLC branch. If the main branch fails, all other branches will fail; there is also a control method for achieving current sharing in parallel LLC resonant converters through virtual impedance, which requires separate control of the four loops, increasing the load rate of the microcontroller. Although this method has good heavy-load regulation effects, there are significant differences under light loads. In new energy fuel cell power supplies, the input fuel cell stack range varies greatly, and the output voltage range is also relatively large. Therefore, a relatively wide gain range is required for the switching power supply. For the safety of the fuel cell stack, it is necessary to evenly control the current during each charging stage. Summary of the Invention

[0003] In view of this, a first aspect of the present invention provides a four-way LLC interleaved parallel circuit structure, aiming to reduce the ripple of the output current waveform and control the stability of the input current.

[0004] An LLC four-way interleaved parallel circuit structure includes: A parallel first LLC branch, a parallel second LLC branch, a parallel third LLC branch, a parallel fourth LLC branch, a sampling module, a DSP, and a drive module corresponding to each LCC branch; Among them, the parallel first LLC branch serves as the basic branch, the parallel second LLC branch leads the parallel first LLC branch by 45 degrees, the parallel third LLC branch leads the parallel second LLC branch by 45 degrees, and the parallel fourth LLC branch leads the parallel third LLC branch by 45 degrees; Among them, each LLC branch includes: an IGBT full-bridge conversion unit, an LLC resonant circuit, an isolation transformer circuit, and a diode full-bridge rectification unit connected in sequence; The IGBT full-bridge conversion unit includes a first switching tube, a second switching tube, a third switching tube, and a fourth switching tube; Among them, the source electrode of the first switching tube is connected to the drain electrode of the second switching tube, the source electrode of the third switching tube is connected to the drain electrode of the fourth switching tube, the drain electrodes of the first switching tube and the third switching tube are connected, and the source electrodes of the second switching tube and the fourth switching tube are connected; The first switching tube and the second switching tube form the lagging arm of the full bridge, and the third switching tube and the fourth switching tube form the leading arm of the full bridge; The sampling module is used to collect the four-way LLC output current; The DSP is set as the main loop control module, the current sharing loop control module, the look-up table and interleaving control module; The main loop control module obtains the output sampling current and obtains the look-up table pointer through the processing circuit; The current sharing loop control module obtains the output sampling current and obtains the four-way output current sharing compensation phase shift through the processing circuit; The look-up table and interleaving control module obtains the look-up table pointer and the four-way output current sharing compensation phase shift, and obtains the four-way drive signals through the processing circuit.

[0005] Specifically, the leading degree of the leading arm compared to the lagging arm of each LLC branch is used as the phase shift control, and the switching frequencies of the leading arm and the lagging arm are the same; The driving of the first switching tube and the second switching tube of the lagging arm of each LLC branch is complementary, and a first dead zone is set during this period. The first dead zone is effective at the rising edge and acts on the first switching tube and the second switching tube respectively; The driving of the third switching tube and the fourth switching tube of the leading arm of each LLC branch is complementary, and a first dead zone is set during this period. The first dead zone is effective at the rising edge and acts on the first switching tube and the second switching tube respectively; for the first switching tube of the lagging arm and the fourth switching tube of the leading arm of each LLC branch, the first switching tube conducts after the fourth switching tube, and the lag time is used as the loop adjustment phase; for the second switching tube of the lagging arm and the third switching tube of the leading arm, the second switching tube conducts after the fourth switching tube, and the lag time is used as the loop adjustment phase.

[0006] Specifically, the resonant circuit includes a resonant inductor, a resonant capacitor, and a parallel inductor; One end of the resonant inductor is connected to the midpoint of the lagging arm, and the other end is connected to the resonant capacitor; The other end of the resonant capacitor is connected to the parallel inductor and the primary side of the isolation transformer circuit. The parallel inductor and the other end of the isolation transformer circuit are connected to the midpoint of the leading arm; The primary side of the isolation transformer circuit is in parallel with the parallel inductor, and the two ends of the secondary side are respectively connected to the two midpoints of the diode rectifier bridge.

[0007] Specifically, the processing circuit of the main loop control module includes: a first adder, a second adder, a third adder, a first comparator, a second comparator, a first PI regulator, a second PT regulator, a third PI regulator, a first limiter, a second limiter, a first multiplier, a first divider, and a second divider; The first adder processes the first output sampled current and the second output sampled current and obtains a first adder output signal; The second adder processes the first adder output signal and the third output sampled current and obtains a second adder output signal; The third adder processes the second adder output signal and the fourth output sampled current and obtains the output total current; The first comparator processes the input reference current and the input sampled current and obtains a first error signal; The first PI regulator processes the first error signal and obtains an input current loop output; The first multiplier processes the input current loop output and the input voltage; The first divider processes the signal processed by the first multiplier and the output voltage and obtains an output current loop reference signal; The second divider processes the input voltage and the output voltage and obtains a gain signal; The second comparator processes the output current loop reference signal and the output total current and obtains a second error signal; The second PI regulator and the second limiter process the second error signal in sequence and obtain an output current loop output; The third PI regulator processes the gain signal and obtains a maximum pointer limit signal; The second limiter processes the maximum pointer limit signal and the output current loop output and obtains a look-up table pointer.

[0008] Specifically, the processing circuit of the current sharing loop control module includes: a fourth adder, a fifth adder, a sixth adder, a third divider, and a four-way output current sharing compensation phase shift circuit; The fourth adder processes the first output sampled current and the second output sampled current and obtains a fourth adder output signal; The fifth adder processes the fourth adder output signal and the third output sampled current and obtains a fifth adder output signal; The sixth adder processes the fifth adder output signal and the fourth output sampled current and obtains the output total current; The third divider processes the output total current to obtain a quarter current sharing signal; The four-way output current sharing compensation phase-shifting circuit includes a comparator, a PI regulator, and a limiter; the sampled currents of the four-way outputs and the one-quarter current sharing signal sequentially pass through the comparator, the PI regulator, and the limiter to obtain the phase-shifting signals for current sharing compensation of each output.

[0009] Specifically, the processing circuit of the look-up table and interleaving control module includes a look-up table module, a first PWM module, a second PWM module, a third PWM module, and a fourth PWM module; The look-up table module processes the look-up table pointer and obtains a period signal and a phase signal; The first PWM module processes the phase-shifting signal for current sharing compensation of the first branch output, the period signal, the phase signal, and the 0-degree signal to obtain the driving signals for the 4 switching tubes of the first branch; The second PWM module processes the phase-shifting signal for current sharing compensation of the second branch output, the period signal, the phase signal, and the 45-degree signal to obtain the driving signals for the 4 switching tubes of the second branch; The third PWM module processes the phase-shifting signal for current sharing compensation of the third branch output, the period signal, the phase signal, and the 90-degree signal to obtain the driving signals for the 4 switching tubes of the third branch; The fourth PWM module processes the phase-shifting signal for current sharing compensation of the fourth branch output, the period signal, the phase signal, and the 135-degree signal to obtain the driving signals for the 4 switching tubes of the fourth branch.

[0010] Specifically, the look-up table module queries a two-dimensional data table, and each element contains two elements, frequency and phase, which respectively control the driving frequency and the first phase shift.

[0011] In a second aspect, based on the circuit structure of the above solution, a control method for a wide-range four-way interleaved parallel LLC is proposed, including a main loop control, a current sharing loop control, and a look-up table and interleaving control: Among them, the main loop control includes the following steps: Process the sampled currents of the four-way outputs and obtain the total output current; Process the input reference current, the input sampled current, the input voltage, and the output voltage to obtain the reference signal of the output current loop; Process the input voltage and the output voltage to obtain a gain signal; Process the gain signal to obtain the maximum pointer limit signal; Process the reference signal of the output current loop and the total output current to obtain the output of the output current loop; Process the maximum pointer limit signal and the output of the output current loop to obtain the look-up table pointer; Among them, the current sharing loop control includes the following steps: Process the sampled currents of the four-way outputs and obtain the total output current; Process the output total current and obtain a quarter current sharing signal; Process the four-way output sampled current and the quarter current sharing signal and obtain the current sharing compensation phase shift signals for each output; Among them, the look-up table and interleaved control include the following steps: Process the look-up table pointer and obtain a periodic signal and a phase signal; Process the current sharing compensation phase shift signals for each output, the periodic signal, the phase signal, and the interleaved signal and obtain the drive signals for 4 switching tubes for each output; The interleaved control signals are: 0 degrees, 45 degrees, 90 degrees, 135 degrees.

[0012] On the basis of the above solution, the method for generating the maximum pointer limit signal is as follows: S1: Obtain the maximum gain and the minimum gain, and divide the gain into several segments according to a linear rule; S2: For each gain in S1, select the operating point at its maximum allowable power; S3: Look up the pointer in the look-up table for the point obtained in S2. If the operating point exceeds the look-up table range, expand the table according to the look-up table rule, and map the operating point obtained in S2 to the re-expanded table as a pointer; S4: Linearly fit the pointer obtained in S3 to obtain a linear function of the maximum pointer limit and the gain; S5: Adjust the gain parameter according to the fitted linear function to finally obtain the maximum pointer limit signal for the loop output.

[0013] On the basis of the above solution, the operating switching frequency fw of the switching tube satisfies that the voltage gain Gw at this frequency is greater than the actual required voltage gain Gr. The relationship between the voltage gain Gw and the operating switching frequency fw is: ; Among them: ; K is the ratio of the resonant inductor Lr to the exciting inductor Lm, fn is the ratio of the operating switching frequency fw to the resonant frequency fr, Zo is the equivalent impedance, Re is the equivalent resistance of the transformer secondary load to the primary side, Cr is the resonant capacitor, m is the turns ratio of the transformer primary and secondary sides, Ro is the actual resistance value of the transformer secondary load, and Q is the quality factor; The actual required voltage gain Gr is: .

[0014] The beneficial effects of the present invention: The present invention adopts a four-way LLC parallel connection to achieve high-power control, reduces the size of the magnetic components, increases the power density, and at the same time reduces the current ripple; the parallel interleaved loop method adopted by the present invention effectively balances the dynamic and static regulation of the LLC; the present invention effectively balances the working currents of each branch through current sharing control. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention has the following drawings: Figure 1 Overall structure diagram; Figure 2 Main power topology diagram; Figure 3 Main loop control circuit flowchart; Figure 4 Current sharing loop control flowchart; Figure 5 Look-up table and interleaved control flowchart; Figure 6 Single-way LLC four-way drive waveform diagram; Figure 7 Interleaved drive schematic diagram; Figure 8 Linear function of Psr_Max and gain Gain. SPECIFIC EMBODIMENTS

[0016] To make the objectives, advantages, and features of the present invention more obvious, the present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0017] As Figure 1As shown in the figure, an LLC four-way interleaved parallel circuit structure includes a DSP, multiple PI regulators, multiple PWM control units, and a parallel full-bridge LLC resonant converter composed of multiple converter LLC branches connected in parallel. The primary side of each LLC branch includes switching tubes Sn1, Sn2, Sn3, Sn4 (n = 1, 2, 3, 4), resonant capacitors Crn (n = 1, 2, 3, 4), resonant inductors Lrn (n = 1, 2, 3, 4), and exciting inductors Lmn (n = 1, 2, 3, 4). The resonant capacitors Crn (n = 1, 2, 3, 4), resonant inductors Lrn, and exciting inductors Lmn together form a resonant cavity. The switching tubes Sn1, Sn2, Sn3, Sn4 (n = 1, 2, 3, 4) form a full bridge. A diode and a capacitor are connected in parallel across each switching tube. One end of the resonant inductor Lrn is connected in series with one end of the resonant capacitor Crn. After series connection, the other end of the resonant inductor Lrn is connected to the midpoint An of the left bridge arm of the primary-side full bridge. After series connection, the other end of the resonant capacitor Crn is connected to one end of the primary winding of the transformer Tn (n = 1, 2, 3, 4). The other end of the primary winding of the transformer Tn is connected to the midpoint Bn of the right bridge arm of the full bridge (n = 1, 2, 3, 4). The exciting inductor Lmn is connected across the two ends of the primary winding of the transformer Tn. The secondary side of the converter module includes diodes Dn1, Dn2, Dn3, Dn4 (n = 1, 2, 3, 4). The diodes Dn1, Dn2, Dn3, Dn4 form a diode rectifier bridge. One end of the secondary winding of the transformer Tn is connected to the midpoint Cn of the left bridge arm of the diode rectifier bridge (n = 1, 2, 3, 4), and the other end is connected to the midpoint Dn of the right bridge arm of the diode rectifier bridge (n = 1, 2, 3, 4). A filter capacitor Con (n = 1, 2, 3, 4) is connected in parallel across the output terminals of the diode rectifier bridge. The load resistor RLoad is connected in parallel with the filter capacitor Con.

[0018] Among them, the PI regulator is composed of a proportional link and an integral link, and its mathematical expression is P + I / S. Where P is the proportional coefficient, I is the integral coefficient, and S is the integrator. The error signal forms a control quantity through a linear combination of proportion and integration. The outer loop uses this control quantity and the given value to control the controlled object, and the inner loop uses this control quantity to query and obtain a control quantity to control the controlled object; the control quantity is the frequency of the drive signals of the switching tubes Sn1, Sn2, Sn3, Sn4 (n = 1, 2, 3, 4) and the phase of the switching tubes Sn3 and Sn4. The controlled object is controlled by changing the frequency of the switching tubes Sn1, Sn2, Sn3, Sn4 and the phase of the switching tubes Sn3 and Sn4.

[0019] The frequency Fw and the phase Pwcn (n = 1, 2, 3, 4) are sent into the PWM control unit, and the PWM control unit generates four drive signals gsn1, gsn3 (n = 1, 2, 3, 4) with a switching period of 1 / Fw according to the working switching frequency Fw.

[0020] Preferably, the duty cycles of the driving signals gsn1 and gsn3 are both set to 0.5 in the PWM control unit, and the phase shift of gsn3 is (n - 1) 45 + Pwcn (n = 1, 2, 3, 4), and then a driving signal gsn4 complementary to the driving signal gsn2 is generated through the complementary module of the PWM control unit, so as to achieve a constant steady current and a loop control with current sharing for a four-way interleaved 180+ parallel LLC.

[0021] As Figure 2 shown, in the main power topology diagram: gs11, gs12, gs13, gs14 are the driving signals of the first branch, where gs11 and gs12 are the driving signals of the lagging leg, and gs11 and gs12 are complementary outputs; where gs13 and gs14 are the driving signals of the leading leg, and gs13 and gs14 are complementary outputs; when the LLC branch works, gs11 and gs14 are output simultaneously or with a phase shift, and gs12 and gs13 are output simultaneously or with a phase shift. gs21, gs22, gs23, gs24 are the driving signals of the second branch, where gs21 and gs22 are the driving signals of the lagging leg, and gs21 and gs22 are complementary outputs; where gs23 and gs24 are the driving signals of the leading leg, and gs23 and gs24 are complementary outputs; when the LLC branch works, gs21 and gs24 are output simultaneously or with a phase shift, and gs22 and gs23 are output simultaneously or with a phase shift. gs31, gs32, gs33, gs34 are the driving signals of the third branch, where gs31 and gs32 are the driving signals of the lagging leg, and gs31 and gs32 are complementary outputs; where gs33 and gs34 are the driving signals of the leading leg, and gs33 and gs34 are complementary outputs; when the LLC branch works, gs31 and gs34 are output simultaneously or with a phase shift, and gs32 and gs33 are output simultaneously or with a phase shift. gs41, gs42, gs43, gs44 are the driving signals of the third branch, where gs41 and gs42 are the driving signals of the lagging leg, and gs41 and gs42 are complementary outputs; where gs43 and gs44 are the driving signals of the leading leg, and gs43 and gs44 are complementary outputs; when the LLC branch works, gs41 and gs44 are output simultaneously or with a phase shift, and gs42 and gs43 are output simultaneously or with a phase shift.

[0022] As Figure 3As shown in the main loop control circuit flowchart: Iref is the voltage reference, Iin is the input current sampling, and PIin is the PI processing module for the current loop. Error is the input current loop error signal, and Error = Iref – Iin. Error undergoes PI processing by PIIn to obtain the Lout signal, and Lout is the output signal of the current loop. Lout passes through boundary limiting to obtain L1out. L1out is multiplied by Vin through the multiplier MULT1 and then divided by the output voltage Vout through the divider DIVD1 to obtain Iref_out, that is, Iref_out = L1out Vin / Vout; Iref_out serves as the reference signal for the output current loop.

[0023] Iout is the total output current, which is obtained by summing the four branch currents through the adders SUMP1, SUMP2, and SUMP3. The difference between Iref_out and Iout is taken by the comparator COMPout to obtain the output current loop error signal Error2. Error2 undergoes PI processing by the PLout module to obtain L2out. L2out passes through boundary limiting to obtain L3out. L3out passes through Psr_Max limiting to obtain the output query pointer Psr.

[0024] Psr_Max is the gain limiting pointer, which is obtained by the PI processing of the gain signal Gain through the G2Psr module. The gain is obtained by dividing the output voltage by the input voltage through the divider DIVD2, that is, Gain = Vo / Vin.

[0025] As Figure 4As shown in the current sharing loop control flow chart: Is1, Is2, Is3, and Is4 are the output current sampling signals of the four-branch LLC respectively. The sum of the four currents and the constant 4Const pass through adders SUMP4, SUMP4, SUMP6, and multiplier DIDV3 to obtain the average signal Varage as the reference input of the current sharing loop. Phase_Dlta1, Phase_Dlta2, Phase_Dlta3, and Phase_Dlta4 are the outputs of the current sharing loop. They are respectively compared by comparators COM1, COM2, COM3, and COM4 with Is1, Is2, Is3, and Is4, and then adjusted and output through their respective PI modules PI1, PI2, PI3, and PI4, and obtained after boundary limitation. Phase_Dlta1, Phase_Dlta2, Phase_Dlta3, and Phase_Dlta4 are respectively the compensation phases of the phase Phase obtained by looking up the table with pointers, that is, Phase_Dlta1, Phase_Dlta2, Phase_Dlta3, and Phase_Dlta4 are added to Phase respectively as the phase inputs of PWM1, PWM2, PWM3, and PWM4. Phase and PWM1, PWM2, PWM3, and PWM4 are the phase signals and PWM modulation modules of the look-up table and interleaved flow chart respectively.

[0026] As Figure 5 As shown in the look-up table and interleaved flow chart: The query pointer Psr queries the two-dimensional data table PPHBOX to obtain the basic period period and phase Phase of the PWM modulation. The loop compensation signals Phase_Dlta1, Phase_Dlta2, Phase_Dlta3, and Phase_Dlta4 obtained by current sharing are added to Phase respectively to obtain Phase1, Phase2, Phase3, and Phase4. Phase1, Phase2, Phase3, and Phase4 are respectively used as the modulation inputs of PWM1, PWM2, PWM3, and PWM4, and act together with Period and the interleaved phases of 0 degrees, 45 degrees, 90 degrees, and 135 degrees of each PWM modulation module to obtain the drive signals of the four branches. Period determines the period of all drives, Phase1, Phase2, Phase3, and Phase4 respectively determine the phase time between the leading wall and the lagging wall of each branch, and the interleaved input determines the interleaved phase between each branch.

[0027] As Figure 6As shown in the single-channel LLC four-channel drive waveform diagram: Phase_Deltan represents Phase_Delta1, Phase_Delta2, Phase_Delta3, and Phase_Delta4 respectively, that is, n = 1, 2, 3, 4. Similarly, n in gsn1, gsn2, gsn3, and gsn4 is also 1, 2, 3, and 4 respectively. When n = 1, it is the drive of the first branch LLC; when n = 2, it is the drive of the second branch LLC; when n = 3, it is the drive of the third branch LLC; when n = 4, it is the drive of the fourth branch LLC. For a single-channel LLC, due to the influence of the phase Phase between its two bridge arms, there is a leading and lagging relationship. For the nth (n = 1, 2, 3, 4) LLC, the upper and lower transistors of its leading wall are driven by gns1 and gns2 respectively, and the upper and lower transistors of its lagging wall are driven by gns3 and gns4 respectively. When the LLC works, the drive signals of gns1 and gns4 are phase-shifted, the drive signals of gns2 and gns3 are phase-shifted, the drive signals of gns1 and gns2 are complementary, and the drive signals of gns3 and gns4 are complementary, thus realizing the adjustment of LLC look-up table frequency modulation phase shift.

[0028] As Figure 7 shown in the interleaved drive schematic diagram: The waveform frequencies of the nth (n = 1, 2, 3, 4) switching transistors of the first branch, the second branch, the third branch, and the fourth branch are the same, the duty cycles are the same, and they are interleaved with each other by 45 degrees, thus achieving the purpose of interleaved parallel connection.

[0029] Furthermore, the rules for making the Psr look-up table (PPHBOX) are as follows: When the input is 300V to 600V and the output is 200V to 1000V, the maximum gain Gmax = 1000V / 300V, and the minimum gain gmin = 200V / 600V The planning goal of the gain simulation range: Input voltage Output voltage 600V 200 300V 200 300 1000 According to the maximum allowable working power at the working point, find the working point and form an initial simple table: The first step: Find the working point of the LLC corresponding to an input of 600V and an output of 200V. This point includes the period and phase; The second step: Find the working points between an input of 600V and a reduced input of 300V at an output of 200V. All points include the period and phase. The input changes linearly from 600V to 300V, and an additional query working point is added when encountering special situations; The third step: Find the working points between an output of 200V and an output of 1000V at an input of 300V. All points include the period and phase. The output changes linearly from 200V to 1000V, and an additional query working point is added when encountering special situations; Finally, N working points are obtained according to the above plan, forming the following simple table

[0030] Step 4: Expand it into the final two-dimensional table according to the rules: The expansion examples are as follows: Expansion from working point 0 to working point 1: According to the characteristic of LLC, P0 <= P1. To maintain gain consistency, the simple table ensures that PH0 >= PH1. There are three cases for table expansion: 1) P0 = P1, PH0 > PH1 2) P0 < P1, PH0 => PH1 3) P0 < P1, PH0 > PH1 Expansion in the first case:

[0031] Expansion in the second case:

[0032] Expansion in the third case

[0033] In another embodiment, a control method for a wide-range four-way interleaved parallel LLC is proposed based on the above circuit structure, including main loop control, current sharing loop control, look-up table and interleaved control: Among them, the main loop control includes the following steps: Process the four-way output sampled current and obtain the total output current; Process the input reference current, input sampled current, input voltage, output voltage and obtain the output current loop reference signal; Process the input voltage and the output voltage and obtain the gain signal; Process the gain signal and obtain the maximum pointer limit signal; Process the output current loop reference signal, the total output current and obtain the output of the output current loop; Process the maximum pointer limit signal and the output of the output current loop and obtain the look-up table pointer; Among them, the current sharing loop control includes the following steps: Process the four-way output sampled current and obtain the total output current; Process the total output current and obtain the one-quarter current sharing signal; Process the four-way output sampled current and the one-quarter current sharing signal and obtain the phase shift compensation signal for current sharing of each output; Among them, the look-up table and interleaved control include the following steps: Process the look-up table pointer and obtain the periodic signal and the phase signal; Process the phase-shifted current-sharing signals, periodic signals, phase signals, and interleaving signals of each output, and obtain the driving signals of four switching tubes for each path; The interleaving control signals are: 0 degrees, 45 degrees, 90 degrees, and 135 degrees.

[0034] Furthermore, the rule for converting the G2Psr gain into the maximum pointer is as follows: The first step: the maximum gain Gmax and the minimum gain gmin. Divide the gain from gmin to gmax into N segments according to the linear rule; The second step: for each gain in the first step, select the operating point at 120% of the power that allows the maximum allowable power; The third step: look up the pointer of the point obtained in the second step in the PPHBOX table. If the operating point exceeds the range of PPHBOX, expand the PPHBOX table according to the rules of PPHBOX, and map the operating point obtained in the second step to the re-expanded PPHBOX table; The fourth step: linearly fit the pointer obtained in the third step to obtain the linear function of Psr_Max and the gain Gain; (as Figure 8 shown) The fifth step: adjust the G2Psr parameter according to the fitted linear function to finally obtain the maximum pointer limit Psr_Max of the loop output.

[0035] Furthermore, the operating switching frequency fw of the switching tube satisfies that the voltage gain Gw at this frequency is greater than the actually required voltage gain Gr. The relationship between the voltage gain Gw and the operating switching frequency fw is: ; Where: ; K is the ratio of the resonant inductor Lr to the exciting inductor Lm, fn is the ratio of the operating switching frequency fw to the resonant frequency fr, Zo is the equivalent impedance, Re is the equivalent resistance of the transformer secondary load to the primary side, Cr is the resonant capacitor, m is the turns ratio of the transformer primary and secondary sides, Ro is the actual resistance value of the transformer secondary load, and Q is the quality factor; The actually required voltage gain Gr is: .

[0036] It should be noted that any process or method description in the embodiments can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a specific logical function or process. Moreover, the scope of the preferred embodiments of the present invention includes additional implementations, where functions can be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed. This should be understood by those skilled in the technical field to which the embodiments of the present invention pertain.

[0037] It should be noted that for the logic and / or steps in the embodiments, for example, which can be considered as a defined sequence list of executable instructions for implementing logical functions, can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing if necessary, and then stored in a computer memory.

[0038] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits with suitable combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0039] Those of ordinary skill in the art can understand that all or part of the steps to implement the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0040] In addition, each functional module in the embodiments of the present invention can be integrated into a processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules. When the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.

[0041] The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disc, etc.

[0042] The above embodiments have described the technical solutions of the present invention in detail. Obviously, the present invention is not limited to the described embodiments. Based on the embodiments of the present invention, those familiar with the technical field can also make various changes accordingly, but any changes equivalent or similar to the present invention fall within the scope of protection of the present invention.

[0043] The content not described in detail in this specification belongs to the well-known prior art of those skilled in the art.

Claims

1. An LLC four-way staggered parallel circuit structure, characterized in that: include: A first LLC branch in parallel, a second LLC branch in parallel, a third LLC branch in parallel, a fourth LLC branch in parallel, a sampling module, a DSP, and a driving module corresponding to each LCC branch; The first parallel LLC branch is used as a basic branch, the second parallel LLC branch leads the first parallel LLC branch by 45 degrees, the third parallel LLC branch leads the second parallel LLC branch by 45 degrees, and the fourth parallel LLC branch leads the third parallel LLC branch by 45 degrees; Each LLC branch includes: an IGBT full-bridge conversion unit, an LLC resonant circuit, an isolation transformer circuit, and a diode full-bridge rectifier unit connected in sequence; The IGBT full-bridge conversion unit includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube; The source of the first switch tube is connected to the drain of the second switch tube, the source of the third switch tube is connected to the drain of the fourth switch tube, the drain of the first switch tube is connected to the drain of the third switch tube, and the source of the second switch tube is connected to the source of the fourth switch tube; The first switch tube and the second switch tube form a lagging arm of the full bridge, and the third switch tube and the fourth switch tube form a leading arm of the full bridge; The sampling module is used to collect four-channel LLC output current; The DSP is configured as a main loop control module, a current sharing loop control module, a table lookup and interleaving control module; The main loop control module obtains the output sampling current and obtains the table lookup pointer through the processing circuit; The current sharing loop control module obtains the output sampling current and obtains the four-way output current sharing compensation phase shift through the processing circuit; The table lookup and interleaving control module obtains the table lookup pointer and the four-way output current sharing compensation phase shift, and obtains four-way driving signals through a processing circuit.

2. The circuit structure according to claim 1, characterized in that: The degree of advance of the leading arm of each LLC branch over the lagging arm is used as phase shift control, and the switching frequency of the leading arm and the lagging arm is the same; The driving of the first switch tube and the second switch tube of each LLC branch lagging arm is complementary, during which a first dead zone is set, and the rising edge of the first dead zone is effective, acting on the first switch tube and the second switch tube respectively; The third switch tube and the fourth switch tube of the leading arm of each LLC branch are driven complementary, and a first dead zone is set during the period. The rising edge of the first dead zone is effective, and acts on the first switch tube and the second switch tube respectively; the first switch tube of the lagging arm and the fourth switch tube of the leading arm of each LLC branch, the first switch tube lags behind the fourth switch tube when turned on, and the lag time is used as the loop adjustment phase; the second switch tube of the lagging arm and the third switch tube of the leading arm, the second switch tube lags behind the fourth switch tube when turned on, and the lag time is used as the loop adjustment phase.

3. The circuit structure according to claim 1, characterized in that: The resonant circuit comprises a resonant inductor, a resonant capacitor, and a parallel inductor; One end of the resonant inductor is connected to the midpoint of the lagging arm, and the other end is connected to the resonant capacitor; The other end of the resonant capacitor is connected to the primary side of the parallel inductor and the isolation transformer circuit, and the other end of the parallel inductor and the isolation transformer circuit is connected to the midpoint of the super forearm; The primary side of the isolation transformer circuit is connected in parallel with the parallel inductor, and the two ends of the secondary side are respectively connected to the two midpoints of the diode rectifier bridge.

4. The circuit structure according to claim 1, characterized in that: The processing circuit of the main loop control module includes: a first adder, a second adder, a third adder, a first comparator, a second comparator, a first PI regulator, a second PT regulator, a third PI regulator, a first limiter, a second limiter, a first multiplier, a first divider, and a second divider; The first adder processes the first output sampling current and the second output sampling current to obtain a first adder output signal; The second adder processes the first adder output signal and the third output sampling current to obtain a second adder output signal; The third adder processes the output signal of the second adder and the fourth output sampling current to obtain the output total current; The first comparator processes the input reference current and the input sampling current and obtains a first error signal; The first PI regulator processes the first error signal and obtains an input current loop output; The first multiplier processes the input current loop output and the input voltage; The first divider processes the signal processed by the first multiplier and the output voltage and obtains an output current loop reference signal; The second divider processes the input voltage and the output voltage and obtains a gain signal; The second comparator processes the output current loop reference signal and the output total current and obtains a second error signal; The second PI regulator and the second limiter sequentially process the second error signal and obtain an output current loop output; The third PI regulator processes the gain signal and obtains a maximum pointer limit signal; The second limiter processes the maximum pointer limit signal and the output current loop output and obtains a table lookup pointer.

5. The circuit structure according to claim 1, characterized in that: The processing circuit of the current sharing loop control module includes: a fourth adder, a fifth adder, a sixth adder, a third divider, and a four-way output current sharing compensation phase shift circuit; The fourth adder processes the first output sampling current and the second output sampling current to obtain a fourth adder output signal; The fifth adder processes the fourth adder output signal and the third output sampling current to obtain a fifth adder output signal; The sixth adder processes the fifth adder output signal and the fourth output sampling current to obtain the output total current; The third divider processes the output total current to obtain a quarter current sharing signal; The four-way output current sharing compensation phase shift circuit includes a comparator, a PI regulator, and a limiter; the four-way output sampling current and a quarter of the current sharing signal are processed by the comparator, the PI regulator, and the limiter in turn to obtain the output current sharing compensation phase shift signal of each way.

6. The circuit structure according to claim 1, characterized in that: The processing circuit of the table lookup and interleaving control module includes a table lookup module, a first PWM module, a second PWM module, a third PWM module, and a fourth PWM module; The table lookup module processes the table lookup pointer and obtains a period signal and a phase signal; The first PWM module processes the first branch output current sharing compensation phase shift signal, period signal, phase signal, and 0 degree signal and obtains four switch tube drive signals of the first branch; The second PWM module processes the second branch output current sharing compensation phase shift signal, period signal, phase signal, 45 degree signal and obtains the second branch four switch tube drive signals; The third PWM module processes the output current sharing compensation phase shift signal, period signal, phase signal, and 90-degree signal of the third branch and obtains four switch tube drive signals of the third branch; The fourth PWM module processes the fourth branch output current sharing compensation phase shift signal, period signal, phase signal, and 135-degree signal and obtains four switch tube drive signals of the fourth branch.

7. The circuit structure according to claim 6, characterized in that: The table lookup module queries a two-dimensional data table, each element of which includes two elements, frequency and phase, which respectively control the driving frequency and the first phase shift.

8. A control method for a wide range four-way staggered parallel LLC, characterized in that: Based on the circuit structure as described in any one of claims 1 to 7, including main loop control, current sharing loop control, table lookup and interleaving control: Wherein, the main loop control comprises the following steps: Process the four-way output sampling current and obtain the total output current; Processing input reference current, input sampling current, input voltage, output voltage and obtaining output current loop reference signal; Processing input voltage and output voltage and obtaining gain signal; Processing the gain signal and obtaining a maximum pointer limit signal; Processing the output current loop reference signal, the output total current and obtaining the output current loop output; Processing the maximum pointer limit signal and the output current loop output and obtaining the table lookup pointer; The current sharing loop control includes the following steps: Process the four-way output sampling current and obtain the total output current; Process the total output current and obtain a quarter current sharing signal; Process the four-way output sampling current and one-quarter current sharing signal and obtain the output current sharing compensation phase shift signal of each way; The table lookup and interleaving control comprises the following steps: Process the table lookup pointer and obtain the period signal and phase signal; Process the output current sharing compensation phase shift signal, period signal, phase signal, interleaved signal of each channel and obtain the driving signal of 4 switch tubes of each channel; The staggered control signals are: 0 degrees, 45 degrees, 90 degrees, and 135 degrees.

9. The control method according to claim 8, characterized in that: The method for generating the maximum pointer limit signal is: S1: Get the maximum gain and the minimum gain, and divide the gain into several segments according to the linear rule; S2: For each gain of S1, select the operating point at the maximum allowable power; S3: Find the pointer of the point obtained by S2 in the lookup table. If the working point exceeds the lookup range, expand the table according to the lookup rule, and make the working point obtained by S2 a pointer corresponding to the newly expanded table; S4: linearly fit the pointer obtained in S3 to obtain a linear function of maximum pointer limit and gain; S5: Adjust the gain parameter according to the fitted linear function, and finally obtain the loop output maximum pointer limit signal.

10. The control method according to claim 8, characterized in that: The working switching frequency fw of the switch tube satisfies that the voltage gain Gw at this frequency is greater than the actually required voltage gain Gr. The relationship between the voltage gain Gw and the working switching frequency fw is: ； in: ； K is the ratio of the resonant inductance Lr to the excitation inductance Lm, fn is the ratio of the working switching frequency fw to the resonant frequency fr, Zo is the equivalent impedance, Re is the equivalent resistance of the transformer secondary load to the primary side, Cr is the resonant capacitance, m is the transformer primary-to-secondary ratio, Ro is the actual resistance value of the transformer secondary load, and Q is the quality factor; The actual required voltage gain Gr is: 。

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