Doherty amplifier circuit and semiconductor device

Abstract

The invention provides a Doherty amplifier circuit and a semiconductor device. A Doherty amplifier circuit is provided with: a distributor that distributes an input signal that is input into a first signal and a second signal; the main amplifier is used for amplifying the first signal and outputting the amplified signal as a fourth signal; the first peak amplifier is used for amplifying the second signal and outputting the amplified signal as a fifth signal; a synthesizer which synthesizes the fourth signal and the fifth signal and outputs the synthesized signal as an output signal to an output terminal; the first matching circuit is connected between the distributor and the main amplifier; and a second matching circuit connected between the distributor and the first peak amplifier, the absolute value of the return loss when viewed from the distributor to the second matching circuit being greater than the absolute value of the return loss when viewed from the distributor to the first matching circuit in the operating band.

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit and a semiconductor device. Background Art

[0002] There is known an N-way (N ≥ 3) Doherty amplifier circuit that uses a main amplifier and two or more peak amplifiers (for example, Patent Document 1 and Patent Document 2).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: U.S. Patent No. 8,022,760 Specification

[0006] Patent Document 2: U.S. Patent No. 10,601,375 Specification

[0007] However, in a Doherty amplifier circuit, it is required to improve efficiency and suppress distortion. Summary of the Invention

[0008] The present disclosure has been made in view of the above problems, and an object thereof is to improve characteristics.

[0009] One embodiment of the present disclosure is a Doherty amplifier circuit including: a divider that divides an input signal input thereto into a first signal and a second signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a combiner that combines the fourth signal and the fifth signal and outputs the combined signal as an output signal to an output terminal; a first matching circuit connected between the divider and the main amplifier; and a second matching circuit connected between the divider and the first peak amplifier, wherein in a working frequency band, an absolute value of return loss when looking at the second matching circuit from the divider is greater than an absolute value of return loss when looking at the first matching circuit from the divider.

[0010] One embodiment of the present disclosure is a semiconductor device, which is a semiconductor device for a Doherty amplifier circuit, and includes: a package having a base, a first input lead, and a second input lead; a first semiconductor chip mounted on the base, the first semiconductor chip including a main amplifier that amplifies a first signal obtained by distributing an input signal; a second semiconductor chip mounted on the base, the second semiconductor chip including a first peak amplifier that amplifies a second signal obtained by distributing the input signal; a first capacitor mounted on the base, a first end of the first capacitor being electrically connected to the base; a second capacitor mounted on the base, a first end of the second capacitor being electrically connected to the base; a third capacitor mounted on the base, a first end of the third capacitor being electrically connected to the base; a first inductor, a first end of the first inductor being electrically connected to the first input lead, and a second end of the first inductor being electrically connected to a second end of the first capacitor; a second inductor, a first end of the second inductor being electrically connected to the second end of the first capacitor, and a second end of the second inductor being electrically connected to a second end of the second capacitor; a third inductor, a first end of the third inductor being electrically connected to the second end of the second capacitor, and a second end of the third inductor being electrically connected to an input pad of the first semiconductor chip; a fourth inductor, a first end of the fourth inductor being electrically connected to the second input lead, and a second end of the fourth inductor being electrically connected to a second end of the third capacitor; and a fifth inductor, a first end of the fifth inductor being electrically connected to the second end of the third capacitor, and a second end of the fifth inductor being electrically connected to an input pad of the second semiconductor chip.

[0011] Advantages of the Invention

[0012] According to the present disclosure, characteristics can be improved. Description of the Drawings

[0013] Figure 1 It is a block diagram of the Doherty amplifier circuit of Embodiment 1.

[0014] Figure 2 It is a circuit diagram of the second-stage matching circuit in Embodiment 1.

[0015] Figure 3 It is a circuit diagram of the first-stage matching circuit in Embodiment 1.

[0016] Figure 4 It is a Smith chart showing impedance matching of the fundamental wave using the first-stage matching circuit in Embodiment 1.

[0017] Figure 5 It is a Smith chart of the second harmonic using the first-stage matching circuit in Embodiment 1.

[0018] Figure 6 It is a diagram showing the efficiency with respect to the phase of the impedance Z6(2f) when looking forward from the gate of the transistor to the previous stage.

[0019] Figure 7 It is a Smith chart of the second harmonic of the two-stage matching circuit in Example 1.

[0020] Figure 8 It is a Smith chart showing the impedance matching of the fundamental wave using the two-stage matching circuit in Example 1.

[0021] Figure 9 It is a diagram showing S11 with respect to frequency in the simulation.

[0022] Figure 10 It is a diagram showing S21 with respect to frequency in the simulation.

[0023] Figure 11 It is a circuit diagram of a part of the Doherty amplifier circuit of Comparative Example 1.

[0024] Figure 12 It is a circuit diagram of a part of the Doherty amplifier circuit of Comparative Example 2.

[0025] Figure 13 It is a circuit diagram of a part of the Doherty amplifier circuit of Example 1.

[0026] Figure 14 It is a circuit diagram of a part of the Doherty amplifier circuit of Example 2.

[0027] Figure 15 It is a diagram showing the gain with respect to the input power in Comparative Example 1, Comparative Example 2, Example 1, and Example 2.

[0028] Figure 16 It is a top view of the semiconductor device of Example 3.

[0029] Figure 17 It is a top view of the semiconductor device of Modification 1 of Example 3.

[0030] Description of reference numerals:

[0031] 10: Main amplifier;

[0032] 12 (first peak amplifier), 14 (second peak amplifier): Peak amplifiers;

[0033] 16: Divider;

[0034] 18: Combiner;

[0035] 30 (first matching circuit), 31 (second matching circuit), 32 (third matching circuit), 33, 34, 35: Matching circuits;

[0036] 36, 37, 38, 39: Bias circuits;

[0037] 40: Package;

[0038] 41: Base;

[0039] 42: Housing;

[0040] 44a (first input lead), 44b (second input lead), 44c, 45a, 45b, 45c: Leads;

[0041] 50a (first semiconductor chip), 50b (second semiconductor chip), 50c: Semiconductor chips;

[0042] 51: Semiconductor substrate;

[0043] 52, 53: Bond pads;

[0044] 55a, 55b, 55c: Capacitive components;

[0045] 56: Dielectric substrate;

[0046] 57: Electrode;

[0047] 61, 62, 63, 64, 65, 66: Bonding wires;

[0048] 100, 102, 104, 110, 112: Doherty amplifier circuits;

[0049] 106, 108: Semiconductor devices;

[0050] L1 (first inductor), L2 (second inductor), L3 (third inductor), L4 (fourth inductor), L5 (fifth inductor): Inductors;

[0051] C1 (first capacitor), C2 (second capacitor), C3 (third capacitor): Capacitors;

[0052] N1 (first node), N2 (second node), N3 (third node): Nodes;

[0053] S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal): Signals;

[0054] Sin: Input signal;

[0055] Sout: Output signal;

[0056] Tin: Input terminal;

[0057] Tout: Output terminal. Detailed implementation

[0058] [Description of the embodiments of the present disclosure]

[0059] First, the content of the embodiments of the present disclosure will be listed for description.

[0060] (1) An embodiment of the present disclosure is a Doherty amplifier circuit, comprising: a splitter that distributes an input signal into a first signal and a second signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a combiner that combines the fourth signal and the fifth signal and outputs the combined signal as an output signal to an output terminal; a first matching circuit connected between the splitter and the main amplifier; and a second matching circuit connected between the splitter and the first peak amplifier. In the operating frequency band, the absolute value of the return loss when looking from the splitter to the second matching circuit is greater than the absolute value of the return loss when looking from the splitter to the first matching circuit. Thereby, the gain of the first peak amplifier can be increased, and thus distortion can be suppressed. Thereby, the characteristics can be improved.

[0061] (2) In the above (1), it may also be that at a frequency twice the center frequency of the operating frequency band, the impedance when looking from the main amplifier to the first matching circuit is capacitive, and at a frequency twice the center frequency, the impedance when looking from the first peak amplifier to the second matching circuit is inductive. Thereby, the efficiency will be improved, and thus the characteristics can be further improved.

[0062] (3) In the above (2), it may also be that the first matching circuit is a two-stage matching circuit including a first inductor, a second inductor, a third inductor, a first capacitor, and a second capacitor. Among them, the first end of the first inductor is electrically connected to the distributor, and the second end of the first inductor is electrically connected to a first node. The first end of the second inductor is electrically connected to the first node, and the second end of the second inductor is electrically connected to a second node. The first end of the third inductor is electrically connected to the second node, and the second end of the third inductor is electrically connected to the main amplifier. The first capacitor is shunt-connected to the first node, and the second capacitor is shunt-connected to the second node. The second matching circuit is a single-stage matching circuit including a fourth inductor, a fifth inductor, and a third capacitor. Among them, the first end of the fourth inductor is electrically connected to the distributor, and the second end of the fourth inductor is electrically connected to a third node. The first end of the fifth inductor is electrically connected to the third node, and the second end of the fifth inductor is electrically connected to the first peak amplifier. The third capacitor is shunt-connected to the third node. Thus, the characteristics can be further improved.

[0063] (4) In the above (3), it may also be that in the operating frequency band, the ratio of the absolute value of the second impedance when looking from the first inductor to the first node to the absolute value of the first impedance when looking from the third inductor to the main amplifier is set as the first ratio. The ratio of the absolute value of the third impedance when looking from the distributor to the first inductor to the absolute value of the second impedance is set as the second ratio. The ratio of the absolute value of the fifth impedance when looking from the fourth inductor to the third node to the absolute value of the fourth impedance when looking from the fifth inductor to the first peak amplifier is set as the third ratio. The ratio of the absolute value of the sixth impedance when looking from the distributor to the fourth inductor to the absolute value of the fifth impedance is set as the fourth ratio. At this time, the ratio of the first ratio to the second ratio is greater than the ratio of the third ratio to the fourth ratio. Thus, the gain of the peak amplifier can be improved.

[0064] (5) In the above (4), it may also be that the first ratio is greater than the second ratio. Thus, the efficiency of the main amplifier can be improved.

[0065] (6) In any one of the above (1) to (5), it may also be that the Doherty amplifier circuit includes: a second peak amplifier that amplifies a third signal and outputs the amplified signal as a sixth signal; and a third matching circuit connected between the distributor and the second peak amplifier, where the input power of the input signal for turning on the second peak amplifier is greater than the input power of the input signal for turning on the first peak amplifier. The distributor distributes the input signal into the first signal, the second signal, and the third signal, and the synthesizer synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal as the output signal to the output terminal. Thus, when there are two or more peak amplifiers, the characteristics can be improved.

[0066] (7) In the above (6), it may also be that in the operating frequency band, the absolute value of the return loss when looking from the distributor to the third matching circuit is greater than the absolute value of the return loss when looking from the distributor to the first matching circuit. Thus, distortion can be further suppressed.

[0067] (8) In the above (7), it may also be that at a frequency twice the center frequency of the operating frequency band, the impedance when looking from the main amplifier to the first matching circuit is capacitive, at a frequency twice the center frequency, the impedance when looking from the first peak amplifier to the second matching circuit is inductive, and at a frequency twice the center frequency, the impedance when looking from the second peak amplifier to the third matching circuit is inductive. Thus, distortion can be further suppressed.

[0068] (9) In the above (6), it may also be that in the operating frequency band, the absolute value of the return loss when looking from the distributor to the third matching circuit is less than the absolute value of the return loss when looking from the distributor to the second matching circuit. Thus, the efficiency can be improved.

[0069] (10) In the above (9), it may also be that at a frequency twice the center frequency of the operating frequency band, the impedance when looking from the main amplifier to the first matching circuit is capacitive, at a frequency twice the center frequency, the impedance when looking from the first peak amplifier to the second matching circuit is inductive, and at a frequency twice the center frequency, the impedance when looking from the second peak amplifier to the third matching circuit is capacitive. Thus, the efficiency can be further improved.

[0070] (11)One embodiment of the present disclosure is a semiconductor device, which is a semiconductor device for a Doherty amplifier circuit, and includes: a package having a base, a first input lead, and a second input lead; a first semiconductor chip mounted on the base, the first semiconductor chip including a main amplifier that amplifies a first signal obtained by distributing an input signal; a second semiconductor chip mounted on the base, the second semiconductor chip including a first peak amplifier that amplifies a second signal obtained by distributing the input signal; a first capacitor mounted on the base, a first end of the first capacitor being electrically connected to the base; a second capacitor mounted on the base, a first end of the second capacitor being electrically connected to the base; a third capacitor mounted on the base, a first end of the third capacitor being electrically connected to the base; a first inductor, a first end of the first inductor being electrically connected to the first input lead, and a second end of the first inductor being electrically connected to a second end of the first capacitor; a second inductor, a first end of the second inductor being electrically connected to the second end of the first capacitor, and a second end of the second inductor being electrically connected to a second end of the second capacitor; a third inductor, a first end of the third inductor being electrically connected to the second end of the second capacitor, and a second end of the third inductor being electrically connected to an input pad of the first semiconductor chip; a fourth inductor, a first end of the fourth inductor being electrically connected to the second input lead, and a second end of the fourth inductor being electrically connected to a second end of the third capacitor; and a fifth inductor, a first end of the fifth inductor being electrically connected to the second end of the third capacitor, and a second end of the fifth inductor being electrically connected to an input pad of the second semiconductor chip. Thereby, the characteristics can be improved.

[0071] [Details of the Embodiment of the Present Disclosure]

[0072] Hereinafter, specific examples of the Doherty amplifier circuit and the semiconductor device according to the embodiment of the present disclosure will be described with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0073] [Example 1]

[0074] As the Doherty amplifier circuit, a high-output high-frequency amplifier circuit for a mobile communication base station will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 20 GHz or less. Figure 1 It is a block diagram of the Doherty amplifier circuit of Example 1.

[0075] As shown in Figure 1As shown, in Doherty amplifier circuit 100, a main amplifier 10, a peak amplifier 12 (first peak amplifier), and a peak amplifier 14 (second peak amplifier) are connected in parallel between a divider 16 and a combiner 18. Thus, Doherty amplifier circuit 100 is a three-way amplifier circuit. The Doherty amplifier circuit may also be an N-way Doherty amplifier circuit having one or more than three peak amplifiers.

[0076] A high-frequency signal is input as an input signal Sin to an input terminal Tin. Divider 16 distributes the input signal Sin input to input terminal Tin into a signal S1 (first signal), a signal S2 (second signal), and a signal S3 (third signal). Divider 16 is, for example, a Wilkinson-type divider.

[0077] The path of input signal S1 includes a matching circuit 30, a bias circuit 36, a main amplifier 10, a bias circuit 39, and a matching circuit 33. The path of input signal S2 includes a matching circuit 31, a bias circuit 37, a peak amplifier 12, and a matching circuit 34. The path of input signal S3 includes a matching circuit 32, a bias circuit 38, a peak amplifier 14, and a matching circuit 35.

[0078] Matching circuits 30 to 32 match the impedances when looking from divider 16 to matching circuits 30 to 32 respectively with the impedances when looking from matching circuits 30 to 32 to main amplifier 10, peak amplifier 12, and peak amplifier 14 respectively. Bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to the gates G of main amplifier 10, peak amplifier 12, and peak amplifier 14 respectively, suppressing leakage of signals S1 to S3 to the bias terminal.

[0079] Main amplifier 10, peak amplifier 12, and peak amplifier 14 amplify signals S1, S2, and S3 respectively, and output the amplified signals S4 (fourth signal), S5 (fifth signal), and S6 (sixth signal) respectively. Bias circuit 39 supplies a drain bias voltage VD to the drains D of main amplifier 10, peak amplifier 12, and peak amplifier 14, suppressing leakage of signal S4 to the bias terminal. Matching circuits 33 to 35 match the impedances when looking from main amplifier 10, peak amplifier 12, and peak amplifier 14 to matching circuits 33 to 35 respectively with the impedances when looking from matching circuits 33 to 35 to combiner 18 respectively. Combiner 18 combines signals S4 to S6, and outputs the combined signal as an output signal Sout to an output terminal Tout.

[0080] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), such as GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). The sources S of the transistors Q1 to Q3 are grounded, the signals S1 to S3 are respectively input to the gates G, and the signals S4 to S6 are respectively output from the drains D.

[0081] When the input power of the input signal Sin increases, the main amplifier 10 starts to operate. Until the input power at which the main amplifier 10 starts to saturate, the peak amplifier 12 and the peak amplifier 14 do not operate, and the main amplifier 10 amplifies the input signal. At the input power at which the main amplifier 10 starts to saturate, the peak amplifier 12 starts to operate. Until the input power at which the peak amplifier 12 starts to saturate, the peak amplifier 14 does not operate, and the main amplifier 10 and the peak amplifier 12 amplify the input signal. At the input power at which the peak amplifier 12 starts to saturate, the peak amplifier 14 starts to operate. Thereafter, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 amplify the input signal Sin. Thus, the input power for turning on the peak amplifier 12 is greater than the input power for turning on the main amplifier 10, and the input power for turning on the peak amplifier 14 is greater than the input power for turning on the peak amplifier 12. The main amplifier 10 is, for example, a class A or AB amplifier, and the peak amplifiers 12 and 14 are, for example, class C amplifiers.

[0082] In the first embodiment, the absolute value of the return loss when looking from the distributor 16 to the matching circuit 30 is less than the absolute value of the return loss when looking from the distributor 16 to the matching circuit 31. Thus, the gain of the main amplifier 10 is lower than the gain of the peak amplifier 12. On the other hand, the efficiency of the main amplifier 10 is higher than the efficiency of the peak amplifier 12. The absolute value of the return loss when looking from the distributor 16 to the matching circuit 32 is greater than the absolute value of the return loss when looking from the distributor 16 to the matching circuit 30. It should be noted that the return loss RL when looking from the distributor 16 to the matching circuits 30 to 32 is expressed as RL = 20log using the reflection coefficient |Γ| when looking from the distributor 16 to the matching circuits 30 to 32 in the operating frequency band. 10|Γ| [dB]. Here, the impedance when looking from the distributor 16 to the matching circuits 30 to 32 in the operating frequency band is set as Z, and the reference impedance is set as Zo. At this time, the reflection coefficient |Γ| is |Γ| = |(Z - Zo) / (Z + Zo)|, which corresponds to the absolute value |S11| of the S parameter S11.

[0083] [Examples of Matching Circuits]

[0084] As examples of the matching circuits 30 to 32, the second - stage matching circuit 30a and the first - stage matching circuit 30b will be described. The second - stage matching circuit 30a and the first - stage matching circuit 30b are just examples, and the circuit configurations are not limited to those of the second - stage matching circuit 30a and the first - stage matching circuit 30b.

[0085] Figure 2 is the circuit diagram of the second - stage matching circuit in Embodiment 1. The terminal T1 is Figure 1 the output terminal of the distributor 16. The terminal T2 is the output terminal of the transistors Q (corresponding to Figure 1 the transistors Q1 to Q3) used in the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. The source S of the transistor Q is grounded, and the drain D is electrically connected to the terminal T2.

[0086] The second - stage matching circuit 30a includes a transmission line TL1, inductors L1 to L3, a capacitor C1, and a capacitor C2. The transmission line TL1 is, for example, equivalent to a line provided on a circuit board. The first end of the inductor L1 (first inductor) is electrically connected to the terminal T1 via the transmission line TL1, and the second end of the inductor L1 is electrically connected to the node N1 (first node). The first end of the inductor L2 (second inductor) is electrically connected to the node N1, and the second end of the inductor L2 is electrically connected to the node N2 (second node). The first end of the inductor L3 (third inductor) is electrically connected to the node N2, and the second end of the inductor L3 is electrically connected to the gate G of the transistor Q. The capacitor C1 (first capacitor) is shunt - connected to the node N1. The capacitor C2 (second capacitor) is shunt - connected to the node N2.

[0087] Let the impedances of the fundamental wave (signal in the operating frequency band) when looking from the terminal T1, inductor L1, node N1, inductor L2, node N2, and inductor L3 to the transistor Q be Z1(f), Z2(f), Z3(f), Z4(f), Z5(f), and Z6(f) respectively. Let the impedances of the second - harmonic wave (signal with a frequency twice that of the operating frequency band) when looking from the gate G, inductor L3, node N2, inductor L2, and transmission line TL1 to the terminal T1 side be Z6(2f), Z5(2f), Z4(2f), Z3(2f), and Z1(2f) respectively.

[0088] Figure 3This is the circuit diagram of the first-stage matching circuit in Embodiment 1. The first-stage matching circuit 30b includes a transmission line TL2, an inductor L4, an inductor L5, and a capacitor C3. The transmission line TL2 is, for example, equivalent to a line provided on a circuit board. The first end of the inductor L4 (the fourth inductor) is electrically connected to the terminal T1 via the transmission line TL2, and the second end of the inductor L4 is electrically connected to the node N3 (the third node). The first end of the inductor L5 (the fifth inductor) is electrically connected to the node N3, and the second end of the inductor L5 is electrically connected to the gate G of the transistor Q. The capacitor C3 (the third capacitor) is shunt-connected to the node N3.

[0089] Let the impedances of the fundamental waves when looking at the transistor Q from the terminal T1, the inductor L4, the node N3, and the inductor L5 be Z1(f), Z7(f), Z8(f), and Z6(f), respectively. Let the impedances of the second harmonics when looking at the terminal T1 from the gate G, the inductor L5, and the transmission line TL2 be Z6(2f), Z8(2f), and Z1(2f), respectively.

[0090] [Explanation of impedance matching achieved by the matching circuit]

[0091] The impedance matching is explained using the second-stage matching circuit 30a and the first-stage matching circuit 30b. The method of impedance matching is not limited to the method described below.

[0092] Figure 4 This is a Smith chart showing the impedance matching of the fundamental wave using the first-stage matching circuit in Embodiment 1. For easy observation Figure 4 , for convenience, the reference impedance Z0 is set to 5 Ω. The impedance Z1(f) when looking at the first-stage matching circuit 30b from the terminal T1 is 50 Ω and is located on the approximate real axis. In an example where a GaN HEMT is used as the transistor Q, the absolute value of the impedance Z6(f) when looking at the gate G from the first-stage matching circuit 30b is 0.15 Ω and is capacitive. The inductor L5 transforms the impedance Z6(f) into Z8(f). The capacitor C3 transforms the impedance Z8(f) into an impedance Z7(f) on the approximate real axis. The transmission line TL2 and the inductor L4 transform the impedance Z7(f) into the impedance Z1(f).

[0093] For example, in a GaN HEMT with an operating frequency band of 2 GHz and a maximum output power of 200 W, the absolute value of the impedance Z6(f) is 0.15 Ω. Thus, the absolute value of the input impedance of a transistor with a large output power is low. On the other hand, the impedance Z1(f) corresponding to the output impedance of the distributor 16 is 50 Ω. Thus, the absolute value of the impedance Z1(f) is about 300 times the absolute value of the impedance Z6(f).

[0094] As a method of transforming the impedance Z6(f) into the impedance Z1(f), it can be considered that after transforming the impedance Z6(f) into an impedance on the real axis with substantially unchanged absolute value, a quarter-wavelength line impedance transformer is used to transform 0.15 Ω into 50 Ω. However, if a quarter-wavelength line is used to transform from 0.15 Ω to 50 Ω, the impedance transformation ratio becomes about 300 times, and it is difficult to match it in a wide frequency band.

[0095] Therefore, in the first-stage matching circuit 30b, the impedance Z7(f) is set to about 3 Ω on the approximate real axis. In this way, Z7(f) is set to about √(Z6(f) × Z1(f)). Thus, the transformation from the impedance Z6(f) through Z7(f) to Z1(f) is achieved by performing two impedance transformations of approximately 20 times each, from 0.15 Ω through 3 Ω to 50 Ω. When the absolute values of the impedances Z6(f), Z7(f), and Z1(f) are set to 0.15 Ω, 3 Ω, and 50 Ω respectively, the impedance transformation ratio |Z7(f)| / |Z6(f)| = 20, and the impedance transformation ratio |Z1(f)| / |Z7(f)| = 16.7. In this way, the impedance transformation ratios |Z7(f)| / |Z6(f)| and |Z1(f)| / |Z7(f)| can be reduced, and thus broadbanding can be achieved.

[0096] Figure 5 It is a Smith chart of the second harmonic of the first-stage matching circuit in Embodiment 1. As Figure 5 shown, it is required that the signal of the second harmonic does not leak to the distributor 16. Therefore, the impedance Z1(2f) is substantially open. The transmission line TL2, the inductor L4, and the capacitor C3 transform the impedance Z1(2f) into Z8(2f) on the outer circumference of the Smith chart. Further, the inductor L5 transforms the impedance Z8(2f) into Z6(2f) on the outer circumference of the Smith chart. The impedance Z6(2f) is inductive.

[0097] Figure 6 It is a diagram showing the efficiency with respect to the phase of the impedance Z6(2f) looking from the gate of the transistor to the previous stage. It is shown by taking a GaN HEMT with an operating frequency band of 2 GHz and a maximum output power of 200 W as an example. The phase of the impedance Z6(2f) on the horizontal axis is Figure 5 the phase on the Smith chart of. The phase at the open position is 0°, and when the phase starts to increase from 0°, it means that the impedance Z6(2f) rotates counterclockwise around the center of the Smith chart. When the phase starts to decrease from 0°, it means that the impedance Z6(2f) rotates clockwise around the center of the Smith chart. The phases at the short-circuit positions are 180° and -180°. The efficiency on the vertical axis is the drain efficiency.

[0098] As Figure 6As shown, the efficiency is the lowest near the phase of 130°, and the highest near the phase of 150°. As the phase ranges from 130° through -180° to 150°, the efficiency increases. In the range R1 near the phase of 20° to 70°, the efficiency decreases. On the other hand, in the range R2 of the phase from -90° to -180°, the efficiency increases. Thus, in order to improve the efficiency, not only is it necessary to match the impedance of the fundamental wave as Figure 4 but it is also important to adjust the phase of the second harmonic.

[0099] Therefore, the following describes the improvement in efficiency by using the second-order matching circuit 30a. Figure 7 is the Smith chart of the second harmonic of the second-order matching circuit in Embodiment 1. As Figure 7 shown, the transmission line TL1, the inductor L1, and the capacitor C1 transform the impedance Z1(2f) at the open-circuit position to Z3(2f) on the outer circumference of the Smith chart. Further, the inductor L2 transforms the impedance Z3(2f) to Z4(2f) on the outer circumference of the Smith chart. The position of the impedance Z4(2f) is approximately the same as Figure 5 the position of the impedance Z6(2f) of

[0100] Figure 8 is the Smith chart showing the impedance matching of the fundamental wave of the second-order matching circuit in Embodiment 1. As Figure 8 shown, in the second-order matching circuit 30a, Figure 2 the inductor L3 of

[0101] transforms the impedance Z6(f) to Z5(f). The capacitor C2 transforms the impedance Z5(f) to the impedance Z4(f). The inductor L2 transforms the impedance Z4(f) to the impedance Z3(f). The capacitor C1 transforms the impedance Z3(f) to the impedance Z2(f). The transmission line TL1 and the inductor L1 transform the impedance Z2(f) to the impedance Z1(f). Thus, the impedance Z6(f) can be transformed to Z1(f). Figure 7 In the case where the impedance Z6(2f) of the second harmonic is made capacitive as Figure 8 and the impedance Z6(f) of the fundamental wave is transformed to Z1(f) as Figure 7 by reducing the inductor L3 and the capacitor C2, the impedances Z5(f) and Z4(f) hardly move from the impedance Z6(f). By increasing the inductor L2, Figure 8The impedance Z3(f) also rotates near the periphery. When the impedance Z2(f) is transformed to the real axis from the impedance Z3(f) using the capacitor C1, the impedance Z2(f) becomes close to the impedance Z1(f). In one example, the impedance Z2(f) is 30 Ω.

[0102] When the absolute values of the impedances Z6(f), Z2(f), and Z1(f) are set to 0.15 Ω, 30 Ω, and 50 Ω, respectively, the impedance transformation ratio |Z2(f)| / |Z6(f)| = 200, and the impedance transformation ratio |Z1(f)| / |Z2(f)| = 1.7. Thus, the impedance transformation ratio becomes unbalanced. As a result, it becomes difficult to widen the bandwidth.

[0103] As described above, when the two-stage matching circuit 30a is used, the efficiency is high, but the bandwidth becomes narrow. If it is desired to use the two-stage matching circuit 30a to obtain gain over the entire operating frequency band, it is matched in such a way that the overall gain decreases, and the gain decreases. When the one-stage matching circuit 30b is used, the efficiency is low, but the bandwidth is wide. Thus, it is easy to obtain gain over the entire operating frequency band, and the gain increases.

[0104] [Simulation]

[0105] For Figure 2 the two-stage matching circuit 30a and Figure 3 the one-stage matching circuit 30b used as the matching circuit, simulations were performed on S11 and S21 at the terminals T1 and T2.

[0106] The simulation conditions are as follows.

[0107] Transistor Q: GaN HEMT

[0108] Two-stage matching circuit 30a:

[0109] Transmission line TL1: Characteristic impedance: 19 Ω, Electrical length: 87°

[0110] Inductors L1, L2, L3: 0.1 nH, 0.2 nH, 0.022 nH

[0111] Capacitors C1, C2: 42 pF, 20 pF

[0112] One-stage matching circuit 30b:

[0113] Transmission line TL2: Characteristic impedance: 8 Ω, Electrical length: 83°

[0114] Inductors L4, L5: 0.1 nH, 0.137 nH

[0115] Capacitor C3: 108 pF

[0116] Operating frequency band: 1.8 Hz to 2.2 GHz

[0117] The electrical length is converted to the phase at 2 GHz.

[0118] Figure 9 It is a graph showing S11 with respect to frequency in the simulation. The frequency on the horizontal axis is the frequency of the high-frequency signal input to terminal T1. The S11 on the vertical axis is the absolute value of the S-parameter S11 of terminal T1, which corresponds to the absolute value of the reflection coefficient. In addition, S11 corresponds to the return loss. When S11 approaches 0 dB, the absolute value of the return loss is small. When S11 approaches 0, that is, when the negative dB value is large, the absolute value of the return loss is large. The case of using the two-stage matching circuit 30a and the case of using the one-stage matching circuit 30b are shown.

[0119] Figure 10 It is a graph showing S21 with respect to frequency in the simulation. The S21 on the vertical axis is the absolute value of the S-parameter S21 from terminal T1 to terminal T2, which is the passing characteristic. S21 corresponds to the gain. When S21 is large, the gain is large.

[0120] As Figure 9 shown, when using the one-stage matching circuit 30b, the absolute value of the return loss is larger than the case of using the two-stage matching circuit 30a. Therefore, as Figure 10 shown, in the entire region of the operating frequency band, the gain is more than 1 dB larger.

[0121] [Comparison between the comparative example and the embodiment]

[0122] Figure 11 , Figure 12 , Figure 13 and Figure 14 are respectively the circuit diagrams of a part of the Doherty amplifier circuits of Comparative Example 1, Comparative Example 2, Embodiment 1, and Embodiment 2. In Figures 11 to 14 , the power divider 16, the matching circuits 30 to 32, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are illustrated.

[0123] As Figure 11 shown, in the Doherty amplifier circuit 110 of Comparative Example 1, the matching circuits 30 to 32 are the two-stage matching circuit 30a having the inductors L1 to L3, the capacitor C1, and the capacitor C2.

[0124] As Figure 12 shown, in the Doherty amplifier circuit 112 of Comparative Example 2, the matching circuit 30 is the one-stage matching circuit 30b having the inductor L4, the inductor L5, and the capacitor C3. The matching circuits 31 and 32 are the two-stage matching circuit 30a having the inductors L1 to L3, the capacitor C1, and the capacitor C2.

[0125] As Figure 13 shown, in the Doherty amplifier circuit 102 of Embodiment 1, the matching circuit 30 is a two-stage matching circuit 30a having inductors L1 to L3, capacitors C1, and capacitor C2. The matching circuits 31 and 32 are single-stage matching circuits 30b having inductor L4, inductor L5, and capacitor C3.

[0126] As Figure 14 shown, in the Doherty amplifier circuit 104 of Embodiment 2, the matching circuits 30 and 32 are two-stage matching circuits 30a having inductors L1 to L3, capacitors C1, and capacitor C2. The matching circuit 31 is a single-stage matching circuit 30b having inductor L4, inductor L5, and capacitor C3.

[0127] Figure 15 is a graph showing the gain with respect to the input power in Comparative Example 1, Comparative Example 2, Embodiment 1, and Embodiment 2. The horizontal axis corresponds to the input power Pin of the input signal Sin. The gain on the vertical axis is the power gain, which is different from the small-signal S21 of Figure 10 , but when S21 is large, the power gain also increases. The solid line represents the gain of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, and the sum of the dashed lines represents the overall gain of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14.

[0128] As Figure 15 shown, in the Doherty amplifier circuit 110 of Comparative Example 1, in order to increase the efficiency, the two-stage matching circuit 30a is used as the matching circuits 30 to 32 as Figure 11 shown. In the range up to the input power Pin being the power P1, the gain of the main amplifier 10 is substantially constant. When the input power Pin is greater than the power P1, the main amplifier 10 saturates and the gain of the main amplifier 10 decreases.

[0129] Near the power P1, the peak amplifier 12 starts to operate. When the input power Pin starts to increase from the power P1, the gain of the peak amplifier 12 gradually increases and saturates at the power P2. The gain when the peak amplifier 12 saturates is less than the gain when the main amplifier 10 saturates. When the input power is greater than the power P2, the peak amplifier 12 saturates and the gain of the peak amplifier 12 decreases.

[0130] Near the power P2, the peak amplifier 14 starts to operate. When the input power Pin starts to increase from the power P2, the gain of the peak amplifier 14 gradually increases and saturates at the power P3. The gain when the peak amplifier 14 saturates is less than the gain when the main amplifier 10 saturates. When the input power is greater than the power P3, the peak amplifier 14 saturates and the gain of the peak amplifier 14 decreases.

[0131] The reason for the different gain operations in the main amplifier 10, peak amplifier 12, and peak amplifier 14 is that: the main amplifier 10 is an AB - class operating amplifier, and the peak amplifiers 12 and 14 are C - class operating amplifiers.

[0132] The total gain is approximately fixed within the range where the input power Pin is up to the power P1. When the input power Pin is greater than the power P1, the total gain decreases as the gain of the main amplifier 10 decreases, and then increases as the gain of the peak amplifier 12 increases and becomes approximately fixed. When the input power Pin is greater than the power P2, the total gain decreases as the gain of the peak amplifier 12 decreases, and then increases as the gain of the peak amplifier 14 increases and becomes approximately fixed. When the input power Pin is greater than the power P3, the total gain decreases as the gain of the peak amplifier 14 decreases.

[0133] In Comparative Example 1, due to the gain difference between the main amplifier 10 and the peak amplifiers 12 and 14, the total gain forms a level difference of ΔG1. When the gain is fixed with respect to the input power Pin, the linearity such as AM (Amplitude - Modulation) / AM characteristics is good. In Comparative Example 1, since the level difference ΔG1 is formed, the AM / AM characteristics deteriorate and the distortion characteristics deteriorate.

[0134] In the Doherty amplifier circuit 112 of Comparative Example 2, as Figure 12 shown, the first - stage matching circuit 30b is used as the matching circuit 30, and the second - stage matching circuit 30a is used as the matching circuits 31 and 32. As Figure 15 shown, the gain of the main amplifier 10 is greater than that of the Doherty amplifier circuit 110 of Comparative Example 1. Thus, the level difference ΔG2 of the total gain near the power P2 of the input power Pin is greater than ΔG1. Thus, the AM / AM characteristics deteriorate compared to the Doherty amplifier circuit 110 of Comparative Example 1. Moreover, since the matching circuit 30 uses the first - stage matching circuit 30b, the efficiency of the main amplifier 10 decreases.

[0135] In the Doherty amplifier circuit 102 of Embodiment 1, as Figure 13 shown, the second - stage matching circuit 30a is used as the matching circuit 30, and the first - stage matching circuit 30b is used as the matching circuits 31 and 32. As Figure 15In this way, the gains of peak amplifier 12 and peak amplifier 14 are greater than those of Doherty amplifier circuit 110 of Comparative Example 1. As a result, the difference in the overall gain around power P2 for input power Pin becomes smaller. Thus, the AM / AM characteristic is improved compared to Doherty amplifier circuit 110 of Comparative Example 1. Since matching circuit 31 and matching circuit 32 use first-stage matching circuit 30b, the efficiency of peak amplifier 12 and peak amplifier 14 will decrease. However, since main amplifier 10 mainly amplifies input signal Sin, the impact of the decrease in the efficiency of peak amplifier 12 and peak amplifier 14 is small when considering the entire Doherty amplifier circuit.

[0136] In Doherty amplifier circuit 104 of Embodiment 2, as Figure 14 such, second-stage matching circuit 30a is used as matching circuit 30 and matching circuit 32, and first-stage matching circuit 30b is used as matching circuit 31. As Figure 15 such, the gain of peak amplifier 12 is greater than that of Doherty amplifier circuit 110 of Comparative Example 1. As a result, the difference in the overall gain around power P2 for input power Pin becomes smaller. A difference ΔG3 in the overall gain around power P3 occurs. Thus, the AM / AM characteristic deteriorates compared to Doherty amplifier circuit 102 of Embodiment 1. However, since matching circuit 32 uses second-stage matching circuit 30a, the efficiency of peak amplifier 14 is improved, and the overall efficiency is improved compared to Doherty amplifier circuit 102 of Embodiment 1.

[0137] Table 1 is a table showing the characteristics (efficiency, distortion, and phase difference) of each Doherty amplifier circuit 110, 112, 102, and 104. "30" to "32" are the stages of matching circuit 30 to matching circuit 32. "1" represents first-stage matching circuit 30b, and "2" represents second-stage matching circuit 30a. "Efficiency" represents drain efficiency, "distortion" represents the AM / AM characteristic, and "phase difference" represents the phase difference between matching circuit 30 to matching circuit 32. "A" for each characteristic indicates good characteristics. "B" indicates good characteristics although not as good as A. "B-" indicates slightly worse characteristics than B. "C" indicates poor characteristics. "D" indicates very poor characteristics.

[0138] [Table 1]

[0139] 30 31 32 Efficiency Distortion Phase difference 110 2 2 2 A C A 112 1 2 2 D D B 102 2 1 1 B- A B 104 2 1 2 B B B

[0140] As shown in Table 1, in Doherty amplifier circuit 110 of Comparative Example 1, since second-stage matching circuit 30a is used for matching circuit 30 to matching circuit 32, the efficiency is A. The distortion is C. Since matching circuit 30 to matching circuit 32 are the same, the phase difference between matching circuit 30 to matching circuit 32 is almost zero, and the phase difference is A.

[0141] In the Doherty amplifier circuit 112 of Comparative Example 2, the efficiency and distortion are worse than those of the Doherty amplifier circuit 110, being D. Due to the different number of stages of the matching circuits 30 to 32, the phase difference is worse than that of the Doherty amplifier circuit 110. However, since phase adjustment can be performed, it does not reach the level of being a problem.

[0142] In the Doherty amplifier circuit 102 of Embodiment 1, the efficiency is worse than that of the Doherty amplifier circuit 110, being B-, but the distortion is A. The phase difference is B. In the Doherty amplifier circuit 104 of Embodiment 2, the efficiency is slightly better than that of the Doherty amplifier circuit 102 of Embodiment 1, being B. The distortion is slightly worse than that of the Doherty amplifier circuit 102, being B, but better than that of the Doherty amplifier circuit 110.

[0143] [Description of Embodiment]

[0144] According to Embodiment 1 and Embodiment 2, the matching circuit 30 (first matching circuit) is connected between the distributor 16 and the main amplifier 10. The matching circuit 31 (second matching circuit) is connected between the distributor 16 and the peak amplifier 12. As Figure 9 such, in the operating frequency band, the absolute value of the return loss RL2 when looking at the matching circuit 31 from the distributor 16 is greater than the absolute value of the return loss RL1 when looking at the matching circuit 30 from the distributor 16. Thereby, as Figure 10 such, the gain of the peak amplifier 12 can be increased. Thereby, as Figure 15 such, the difference between the maximum and minimum of the total gain can be reduced, and distortion can be suppressed. Thereby, the characteristics can be improved.

[0145] The absolute value of the return loss RL2 can be greater than the absolute value of the return loss RL1 at any frequency in the operating frequency band. At any frequency in the operating frequency band, the absolute value of the return loss RL2 can be greater than the absolute value of the return loss RL1 by 1 dB or more, and can be greater than 5 dB or more. Thereby, the gain of the peak amplifier 12 can be further increased. When the absolute value of the return loss RL1 is too small, the gain of the main amplifier 10 deteriorates excessively. From this viewpoint, at any frequency in the operating frequency band, the absolute value of the return loss RL1 can be 3 dB or more.

[0146] As Figures 5 to 7 such, at a frequency 2f which is twice the center frequency of the operating frequency band, the impedance when looking at the matching circuit 30 from the main amplifier 10 is capacitive. The impedance when looking at the matching circuit 31 from the peak amplifier 12 is inductive. Thereby, the efficiency of the main amplifier 10 can be increased, and thus the overall efficiency is increased. Thereby, the characteristics can be further improved.

[0147] In a Smith chart, when the angle counterclockwise from the open-circuit position is set as the phase, the phase of the impedance Z6(2f) when looking from the main amplifier 10 toward the matching circuit 30 can be set to be -180° or more and -20° or less, and can be set to be -180° or more and -90° or less. Thereby, the efficiency of the main amplifier 10 can be improved. The phase of the impedance Z6(2f) when looking from the peak amplifier 12 toward the matching circuit 31 can be set to be 0° or more and 90° or less, and can be set to be 20° or more and 70° or less. Thereby, the gain of the peak amplifier 12 can be improved.

[0148] The Doherty amplifier circuit may also be a two-way Doherty amplifier circuit without the peak amplifier 14 provided. In the case of a three-way Doherty amplifier circuit having the peak amplifier 14 and the matching circuit 32 (third matching circuit), the balance between efficiency and distortion is important. Therefore, the absolute value of the return loss RL2 can be made greater than the absolute value of the return loss RL1. Thereby, the characteristics can be improved in the three-way Doherty amplifier circuit.

[0149] In the Doherty amplifier circuit 102 of Embodiment 1, the absolute value of the return loss RL3 when looking from the distributor 16 toward the matching circuit 32 is greater than the absolute value of the return loss RL1 when looking from the distributor 16 toward the matching circuit 30. Thereby, as Figure 10 such, the gain of the peak amplifier 14 can be improved. Thereby, as Figure 15 such, the difference between the highest and lowest of the total gain can be reduced, and distortion can be suppressed.

[0150] At any frequency in the operating frequency band, the absolute value of the return loss RL3 can be 1 dB or more greater than the absolute value of the return loss RL1, and can be 5 dB or more greater. At any frequency in the operating frequency band, the absolute value of the return loss RL1 can be 3 dB or more.

[0151] At the frequency 2f, the impedance when looking from the peak amplifier 14 toward the matching circuit 32 is inductive. Thereby, distortion can be further suppressed.

[0152] In the Doherty amplifier circuit 104 of Embodiment 2, the absolute value of the return loss RL3 when looking from the distributor 16 toward the matching circuit 32 is less than the absolute value of the return loss RL2 when looking from the distributor 16 toward the matching circuit 31. Thereby, the efficiency of the peak amplifier 14 can be improved.

[0153] The absolute value of the return loss RL3 can be less than the absolute value of the return loss RL2 at any frequency in the operating frequency band. At any frequency in the operating frequency band, the absolute value of the return loss RL3 can be 1 dB or more less than the absolute value of the return loss RL2, and can be 5 dB or more less. At any frequency in the operating frequency band, the absolute value of the return loss RL3 can be 3 dB or more.

[0154] At frequency 2f, the impedance when looking from the peak amplifier 14 towards the matching circuit 32 is capacitive. Thus, the efficiency can be further improved.

[0155] The circuit configurations of the matching circuits 30 to 32 are not limited to Figure 2 and Figure 3 the configurations as long as the return loss becomes a desired value. The two-stage matching circuit 30a is used as the matching circuit 30, and the one-stage matching circuit 30b is used as the matching circuit 31. Thus, the absolute value of the return loss RL2 can be made greater than the absolute value of the return loss RL1. In addition, at frequency 2f, the impedance when looking from the main amplifier 10 towards the matching circuit 30 can be made capacitive, and the impedance when looking from the peak amplifier 12 towards the matching circuit 31 can be made inductive. Thus, the characteristics can be further improved.

[0156] As in the Doherty amplifier circuit 102 of Embodiment 1, the one-stage matching circuit 30b can be used as the matching circuit 32. Thus, the absolute value of the return loss RL3 can be made greater than the absolute value of the return loss RL1. In addition, at frequency 2f, the impedance when looking from the peak amplifier 14 towards the matching circuit 32 can be made inductive.

[0157] As in the Doherty amplifier circuit 104 of Embodiment 2, the two-stage matching circuit 30a can be used as the matching circuit 32. Thus, the absolute value of the return loss RL3 can be made less than the absolute value of the return loss RL2. In addition, at frequency 2f, the impedance when looking from the peak amplifier 14 towards the matching circuit 32 can be made capacitive.

[0158] As Figure 8 such, in the two-stage matching circuit 30a, at the center frequency of the operating frequency band, the absolute value of the impedance Z6(f) (first impedance) when looking from the inductor L3 towards the gate G is set as |Z6(f)|. The absolute value of the impedance Z2(f) (second impedance) when looking from the inductor L1 towards the node N1 is set as |Z2(f)|. The absolute value of the impedance Z1(f) (third impedance) when looking from the divider 16 towards the inductor L1 is set as |Z1(f)|. The ratio |Z2(f)| / |Z6(f)| of |Z2(f)| to |Z6(f)| is set as the first ratio R1. The ratio |Z1(f)| / |Z2(f)| of |Z1(f)| to |Z2(f)| is set as the second ratio R2. When |Z6(f)|, |Z2(f)|, and |Z1(f)| are set as 0.15Ω, 30Ω, and 50Ω respectively, the first ratio R1 = 200, the second ratio R2 = 1.67, and the ratio R1 / R2 of the first ratio R1 to the second ratio R2 is approximately 120.

[0159] As Figure 4As such, in the first-stage matching circuit 30b, at the center frequency of the operating frequency band, the absolute value of the impedance Z6(f) (the fourth impedance) when looking from the inductor L5 toward the gate G is set as |Z6(f)|. The absolute value of the impedance Z7(f) (the fifth impedance) when looking from the inductor L4 toward the node N3 is set as |Z7(f)|. The absolute value of the impedance Z1(f) (the sixth impedance) when looking from the divider 16 toward the inductor L4 is set as |Z1(f)|. The ratio |Z7(f)| / |Z6(f)| of |Z7(f)| to |Z6(f)| is set as the third ratio R3. The ratio |Z1(f)| / |Z7(f)| of |Z1(f)| to |Z7(f)| is set as the fourth ratio R4. When |Z6(f)|, |Z7(f)|, and |Z1(f)| are set as 0.15 Ω, 3 Ω, and 50 Ω respectively, the third ratio R3 = 20, the fourth ratio R4 = 16.7, and the ratio R3 / R4 of the third ratio R3 to the fourth ratio R4 is approximately 1.20.

[0160] As described above, make the ratio R1 / R2 greater than the ratio R3 / R4. Thereby, the efficiency of the main amplifier 10 with the matching circuit 30 set as the second-stage matching circuit 30a can be improved, and the gain of the peak amplifier 12 with the matching circuit 31 set as the first-stage matching circuit 30b can be improved. The ratio R1 / R2 can be set to be 2 times or more of the ratio R3 / R4, can be set to be 10 times or more, can be set to be 50 times or more. From the viewpoint of not making the ratio R1 / R2 too large, the ratio R1 / R2 can be set to be 1000 times or less of the ratio R3 / R4.

[0161] In the second-stage matching circuit 30a, the first ratio R1 is greater than the second ratio R2. Thereby, the efficiency of the main amplifier 10 with the matching circuit 30 set as the second-stage matching circuit 30a can be improved. The first ratio R1 can be set to be 2 times or more of the second ratio R2, can be set to be 10 times or more, can be set to be 100 times or more. From the viewpoint of not making the first ratio R1 too large, the first ratio R1 can be set to be 1000 times or less of the second ratio R2.

[0162] From the viewpoint of Figure 7 rotating the phase from the impedance Z3(2f) to Z4(2f) in Figure 8 and reducing the movement from the impedance Z6(f) to Z5(f) in Figure 8 consideration, the inductance of the inductor L2 can be greater than the inductance of the inductor L3, and can be set to be 2 times or more. From the viewpoint of

[0163] In the first-stage matching circuit 30b, the third ratio R3 can be set to be 0.1 times or more and 10 times or less of the fourth ratio R4, can be set to be 0.2 times or more and 5 times or less, and can be set to be 0.5 times or more and 2 times or less. Thereby, the gain of the peak amplifier 12 with the matching circuit 31 as the first-stage matching circuit 30b can be increased.

[0164] [Embodiment 3]

[0165] Embodiment 3 and Modification 1 thereof are examples of semiconductor devices for Doherty amplifier circuits of Embodiment 1 and Embodiment 2. Figure 16 is a top view of the semiconductor device of Embodiment 3. In Figure 16 it, the lid of the package 40 is not shown. The thickness direction of the base 41 of the package 40 is set as the Z direction, the direction from the leads 44a to 44c to the leads 45a to 45c is set as the X direction, and the direction orthogonal to the X direction and the Z direction is set as the Y direction.

[0166] As Figure 16 shown, in the semiconductor device 106 of Embodiment 3, the package 40 has at least a base 41 whose upper surface is conductive, a frame 42, leads 44a to 44c, and leads 45a to 45c. The base 41 is a conductive substrate such as a laminated substrate of copper and molybdenum, etc. A reference potential such as a ground potential is supplied to the base 41. Semiconductor chips 50a to 50c and capacitive components 55a to 55c are mounted on the base 41. The frame 42 is provided on the base 41 so as to surround the semiconductor chips 50a to 50c and the capacitive components 55a to 55c. The frame 42 is a dielectric layer made of a resin such as glass epoxy or ceramic, etc.

[0167] The leads 44a to 44c are provided on one side in the X direction of the frame 42. The leads 45a to 45c are provided on the + side in the X direction of the frame 42. The leads 44a to 44c and the leads 45a to 45c are metal layers or metal plates such as copper, etc. Signals S1 to S3 are respectively input to the leads 44a to 44c, and signals S4 to S6 are respectively output from the leads 45a to 45c.

[0168] Each of the semiconductor chips 50a to 50c includes a semiconductor substrate 51, a pad 52 provided on the upper surface of the semiconductor substrate 51, a pad 53, and an electrode provided on the lower surface of the semiconductor substrate 51. The pad 52, the pad 53, and the electrode on the lower surface of the semiconductor substrate 51 are a gate electrode, a drain electrode, and a source electrode respectively, and the pad 52 and the pad 53 are an input pad and an output pad respectively. Provided on the semiconductor substrate 51 is Figure 1The transistors Q1 to Q3 shown. When the transistors Q1 to Q3 are GaN HEMTs, the semiconductor substrate 51 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. When the transistors Q1 to Q3 are LDMOS, the semiconductor substrate 51 is, for example, a silicon (Si) substrate. The pads 52, the pads 53, and the electrodes are metal layers such as gold layers, etc.

[0169] The capacitive components 55a to 55c include a dielectric substrate 56, an electrode 57 provided on the upper surface of the dielectric substrate 56, and an electrode provided on the lower surface of the dielectric substrate 56. A capacitor is formed by the electrode 57 on the upper surface and the electrode on the lower surface of the dielectric substrate 56 with the dielectric substrate 56 in between. The dielectric substrate 56 is, for example, an alumina substrate or a barium titanate substrate. The electrode 57 is, for example, a metal layer such as a gold layer.

[0170] Two capacitive components 55a and 55b are provided between the lead 44a and the semiconductor chip 50a. One capacitive component 55c is provided between each of the lead 44b and the lead 44c and the semiconductor chip 50b and the semiconductor chip 50c, respectively.

[0171] The bonding wire 61 electrically connects the lead 44a and the electrode 57 of the capacitive component 55a. The bonding wire 62 electrically connects the electrode 57 of the capacitive component 55a and the electrode 57 of the capacitive component 55b. The bonding wire 63 electrically connects the electrode 57 of the capacitive component 55b and the pad 52 of the semiconductor chip 50a. The bonding wire 64 electrically connects the lead 44b (and the lead 44c) and the electrode 57 of the capacitive component 55c. The bonding wire 65 electrically connects the electrode 57 of the capacitive component 55c and the pad 52 of the semiconductor chip 50b (and the semiconductor chip 50c). The bonding wires 66 respectively electrically connect the pads 53 of the semiconductor chips 50a to 50c and the leads 45a to 45c. The bonding wires 61 to 66 are metal wires such as gold wires or aluminum wires, etc.

[0172] The bonding wires 61 to 65 respectively correspond to Figure 13 the inductors L1 to L5. The capacitive components 55a to 55c respectively correspond to Figure 13 the capacitors C1 to C3. Thus, the bonding wires 61 to 63, the capacitive component 55a, and the capacitive component 55b form a second-stage matching circuit 30a, and the bonding wire 64, the bonding wire 65, and the capacitive component 55c form a first-stage matching circuit 30b.

[0173] [Modification Example 1 of Embodiment 3]

[0174] Figure 17 is a top view of the semiconductor device of Modification Example 1 of Embodiment 3. As Figure 17As shown, in the semiconductor device 108 of Modification 1 of Embodiment 3, a capacitive component 55a and a capacitive component 55b are provided between the lead 44c and the semiconductor chip 50c. A bonding wire 61 electrically connects the lead 44c and the electrode 57 of the capacitive component 55a. A bonding wire 63 electrically connects the electrode 57 of the capacitive component 55b and the pad 52 of the semiconductor chip 50c. Other configurations are the same as those of Embodiment 3 Figure 16 and will not be described herein.

[0175] According to Embodiment 3 and its Modification 1, as Figure 16 and Figure 17 shown, the semiconductor chip 50a (first semiconductor chip) includes a main amplifier 10, the semiconductor chip 50b (second semiconductor chip) includes a peak amplifier 12, and the semiconductor chip 50c (third semiconductor chip) includes a peak amplifier 14.

[0176] Capacitors C1 to C3 respectively correspond to the capacitive components 55a to 55c and are mounted on the base 41. The first end of the capacitor C1 is electrically connected to the base 41. The inductor L1 corresponds to the bonding wire 61. The first end of the inductor L1 is electrically connected to the lead 44a (first input lead), and the second end of the inductor L1 is electrically connected to the second end of the capacitor C1. The inductor L2 corresponds to the bonding wire 62. The first end of the inductor L2 is electrically connected to the second end of the capacitor C1, and the second end of the inductor L2 is electrically connected to the second end of the capacitor C2. The inductor L3 corresponds to the bonding wire 63. The first end of the inductor L3 is electrically connected to the second end of the capacitor C2, and the second end of the inductor L3 is electrically connected to the pad 52 (input pad) of the semiconductor chip 50a. The inductor L4 corresponds to the bonding wire 64. The first end of the inductor L4 is electrically connected to the lead 44b (second input lead), and the second end of the inductor L4 is electrically connected to the second end of the capacitor C3. The inductor L5 corresponds to the bonding wire 65. The first end of the inductor L5 is electrically connected to the second end of the capacitor C3, and the second end of the inductor L5 is electrically connected to the pad 52 (input pad) of the semiconductor chip 50b.

[0177] Accordingly, the matching circuit 30 can be configured as a two-stage matching circuit 30a, and the matching circuit 31 can be configured as a one-stage matching circuit 30b. As a result, the characteristics of the Doherty amplifier circuits 102 and 104 of Embodiment 1 and Embodiment 2 can be improved.

[0178] Although a three-way Doherty amplifier circuit has been described as an example, a two-way Doherty amplifier circuit without the peak amplifier 14 and the matching circuit 32 may also be used. In addition, an N-way Doherty amplifier circuit with N being 4 or more may be used. In this case, only N - 1 peak amplifiers need to be provided.

[0179] The embodiments disclosed herein should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown by the claims, rather than by the foregoing description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A Doherty amplifier circuit, comprising: a distributor for distributing an input signal inputted into a first signal and a second signal; a main amplifier, amplifying the first signal and outputting the amplified signal as a fourth signal; a first peak amplifier, amplifying the second signal and outputting the amplified signal as a fifth signal; a synthesizer, which synthesizes the fourth signal and the fifth signal, and outputs the synthesized signal as an output signal to an output terminal; A first matching circuit connected between the distributor and the main amplifier; as well as A second matching circuit is connected between the distributor and the first peak amplifier. In an operating frequency band, an absolute value of a return loss when viewed from the distributor toward the second matching circuit is greater than an absolute value of a return loss when viewed from the distributor toward the first matching circuit.

2. The Doherty amplifier circuit according to claim 1, wherein: At a frequency twice the center frequency of the operating frequency band, the impedance when looking from the main amplifier to the first matching circuit is capacitive, At a frequency twice the center frequency, the impedance when looking from the first peak amplifier toward the second matching circuit is inductive.

3. The Doherty amplifier circuit according to claim 1 or 2, wherein: The first matching circuit is a two-stage matching circuit including a first inductor, a second inductor, a third inductor, a first capacitor, and a second capacitor, wherein a first end of the first inductor is electrically connected to the distributor and a second end of the first inductor is electrically connected to a first node, a first end of the second inductor is electrically connected to the first node and a second end of the second inductor is electrically connected to a second node, a first end of the third inductor is electrically connected to the second node and a second end of the third inductor is electrically connected to the main amplifier, the first capacitor is shunt-connected to the first node, and the second capacitor is shunt-connected to the second node. The second matching circuit is a first-level matching circuit including a fourth inductor, a fifth inductor and a third capacitor, wherein a first end of the fourth inductor is electrically connected to the distributor and a second end of the fourth inductor is electrically connected to a third node, a first end of the fifth inductor is electrically connected to the third node and a second end of the fifth inductor is electrically connected to the first peak amplifier, and the third capacitor is shunt-connected to the third node.

4. The Doherty amplifier circuit according to claim 3, wherein: In the operating frequency band, a ratio of an absolute value of a second impedance when viewed from the first inductor toward the first node to an absolute value of a first impedance when viewed from the third inductor toward the main amplifier is set to a first ratio, a ratio of an absolute value of a third impedance when viewed from the distributor toward the first inductor to the absolute value of the second impedance is set to a second ratio, a ratio of an absolute value of a fifth impedance when viewed from the fourth inductor toward the third node to an absolute value of a fourth impedance when viewed from the fifth inductor toward the first peak amplifier is set to a third ratio, and a ratio of an absolute value of a sixth impedance when viewed from the distributor toward the fourth inductor to the absolute value of the fifth impedance is set to a fourth ratio, At this time, the ratio of the first ratio to the second ratio is greater than the ratio of the third ratio to the fourth ratio.

5. The Doherty amplifier circuit according to claim 4, wherein: The first ratio is greater than the second ratio.

6. The Doherty amplifier circuit according to claim 1 or 2, comprising: a second peak amplifier, amplifying the third signal and outputting the amplified signal as a sixth signal; and A third matching circuit is connected between the distributor and the second peak amplifier. The input power of the input signal for the second peak amplifier to be turned on is greater than the input power of the input signal for the first peak amplifier to be turned on, The distributor distributes the input signal into the first signal, the second signal, and the third signal, The synthesizer synthesizes the fourth signal, the fifth signal, and the sixth signal, and outputs the synthesized signal as the output signal to the output terminal.

7. The Doherty amplifier circuit according to claim 6, wherein: In the operating frequency band, an absolute value of a return loss when looking from the distributor toward the third matching circuit is greater than an absolute value of a return loss when looking from the distributor toward the first matching circuit.

8. The Doherty amplifier circuit according to claim 7, wherein: At a frequency twice the center frequency of the operating frequency band, the impedance when looking from the main amplifier to the first matching circuit is capacitive, At a frequency twice the center frequency, the impedance when looking from the first peak amplifier to the second matching circuit is inductive, At a frequency twice the center frequency, the impedance when looking from the second peak amplifier toward the third matching circuit is inductive.

9. The Doherty amplifier circuit according to claim 6, wherein: In the operating frequency band, an absolute value of a return loss when viewed from the distributor toward the third matching circuit is smaller than an absolute value of a return loss when viewed from the distributor toward the second matching circuit.

10. The Doherty amplifier circuit according to claim 9, wherein: At a frequency twice the center frequency of the operating frequency band, the impedance when looking from the main amplifier to the first matching circuit is capacitive, At a frequency twice the center frequency, the impedance when looking from the first peak amplifier to the second matching circuit is inductive, At a frequency twice the center frequency, the impedance when looking from the second peak amplifier toward the third matching circuit is capacitive.

11. A semiconductor device, which is a semiconductor device for a Doherty amplifier circuit, comprising: A package having a base, a first input lead, and a second input lead; A first semiconductor chip is mounted on the base, and includes a main amplifier for amplifying a first signal obtained by dividing an input signal; A second semiconductor chip mounted on the base, the second semiconductor chip having a first peak amplifier for amplifying a second signal obtained by dividing the input signal; A first capacitor is mounted on the base, and a first end of the first capacitor is electrically connected to the base; A second capacitor is mounted on the base, and a first end of the second capacitor is electrically connected to the base; A third capacitor is mounted on the base, and a first end of the third capacitor is electrically connected to the base; a first inductor, wherein a first end of the first inductor is electrically connected to the first input lead, and a second end of the first inductor is electrically connected to the second end of the first capacitor; a second inductor, wherein a first end of the second inductor is electrically connected to the second end of the first capacitor, and a second end of the second inductor is electrically connected to the second end of the second capacitor; a third inductor, a first end of the third inductor being electrically connected to the second end of the second capacitor, and a second end of the third inductor being electrically connected to an input pad of the first semiconductor chip; a fourth inductor, wherein a first end of the fourth inductor is electrically connected to the second input lead, and a second end of the fourth inductor is electrically connected to the second end of the third capacitor; as well as A fifth inductor, wherein a first end of the fifth inductor is electrically connected to the second end of the third capacitor, and a second end of the fifth inductor is electrically connected to an input pad of the second semiconductor chip.

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