A method for manufacturing a high-frequency circuit board with a mesh hollow blind slot

Abstract

The invention discloses a method for manufacturing a high-frequency circuit board with a mesh hollow blind slot, comprising the following steps: L1-L2 inner layer process, L3-L4 layer, L5-L6 layer, and L7-L8 layer resistance process; making blind vias in the L1-L8 layer after one lamination; making inner layer circuits in the L9-L10 layer, L11-L12 layer, L13-L14 layer, and L15-L16 layer; laminating the L1-L8 layer and the L9-16 layer twice to make blind vias in the L1-16 layer; making a mesh hollow structure on the L17-18 layer, and drilling air holes on the L19-20 layer; and laminating the L1-16 layer, the L17-18 layer, and the L19-20 layer three times to make blind vias in the L1-20 layer. The present invention designs a mesh hollow structure in the L17-18 layers to form a three-dimensional heat dissipation channel, thereby improving the heat dissipation performance of the multilayer board and reducing the volume of the PCB, which contributes to the miniaturization and lightweight design of electronic equipment; air holes are drilled in the inactive area of the L19-20 layers to release the gas in the board during the pressing process, avoiding pressing delamination due to unclean air exhaust in the mesh position.

Description

Technical Field

[0001] The invention belongs to the technical field of printed circuit boards, and in particular relates to a method for manufacturing a high-frequency circuit board with a mesh hollow blind groove. Background Art

[0002] With the increasing demand for high-performance printed circuit boards in phased array radars, communications equipment, and aerospace electronics systems, multi-layer blind and buried vias, buried resistors, and mesh structures have become key development directions. Traditional multi-layer PCBs significantly improve circuit density, signal transmission quality, and heat dissipation performance by combining multi-level blind vias, buried resistors, and mesh hollow structures, especially for microwave equipment that requires high-frequency signal integrity and mechanical stability.

[0003] In the PCB industry, the manufacturing process for multi-level blind and buried vias (BMVs) with embedded resistors typically utilizes a production process consisting of "inner layer drilling, board electrical and resin plugging, and backdrilling." Multiple copper plating and plugging procedures increase product weight and prevent the effective dissipation of heat generated during use, impacting product performance. Existing processes for achieving these multi-level blind and buried vias in a mesh-like structure still have drawbacks and deficiencies, failing to meet the performance, lightweight, and heat dissipation requirements of radar products.

[0004] The following objective problems exist when using traditional crafts:

[0005] Lamination process defects: When laminating a thin core board (such as 0.127mm) with a mesh hollow area (such as Layer 17-18), insufficient structural support can easily cause the board to sag, resulting in delamination and layer deviation. After high temperature, it will crack and destroy the entire circuit pattern, affecting product performance.

[0006] Defects of the resin plugging process: Since the hollow layers (such as Layer 17-18) need to be plugged with resin, it is easy to cause explosion and delamination after the plugging is subjected to high-temperature baking, resulting in insufficient resin filling; at the same time, when making circuit pads after backfill plating, due to water vapor in the holes, it may cause pad protrusions, welding failure and water vapor accumulation, reducing insulation performance and long-term stability.

[0007] Defects in the copper electroplating process: The hollow area is easy to hide the chemical solution during the chemical copper plating and electroplating process, causing plating defects (abnormal diffusion of the metallized area), interfering with the circuit impedance control and deteriorating the high-frequency signal transmission characteristics.

[0008] In addition, the traditional processing process relies on multiple copper plating plugging and back drilling designs, which increases the weight of the board and blocks the heat dissipation channels, making it difficult to meet the strict requirements of radar equipment for lightweight, efficient heat dissipation and wide temperature range stability. Summary of the Invention

[0009] In order to solve the above problems, the present invention provides a method for manufacturing a high-frequency circuit board with a mesh hollow blind slot, which can improve the stability of the blind hole copper, avoid the occurrence of burst holes and delamination, and improve the quality and stability of the circuit board.

[0010] To this end, the technical solution of the present invention is: a method for manufacturing a high-frequency circuit board with a mesh hollow blind slot, comprising the following steps:

[0011] S1. Use a high-frequency board to make L1 / L2 layers, L3 / L4 layers, L5 / L6 layers, and L7 / L8 layers, wherein a resistor layer structure is embedded in the L3 / L4 layers, L5 / L6 layers, and L7 / L8 layers;

[0012] S2. Place the first prepreg between the L1 / L2 layer, the L3 / L4 layer, the L5 / L6 layer, and the L7 / L8 layer, rivet them together, and then perform heat pressing to obtain the L1 / L8 layer structure;

[0013] S3, back-drill blind vias on the L1 / L8 layer and plug the vias with resin;

[0014] S4. Use epoxy boards to make L9 / L10 layers, L11 / L12 layers, L13 / L14 layers, and L15 / L16 layers, overlap them with the second prepreg, and press them together to obtain an L9 / L16 layer structure;

[0015] S5, riveting the L1 / L8 layer, the third prepreg, and the L9 / L16 layer and then performing heat pressing to obtain the L1 / L16 layer structure;

[0016] S6. Fabricate outer layer circuits on the L1 / L16 layer, and the outer layer circuit fabrication process includes copper reduction and copper deposition processes. Before the copper reduction and copper deposition processes are performed, seal the blind holes of the L1 / L8 layer with high-temperature tape;

[0017] S7. Use a high-frequency board to make the L17 / L18 layer, mill a mesh hollow structure on the surface of the L17 / L18 layer, and make circuits;

[0018] S8. Use high-frequency boards to make the L19 / L20 layers, and process ventilation holes on the edges of the L19 / L20 layers and in areas without circuits.

[0019] S9, pressing the L1 / L16 layer, the L17 / L18 layer, and the L19 / L20 layer, wherein a release film and a fourth prepreg are provided on both sides of the L17 / L18 layer, and pressing to obtain an L1 / L20 layer structure;

[0020] S10. Fabricate outer layer circuits on the L1 / L20 layer, and the outer layer circuit fabrication process includes copper reduction and copper deposition processes. Before performing the copper reduction and copper deposition processes, seal the blind holes of the L1 / L8 layer and the L1 / L16 layer with high temperature tape.

[0021] On the basis of the above scheme and as a preferred scheme of the above scheme: in step S1, the processing steps of the L3 / L4 layer, the L5 / L6 layer, and the L7 / L8 layer include: high-frequency board cutting → board baking → chemical copper plating → inner layer drilling → first inner layer circuit production → first acid etching → resistor layer production → second acid etching → first inner layer AOI → second inner layer circuit production → third alkaline etching → second inner layer AOI → transfer and pressing; wherein, the resistance value of the resistor layer is between 57.5Ω±2.5Ω and 115Ω±5Ω.

[0022] On the basis of the above scheme and as a preferred scheme of the above scheme: the glue content of the first prepreg and the fourth prepreg is 40%, the glue content of the second prepreg is 77%, and the glue content of the third prepreg is 69%.

[0023] On the basis of the above scheme and as a preferred scheme of the above scheme: a double-layer first cured sheet is arranged between the L1 / L2 layer, the L3 / L4 layer, the L5 / L6 layer, and the L7 / L8 layer; a double-layer second cured sheet is arranged between the L9 / L10 layer, the L11 / L12 layer, the L13 / L14 layer, and the L15 / L16 layer; a double-layer third semi-cured sheet is arranged between the L1 / L8 layer and the L9 / L16 layer; a single-layer fourth semi-cured sheet is arranged between the L1 / L16 layer, the L17 / L18 layer, and the L19 / L20 layer.

[0024] On the basis of the above scheme and as a preferred scheme of the above scheme: the outer layer circuit of the L1 / L16 layer described in step S6, the processing steps are: sealing the blind holes of the L1 / L8 layer with high-temperature tape → reducing copper, tearing off the high-temperature tape after copper reduction → inner layer drilling → plasma treatment → sealing the blind holes of the L1 / L8 layer with high-temperature tape → chemical copper deposition, tearing off the high-temperature tape after chemical copper deposition → electroplating thickening → back drilling → outer layer etching → etching inspection → resin plugging → inner layer circuit production → acid etching → inner layer AOI → transfer and pressing.

[0025] On the basis of the above scheme and as a preferred scheme of the above scheme: the processing steps of the L17 / L18 layer in step S7 are: high-frequency board cutting → baking board → inner layer drilling → milling out a mesh hollow structure → acid etching → inner layer AOI.

[0026] On the basis of the above scheme and as a preferred scheme of the above scheme: the processing steps of the L19 / L20 layer in step S8 are: high-frequency board cutting → board baking → inner layer drilling of air holes → inner layer circuit production → acid etching → inner layer AOI.

[0027] On the basis of the above scheme and as a preferred scheme of the above scheme: the processing steps of the outer layer circuit described in step S10 are: sealing the blind holes of the L1 / L8 layer and the L1 / L16 layer with high-temperature tape → reducing copper on the substrate, tearing off the high-temperature tape after copper reduction → drilling the outer layer → plasma treatment → sealing the blind holes of the L1 / L8 layer and the L1 / L16 layer with high-temperature tape → copper deposition, tearing off the high-temperature tape after copper deposition → back drilling → outer layer etching → etching inspection → resin plugging → sealing the blind holes of the L1 / L8 layer and the L1 / L16 layer with high-temperature tape → reducing copper on the substrate → copper deposition, tearing off the high-temperature tape after copper deposition → pulse electroplating → making outer layer circuits → acid etching → outer layer AOI → measuring resistance → semi-finished product testing → solder mask → text → surface treatment → finished product testing → molding → finished product inspection → packaging.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] A mesh hollow structure is designed on the L17-18 layer to form a three-dimensional heat dissipation channel, which improves the heat dissipation performance of the multi-layer board. At the same time, it reduces the volume of the PCB and the number and length of some unnecessary wiring layers, which helps to miniaturize and lightweight the design of electronic equipment. It is more suitable for the field of electronic radar and is lighter than traditional PCBs.

[0030] Drill ventilation holes in the ineffective areas of the L19-20 layer. The ventilation holes can cover all the ineffective areas of the inner layer and release the gas in the board during the pressing process to avoid lamination due to unclean air discharge in the mesh position.

[0031] Using a fourth curing sheet and release film with 40% adhesive content on both sides of the L17-18 layer can prevent the mesh area from sinking after lamination and the adhesive from flowing from the air holes to the board surface, resulting in uneven adhesive flow and residual adhesive accumulation.

[0032] During the circuit board manufacturing process, a combination of two blind holes and three back drilling processes is used. Compared with the conventional blind hole, which requires one back drilling on the front side and three back drilling on the back side after the buried resistance layer and the mesh layer are pressed together, the choice of two blind holes and three back drilling is a complementary combination, which can reduce the difficulty of the processing technology of the two and reduce the process flow, and ultimately realize the cross blind hole structure design.

[0033] Before copper reduction and copper deposition, high-temperature tape is applied to isolate the chemical solution from penetrating into the blind hole, thus avoiding corrosion of the hard gold layer and void defects in the hole, and ensuring the uniformity of the copper thickness in the hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural schematic diagram of the present invention.

[0035] Marked in the figure: L1 / L2 layer 1, L3 / L4 layer 2, L5 / L6 layer 3, L7 / L8 layer 4, L9 / L10 layer 5, L11 / L12 layer 6, L13 / L14 layer 7, L15 / L16 layer 8, L17 / L18 layer 9, L19 / L20 layer 10, first semi-cured sheet 11, second semi-cured sheet 12, third semi-cured sheet 13, fourth semi-cured sheet 14, release film 15. DETAILED DESCRIPTION

[0036] The mesh hollow blind slot high-frequency circuit board described in this embodiment is a 20-layer circuit board, which is divided into a high-speed transmission layer (L1 / L8 layer), a normal signal layer (L9 / L16 layer), a hollow layer (L17 / L18 layer), and a breathable layer (L19 / L20 layer).

[0037] The specific production method is as follows:

[0038] S1. Use a high-frequency board to make L1 / L2 layer 1, L3 / L4 layer 2, L5 / L6 layer 3, and L7 / L8 layer 4, wherein a resistor layer structure is embedded in L3 / L4 layer 2, L5 / L6 layer 3, and L7 / L8 layer 4.

[0039] The high-frequency board used for the L1 / L2 layer 1 is Tyconic TSM-DS3-0100-CL1 / CL1, with a thickness of 0.254mm. The high-frequency board used for the L3 / L4 layer 2, L5 / L6 layer 3, and L7 / L8 layer 4 is Tyconic TSM-DS3-0100-C1 / C1, with a square resistance of 50 and a thickness of 0.254mm.

[0040] The inner layer circuits are made directly after cutting. The inner layer adopts LDI imaging technology. The free expansion and contraction function of LDI avoids the defects of insufficient positioning accuracy of traditional exposure machines. The positioning accuracy can reach within 20um to meet the compact and high-density interconnection characteristics of the product.

[0041] The processing steps of L1 / L2 layer 1 are: cutting → baking → inner layer drilling → inner layer circuit → acid etching → inner layer AOI → transfer and pressing;

[0042] The processing steps for L3 / L4 layer 2, L5 / L6 layer 3, and L7 / L8 layer 4 are: cutting → baking plate → copper → inner layer drilling → inner layer circuit → acid etching → bubble resistor → acid etching → inner layer AOI → inner layer circuit → alkaline etching → inner layer AOI → transfer and pressing.

[0043] The inner resistor structure of layers L3-L8 is particularly important for resistor etching. Etching parameters for the resistor layer: Turn off the second stage of etching and adjust the alkaline etching speed to 3m / min to protect the resistor layer from damage. After stripping the film, rinse the inner layer with pure water and measure the resistor value. Control the resistor value between 57.5Ω±2.5Ω and 115Ω±5Ω, and pay attention to protecting the resistor.

[0044] Operation process: Hold the board with both hands to prevent the substrate from breaking during the circulation process. Scratches, chemical contamination, moisture and other problems are not allowed. The gold plating in the blind hole, copper reduction, copper precipitation and other processes involving chemicals must be protected with tape.

[0045] S2. Place two first prepregs 11 between the L1 / L2 layer 1, the L3 / L4 layer 2, the L5 / L6 layer 3, and the L7 / L8 layer 4, rivet them together, and then perform heat pressing to obtain the L1 / L8 layer structure.

[0046] The first prepreg 11 has a model of Taikangli FR-28-0040-50, a size of 457*610, a thickness of 102 microns, a moisture absorption rate of 2.74%, a glue content of 40%, a curing temperature of 188° C., and contains halogen.

[0047] The pressing heating rate is controlled within the range of 1.5±0.5℃ / min (material temperature is in the range of 80~140℃), the maximum pressure is 420PSI, and high pressure is switched when the outer layer material temperature is 80-100℃. The curing temperature is: ≥195℃, and the curing time is ≥60min.

[0048] S3. For the L1 / L8 layer after lamination, the processing flow is: lamination → etching → inner layer drilling → plasma → copper deposition → drilling → outer layer etching → etching inspection → resin plugging → inner layer circuit → inner layer AOI → transfer to lamination.

[0049] After one-time lamination, blind vias are made in the L1-L8 layers. The key control measures for back drilling are STUB of 0.1-0.2mm, back drilling accuracy (hole-to-line distance ≤ 0.1mm), and resin plug hole fullness reaching 100%.

[0050] S4. Use epoxy board to make L9 / L10 layer 5, L11 / L12 layer 6, L13 / L14 layer 7, and L15 / L16 layer 8. Measure the expansion and contraction of L1-L8 layers and take the average value to make inner layer circuits of L9 / L10 layer 5, L11 / L12 layer 6, L13 / L14 layer 7, and L15 / L16 layer 8. After overlapping with the second prepreg 12, press together to obtain the L9 / L16 layer structure.

[0051] The epoxy board is Shengyi S1000-2M FR-4, with a thickness of 0.1 mm, a glass transition temperature of 180° C., a size of 41*49 inches, 1 / 1 oz (copper-free), and halogen-resistant.

[0052] The processing flow of L9 / L10 layer 5, L11 / L12 layer 6, L13 / L14 layer 7, and L15 / L16 layer 8 is: cutting → baking → inner layer drilling → inner layer circuit → acid etching → inner layer AOI → transfer and pressing;

[0053] The processing flow of the L9 / L16 layer is as follows: two second prepregs 12 are overlapped between the L9 / L10 layer 5, the L11 / L12 layer 6, the L13 / L14 layer 7, and the L15 / L16 layer 8. The second prepreg model is Shengyi S1000-2MB, with a size of 520*413, a thickness of 60 microns, a dielectric constant of 3.55, a glue content of 77%, a glass transition temperature of 180°C, and halogen.

[0054] S5. Rivet the L1 / L8 layer, the third prepreg 13, and the L9 / L16 layer and then perform hot pressing to obtain an L1 / L16 layer structure; the third prepreg 13 has a double-layer structure. The model of the third prepreg 13 is Tenghui VT-447, with a size of 500*620, a thickness of 89 microns, a dielectric constant of 3.6, a glue content of 69%, and halogen.

[0055] S6. Fabricate outer layer circuits on the L1 / L16 layer, and the outer layer circuit fabrication process includes copper reduction and copper deposition processes. Before the copper reduction and copper deposition processes are performed, seal the blind holes of the L1 / L8 layer with high-temperature tape;

[0056] The outer layer circuitry of the L1 / L16 layers is fabricated as follows: lamination → copper reduction (with blind vias protected by tape) → inner layer drilling → plasma → copper plating (with blind vias protected by tape) → back drilling → outer layer etching → etch inspection → resin plugging → inner layer circuitry → acid etching → inner layer AOI → lamination. During back drilling (with a controlled stub of 0.1-0.2mm), the resin plugging achieves 100% fill.

[0057] S7. Use a high-frequency board to make L17 / L18 layer 9, mill a mesh hollow structure on the surface of L17 / L18 layer 9, and make circuits; the high-frequency board model used for L17 / L18 layer 9 is Taiconic TSM-DS3-0100-CL1 / CL1, with a thickness of 0.254mm.

[0058] The processing flow of L17 / L18 layer 9 is: cutting → baking → inner layer drilling → forming (milling mesh hollow structure) → acid etching → inner layer AOI → transfer and pressing.

[0059] S8. Use a high-frequency board to make L19 / L20 layer 10, and process ventilation holes on the edge of the L19 / L20 layer 10 board and the non-circuit area; the high-frequency board model used for L19 / L20 layer 10 is Taiconic TSM-DS3-0100-CL1 / CL1, with a thickness of 0.254mm.

[0060] The processing flow for L19 / L20 layer 10 is: cutting → baking → inner layer drilling (drilling vent holes) → inner layer circuitry → acid etching → inner layer AOI → transfer to lamination. The vent holes cover all inactive areas of the inner layer, releasing air from the board during lamination and preventing lamination due to incomplete air evacuation at the mesh locations.

[0061] S9, press the L1 / L16 layer, L17 / L18 layer 9 and L19 / L20 layer 10, wherein the release film 15 and the fourth semi-cured sheet 14 are set on both sides of the L17 / L18 layer 9, and the L1 / L20 layer structure is obtained by pressing; the L1-L20 layers are pressed using the fourth semi-cured sheet 14 and the release film 15 with semi-flowing glue to prevent the mesh area from sinking after pressing and the glue flowing from the air holes to the board surface, resulting in uneven glue flow and residual glue accumulation.

[0062] Based on the material properties of the circuit board and mesh structure, to prevent dents and cracks in the inner lamination and mesh surface, the fourth prepreg sheet was selected from Taikangli FR-28-0040-50, which has strong adhesion, high temperature resistance, and excellent electrical properties. It measures 457 x 610 mm, is 102 microns thick, has a moisture absorption rate of 2.74%, contains 40% glue, and cures at 188°C. It is halogen-free. Temperature and humidity control: Maintaining appropriate temperature and humidity in the production environment prevents overly rapid or uneven curing of the glue. Controlling the amount and uniformity of glue flow: By adjusting the parameters of the glue dispensing equipment, ensure that the PP evenly covers the contact surface between the circuit board and the mesh structure, avoiding voids, excessive glue accumulation, and glue flow.

[0063] S10. Make outer layer circuits on L1 / L20 layers. The processing steps are: lamination → substrate copper reduction (seal the blind holes of L1 / L8 and L1 / L16 layers with high temperature tape before copper reduction, and tear off the high temperature tape after copper reduction) → outer layer drilling → plasma → copper deposition (seal the blind holes of L1 / L8 and L1 / L16 layers with high temperature tape before copper deposition, and tear off the high temperature tape after copper deposition) → back drilling → outer layer etching → etching inspection → resin plugging → substrate copper reduction (seal the blind holes of L1 / L8 and L1 / L16 layers with high temperature tape before copper reduction) → copper deposition (keep the blind holes of L1 / L8 and L1 / L16 layers sealed with high temperature tape, and tear off the high temperature tape after copper deposition) → pulse plating → outer layer circuits → acid etching → outer layer AOI → resistance measurement → semi-finished product testing → solder mask → text → surface treatment → finished product testing → molding → finished product inspection → packaging.

[0064] The matters needing attention when making this embodiment are as follows:

[0065] The produced circuit board has 20 layers, a total board thickness of 5.8mm, an inner layer copper thickness of 35um, and a large amount of glue filling (the residual copper rate of each layer is 40%), which is prone to uneven glue flow and causes voids in the board. Therefore, silicone pad-type pressing is used in the board thickness pressing to make the board thickness more uniform. The thickness of the dielectric layer of the second outer layer (L1-L8, L1-L16 layers) is controlled to 0.1mm±10%, reducing the difficulty of subsequent blind hole infiltration of chemicals and regulating electroplating.

[0066] The circuit board produced in this embodiment is a twenty-layer mixed-press board: a TSM-DS3+FR-4 PCB product. The inner layer wiring is relatively dense, with a minimum spacing of 5 mils, and the production method adopts a new process method: layered blind hole production (three blind and one buried + three pressings). During the riveting process, interlayer alignment becomes a top priority. Misalignment will cause a short circuit. For this reason, a high-precision electromagnetic hot-melt machine is first used to rivet the stacked layers together, and then rivets are used for secondary reinforcement. This prevents sliding or offset during the hot pressing process, ensuring the accuracy of interlayer alignment.

[0067] The minimum hole diameter during drilling is 0.35mm. A new coated drill bit is used with drilling parameters: speed S110, feed F0.9, retract R12.7, and life N (hole) 400 to complete through-hole production. The inner layer copper thickness of this product is 1 ounce, the finished product is 1.5 ounces, and the total board thickness is 5.8mm. During the drilling process, it is easy to cause tool breakage, rough hole walls, and flashing. For this reason, the middle of the hole plate is hollowed out by etching in the inner layer design, which can effectively reduce the copper thickness and reduce drill bit wear, improve quality, and achieve clean chip removal of the drill bit, without needle breakage, hole roughness <30um, and no nail head (<1 / 2 of the copper thickness).

[0068] After the blind vias are created through a single press, a second press cycle focuses on controlling the copper requirements for the blind vias. Layers of tape are applied to protect the blind vias, and the tape is removed during copper plating to ensure the holes meet copper requirements. All blind vias treated with chemical treatments must be protected with tape. After the third press cycle, the total board thickness is 5.8mm, with a minimum hole diameter of 0.35mm. This ensures that the copper in the vias meets customer requirements, while the surface copper thickness meets etching requirements. Pulse plating is used to improve the through-hole capability of the chemical.

[0069] After the outer layer is etched, an intermediate test process is added to test the network connectivity; after the product is finished, thermal shock test, hot and cold cycle test, reflow soldering test, section measurement of blind and buried vias / through hole copper thickness, surface copper thickness, aperture, molding size, etc. are performed according to GJB362C-2021 and QJ831B-2011; appearance problems are checked according to GJB362C-2021 and QJ831B-2011.

[0070] During the three pressings, the expansion and shrinkage control is as follows: first, the inner layer graphics of the L1-L8 layers are pre-enlarged by 0.08%. After the first pressing is completed, the actual expansion and shrinkage of the "L1-L8" sub-layers are measured. According to the average expansion and shrinkage of the sub-layers, the drilling and circuit production data of the "L9-L16" layers are calculated to ensure that the expansion and shrinkage of each inner layer board in the second pressing is consistent, meeting the requirement of no offset between the layers.

[0071] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a high-frequency circuit board with a mesh hollow blind slot, characterized by: The following steps are involved: S1. Use a high-frequency board to make L1 / L2 layers, L3 / L4 layers, L5 / L6 layers, and L7 / L8 layers, wherein a resistor layer structure is embedded in the L3 / L4 layers, L5 / L6 layers, and L7 / L8 layers; S2. Place the first prepreg between the L1 / L2 layer, the L3 / L4 layer, the L5 / L6 layer, and the L7 / L8 layer, rivet them together, and then perform heat pressing to obtain the L1 / L8 layer structure; S3, back-drill blind vias on the L1 / L8 layer and plug the vias with resin; S4. Use epoxy boards to make L9 / L10 layers, L11 / L12 layers, L13 / L14 layers, and L15 / L16 layers, overlap them with the second prepreg, and press them together to obtain an L9 / L16 layer structure; S5, riveting the L1 / L8 layer, the third prepreg, and the L9 / L16 layer and then performing heat pressing to obtain the L1 / L16 layer structure; S6. Fabricate outer layer circuits on the L1 / L16 layer, and the outer layer circuit fabrication process includes copper reduction and copper deposition processes. Before the copper reduction and copper deposition processes are performed, seal the blind holes of the L1 / L8 layer with high-temperature tape; S7. Use a high-frequency board to make the L17 / L18 layer, mill a mesh hollow structure on the surface of the L17 / L18 layer, and make circuits. The mesh hollow structure is used to form a three-dimensional heat dissipation channel and reduce the volume of the PCB; S8. Use high-frequency boards to make the L19 / L20 layers, and process ventilation holes on the edges of the L19 / L20 layers and in areas without circuits. S9, pressing the L1 / L16 layer, the L17 / L18 layer, and the L19 / L20 layer, wherein a release film and a fourth prepreg are provided on both sides of the L17 / L18 layer, and pressing to obtain an L1 / L20 layer structure; S10. Fabricate outer layer circuits on the L1 / L20 layer, and the outer layer circuit fabrication process includes copper reduction and copper deposition processes. Before performing the copper reduction and copper deposition processes, seal the blind holes of the L1 / L8 layer and the L1 / L16 layer with high-temperature tape to prevent the chemical solution from penetrating into the blind holes.

2. The method for manufacturing a high-frequency circuit board with a mesh hollow blind slot according to claim 1, characterized in that: In step S1, the processing steps of the L3 / L4 layer, the L5 / L6 layer, and the L7 / L8 layer include: high-frequency board cutting → board baking → chemical copper plating → inner layer drilling → first inner layer circuit production → first acid etching → resistor layer production → second acid etching → first inner layer AOI → second inner layer circuit production → third alkaline etching → second inner layer AOI → transfer and pressing; wherein the resistance value of the resistor layer is between 55Ω and 120Ω.

3. The method for manufacturing a high-frequency circuit board with a mesh hollow blind slot according to claim 1, characterized in that: The first prepreg and the fourth prepreg have a glue content of 40%, the second prepreg has a glue content of 77%, and the third prepreg has a glue content of 69%.

4. The method for manufacturing a high-frequency circuit board with a mesh hollow blind slot according to claim 3, characterized in that: A double-layer first cured sheet is arranged between the L1 / L2 layer, the L3 / L4 layer, the L5 / L6 layer, and the L7 / L8 layer; a double-layer second cured sheet is arranged between the L9 / L10 layer, the L11 / L12 layer, the L13 / L14 layer, and the L15 / L16 layer; a double-layer third semi-cured sheet is arranged between the L1 / L8 layer and the L9 / L16 layer; a single-layer fourth semi-cured sheet is arranged between the L1 / L16 layer, the L17 / L18 layer, and the L19 / L20 layer.

5. The method for manufacturing a high-frequency circuit board with a mesh hollow blind slot according to claim 1, characterized in that: The outer layer circuit of the L1 / L16 layer described in step S6 is processed as follows: seal the blind hole of the L1 / L8 layer with high temperature tape → reduce copper, tear off the high temperature tape after copper reduction → drill the inner layer → plasma treatment → seal the blind hole of the L1 / L8 layer with high temperature tape → chemical copper deposition, tear off the high temperature tape after chemical copper deposition → electroplating and thickening → back drilling → outer layer etching → etching inspection → resin plugging → inner layer circuit production → acid etching → inner layer AOI → transfer and lamination.

6. The method for manufacturing a high-frequency circuit board with a mesh hollow blind slot according to claim 1, characterized in that: The processing steps of the L17 / L18 layer in step S7 are: high-frequency board cutting → board baking → inner layer drilling → milling out a mesh hollow structure → acid etching → inner layer AOI.

7. The method for manufacturing a high-frequency circuit board with a mesh hollow blind slot according to claim 1, characterized in that: The processing steps of the L19 / L20 layer in step S8 are: high-frequency board cutting → board baking → inner layer air hole drilling → inner layer circuit production → acid etching → inner layer AOI.

8. The method for manufacturing a high-frequency circuit board with a mesh hollow blind slot according to claim 1, characterized in that: The outer layer circuit described in step S10 has the following processing steps: sealing the blind holes of the L1 / L8 layer and the L1 / L16 layer with high temperature tape → reducing copper on the substrate, and removing the high temperature tape after reducing copper → drilling the outer layer → plasma treatment → sealing the blind holes of the L1 / L8 layer and the L1 / L16 layer with high temperature tape → copper deposition, and removing the high temperature tape after copper deposition → back drilling → outer layer etching → etching inspection → resin plugging → sealing the blind holes of the L1 / L8 layer and the L1 / L16 layer with high temperature tape → reducing copper on the substrate → copper deposition, and removing the high temperature tape after copper deposition → pulse electroplating → making outer layer circuits → acid etching → outer layer AOI → measuring resistance → semi-finished product testing → solder mask → text → surface treatment → finished product testing → molding → finished product inspection → packaging.

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