Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a substrate, a plurality of magnetic tunneling junction (MTJ) structures, and a writing structure. The MTJ structures are disposed on the substrate, and the write-in structure is disposed on the plurality of MTJ structures and is connected to the plurality of MTJ structures. The write structure includes a plurality of spin-orbital torque (SOT) patterns, and a conductive layer. The conductive layer includes a plurality of conductive layers. The plurality of SOT patterns are separated from each other, and each SOT pattern is disposed on and connected to one of the plurality of MTJ structures. The conductive layer covers the plurality of SOT patterns, is partially disposed on the plurality of SOT patterns in the vertical direction, and is partially disposed between the plurality of SOT patterns in the first horizontal direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a magnetic tunneling junction (MTJ) structure and a manufacturing method thereof. Background Art

[0002] Basically, there are two types of data memory devices used in electronic products, namely non-volatile and volatile memory devices. Magnetic random access memory (MRAM) is a non-volatile memory technology. Different from the current general standard storage devices, MRAM uses magnetism to store data instead of using charge for data storage. Generally speaking, an MRAM cell includes a data layer and a reference layer. The data layer is composed of a magnetic material, and the magnetization state of the data layer can be switched between two opposite states by applying a magnetic field, thereby storing binary information. The reference layer can be composed of a magnetized material, and its magnetization state can be locked. During a read operation, when the magnetization directions of the data layer and the reference layer are the same or different, the resistance of the MRAM cell is different, so the magnetization polarity of the data layer can be correspondingly identified. The structure of the MRAM device will vary depending on the technology used to magnetize the data layer. Currently, the more common ones are spin-transfer torque (STT)-type MRAM and spin-orbit torque (SOT)-type MRAM. STT-type MRAM and SOT-type MRAM have different advantages and disadvantages. How to improve the disadvantages of the MRAM device through structural, material, or / and manufacturing process design to enhance its productization value is an ongoing research direction for relevant professionals. Summary of the Invention

[0003] The present invention provides a semiconductor device and a manufacturing method thereof. A spin-orbit torque (SOT) pattern and a conductive layer are provided in a write structure, thereby reducing the overall resistance of the write structure while maintaining the required programming effect or / and magnetization effect, and further improving the operating performance of the semiconductor device.

[0004] An embodiment of the present invention provides a semiconductor device, including a substrate, a plurality of magnetic tunneling junction (MTJ) structures, and a writing structure. The plurality of magnetic tunneling junction structures are disposed on the substrate. The writing structure is disposed on the plurality of magnetic tunneling junction structures and connected to the plurality of magnetic tunneling junction structures. The writing structure includes a plurality of spin-orbit torque (SOT) patterns and a conductive layer. The plurality of spin-orbit torque patterns are separated from each other, and each spin-orbit torque pattern is disposed on one of the plurality of magnetic tunneling junction structures and connected to this magnetic tunneling junction structure. The conductive layer covers the plurality of spin-orbit torque patterns. The conductive layer is partially disposed on the plurality of spin-orbit torque patterns in a vertical direction and partially disposed between the plurality of spin-orbit torque patterns in a first horizontal direction.

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps. Form a plurality of magnetic tunneling junction (MTJ) structures on a substrate, and form a writing structure on the plurality of magnetic tunneling junction structures. The writing structure is connected to the plurality of magnetic tunneling junction structures, and the writing structure includes a plurality of spin-orbit torque (SOT) patterns and a conductive layer. The plurality of spin-orbit torque patterns are separated from each other, and each spin-orbit torque pattern is disposed on one of the plurality of magnetic tunneling junction structures and connected to this magnetic tunneling junction structure. The conductive layer covers the plurality of spin-orbit torque patterns. The conductive layer is partially disposed on the plurality of spin-orbit torque patterns in a vertical direction and partially disposed between the plurality of spin-orbit torque patterns in a first horizontal direction. Description of the Drawings

[0006] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0007] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0008] Figure 3 is a top-view schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0009] Figures 4 to 10 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where

[0010] Figure 5 is Figure 4 a schematic diagram of the situation after;

[0011] Figure 6 is Figure 5 a schematic diagram of the situation after;

[0012] Figure 7 For Figure 6 schematic diagram of subsequent condition;

[0013] Figure 8 For Figure 7 schematic diagram of subsequent condition;

[0014] Figure 9 For Figure 8 schematic diagram of subsequent condition;

[0015] Figure 10 For Figure 9 schematic diagram of subsequent condition.

[0016] Symbol Explanation

[0017] 10: Substrate

[0018] 12: Dielectric layer

[0019] 14: Dielectric layer

[0020] 16: Connection structure

[0021] 18: Stop layer

[0022] 20: Dielectric layer

[0023] 22: Connection structure

[0024] 22A: Barrier layer

[0025] 22B: Conductive layer

[0026] 24: Bottom electrode

[0027] 26: Reference layer

[0028] 28: Barrier layer

[0029] 30: Free layer

[0030] 32: SOT layer

[0031] 34: Capping layer

[0032] 36: Dielectric layer

[0033] 38: Dielectric layer

[0034] 40: Dielectric layer

[0035] 42: SOT material

[0036] 42P: SOT pattern

[0037] 44: Barrier material

[0038] 44A: Barrier layer

[0039] 44B: Barrier layer

[0040] 46: Conductive material

[0041] 46A: Conductive layer

[0042] 46B: Conductive layer

[0043] 48: Stop layer

[0044] 50: Dielectric layer

[0045] 90: Planarization process

[0046] 100: Semiconductor device

[0047] BS: Bottom surface

[0048] CH: Contact opening

[0049] CS: Interconnection structure

[0050] CT: Connection structure

[0051] D1: First horizontal direction

[0052] D2: Second horizontal direction

[0053] D3: Vertical direction

[0054] E1: First electrode

[0055] E2: Second electrode

[0056] MS: MTJ structure

[0057] P1: First part

[0058] P2: Second part

[0059] R1: First region

[0060] R2: Second region

[0061] TR1: First trench

[0062] TR2: Second trench

[0063] TS: Top surface

[0064] WS: Write structure Detailed implementation manners

[0065] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the present invention. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those of ordinary skill in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the present invention.

[0066] Before further describing the embodiments, the following first explains specific terms used throughout the text.

[0067] The terms "on", "above", and "over" should be construed in the broadest sense, such that "on" not only means "directly on" something but also includes the meaning of being on something with other intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also can include the meaning of being "above" or "over" something with no other intervening features or layers therebetween (i.e., directly on something).

[0068] Ordinal numbers such as "first", "second", etc. used in the specification and claims are used to modify elements of the claims. Unless otherwise specified, they do not inherently imply or represent that the claimed element has any previous ordinal number, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0069] The term "etch" is generally used herein to describe a manufacturing process for patterning a material such that at least a portion of the material remains after etching. When "etching" a material, at least a portion of the material can be retained after etching. In contrast, when "removing" a material, substantially all of the material can be removed during the process. However, in some embodiments, "removing" can be considered a broad term and include etching.

[0070] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a material layer to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0071] Please refer to Figure 1 . Figure 1 The schematic diagram of a semiconductor device 100 according to an embodiment of the present invention is shown. As Figure 1As shown, the semiconductor device 100 includes a substrate 10, a plurality of magnetic tunneling junction (MTJ) structures (such as the MTJ structure MS), and a write structure WS. The plurality of MTJ structures MS are disposed on the substrate 10. The write structure WS is disposed on and connected to the plurality of MTJ structures MS. The write structure WS includes a plurality of spin-orbit torque (SOT) patterns (such as the SOT pattern 42P) and a conductive layer 46A. The plurality of SOT patterns 42P are separated from each other, and each SOT pattern 42P is disposed on and connected to one of the plurality of MTJ structures MS. The conductive layer 46A covers the plurality of SOT patterns 42P. The conductive layer 46A is partially disposed on the plurality of SOT patterns 42P in a vertical direction D3 and is partially disposed between the plurality of SOT patterns 42P in a first horizontal direction D1. The SOT pattern 42P can be used to generate a spin-orbit torque-based magnetization effect on the magnetic material in the MTJ structure MS to perform a programming operation on the memory device. However, the resistivity of the material generally used to form the SOT pattern 42P is relatively high, which is not conducive to related operations. Setting the SOT pattern 42P and the conductive layer 46A in the write structure WS can utilize the conductive layer 46A with a lower resistivity to reduce the overall resistance of the write structure WS, thereby improving the operating performance of the memory cell and the semiconductor device 100 and / or improving the power consumption of the semiconductor device 100 during operation.

[0072] In some embodiments, the vertical direction D3 can be regarded as the thickness direction of the substrate 10. The substrate 10 can have an upper surface TS and a bottom surface BS opposite to each other in the vertical direction D3. The above MTJ structure MS and the writing structure WS can be disposed on one side of the upper surface TS. The horizontal direction (such as the first horizontal direction D1, the second horizontal direction D2, and other horizontal directions) that is substantially orthogonal to the vertical direction D3 can be substantially parallel to the upper surface TS and / or the bottom surface BS of the substrate 10, but is not limited thereto. In addition, the distance in the vertical direction D3 between a position or / and component that is relatively higher in the vertical direction D3 described herein and the bottom surface BS of the substrate 10 can be greater than the distance in the vertical direction D3 between a position or / and component that is relatively lower in the vertical direction D3 and the bottom surface BS of the substrate 10. The lower part or bottom of each component can be closer to the bottom surface BS of the substrate 10 in the vertical direction D3 than the upper part or top of this component. Another component above a certain component can be regarded as being relatively farther from the bottom surface BS of the substrate 10 in the vertical direction D3, and another component below a certain component can be regarded as being relatively closer to the bottom surface BS of the substrate 10 in the vertical direction D3, but is not limited thereto. It should be noted that the upper surface of a certain component described herein can include the topmost surface of this component in the vertical direction D3, and the bottom surface of a certain component can include the bottommost surface of this component in the vertical direction D3, but is not limited thereto. In addition, the situation where a specific component is disposed between two other objects in a certain direction described herein can include but is not limited to the situation where this component is sandwiched between these two objects in this direction.

[0073] In some embodiments, the substrate 10 may include a first region R1 and a second region R2. The above MTJ structure MS and the write structure WS may be disposed on the first region R1. The first region R1 may be regarded as a memory cell region, and the second region R2 may be regarded as a logic region, but not limited thereto. In some embodiments, the semiconductor device 100 may further include a dielectric layer 12, a dielectric layer 14, a plurality of connection structures 16, a stop layer 18, a dielectric layer 20, a plurality of connection structures 22, a capping layer 34, a dielectric layer 36, a dielectric layer 38, a dielectric layer 40, and an interconnect structure CS. The dielectric layer 12, the dielectric layer 14, the connection structures 16, the stop layer 18, the dielectric layer 20, the dielectric layer 38, and the dielectric layer 40 may be partially disposed on the first region R1 and partially disposed on the second region R2. The capping layer 34 and the dielectric layer 36 may be disposed on the first region R1, and the interconnect structure CS may be disposed on the second region R2. In some embodiments, the substrate 10 may include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate may include, for example, a silicon substrate, a silicon-germanium semiconductor substrate, or a silicon-on-insulator (SOI) substrate, etc. The non-semiconductor substrate may include a glass substrate, a plastic substrate, or a ceramic substrate, etc., but not limited thereto. For example, when the substrate 10 includes a semiconductor substrate, a plurality of silicon-based field effect transistors (not shown), dielectric layers covering the silicon-based field effect transistors (such as the dielectric layer 12 and the dielectric layer 14), and the connection structures 16 may be disposed on the semiconductor substrate as needed, but not limited thereto. The stop layer 18 may be disposed between the dielectric layer 14 and the dielectric layer 20 in the vertical direction D3. The connection structure 22 may be disposed under the corresponding MTJ structure MS, and the connection structure 22 may penetrate through the dielectric layer 20 and the stop layer 18 in the vertical direction D3 to be connected to the corresponding MTJ structure MS and the connection structure 16 respectively. The capping layer 34 may be disposed on the dielectric layer 20 and the sidewalls of each MTJ structure MS. The dielectric layer 36 may be disposed on the capping layer 34, and the capping layer 34 and the dielectric layer 36 may be located between adjacent MTJ structures MS in the horizontal direction. The dielectric layer 38 may be disposed on the dielectric layer 20 and the dielectric layer 36, and the dielectric layer 40 may be disposed on the dielectric layer 38.

[0074] In some embodiments, each MTJ structure MS may be electrically connected to the above-mentioned silicon-based field-effect transistor downward through the connection structure 22 and the connection structure 16, and the interconnect structure CS may be electrically connected to the above-mentioned silicon-based field-effect transistor downward through the connection structure 16, but not limited thereto. In some embodiments, each connection structure 16 may be regarded as a trench conductor and mainly extends in the horizontal direction, the connection structure 22 may be regarded as a via conductor and mainly extends in the vertical direction D3, and the interconnect structure CS may include a via conductor portion (such as the portion disposed in the contact opening CH) and a trench conductor portion disposed on the via conductor portion (such as the portion disposed in the second trench TR2). In some embodiments, the semiconductor device 100 may further include a stop layer 48, a dielectric layer 50, a first electrode E1, a second electrode E2, and a connection structure CT. The stop layer 48 may be disposed above the first region R1 and the second region R2 and cover the dielectric layer 40, the write structure WS, and the interconnect structure CS. The dielectric layer 50 may be disposed on the stop layer 48, and the connection structure CT may penetrate the dielectric layer 50 and the stop layer 48 in the vertical direction D3 to be connected to the corresponding interconnect structure CS. In some embodiments, the write structure WS may extend along the first horizontal direction D1. The first electrode E1 and the second electrode E2 are disposed on the write structure WS and may penetrate the dielectric layer 50 and the stop layer 48 in the vertical direction D3 to be connected to the write structure WS, and the first electrode E1 and the second electrode E2 may be respectively located above the opposite ends of the write structure WS in the first horizontal direction D1. Each MTJ structure MS and the corresponding write structure WS and the connection structure 22 may form a memory cell, such as a magnetic random access memory (MRAM) cell. A current may be formed in the write structure WS through the first electrode E1 and the second electrode E2. The current may form a magnetic moment and a magnetization effect that affect the MTJ structure MS through the SOT pattern 42P in the write structure WS. In some embodiments, the magnetization effect generated by the current passing through the write structure WS may be combined with the magnetization effect generated by the current provided to the MTJ structure MS through the connection structure 22 to perform a programming operation on the magnetic layer in a specific MTJ structure MS, but not limited thereto.

[0075] Please refer to Figures 1 to 3 。 Figure 2 The cross-sectional schematic diagram of the semiconductor device of this embodiment is shown, and Figure 3 The top view schematic diagram of the semiconductor device of this embodiment is shown. In some embodiments, Figure 1 A part of (such as a part corresponding to the first region R1) may be regarded as the cross-sectional schematic diagram shown along the Figure 3 A-A' cross-sectional line in Figure 2can be regarded as a cross-sectional schematic diagram drawn along the Figure 3 B-B' cross-section line in Figure 3 , but not limited thereto. In addition, Figures 1 to 3 mainly shows the arrangement of the write structure WS, the SOT pattern 42P, the MTJ structure MS, and the dielectric layer 40 in a top view, without showing other components of the semiconductor device. As

[0076] shown, in some embodiments, the semiconductor device 100 may include a plurality of write structures WS. Each write structure WS may extend along a first horizontal direction D1, and a plurality of MTJ structures MS corresponding to the same write structure WS may be arranged along the first horizontal direction D1. In addition, the plurality of write structures WS may be arranged along a second horizontal direction D2, and the MTJ structures MS corresponding to different but adjacent write structures WS may be offset from each other in the second horizontal direction D2, thereby reducing the interference effect between the MTJ structures MS and reducing the area of the memory cell region and / or increasing the setting density of the MTJ structures MS. In some embodiments, the write structure WS may be disposed in a dielectric layer (such as a dielectric layer composed of the dielectric layer 38 and the dielectric layer 40). This dielectric layer may include a first layer (such as the dielectric layer 38) and a second layer (such as the dielectric layer 40) disposed on the first layer. The write structure WS may be partially disposed in the dielectric layer 38 and partially disposed in the dielectric layer 40, and the dielectric constant of the dielectric layer 40 may be lower than that of the dielectric layer 38, thereby enhancing the isolation effect between adjacent write structures, but not limited thereto. Figure 2The situation shown), thereby enhancing the protection effect on the SOT pattern 42P. For example, but not limited to, covering the SOT pattern 42P with the barrier layer 44A reduces the negative impact caused by external substances entering the SOT pattern 42P through the dielectric layer (such as the dielectric layer 38 or / and the dielectric layer 40). In some embodiments, the write structure WS may include a plurality of first parts P1 and a plurality of second parts P2 arranged alternately along the first horizontal direction D1. Each first part P1 may consist of one of the plurality of SOT patterns 42P, the barrier layer 44A disposed on this SOT pattern 42P, and the conductive layer 46A disposed on this SOT pattern 42P, and each second part P2 may consist of a part of the barrier layer 44A located between the plurality of SOT patterns 42P in the first horizontal direction D1 and a part of the conductive layer 46A located between the plurality of SOT patterns 42P in the first horizontal direction D1. In other words, the write structure WS may include a first part P1 consisting of the SOT pattern 42P, the barrier layer 44A, and the conductive layer 46A and a second part P2 consisting of the barrier layer 44A and the conductive layer 46A arranged alternately and connected to each other in the first horizontal direction D1, thereby reducing the overall resistance of the write structure WS while maintaining the required programming effect or / and magnetization effect of the write structure WS.

[0077] In some embodiments, each MTJ structure MS may include a bottom electrode 24, a reference layer 26, a barrier layer 28, a free layer 30, and a spin-orbit torque layer (such as the SOT layer 32) stacked in sequence from bottom to top. Each SOT pattern 42P may be connected to the SOT layer 32 in the MTJ structure MS disposed therebelow, and the SOT layer 32 disposed above the free layer 30 and the corresponding SOT pattern 42P may respectively include SOT materials. The SOT material may be defined as a material that can generate the spin Hall effect and / or has a large spin-orbit coupling strength, so as to generate a spin-orbit torque on the free layer 30 to change the direction of its magnetic torque. The material composition of the SOT pattern 42P and the material composition of the SOT layer 32 may be the same or different from each other according to design requirements. In some embodiments, the SOT layer 32 may be formed together with other material layers in the MTJ structure MS through a patterning process. For example, an ion beam etching (IBE) process or other suitable methods may be used for patterning, and at least a part of the SOT layer 32 may be used as a hard mask layer when the IBE process etches other material layers, so the hardness requirement for the SOT layer 32 is relatively high. In contrast, the SOT pattern 42P may not be patterned together with other materials. For example, it may be patterned through a reactive-ion etching (RIE) process or other suitable methods, so the hardness requirement for the SOT pattern 42P is relatively low, and the hardness of each SOT layer 32 may thus be higher than the hardness of each SOT pattern 42P. In addition, since the resistivity of general SOT materials is relatively high, in the case of having the SOT layer 32, the spin-orbit torque may be mainly generated by the SOT layer 32, and the SOT pattern 42P that is relatively far from the free layer 30 may use an SOT material with a relatively low resistivity to reduce the overall resistance of the write structure WS. In this case, the resistivity of each SOT pattern 42P may be lower than the resistivity of each SOT layer 32. For example, the material of the SOT layer 32 may include hafnium (Hf), rhenium (Re), ruthenium (Ru), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), iridium (Ir), palladium (Pd), alloys of the above materials (such as IrPt, PtAu, PtPd, BiSb, etc.), compounds of the above materials (such as PtS, WTe2, etc.), or other suitable materials (such as BiSb), and the material of the SOT pattern 42P may include W, Au, Ir, Ta, BiSb, or other suitable materials.In addition, in some embodiments, in a situation where the semiconductor device 100 is viewed along the vertical direction D3, the SOT pattern 42P may completely cover or overlap the corresponding MTJ structure MS and the SOT layer 32 therein. In other words, the lengths of each SOT pattern 42P in the first horizontal direction D1 and the second horizontal direction D2 may be greater than the lengths of each SOT layer 32 in the first horizontal direction D1 and the second horizontal direction D2, respectively, and the projected area of each SOT pattern 42P in the vertical direction D3 may be greater than the projected area of each SOT layer in the vertical direction D3.

[0078] In some embodiments, the SOT pattern 42P may be in direct contact with the corresponding SOT layer 32, but is not limited thereto. The free layer 30 and the reference layer 26 may include ferromagnetic materials such as iron, cobalt, nickel, cobalt-iron (CoFe) alloy, cobalt-iron-boron (CoFeB), or other suitable ferromagnetic materials. In some embodiments, the reference layer 26 may form a pinned layer with an antiferromagnetic layer (not shown) and have a fixed magnetic moment direction. The antiferromagnetic layer may include antiferromagnetic materials such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), cobalt / platinum (Co / Pt) composite layer, or other suitable antiferromagnetic materials. The barrier layer 28 may include insulating materials such as magnesium oxide (MgO), aluminum oxide, or other suitable insulating materials, and the bottom electrode 24 may include metallic materials such as tantalum (Ta), platinum (Pt), ruthenium (Ru), composite layers or alloys of the above materials, or other suitable conductive materials. In addition, the dielectric layer 12, the dielectric layer 14, the dielectric layer 20, the dielectric layer 36, and the dielectric layer 38 may respectively include oxide dielectric materials, low dielectric constant dielectric materials (e.g., but not limited to dielectric materials with a dielectric constant lower than 2.9), or other suitable dielectric materials, and the dielectric layer 40 and the dielectric layer 50 may respectively include low dielectric constant dielectric materials or ultra low dielectric constant (ULK) dielectric materials (e.g., but not limited to dielectric materials with a dielectric constant lower than 2.7), such as benzocyclclobutene (BCB), hydrogen silsesquioxane (HSQ), methyl silesquioxane (MSQ), silicon oxycarbide hydride (SiOC-H), porous dielectric materials, or other suitable dielectric materials. In addition, the hardness of general low dielectric constant dielectric materials is relatively low (e.g., when using a porous structure to achieve the effect of reducing the dielectric constant), so in order to reduce the impact on the yield of related manufacturing processes, it is preferably to use a material with a relatively high dielectric constant but also a relatively high hardness to form the dielectric layer 38, and use a material with a relatively low dielectric constant to form the dielectric layer 40, thereby reducing the signal interference between adjacent write structures WS and / or adjacent interconnect structures CS. Therefore, the dielectric constant of the dielectric layer 40 may be lower than that of the dielectric layer 38, but is not limited thereto.The stop layer 18 and the stop layer 48 may include a nitrogen doped carbide layer (NDC), silicon nitride, silicon carbon nitride (SiCN), or other suitable insulating materials, and the capping layer 34 may include silicon nitride or other dielectric materials different from the dielectric layer 36. Thus, the capping layer 34 can be used as an etch stop layer, but not limited thereto.

[0079] In some embodiments, the above-mentioned connection structure 16, interconnect structure CS, connection structure CT, first electrode E1, and second electrode E2 may respectively include a barrier layer and a conductive layer disposed on the barrier layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive barrier materials, and the conductive layer may include tungsten, copper, aluminum, titanium-aluminum alloy, cobalt tungsten phosphide, or other suitable conductive materials with relatively low resistivity. For example, the connection structure 22 may include a barrier layer 22A and a conductive layer 22B disposed on the barrier layer 22A, and the interconnect structure CS may include a barrier layer 44B and a conductive layer 46B disposed on the barrier layer 44B, but not limited thereto. In some embodiments, the barrier layer 44A and the conductive layer 46A in the write structure WS may be formed together with the barrier layer 44B and the conductive layer 46B in the interconnect structure CS by the same manufacturing process, and the material composition of the barrier layer 44A may be the same as that of the barrier layer 44B, and the material composition of the conductive layer 46A may be the same as that of the conductive layer 46B, but not limited thereto.

[0080] Please refer to Figures 1 to 10 . Figures 4 to 10 FIG. is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where Figure 5 illustrates Figure 4 the situation after Figure 6 illustrates Figure 5 the situation after Figure 7 illustrates Figure 6 the situation after Figure 8 illustrates Figure 7 the situation after Figure 9 illustrates Figure 8 the situation after, and Figure 10 illustrates Figure 9 the situation after. In some embodiments, Figure 1 may be regarded as illustrating Figure 10 the situation after, but not limited thereto. As Figure 1As shown, this embodiment provides a method for manufacturing a semiconductor device, including the following steps. A plurality of MTJ structures MS are formed on a substrate 10, and a write structure WS is formed on the plurality of MTJ structures MS. The write structure WS is connected to the plurality of MTJ structures MS, and the write structure WS includes a plurality of SOT patterns 42P and a conductive layer 46A. The plurality of SOT patterns 42P are separated from each other, and each SOT pattern 42P is disposed on and connected to one of the plurality of MTJ structures MS. The conductive layer 46A covers the plurality of SOT patterns 42P, and the conductive layer 46A is partially disposed on the plurality of SOT patterns 42P in the vertical direction D3 and partially disposed between the plurality of SOT patterns 42P in the first horizontal direction D1.

[0081] Further, the manufacturing method of this embodiment may include but is not limited to the following steps. As Figure 4 shown, a dielectric layer 12, a dielectric layer 14, a connection structure 16, a stop layer 18, and a dielectric layer 20 may be formed on a first region R1 and a second region R2 of the substrate 10. Then, a plurality of connection structures 22, a plurality of MTJ structures MS, a capping layer 34, and a dielectric layer 36 are formed on the first region R1. After that, a dielectric layer 38 and a dielectric layer 40 are formed on the first region R1 and the second region R2. In some embodiments, the dielectric layer 38 may be formed by spin coating, so the dielectric layer 38 may have a relatively flat upper surface, but it is not limited thereto. The dielectric layer 38 and the dielectric layer 40 may be regarded as the first layer and the second layer of a dielectric layer, respectively, and this dielectric layer may cover the plurality of MTJ structures MS. Then, as Figure 5 shown, a first trench TR1 may be formed in the dielectric layer (such as the dielectric layer composed of the dielectric layer 38 and the dielectric layer 40) on the first region R1, and a second trench TR2 may be formed in the dielectric layer (such as the dielectric layer composed of the dielectric layer 38 and the dielectric layer 40) on the second region R2. The first trench TR1 may be formed by removing a part of the dielectric layer 40, the dielectric layer 38, the capping layer 34, and the dielectric layer 36, and the first trench TR1 may expose the corresponding plurality of MTJ structures MS (such as the SOT layer 32 in the MTJ structure MS). In some embodiments, the first trench TR1 and the second trench TR2 may be formed together by the same manufacturing process (such as but not limited to a lithography etching manufacturing process), and the first trench TR1 and the second trench TR2 may have substantially equal depths, but it is not limited thereto.

[0082] As Figure 6 and Figure 7As shown, a plurality of SOT patterns 42P may be formed in the first trench TR1, and the plurality of SOT patterns 42P are separated from each other. In some embodiments, an SOT material 42 may be formed on the surfaces of the first trench TR1, the second trench TR2, and the dielectric layer 40, and the SOT material 42 may be patterned to form the SOT pattern 42P. Therefore, the SOT material 42 formed in the second trench TR2 and on the dielectric layer 40 may be completely removed by the patterning process. Then, as Figure 8 shown, a contact opening CH may be formed below the second trench TR2. The contact opening CH is connected to the second trench TR2, and the SOT pattern 42P is formed in the first trench TR1 before the contact opening CH is formed. This can avoid the SOT material 42 remaining in the deeper contact opening CH and being unable to be completely removed, but this is not limiting. The contact opening CH may penetrate through a part of the dielectric layer 38, the dielectric layer 40, and the stop layer 18 in the vertical direction D3 to expose the corresponding connection structure 16. As Figure 9 shown, a barrier material 44 and a conductive material 46 may be formed comprehensively on the substrate 10, and the conductive material 46 is formed on the barrier material 44. The barrier material 44 may be conformally formed on the surface of the first trench TR1, the SOT pattern 42P, the surface of the second trench TR2, the surface of the contact opening CH, and the surface of the dielectric layer 40, and the conductive material 46 may be partially formed in the first trench TR1, the second trench TR2, and the contact opening CH. In some embodiments, the barrier material 44 and the conductive material 46 may fill the second trench TR2 and the contact opening CH, the barrier material 44, the conductive material 46, and the SOT pattern 42P may fill the first trench TR1, and the barrier material 44 and the conductive material 46 may be partially formed outside the first trench TR1, the second trench TR2, and the contact opening CH.

[0083] After that, as Figure 9 and Figure 10As shown, a planarization fabrication process 90 can be performed to remove the conductive material 46 and the barrier material 44 located outside the first trench TR1, the second trench TR2, and the contact opening CH. Thus, a conductive layer 46A and a barrier layer 44A are formed in the first trench TR1, and a conductive layer 46B and a barrier layer 44B are formed in the second trench TR2 and the contact opening CH. Furthermore, a write structure WS and an interconnect structure CS are formed on the first region R1 and the second region R2, respectively. By the above fabrication method, the conductive layer 46A and the barrier layer 44B of the write structure WS can be formed together with the interconnect structure CS by the same fabrication process, but this is not limited thereto. In the write structure WS, the barrier layer 44A is formed in the first trench TR1, on the plurality of SOT patterns 42P, and on the surface of the first trench TR1, and the conductive layer 46A is formed on the barrier layer 44A. In the interconnect structure CS, the conductive layer 46B and the barrier layer 44B are partially formed in the contact opening CH and partially formed in the second trench TR2. In some embodiments, the planarization fabrication process 90 may include a chemical mechanical polishing (CMP) fabrication process, a back-etching fabrication process, or other suitable planarization methods. A part of the dielectric layer 40 may be removed by the planarization fabrication process 90, and the upper surfaces of the write structure WS, the interconnect structure CS, and the dielectric layer 40 may be substantially coplanar, but this is not limited thereto. It should be noted that the method for forming the write structure WS and the interconnect structure CS of the present invention may include but is not limited to the above Figures 5 to 10 shown steps, and other suitable methods may be used to form the write structure WS and the interconnect structure CS as Figure 10 shown according to the design requirements. Then, as Figure 10 and Figure 1 shown, the above-mentioned stop layer 48, dielectric layer 50, first electrode E1, second electrode E2, and connection structure CT can be formed, and then a semiconductor device 100 as Figure 1 shown is formed.

[0084] In summary, in the semiconductor device and its fabrication method of the present invention, by providing SOT patterns and a conductive layer in the write structure, the overall resistance of the write structure can be reduced by using the conductive layer with a lower resistivity, and the required programming effect or / and magnetization effect can be maintained. Furthermore, the operating performance of the memory cells and the semiconductor device can be improved or / and the power consumption of the semiconductor device during operation can be improved.

[0085] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: substrate; A plurality of magnetic tunneling junction (MTJ) structures are disposed on the substrate; as well as A write structure is disposed on the plurality of magnetic tunnel junction structures and connected to the plurality of magnetic tunnel junction structures, wherein the write structure comprises: A plurality of spin-orbit torque (SOT) patterns, wherein the plurality of SOT patterns are separated from each other, wherein each of the SOT patterns is disposed on one of the plurality of magnetic tunneling junction structures and connected to the magnetic tunneling junction structure; as well as A conductive layer covers the multiple spin-orbit torque patterns, wherein the conductive layer is partially disposed on the multiple spin-orbit torque patterns in a vertical direction and partially disposed between the multiple spin-orbit torque patterns in a first horizontal direction.

2. The semiconductor device as claimed in claim 1, wherein each of the magnetic tunneling junction structures comprises: Free layer; as well as The spin-orbit torque layer is arranged on the free layer, wherein each of the spin-orbit torque patterns is connected to the spin-orbit torque layer of the magnetic tunnel junction structure arranged thereunder. 3 . The semiconductor device as claimed in claim 2 , wherein a material composition of the plurality of spin-orbit torque patterns is different from a material composition of the plurality of spin-orbit torque layers. 4 . The semiconductor device as claimed in claim 2 , wherein a hardness of each of the spin-orbit torque layers is higher than a hardness of each of the spin-orbit torque patterns. 5 . The semiconductor device as claimed in claim 2 , wherein a resistivity of each of the spin-orbit torque patterns is lower than a resistivity of each of the spin-orbit torque layers.

6. The semiconductor device according to claim 1, further comprising: The dielectric layer is disposed on the substrate, wherein the write structure is disposed in the dielectric layer and extends along the first horizontal direction, and the plurality of magnetic tunnel junction structures are arranged along the first horizontal direction.

7. The semiconductor device according to claim 6, wherein the write structure further comprises: A barrier layer is disposed between the conductive layer and each of the spin-orbit torque patterns, wherein a portion of the barrier layer is sandwiched between the dielectric layer and one of the plurality of spin-orbit torque patterns in a second horizontal direction, and the second horizontal direction is orthogonal to the first horizontal direction.

8. A semiconductor device as described in claim 7, wherein the write structure includes a plurality of first parts and a plurality of second parts arranged alternately along the first horizontal direction, each of the first parts is composed of one of the plurality of spin-orbit torque patterns, the barrier layer arranged on the spin-orbit torque pattern, and the conductive layer arranged on the spin-orbit torque pattern, and each of the second parts is composed of a portion of the barrier layer located between the plurality of spin-orbit torque patterns in the first horizontal direction and a portion of the conductive layer located between the plurality of spin-orbit torque patterns in the first horizontal direction.

9. The semiconductor device of claim 6, wherein the dielectric layer comprises: First floor; as well as The second layer is disposed on the first layer, wherein the writing structure is partially disposed in the first layer and partially disposed in the second layer, and the dielectric constant of the second layer is lower than the dielectric constant of the first layer.

10. The semiconductor device according to claim 1, further comprising: The first electrode and the second electrode are disposed on the writing structure and connected to the writing structure, wherein the first electrode and the second electrode are respectively located on two opposite ends of the writing structure in the first horizontal direction.

11. A method for manufacturing a semiconductor device, comprising: forming a plurality of magnetic tunneling junction (MTJ) structures on the substrate; as well as A write structure is formed on the plurality of magnetic tunnel junction structures, wherein the write structure is connected to the plurality of magnetic tunnel junction structures, and the write structure comprises: A plurality of spin-orbit torque (SOT) patterns, wherein the plurality of SOT patterns are separated from each other, wherein each of the SOT patterns is disposed on one of the plurality of magnetic tunneling junction structures and connected to the magnetic tunneling junction structure; as well as A conductive layer covers the multiple spin-orbit torque patterns, wherein the conductive layer is partially disposed on the multiple spin-orbit torque patterns in a vertical direction and partially disposed between the multiple spin-orbit torque patterns in a first horizontal direction.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the method for forming the write structure comprises: forming a dielectric layer on the substrate, wherein the dielectric layer covers the plurality of magnetic tunnel junction structures; forming a first trench in the dielectric layer, wherein the first trench exposes each of the magnetic tunneling junction structures; forming the plurality of spin-orbit torque patterns in the first trench; as well as The conductive layer is formed in the first trench.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the substrate comprises a first region and a second region, the plurality of magnetic tunneling junction structures and the writing structure are disposed on the first region, and the method further comprises: An interconnection structure is formed on the second region, wherein the conductive layer of the write structure and the interconnection structure are formed by the same manufacturing process.

14. The method for manufacturing a semiconductor device as claimed in claim 13, wherein the dielectric layer is formed on the first region and the second region, and the method for forming the interconnect structure comprises: forming a second trench in the dielectric layer above the second region, wherein the first trench and the second trench are formed by the same manufacturing process; forming a contact opening below the second trench, wherein the contact opening is connected to the second trench, and the plurality of spin-orbit torque patterns are formed in the first trench before the contact opening is formed; forming a conductive material on the substrate, wherein the conductive material is partially formed in the first trench, partially formed in the second trench and the contact opening, and partially formed outside the first trench, the second trench, and the contact opening; as well as A planarization process is performed to remove the conductive material outside the first trench, the second trench and the contact opening.

15. The method for manufacturing a semiconductor device according to claim 12, wherein the dielectric layer comprises: First floor; as well as The second layer is disposed on the first layer, wherein the writing structure is partially disposed in the first layer and partially disposed in the second layer, and the dielectric constant of the second layer is lower than the dielectric constant of the first layer.

16. The method for manufacturing a semiconductor device according to claim 12, wherein the first trench extends along the first horizontal direction, the plurality of magnetic tunneling junction structures are arranged along the first horizontal direction, and the method for forming the write structure further comprises: A barrier layer is formed in the first trench, wherein the barrier layer is formed on the plurality of spin-orbit torque patterns and on a surface of the first trench, the conductive layer is formed on the barrier layer, a portion of the barrier layer is sandwiched between the dielectric layer and one of the plurality of spin-orbit torque patterns in a second horizontal direction, and the second horizontal direction is orthogonal to the first horizontal direction.

17. The method for manufacturing a semiconductor device as claimed in claim 11, wherein each of the magnetic tunneling junction structures comprises: Free layer; as well as The spin-orbit torque layer is arranged on the free layer, wherein each of the spin-orbit torque patterns is connected to the spin-orbit torque layer of the magnetic tunnel junction structure arranged thereunder. 18 . The method for manufacturing a semiconductor device as claimed in claim 17 , wherein a material composition of the plurality of spin-orbit torque patterns is different from a material composition of the plurality of spin-orbit torque layers. 19 . The method for manufacturing a semiconductor device as claimed in claim 17 , wherein a hardness of each of the spin-orbit torque layers is higher than a hardness of each of the spin-orbit torque patterns. 20 . The method for manufacturing a semiconductor device as claimed in claim 17 , wherein a resistivity of each of the spin-orbit torque patterns is lower than a resistivity of each of the spin-orbit torque layers.

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