A current-enhanced multi-channel isolated AlGaN / GaN CAVER device

Abstract

The application relates to a current-enhanced multi-channel isolated AlGaN / GaN CAVET device, and belongs to the technical field of microelectronics. The device comprises a drain, a substrate, a GaN buffer layer, a current blocking layer, a current isolation layer, and further comprises alternately-stacked barrier layers and channel layers above the current blocking layer and the current isolation layer, wherein a channel isolation layer is embedded between adjacent barrier layers and channel layers for isolating current. The application discards the design of taking an aperture as a current channel, adopts a gate voltage to regulate the hole concentration at the current blocking layer and the gate sidewall, so that the opening and closing of the device are realized. In the multi-channel design, the problem of mutual depletion of electron gases among the multi-channels in the vertical structure is solved by introducing the isolation layer, and the isolation layer is also embedded in the current blocking layer, so that the depletion effect of P-GaN on the channel is effectively prevented, and the output capacity of the device is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology and relates to a current-enhanced multi-channel isolated AlGaN / GaN CAVET device. Background Technology

[0002] Gallium nitride (GaN), as a representative of third-generation semiconductor materials, boasts a wide bandgap (3.4 eV), a high critical breakdown field strength (3.3 MV / cm), and a high electron saturation drift velocity (2.5 × 10⁻⁶). 7 With its excellent radiation resistance (cm / s), GaN HEMTs have become an ideal choice for high-voltage, high-frequency power devices. Existing literature primarily focuses on lateral GaN HEMT devices, and the related technologies are relatively mature. Despite significant progress in lateral devices, most lateral HEMTs are still used in the 1kW to 3kW range, while vertical structures are predominantly used in high-voltage, high-current applications. Compared to vertical structures, lateral devices have several serious drawbacks. For example, the high electric field region in lateral devices is located near the gate edge close to the drain. This high electric field injects electrons into surface traps, causing current collapse, a serious reliability issue that further limits the application of lateral devices in high-voltage fields. Furthermore, lateral GaN HEMT devices rely mainly on the active region between the gate and drain to withstand the breakdown voltage. To achieve a large breakdown voltage, a large gate-drain distance is required, increasing the chip area, which is inconsistent with miniaturization requirements and hinders cost reduction. In contrast, the breakdown voltage region of vertical devices is distributed in the vertical drift region, significantly improving the device's breakdown voltage without increasing the lateral dimensions.

[0003] Vertically structured devices (such as CAVETs and MOSFETs) withstand high voltages through their vertical drift regions, achieving kilovolt-level withstand voltages with relatively small lateral dimensions. However, existing vertical GaN devices often struggle to simultaneously achieve high voltage withstand voltages and high current densities. The thickness and doping concentration of the P-GaN layer directly affect the blocking capability and on-resistance (R0). on Studies have shown that when the thickness of P-GaN increases from 1 μm to 3 μm, the breakdown voltage (V) increases. br It can be boosted from 800 V to 1.2 kV, but R on At the same time, it increases by about 40%. In order to improve the current density, researchers tried to introduce a multi-channel structure, but the vertically stacked AlGaN / GaN heterojunction will form a two-dimensional hole gas (2DHG), which recombines and is depleted with the channel electron gas (2DEG), resulting in a decrease in the effective carrier concentration. Simulation shows that the electron concentration of the dual-channel structure is about 25% lower than that of the single-channel structure, which seriously weakens the advantages of the multi-channel design.

[0004] As can be seen from the above, there is an urgent need to develop an innovative structure that can significantly enhance the output current capability of the device while maintaining high voltage withstand performance, so as to expand the application range of GaN vertical devices in high-power applications. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a current-enhanced multi-channel isolated AlGaN / GaN CAVET device. By designing an isolated multi-channel structure, the recombination depletion of electron-hole gas generated by the AlGaN / GaN heterojunction with channel electrons is avoided, thereby improving the output current capability of the device while maintaining its high breakdown voltage performance.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A current-enhancing multi-channel isolated AlGaN / GaN CAVET device, the device comprising:

[0008] Substrate;

[0009] A GaN buffer layer located on the substrate surface;

[0010] A current blocking layer located on the surface of the GaN buffer layer;

[0011] A current isolation structure located on the surface of the GaN buffer layer, which divides the current blocking layer into two parts;

[0012] At least three stacked barrier / channel structures located on the surfaces of the current blocking layer and the current isolation structure;

[0013] Channel isolation layers located between various barrier / channel structures;

[0014] The first source electrode located on the surface of the uppermost barrier / channel structure;

[0015] A second source electrode perpendicular to the stacking direction of the barrier / channel structure and used to connect the channel layers in each barrier / channel structure, wherein the upper surface of the second source electrode is connected to the first source electrode and the lower surface is in contact with the surface of the channel layer in the bottommost barrier / channel structure.

[0016] A passivation layer located on the surface of the uppermost barrier / channel structure and distributed on both sides of the first source electrode;

[0017] The gates located on both sides of the device; and

[0018] The drain electrode is located on the surface of the substrate away from the GaN buffer layer.

[0019] Furthermore, the current isolation structure includes a first current isolation layer and a second current isolation layer distributed on both sides of the first current isolation layer.

[0020] Furthermore, the barrier / channel structure includes a channel layer and a barrier layer, wherein the barrier layer is located on the upper surface of the channel layer.

[0021] Furthermore, the gates located on both sides of the device are insulated from other parts of the device by HfO2 insulating gates.

[0022] Furthermore, there is a gap between the second current isolation layer and the HfO2 insulating gate, with a gap of 100~500 nm.

[0023] Furthermore, the channel isolation layer located between the barrier / channel structure and the HfO2 insulating gate are spaced apart, with a spacing of 100~500 nm.

[0024] Furthermore, the channel layers in each barrier / channel structure have the same thickness, and the barrier layers in each barrier / channel structure have the same thickness.

[0025] The beneficial effects of this invention are as follows: This invention breaks through the traditional design that uses aperture as the current channel, employing gate voltage to regulate the hole concentration at the current blocking layer and gate sidewall, thereby achieving device switching on and off, effectively reducing leakage current. In multi-channel designs, this invention utilizes a SiO2-based isolation layer to isolate the AlGaN barrier layer and the GaN channel layer, avoiding the recombination depletion of electron-hole gas generated in the AlGaN / GaN heterojunction with channel electrons, allowing the multi-channel structure to fully function. Simultaneously, a SiO2 current isolation layer is embedded within the P-GaN current blocking layer, preventing the P-GaN from depleting channel electrons. Based on this, the CAVET device proposed in this invention can significantly improve its output current capability while maintaining high breakdown voltage performance.

[0026] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0028] Figure 1 This is a schematic cross-sectional view of a current-enhanced multi-channel isolated AlGaN / GaN CAVET device provided in an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of the basic structure cross-section;

[0030] Figure 3 This is a comparison graph of the transfer characteristic curves and transconductance characteristic curves of the device and basic structure of the present invention;

[0031] Figure 4 for V G =10 V, V D Comparison of channel electron concentration cross-sectional distribution in the P-GaN current blocking layer of traditional CAVET devices with and without SiO2 current isolation layers at 6 V. Figure 4 (a) Without inserting a SiO2 current isolation layer, Figure 4 (b) is the insertion of a SiO2 current isolation layer;

[0032] Figure 5 for V G =10 V, V D A comparison of electron concentration cross-sectional distributions at 6 V for three structures: a dual-channel structure without a channeling layer, a dual-channel structure with a channeling layer, and a triple-channel structure with a channeling layer (i.e., the example structure of this invention). Figure 5 (a) is a dual-channel structure without a channel isolation layer. Figure 5 (b) is a dual-channel structure with a channel isolation layer. Figure 5 (c) is a three-channel structure with a channel isolation layer;

[0033] Figure 6 This is a comparison chart of the output characteristic curves of the present invention and the basic structure.

[0034] Reference numerals: 101-Drain, 102-Substrate, 103-GaN buffer layer, 104-HfO2 insulating gate, 105-Gate, 106-First source, 107-Passivation layer, 108-First barrier layer, 109-First channel layer, 110-Current blocking layer, 111-First current isolation layer, 112-Second barrier layer, 113-Second channel layer, 114-Third barrier layer, 115-Third channel layer, 116-Second source, 117-Second current isolation layer, 118-First channel isolation layer, 119-Second channel isolation layer. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0036] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0037] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0038] like Figure 1 The image shows a current-enhanced multi-channel isolated AlGaN / GaN CAVET device according to an embodiment of the present invention, which includes a drain 101, a substrate 102, a GaN buffer layer 103, an HfO2 insulating gate 104, a gate 105, a first source 106, a passivation layer 107, a first barrier layer 108, a first channel layer 109, a current blocking layer 110, a first current isolation layer 111, a second barrier layer 112, a second channel layer 113, a third barrier layer 114, a third channel layer 115, a second source 116, a second current isolation layer 117, a first channel isolation layer 118, and a second channel isolation layer 119.

[0039] This CAVET device features an isolated multi-channel structure, including a first channel layer 109, a second channel layer 113, and a third channel layer 115. Each channel is connected via a vertical second source 116. A first channel isolation layer 118 and a second channel isolation layer 119 isolate the first channel layer 109 from its underlying second barrier layer 112, and the second channel layer 113 from its underlying third barrier layer 114. Furthermore, a second current isolation layer 117 is added within the current blocking layer 110 to isolate current and separate the P-GaN current blocking layer 110 from the third channel layer 115.

[0040] The first channel layer 109, the second channel layer 113, and the third channel layer 115 are sequentially stacked between the first source 106 and the first current isolation layer 111, with a consistent thickness ranging from 100 to 400 nm. The second source 116 connects to each of the three channel layers in a direction perpendicular to them. The upper surface of the second source 116 contacts the first source 106 located at the top of the device, and its lower surface contacts the third channel layer 115. The lateral length of the second source 116 ranges from 100 to 1000 nm.

[0041] The first channel isolation layer 118 is embedded in the second barrier layer 112, and its upper surface is in contact with the lower surface of the first channel layer 109, thus isolating the first channel layer 109 from the second barrier layer 112. The second channel isolation layer 119 is embedded in the third barrier layer 114, and its upper surface is in contact with the lower surface of the second channel layer 113, thus isolating the second channel layer 113 from the third barrier layer 114. The thickness of the first channel isolation layer 118 and the second channel isolation layer 119 is consistent, and both range from 1 to 25 nm, with a length of 1 to 5 μm. Neither the first channel isolation layer 118 nor the second channel isolation layer 119 is in contact with the HfO2 insulating gate 104, and their spacing is 100 to 500 nm.

[0042] The first current isolation layer 111 is located in the current blocking layer 110 and divides the current blocking layer 110 into two parts. The upper surface of the first current isolation layer 111 is connected to the third channel layer 115, and the lower surface is connected to the GaN buffer layer 103. The thickness is 1~3 μm and the length is 1~6 μm.

[0043] The second current isolation layer 117 is embedded in the current blocking layer 110 and is distributed on both sides of the first current isolation layer 111. The upper surface of the second current isolation layer 117 is in contact with the lower surface of the third channel layer 115, and the thickness is 0.1~1 μm. The second current isolation layer 117 is not in contact with the HfO2 insulating gate 104, and the spacing is 100~500 nm.

[0044] The first barrier layer 108, the second barrier layer 112, and the third barrier layer 114 have the same thickness before the current isolation layer is inserted, and the thickness ranges from 15 to 50 nm.

[0045] The gate 105 is located on both sides of the device and is insulated from other areas of the device by an HfO2 insulating gate 104. The gate 105 has a thickness of 1~3 μm and a length of 1~2 μm. The HfO2 insulating gate 104 has a thickness of 10~100 nm.

[0046] The first source electrode 106 has a thickness of 100~200 nm and a length of 1~6 μm; the passivation layer 107 is located on both sides of the first source electrode 106, and the passivation layer 107 has a thickness of 200~225 nm and a length of 1~6 μm.

[0047] The thickness of the GaN buffer layer 103 is 3~10 μm.

[0048] This invention breaks through the traditional design that uses aperture as the current channel, employing gate voltage to regulate the hole concentration at the current blocking layer and gate sidewall, thereby achieving device switching on and off. In multi-channel designs, the introduction of a current isolation layer solves the problem of electron gas depletion between multiple channels in vertical structures. Simultaneously, the clever embedding of an isolation layer within the current blocking layer effectively prevents the depletion effect of P-GaN on the channels, thus significantly improving the device's output capability.

[0049] Figure 3 For the comparison of the transfer characteristic curves of the present invention and the basic structure, the basic structure described herein is as follows: Figure 2 As shown. It can be observed that the threshold voltage of both the present invention and the basic structure reaches 2.81 V. V d At 6 V, the saturation current densities of the two devices are 2398.6 mA / mm² and 2075.6 mA / mm², respectively. Compared to the basic structure, the present invention improves the current density by 323 mA / mm² and the maximum transconductance by 70%. This enhanced current density is due to the device being transformed from a single-channel to a three-channel structure, resulting in improved output capability. Simultaneously, a SiO₂-based current isolation layer is embedded within the P-GaN current blocking layer to prevent the P-GaN from depleting electrons in the upper channel. Correspondingly... Figure 4 As can be seen, Figure 4 (a) The midchannel electron concentration is significantly less than Figure 4 (b) The electron concentration in the middle channel, which is due to Figure 4 In (a), the GaN channel layer is in direct contact with the underlying P-GaN. The high concentration of holes in the heavily doped P-GaN will inevitably have a certain depletion effect on the electrons in the upper channel. Figure 4 (b) Inserting a layer of SiO2 between the P-GaN and the upper channel layer can both isolate electrons from downward movement and prevent the P-GaN layer from depleting electrons. Figure 4 (b) shows a high concentration of electrons in almost all of the GaN channel layers.

[0050] from Figure 5 It can be seen that, Figure 5 (a) The channel layer electron concentration distribution region of the dual-channel structure without a channel isolation layer is significantly smaller than that of the channel layer electron concentration distribution region. Figure 5 (b) The dual-channel structure has a channel isolation layer and Figure 5 (c) The electron concentration distribution region in the three-channel configuration with a channel isolation layer is smaller. This is because in the case of multiple channels, the GaN channel layer forms a GaN / AlGaN heterojunction with the underlying AlGaN barrier layer, generating a two-dimensional hole gas (2DHG). Furthermore, since the source is above and the drain is below in vertical devices, the applied stress generates a vertical electric field. Therefore, the generated hole gas moves vertically and recombines with the two-dimensional electron gas in the channel, leading to depletion and a decrease in the channel's electron concentration, thus increasing the resistance. This problem can be effectively avoided by inserting a SiO2-based channel isolation layer of a certain thickness between the AlGaN / GaN heterojunctions to isolate the direct contact between AlGaN and GaN, allowing the multi-channel structure to function fully without being affected by the hole gas.

[0051] Figure 6 This is a comparison chart of the output characteristic curves of the present invention and the basic structure. V g At 5 V, the saturated output current of the example structure of this invention increased from 2012 mA / mm to 3459 mA / mm compared to the basic structure, an improvement of 71.9%; the on-resistance was reduced by 0.38 Ω·mm compared to the basic structure, to only 2.29 Ω·mm.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A current-enhanced multi-channel isolated AlGaN / GaN CAVET device, characterized in that, The device includes: Substrate (102); A GaN buffer layer (103) located on the surface of the substrate (102). A current blocking layer (110) is located on the surface of the GaN buffer layer (103). A current isolation structure located on the surface of the GaN buffer layer (103) divides the current blocking layer (110) into two parts; At least three stacked barrier / channel structures located on the surface of the current blocking layer and the current isolation structure; Channel isolation layer located between the barrier / channel structures; The first source (106) is located on the surface of the uppermost barrier / channel structure. A second source (116) perpendicular to the stacking direction of the barrier / channel structure is used to connect the channel layer in each barrier / channel structure, and the second source (116) is connected to the first source (106); The passivation layer (107) is located on the surface of the uppermost barrier / channel structure and distributed on both sides of the first source electrode (106). Gates (105) located on both sides of the device and adjacent to the two portions of the current blocking layer (110); and The drain (101) is located on the surface of the substrate (102) away from the GaN buffer layer (103).

2. The CAVET device according to claim 1, characterized in that, The current isolation structure includes a first current isolation layer (111) and a second current isolation layer (117) distributed on both sides of the first current isolation layer (111).

3. The CAVET device according to claim 1, characterized in that, The barrier / channel structure includes a channel layer and a barrier layer, with the barrier layer located on the upper surface of the channel layer.

4. The CAVET device according to claim 1, characterized in that, The gates (105) located on both sides of the device are insulated from the rest of the device by HfO2 insulating gates (104).

5. The CAVET device according to claim 2 or 4, characterized in that, The second current isolation layer (117) and the HfO2 insulating gate (104) are spaced apart by a distance of 100~500 nm.

6. The CAVET device according to claim 1 or 4, characterized in that, The channel isolation layer located between the barrier / channel structure and the HfO2 insulating gate (104) are spaced apart by a distance of 100~500 nm.

7. The CAVET device according to claim 1, characterized in that, The channel layers in each of the aforementioned barrier / channel structures have the same thickness, and the barrier layers in each of the aforementioned barrier / channel structures have the same thickness.

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